Commit | Line | Data |
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0468b2d6 MD |
1 | /* |
2 | * Device Tree Source for the r8a7790 SoC | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
0468b2d6 MD |
11 | / { |
12 | compatible = "renesas,r8a7790"; | |
13 | interrupt-parent = <&gic>; | |
8585deb1 TY |
14 | #address-cells = <2>; |
15 | #size-cells = <2>; | |
0468b2d6 MD |
16 | |
17 | cpus { | |
18 | #address-cells = <1>; | |
19 | #size-cells = <0>; | |
20 | ||
21 | cpu0: cpu@0 { | |
22 | device_type = "cpu"; | |
23 | compatible = "arm,cortex-a15"; | |
24 | reg = <0>; | |
25 | clock-frequency = <1300000000>; | |
26 | }; | |
27 | }; | |
28 | ||
29 | gic: interrupt-controller@f1001000 { | |
30 | compatible = "arm,cortex-a15-gic"; | |
31 | #interrupt-cells = <3>; | |
32 | #address-cells = <0>; | |
33 | interrupt-controller; | |
8585deb1 TY |
34 | reg = <0 0xf1001000 0 0x1000>, |
35 | <0 0xf1002000 0 0x1000>, | |
36 | <0 0xf1004000 0 0x2000>, | |
37 | <0 0xf1006000 0 0x2000>; | |
0468b2d6 | 38 | interrupts = <1 9 0xf04>; |
0468b2d6 MD |
39 | }; |
40 | ||
41 | timer { | |
42 | compatible = "arm,armv7-timer"; | |
43 | interrupts = <1 13 0xf08>, | |
44 | <1 14 0xf08>, | |
45 | <1 11 0xf08>, | |
46 | <1 10 0xf08>; | |
47 | }; | |
8f5ec0a5 MD |
48 | |
49 | irqc0: interrupt-controller@e61c0000 { | |
50 | compatible = "renesas,irqc"; | |
51 | #interrupt-cells = <2>; | |
52 | interrupt-controller; | |
8585deb1 | 53 | reg = <0 0xe61c0000 0 0x200>; |
8f5ec0a5 MD |
54 | interrupt-parent = <&gic>; |
55 | interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; | |
56 | }; | |
0468b2d6 | 57 | }; |