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Merge branches 'amba', 'fixes', 'misc' and 'tauros2' into for-next
[deliverable/linux.git] / arch / arm / boot / dts / r8a7790.dtsi
CommitLineData
0468b2d6
MD		 1/*
2 * Device Tree Source for the r8a7790 SoC
3 *
b621f6d4 4 * Copyright (C) 2015 Renesas Electronics Corporation
d8913c67
SS		 5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
0468b2d6
MD		 7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
22a1f595 13#include <dt-bindings/clock/r8a7790-clock.h>
5f75e73c
LP		 14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
0468b2d6
MD		 17/ {
18 compatible = "renesas,r8a7790";
19 interrupt-parent = <&gic>;
8585deb1
TY		 20 #address-cells = <2>;
21 #size-cells = <2>;
0468b2d6 22
6b1d7c68
WS		 23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
05f39916
WS		 28 i2c4 = &iic0;
29 i2c5 = &iic1;
30 i2c6 = &iic2;
31 i2c7 = &iic3;
fad6d45c 32 spi0 = &qspi;
ae8a6146
GU		 33 spi1 = &msiof0;
34 spi2 = &msiof1;
35 spi3 = &msiof2;
36 spi4 = &msiof3;
9f685bfc
BD		 37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
40 vin3 = &vin3;
6b1d7c68
WS		 41 };
42
0468b2d6
MD		 43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu0: cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a15";
50 reg = <0>;
51 clock-frequency = <1300000000>;
b989e138
BC		 52 voltage-tolerance = <1>; /* 1% */
53 clocks = <&cpg_clocks R8A7790_CLK_Z>;
54 clock-latency = <300000>; /* 300 us */
55
56 /* kHz - uV - OPPs unknown yet */
57 operating-points = <1400000 1000000>,
58 <1225000 1000000>,
59 <1050000 1000000>,
60 < 875000 1000000>,
61 < 700000 1000000>,
62 < 350000 1000000>;
0468b2d6 63 };
c1f95979
MD		 64
65 cpu1: cpu@1 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a15";
68 reg = <1>;
69 clock-frequency = <1300000000>;
70 };
71
72 cpu2: cpu@2 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a15";
75 reg = <2>;
76 clock-frequency = <1300000000>;
77 };
78
79 cpu3: cpu@3 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a15";
82 reg = <3>;
83 clock-frequency = <1300000000>;
84 };
2007e74c
MD		 85
86 cpu4: cpu@4 {
87 device_type = "cpu";
88 compatible = "arm,cortex-a7";
89 reg = <0x100>;
90 clock-frequency = <780000000>;
91 };
92
93 cpu5: cpu@5 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a7";
96 reg = <0x101>;
97 clock-frequency = <780000000>;
98 };
99
100 cpu6: cpu@6 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a7";
103 reg = <0x102>;
104 clock-frequency = <780000000>;
105 };
106
107 cpu7: cpu@7 {
108 device_type = "cpu";
109 compatible = "arm,cortex-a7";
110 reg = <0x103>;
111 clock-frequency = <780000000>;
112 };
0468b2d6
MD		 113 };
114
115 gic: interrupt-controller@f1001000 {
e715e9c5 116 compatible = "arm,gic-400";
0468b2d6
MD		 117 #interrupt-cells = <3>;
118 #address-cells = <0>;
119 interrupt-controller;
8585deb1
TY		 120 reg = <0 0xf1001000 0 0x1000>,
121 <0 0xf1002000 0 0x1000>,
122 <0 0xf1004000 0 0x2000>,
123 <0 0xf1006000 0 0x2000>;
5f75e73c 124 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0468b2d6
MD		 125 };
126
23de2278 127 gpio0: gpio@e6050000 {
f98e10c8 128 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 129 reg = <0 0xe6050000 0 0x50>;
5f75e73c 130 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 131 #gpio-cells = <2>;
132 gpio-controller;
133 gpio-ranges = <&pfc 0 0 32>;
134 #interrupt-cells = <2>;
135 interrupt-controller;
81f6883f 136 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
484adb00 137 power-domains = <&cpg_clocks>;
f98e10c8
LP		 138 };
139
23de2278 140 gpio1: gpio@e6051000 {
f98e10c8 141 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 142 reg = <0 0xe6051000 0 0x50>;
5f75e73c 143 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 144 #gpio-cells = <2>;
145 gpio-controller;
56a2182f 146 gpio-ranges = <&pfc 0 32 30>;
f98e10c8
LP		 147 #interrupt-cells = <2>;
148 interrupt-controller;
81f6883f 149 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
484adb00 150 power-domains = <&cpg_clocks>;
f98e10c8
LP		 151 };
152
23de2278 153 gpio2: gpio@e6052000 {
f98e10c8 154 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 155 reg = <0 0xe6052000 0 0x50>;
5f75e73c 156 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 157 #gpio-cells = <2>;
158 gpio-controller;
56a2182f 159 gpio-ranges = <&pfc 0 64 30>;
f98e10c8
LP		 160 #interrupt-cells = <2>;
161 interrupt-controller;
81f6883f 162 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
484adb00 163 power-domains = <&cpg_clocks>;
f98e10c8
LP		 164 };
165
23de2278 166 gpio3: gpio@e6053000 {
f98e10c8 167 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 168 reg = <0 0xe6053000 0 0x50>;
5f75e73c 169 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 170 #gpio-cells = <2>;
171 gpio-controller;
172 gpio-ranges = <&pfc 0 96 32>;
173 #interrupt-cells = <2>;
174 interrupt-controller;
81f6883f 175 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
484adb00 176 power-domains = <&cpg_clocks>;
f98e10c8
LP		 177 };
178
23de2278 179 gpio4: gpio@e6054000 {
f98e10c8 180 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 181 reg = <0 0xe6054000 0 0x50>;
5f75e73c 182 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 183 #gpio-cells = <2>;
184 gpio-controller;
185 gpio-ranges = <&pfc 0 128 32>;
186 #interrupt-cells = <2>;
187 interrupt-controller;
81f6883f 188 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
484adb00 189 power-domains = <&cpg_clocks>;
f98e10c8
LP		 190 };
191
23de2278 192 gpio5: gpio@e6055000 {
f98e10c8 193 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 194 reg = <0 0xe6055000 0 0x50>;
5f75e73c 195 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 196 #gpio-cells = <2>;
197 gpio-controller;
198 gpio-ranges = <&pfc 0 160 32>;
199 #interrupt-cells = <2>;
200 interrupt-controller;
81f6883f 201 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
484adb00 202 power-domains = <&cpg_clocks>;
f98e10c8
LP		 203 };
204
03e2f56b
MD		 205 thermal@e61f0000 {
206 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
207 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
03e2f56b 208 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
d3a439db 209 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
484adb00 210 power-domains = <&cpg_clocks>;
03e2f56b
MD		 211 };
212
0468b2d6
MD		 213 timer {
214 compatible = "arm,armv7-timer";
5f75e73c
LP		 215 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
216 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
217 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
218 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0468b2d6 219 };
8f5ec0a5 220
39cf6d73 221 cmt0: timer@ffca0000 {
37757030 222 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
39cf6d73
LP		 223 reg = <0 0xffca0000 0 0x1004>;
224 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
225 <0 143 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
227 clock-names = "fck";
484adb00 228 power-domains = <&cpg_clocks>;
39cf6d73
LP		 229
230 renesas,channels-mask = <0x60>;
231
232 status = "disabled";
233 };
234
235 cmt1: timer@e6130000 {
37757030 236 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
39cf6d73
LP		 237 reg = <0 0xe6130000 0 0x1004>;
238 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
239 <0 121 IRQ_TYPE_LEVEL_HIGH>,
240 <0 122 IRQ_TYPE_LEVEL_HIGH>,
241 <0 123 IRQ_TYPE_LEVEL_HIGH>,
242 <0 124 IRQ_TYPE_LEVEL_HIGH>,
243 <0 125 IRQ_TYPE_LEVEL_HIGH>,
244 <0 126 IRQ_TYPE_LEVEL_HIGH>,
245 <0 127 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
247 clock-names = "fck";
484adb00 248 power-domains = <&cpg_clocks>;
39cf6d73
LP		 249
250 renesas,channels-mask = <0xff>;
251
252 status = "disabled";
253 };
254
8f5ec0a5 255 irqc0: interrupt-controller@e61c0000 {
220fc352 256 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
8f5ec0a5
MD		 257 #interrupt-cells = <2>;
258 interrupt-controller;
8585deb1 259 reg = <0 0xe61c0000 0 0x200>;
5f75e73c
LP		 260 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
261 <0 1 IRQ_TYPE_LEVEL_HIGH>,
262 <0 2 IRQ_TYPE_LEVEL_HIGH>,
263 <0 3 IRQ_TYPE_LEVEL_HIGH>;
61624caf 264 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
484adb00 265 power-domains = <&cpg_clocks>;
8f5ec0a5 266 };
8c9b1aa4 267
b9fea49c 268 dmac0: dma-controller@e6700000 {
4af0a664 269 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
b9fea49c
LP		 270 reg = <0 0xe6700000 0 0x20000>;
271 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
272 0 200 IRQ_TYPE_LEVEL_HIGH
273 0 201 IRQ_TYPE_LEVEL_HIGH
274 0 202 IRQ_TYPE_LEVEL_HIGH
275 0 203 IRQ_TYPE_LEVEL_HIGH
276 0 204 IRQ_TYPE_LEVEL_HIGH
277 0 205 IRQ_TYPE_LEVEL_HIGH
278 0 206 IRQ_TYPE_LEVEL_HIGH
279 0 207 IRQ_TYPE_LEVEL_HIGH
280 0 208 IRQ_TYPE_LEVEL_HIGH
281 0 209 IRQ_TYPE_LEVEL_HIGH
282 0 210 IRQ_TYPE_LEVEL_HIGH
283 0 211 IRQ_TYPE_LEVEL_HIGH
284 0 212 IRQ_TYPE_LEVEL_HIGH
285 0 213 IRQ_TYPE_LEVEL_HIGH
286 0 214 IRQ_TYPE_LEVEL_HIGH>;
287 interrupt-names = "error",
288 "ch0", "ch1", "ch2", "ch3",
289 "ch4", "ch5", "ch6", "ch7",
290 "ch8", "ch9", "ch10", "ch11",
291 "ch12", "ch13", "ch14";
292 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
293 clock-names = "fck";
484adb00 294 power-domains = <&cpg_clocks>;
b9fea49c
LP		 295 #dma-cells = <1>;
296 dma-channels = <15>;
297 };
298
299 dmac1: dma-controller@e6720000 {
4af0a664 300 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
b9fea49c
LP		 301 reg = <0 0xe6720000 0 0x20000>;
302 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
303 0 216 IRQ_TYPE_LEVEL_HIGH
304 0 217 IRQ_TYPE_LEVEL_HIGH
305 0 218 IRQ_TYPE_LEVEL_HIGH
306 0 219 IRQ_TYPE_LEVEL_HIGH
307 0 308 IRQ_TYPE_LEVEL_HIGH
308 0 309 IRQ_TYPE_LEVEL_HIGH
309 0 310 IRQ_TYPE_LEVEL_HIGH
310 0 311 IRQ_TYPE_LEVEL_HIGH
311 0 312 IRQ_TYPE_LEVEL_HIGH
312 0 313 IRQ_TYPE_LEVEL_HIGH
313 0 314 IRQ_TYPE_LEVEL_HIGH
314 0 315 IRQ_TYPE_LEVEL_HIGH
315 0 316 IRQ_TYPE_LEVEL_HIGH
316 0 317 IRQ_TYPE_LEVEL_HIGH
317 0 318 IRQ_TYPE_LEVEL_HIGH>;
318 interrupt-names = "error",
319 "ch0", "ch1", "ch2", "ch3",
320 "ch4", "ch5", "ch6", "ch7",
321 "ch8", "ch9", "ch10", "ch11",
322 "ch12", "ch13", "ch14";
323 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
324 clock-names = "fck";
484adb00 325 power-domains = <&cpg_clocks>;
b9fea49c
LP		 326 #dma-cells = <1>;
327 dma-channels = <15>;
328 };
ba3240be
KM		 329
330 audma0: dma-controller@ec700000 {
4af0a664 331 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
ba3240be
KM		 332 reg = <0 0xec700000 0 0x10000>;
333 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
334 0 320 IRQ_TYPE_LEVEL_HIGH
335 0 321 IRQ_TYPE_LEVEL_HIGH
336 0 322 IRQ_TYPE_LEVEL_HIGH
337 0 323 IRQ_TYPE_LEVEL_HIGH
338 0 324 IRQ_TYPE_LEVEL_HIGH
339 0 325 IRQ_TYPE_LEVEL_HIGH
340 0 326 IRQ_TYPE_LEVEL_HIGH
341 0 327 IRQ_TYPE_LEVEL_HIGH
342 0 328 IRQ_TYPE_LEVEL_HIGH
343 0 329 IRQ_TYPE_LEVEL_HIGH
344 0 330 IRQ_TYPE_LEVEL_HIGH
345 0 331 IRQ_TYPE_LEVEL_HIGH
346 0 332 IRQ_TYPE_LEVEL_HIGH>;
347 interrupt-names = "error",
348 "ch0", "ch1", "ch2", "ch3",
349 "ch4", "ch5", "ch6", "ch7",
350 "ch8", "ch9", "ch10", "ch11",
351 "ch12";
352 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
353 clock-names = "fck";
484adb00 354 power-domains = <&cpg_clocks>;
ba3240be
KM		 355 #dma-cells = <1>;
356 dma-channels = <13>;
357 };
358
359 audma1: dma-controller@ec720000 {
4af0a664 360 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
ba3240be
KM		 361 reg = <0 0xec720000 0 0x10000>;
362 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
363 0 333 IRQ_TYPE_LEVEL_HIGH
364 0 334 IRQ_TYPE_LEVEL_HIGH
365 0 335 IRQ_TYPE_LEVEL_HIGH
366 0 336 IRQ_TYPE_LEVEL_HIGH
367 0 337 IRQ_TYPE_LEVEL_HIGH
368 0 338 IRQ_TYPE_LEVEL_HIGH
369 0 339 IRQ_TYPE_LEVEL_HIGH
370 0 340 IRQ_TYPE_LEVEL_HIGH
371 0 341 IRQ_TYPE_LEVEL_HIGH
372 0 342 IRQ_TYPE_LEVEL_HIGH
373 0 343 IRQ_TYPE_LEVEL_HIGH
374 0 344 IRQ_TYPE_LEVEL_HIGH
375 0 345 IRQ_TYPE_LEVEL_HIGH>;
376 interrupt-names = "error",
377 "ch0", "ch1", "ch2", "ch3",
378 "ch4", "ch5", "ch6", "ch7",
379 "ch8", "ch9", "ch10", "ch11",
380 "ch12";
381 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
382 clock-names = "fck";
484adb00 383 power-domains = <&cpg_clocks>;
ba3240be
KM		 384 #dma-cells = <1>;
385 dma-channels = <13>;
386 };
387
a3ff2090 388 usb_dmac0: dma-controller@e65a0000 {
d01c8bec 389 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
a3ff2090
YS		 390 reg = <0 0xe65a0000 0 0x100>;
391 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
392 0 109 IRQ_TYPE_LEVEL_HIGH>;
393 interrupt-names = "ch0", "ch1";
394 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
484adb00 395 power-domains = <&cpg_clocks>;
a3ff2090
YS		 396 #dma-cells = <1>;
397 dma-channels = <2>;
398 };
399
400 usb_dmac1: dma-controller@e65b0000 {
d01c8bec 401 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
a3ff2090
YS		 402 reg = <0 0xe65b0000 0 0x100>;
403 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
404 0 110 IRQ_TYPE_LEVEL_HIGH>;
405 interrupt-names = "ch0", "ch1";
406 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
484adb00 407 power-domains = <&cpg_clocks>;
a3ff2090
YS		 408 #dma-cells = <1>;
409 dma-channels = <2>;
410 };
411
edd2b9f4
GL		 412 i2c0: i2c@e6508000 {
413 #address-cells = <1>;
414 #size-cells = <0>;
415 compatible = "renesas,i2c-r8a7790";
416 reg = <0 0xe6508000 0 0x40>;
5f75e73c 417 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
2450badf 418 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
484adb00 419 power-domains = <&cpg_clocks>;
ac8e7f31 420 i2c-scl-internal-delay-ns = <110>;
edd2b9f4
GL		 421 status = "disabled";
422 };
423
424 i2c1: i2c@e6518000 {
425 #address-cells = <1>;
426 #size-cells = <0>;
427 compatible = "renesas,i2c-r8a7790";
428 reg = <0 0xe6518000 0 0x40>;
5f75e73c 429 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
2450badf 430 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
484adb00 431 power-domains = <&cpg_clocks>;
ac8e7f31 432 i2c-scl-internal-delay-ns = <6>;
edd2b9f4
GL		 433 status = "disabled";
434 };
435
436 i2c2: i2c@e6530000 {
437 #address-cells = <1>;
438 #size-cells = <0>;
439 compatible = "renesas,i2c-r8a7790";
440 reg = <0 0xe6530000 0 0x40>;
5f75e73c 441 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
2450badf 442 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
484adb00 443 power-domains = <&cpg_clocks>;
ac8e7f31 444 i2c-scl-internal-delay-ns = <6>;
edd2b9f4
GL		 445 status = "disabled";
446 };
447
448 i2c3: i2c@e6540000 {
449 #address-cells = <1>;
450 #size-cells = <0>;
451 compatible = "renesas,i2c-r8a7790";
452 reg = <0 0xe6540000 0 0x40>;
5f75e73c 453 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
2450badf 454 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
484adb00 455 power-domains = <&cpg_clocks>;
ac8e7f31 456 i2c-scl-internal-delay-ns = <110>;
edd2b9f4
GL		 457 status = "disabled";
458 };
459
05f39916
WS		 460 iic0: i2c@e6500000 {
461 #address-cells = <1>;
462 #size-cells = <0>;
463 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
464 reg = <0 0xe6500000 0 0x425>;
465 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
0d73ca41
WS		 467 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
468 dma-names = "tx", "rx";
484adb00 469 power-domains = <&cpg_clocks>;
05f39916
WS		 470 status = "disabled";
471 };
472
473 iic1: i2c@e6510000 {
474 #address-cells = <1>;
475 #size-cells = <0>;
476 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
477 reg = <0 0xe6510000 0 0x425>;
478 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
0d73ca41
WS		 480 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
481 dma-names = "tx", "rx";
484adb00 482 power-domains = <&cpg_clocks>;
05f39916
WS		 483 status = "disabled";
484 };
485
486 iic2: i2c@e6520000 {
487 #address-cells = <1>;
488 #size-cells = <0>;
489 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
490 reg = <0 0xe6520000 0 0x425>;
491 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
0d73ca41
WS		 493 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
494 dma-names = "tx", "rx";
484adb00 495 power-domains = <&cpg_clocks>;
05f39916
WS		 496 status = "disabled";
497 };
498
499 iic3: i2c@e60b0000 {
500 #address-cells = <1>;
501 #size-cells = <0>;
502 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
503 reg = <0 0xe60b0000 0 0x425>;
504 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
0d73ca41
WS		 506 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
507 dma-names = "tx", "rx";
484adb00 508 power-domains = <&cpg_clocks>;
05f39916
WS		 509 status = "disabled";
510 };
511
22c2b78d 512 mmcif0: mmc@ee200000 {
063e8560 513 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
8c9b1aa4 514 reg = <0 0xee200000 0 0x80>;
5f75e73c 515 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 516 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
108216c1
LP		 517 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
518 dma-names = "tx", "rx";
484adb00 519 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 520 reg-io-width = <4>;
521 status = "disabled";
96370057 522 max-frequency = <97500000>;
8c9b1aa4
GL		 523 };
524
b718aa44 525 mmcif1: mmc@ee220000 {
063e8560 526 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
8c9b1aa4 527 reg = <0 0xee220000 0 0x80>;
5f75e73c 528 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 529 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
108216c1
LP		 530 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
531 dma-names = "tx", "rx";
484adb00 532 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 533 reg-io-width = <4>;
534 status = "disabled";
96370057 535 max-frequency = <97500000>;
8c9b1aa4
GL		 536 };
537
9694c778
LP		 538 pfc: pfc@e6060000 {
539 compatible = "renesas,pfc-r8a7790";
540 reg = <0 0xe6060000 0 0x250>;
541 };
55689bfa 542
b718aa44 543 sdhi0: sd@ee100000 {
df1d0584 544 compatible = "renesas,sdhi-r8a7790";
66f47ed0 545 reg = <0 0xee100000 0 0x328>;
5f75e73c 546 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 547 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
941fe36b
LP		 548 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
549 dma-names = "tx", "rx";
484adb00 550 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 551 status = "disabled";
552 };
553
b718aa44 554 sdhi1: sd@ee120000 {
df1d0584 555 compatible = "renesas,sdhi-r8a7790";
66f47ed0 556 reg = <0 0xee120000 0 0x328>;
5f75e73c 557 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 558 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
941fe36b
LP		 559 dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
560 dma-names = "tx", "rx";
484adb00 561 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 562 status = "disabled";
563 };
564
b718aa44 565 sdhi2: sd@ee140000 {
df1d0584 566 compatible = "renesas,sdhi-r8a7790";
8c9b1aa4 567 reg = <0 0xee140000 0 0x100>;
5f75e73c 568 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 569 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
941fe36b
LP		 570 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
571 dma-names = "tx", "rx";
484adb00 572 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 573 status = "disabled";
574 };
575
b718aa44 576 sdhi3: sd@ee160000 {
df1d0584 577 compatible = "renesas,sdhi-r8a7790";
8c9b1aa4 578 reg = <0 0xee160000 0 0x100>;
5f75e73c 579 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 580 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
941fe36b
LP		 581 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
582 dma-names = "tx", "rx";
484adb00 583 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 584 status = "disabled";
585 };
22a1f595 586
597af20f 587 scifa0: serial@e6c40000 {
59d2b517 588 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
597af20f 589 reg = <0 0xe6c40000 0 64>;
1f4c745b 590 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 591 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
592 clock-names = "sci_ick";
acea43fc
GU		 593 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
594 dma-names = "tx", "rx";
484adb00 595 power-domains = <&cpg_clocks>;
597af20f
LP		 596 status = "disabled";
597 };
598
599 scifa1: serial@e6c50000 {
59d2b517 600 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
597af20f 601 reg = <0 0xe6c50000 0 64>;
1f4c745b 602 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 603 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
604 clock-names = "sci_ick";
acea43fc
GU		 605 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
606 dma-names = "tx", "rx";
484adb00 607 power-domains = <&cpg_clocks>;
597af20f
LP		 608 status = "disabled";
609 };
610
611 scifa2: serial@e6c60000 {
59d2b517 612 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
597af20f 613 reg = <0 0xe6c60000 0 64>;
1f4c745b 614 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 615 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
616 clock-names = "sci_ick";
acea43fc
GU		 617 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
618 dma-names = "tx", "rx";
484adb00 619 power-domains = <&cpg_clocks>;
597af20f
LP		 620 status = "disabled";
621 };
622
623 scifb0: serial@e6c20000 {
59d2b517 624 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
597af20f 625 reg = <0 0xe6c20000 0 64>;
1f4c745b 626 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 627 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
628 clock-names = "sci_ick";
acea43fc
GU		 629 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
630 dma-names = "tx", "rx";
484adb00 631 power-domains = <&cpg_clocks>;
597af20f
LP		 632 status = "disabled";
633 };
634
635 scifb1: serial@e6c30000 {
59d2b517 636 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
597af20f 637 reg = <0 0xe6c30000 0 64>;
1f4c745b 638 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 639 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
640 clock-names = "sci_ick";
acea43fc
GU		 641 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
642 dma-names = "tx", "rx";
484adb00 643 power-domains = <&cpg_clocks>;
597af20f
LP		 644 status = "disabled";
645 };
646
647 scifb2: serial@e6ce0000 {
59d2b517 648 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
597af20f 649 reg = <0 0xe6ce0000 0 64>;
1f4c745b 650 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 651 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
652 clock-names = "sci_ick";
acea43fc
GU		 653 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
654 dma-names = "tx", "rx";
484adb00 655 power-domains = <&cpg_clocks>;
597af20f
LP		 656 status = "disabled";
657 };
658
659 scif0: serial@e6e60000 {
59d2b517 660 compatible = "renesas,scif-r8a7790", "renesas,scif";
597af20f 661 reg = <0 0xe6e60000 0 64>;
1f4c745b 662 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 663 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
664 clock-names = "sci_ick";
acea43fc
GU		 665 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
666 dma-names = "tx", "rx";
484adb00 667 power-domains = <&cpg_clocks>;
597af20f
LP		 668 status = "disabled";
669 };
670
671 scif1: serial@e6e68000 {
59d2b517 672 compatible = "renesas,scif-r8a7790", "renesas,scif";
597af20f 673 reg = <0 0xe6e68000 0 64>;
1f4c745b 674 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 675 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
676 clock-names = "sci_ick";
acea43fc
GU		 677 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
678 dma-names = "tx", "rx";
484adb00 679 power-domains = <&cpg_clocks>;
597af20f
LP		 680 status = "disabled";
681 };
682
683 hscif0: serial@e62c0000 {
59d2b517 684 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
597af20f 685 reg = <0 0xe62c0000 0 96>;
1f4c745b 686 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 687 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
688 clock-names = "sci_ick";
acea43fc
GU		 689 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
690 dma-names = "tx", "rx";
484adb00 691 power-domains = <&cpg_clocks>;
597af20f
LP		 692 status = "disabled";
693 };
694
695 hscif1: serial@e62c8000 {
59d2b517 696 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
597af20f 697 reg = <0 0xe62c8000 0 96>;
1f4c745b 698 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 699 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
700 clock-names = "sci_ick";
acea43fc
GU		 701 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
702 dma-names = "tx", "rx";
484adb00 703 power-domains = <&cpg_clocks>;
597af20f
LP		 704 status = "disabled";
705 };
706
d8913c67
SS		 707 ether: ethernet@ee700000 {
708 compatible = "renesas,ether-r8a7790";
709 reg = <0 0xee700000 0 0x400>;
710 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
484adb00 712 power-domains = <&cpg_clocks>;
d8913c67
SS		 713 phy-mode = "rmii";
714 #address-cells = <1>;
715 #size-cells = <0>;
716 status = "disabled";
717 };
718
f25d6b97
SS		 719 avb: ethernet@e6800000 {
720 compatible = "renesas,etheravb-r8a7790";
721 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
722 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
484adb00 724 power-domains = <&cpg_clocks>;
f25d6b97
SS		 725 #address-cells = <1>;
726 #size-cells = <0>;
727 status = "disabled";
728 };
729
cde630f7
VB		 730 sata0: sata@ee300000 {
731 compatible = "renesas,sata-r8a7790";
732 reg = <0 0xee300000 0 0x2000>;
cde630f7
VB		 733 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
484adb00 735 power-domains = <&cpg_clocks>;
cde630f7
VB		 736 status = "disabled";
737 };
738
739 sata1: sata@ee500000 {
740 compatible = "renesas,sata-r8a7790";
741 reg = <0 0xee500000 0 0x2000>;
cde630f7
VB		 742 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
484adb00 744 power-domains = <&cpg_clocks>;
cde630f7
VB		 745 status = "disabled";
746 };
747
ae0a555b
YS		 748 hsusb: usb@e6590000 {
749 compatible = "renesas,usbhs-r8a7790";
750 reg = <0 0xe6590000 0 0x100>;
751 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
e8295dc3
YS		 753 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
754 <&usb_dmac1 0>, <&usb_dmac1 1>;
755 dma-names = "ch0", "ch1", "ch2", "ch3";
484adb00
GU		 756 power-domains = <&cpg_clocks>;
757 renesas,buswait = <4>;
758 phys = <&usb0 1>;
759 phy-names = "usb";
ae0a555b
YS		 760 status = "disabled";
761 };
762
e089f657
SS		 763 usbphy: usb-phy@e6590100 {
764 compatible = "renesas,usb-phy-r8a7790";
765 reg = <0 0xe6590100 0 0x100>;
766 #address-cells = <1>;
767 #size-cells = <0>;
768 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
769 clock-names = "usbhs";
484adb00 770 power-domains = <&cpg_clocks>;
e089f657
SS		 771 status = "disabled";
772
773 usb0: usb-channel@0 {
774 reg = <0>;
775 #phy-cells = <1>;
776 };
777 usb2: usb-channel@2 {
778 reg = <2>;
779 #phy-cells = <1>;
780 };
781 };
782
9f685bfc
BD		 783 vin0: video@e6ef0000 {
784 compatible = "renesas,vin-r8a7790";
9f685bfc
BD		 785 reg = <0 0xe6ef0000 0 0x1000>;
786 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 787 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
788 power-domains = <&cpg_clocks>;
9f685bfc
BD		 789 status = "disabled";
790 };
791
792 vin1: video@e6ef1000 {
793 compatible = "renesas,vin-r8a7790";
9f685bfc
BD		 794 reg = <0 0xe6ef1000 0 0x1000>;
795 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 796 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
797 power-domains = <&cpg_clocks>;
9f685bfc
BD		 798 status = "disabled";
799 };
800
801 vin2: video@e6ef2000 {
802 compatible = "renesas,vin-r8a7790";
9f685bfc
BD		 803 reg = <0 0xe6ef2000 0 0x1000>;
804 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 805 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
806 power-domains = <&cpg_clocks>;
9f685bfc
BD		 807 status = "disabled";
808 };
809
810 vin3: video@e6ef3000 {
811 compatible = "renesas,vin-r8a7790";
9f685bfc
BD		 812 reg = <0 0xe6ef3000 0 0x1000>;
813 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 814 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
815 power-domains = <&cpg_clocks>;
9f685bfc
BD		 816 status = "disabled";
817 };
818
3ac6a83c
LP		 819 vsp1@fe920000 {
820 compatible = "renesas,vsp1";
821 reg = <0 0xfe920000 0 0x8000>;
822 interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
484adb00 824 power-domains = <&cpg_clocks>;
3ac6a83c
LP		 825
826 renesas,has-sru;
827 renesas,#rpf = <5>;
828 renesas,#uds = <1>;
829 renesas,#wpf = <4>;
830 };
831
832 vsp1@fe928000 {
833 compatible = "renesas,vsp1";
834 reg = <0 0xfe928000 0 0x8000>;
835 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
484adb00 837 power-domains = <&cpg_clocks>;
3ac6a83c
LP		 838
839 renesas,has-lut;
840 renesas,has-sru;
841 renesas,#rpf = <5>;
842 renesas,#uds = <3>;
843 renesas,#wpf = <4>;
844 };
845
846 vsp1@fe930000 {
847 compatible = "renesas,vsp1";
848 reg = <0 0xfe930000 0 0x8000>;
849 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
484adb00 851 power-domains = <&cpg_clocks>;
3ac6a83c
LP		 852
853 renesas,has-lif;
854 renesas,has-lut;
855 renesas,#rpf = <4>;
856 renesas,#uds = <1>;
857 renesas,#wpf = <4>;
858 };
859
860 vsp1@fe938000 {
861 compatible = "renesas,vsp1";
862 reg = <0 0xfe938000 0 0x8000>;
863 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
484adb00 865 power-domains = <&cpg_clocks>;
3ac6a83c
LP		 866
867 renesas,has-lif;
868 renesas,has-lut;
869 renesas,#rpf = <4>;
870 renesas,#uds = <1>;
871 renesas,#wpf = <4>;
872 };
873
874 du: display@feb00000 {
875 compatible = "renesas,du-r8a7790";
876 reg = <0 0xfeb00000 0 0x70000>,
877 <0 0xfeb90000 0 0x1c>,
878 <0 0xfeb94000 0 0x1c>;
879 reg-names = "du", "lvds.0", "lvds.1";
880 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
881 <0 268 IRQ_TYPE_LEVEL_HIGH>,
882 <0 269 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
884 <&mstp7_clks R8A7790_CLK_DU1>,
885 <&mstp7_clks R8A7790_CLK_DU2>,
886 <&mstp7_clks R8A7790_CLK_LVDS0>,
887 <&mstp7_clks R8A7790_CLK_LVDS1>;
888 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
889 status = "disabled";
890
891 ports {
892 #address-cells = <1>;
893 #size-cells = <0>;
894
895 port@0 {
896 reg = <0>;
897 du_out_rgb: endpoint {
898 };
899 };
900 port@1 {
901 reg = <1>;
902 du_out_lvds0: endpoint {
903 };
904 };
905 port@2 {
906 reg = <2>;
907 du_out_lvds1: endpoint {
908 };
909 };
910 };
911 };
912
6a7742b4
SS		 913 can0: can@e6e80000 {
914 compatible = "renesas,can-r8a7790";
915 reg = <0 0xe6e80000 0 0x1000>;
916 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
918 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
919 clock-names = "clkp1", "clkp2", "can_clk";
484adb00 920 power-domains = <&cpg_clocks>;
6a7742b4
SS		 921 status = "disabled";
922 };
923
924 can1: can@e6e88000 {
925 compatible = "renesas,can-r8a7790";
926 reg = <0 0xe6e88000 0 0x1000>;
927 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
929 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
930 clock-names = "clkp1", "clkp2", "can_clk";
484adb00 931 power-domains = <&cpg_clocks>;
6a7742b4
SS		 932 status = "disabled";
933 };
934
fb847575
MU		 935 jpu: jpeg-codec@fe980000 {
936 compatible = "renesas,jpu-r8a7790";
937 reg = <0 0xfe980000 0 0x10300>;
938 interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
939 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
484adb00 940 power-domains = <&cpg_clocks>;
fb847575
MU		 941 };
942
22a1f595
LP		 943 clocks {
944 #address-cells = <2>;
945 #size-cells = <2>;
946 ranges;
947
948 /* External root clock */
949 extal_clk: extal_clk {
950 compatible = "fixed-clock";
951 #clock-cells = <0>;
952 /* This value must be overriden by the board. */
953 clock-frequency = <0>;
954 clock-output-names = "extal";
955 };
956
51d17918
PE		 957 /* External PCIe clock - can be overridden by the board */
958 pcie_bus_clk: pcie_bus_clk {
959 compatible = "fixed-clock";
960 #clock-cells = <0>;
961 clock-frequency = <100000000>;
962 clock-output-names = "pcie_bus";
963 status = "disabled";
964 };
965
c7c2ec3a
KM		 966 /*
967 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
968 * default. Boards that provide audio clocks should override them.
969 */
970 audio_clk_a: audio_clk_a {
971 compatible = "fixed-clock";
972 #clock-cells = <0>;
973 clock-frequency = <0>;
974 clock-output-names = "audio_clk_a";
975 };
976 audio_clk_b: audio_clk_b {
977 compatible = "fixed-clock";
978 #clock-cells = <0>;
979 clock-frequency = <0>;
980 clock-output-names = "audio_clk_b";
981 };
982 audio_clk_c: audio_clk_c {
983 compatible = "fixed-clock";
984 #clock-cells = <0>;
985 clock-frequency = <0>;
986 clock-output-names = "audio_clk_c";
987 };
988
41650f40
SS		 989 /* External USB clock - can be overridden by the board */
990 usb_extal_clk: usb_extal_clk {
991 compatible = "fixed-clock";
992 #clock-cells = <0>;
993 clock-frequency = <48000000>;
994 clock-output-names = "usb_extal";
995 };
996
997 /* External CAN clock */
998 can_clk: can_clk {
999 compatible = "fixed-clock";
1000 #clock-cells = <0>;
1001 /* This value must be overridden by the board. */
1002 clock-frequency = <0>;
1003 clock-output-names = "can_clk";
1004 status = "disabled";
1005 };
1006
22a1f595
LP		 1007 /* Special CPG clocks */
1008 cpg_clocks: cpg_clocks@e6150000 {
1009 compatible = "renesas,r8a7790-cpg-clocks",
1010 "renesas,rcar-gen2-cpg-clocks";
1011 reg = <0 0xe6150000 0 0x1000>;
41650f40 1012 clocks = <&extal_clk &usb_extal_clk>;
22a1f595
LP		 1013 #clock-cells = <1>;
1014 clock-output-names = "main", "pll0", "pll1", "pll3",
1015 "lb", "qspi", "sdh", "sd0", "sd1",
3453ca9e 1016 "z", "rcan", "adsp";
484adb00 1017 #power-domain-cells = <0>;
22a1f595
LP		 1018 };
1019
1020 /* Variable factor clocks */
1021 sd2_clk: sd2_clk@e6150078 {
1022 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1023 reg = <0 0xe6150078 0 4>;
1024 clocks = <&pll1_div2_clk>;
1025 #clock-cells = <0>;
1026 clock-output-names = "sd2";
1027 };
edd7b938 1028 sd3_clk: sd3_clk@e615026c {
22a1f595 1029 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
edd7b938 1030 reg = <0 0xe615026c 0 4>;
22a1f595
LP		 1031 clocks = <&pll1_div2_clk>;
1032 #clock-cells = <0>;
1033 clock-output-names = "sd3";
1034 };
1035 mmc0_clk: mmc0_clk@e6150240 {
1036 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1037 reg = <0 0xe6150240 0 4>;
1038 clocks = <&pll1_div2_clk>;
1039 #clock-cells = <0>;
1040 clock-output-names = "mmc0";
1041 };
1042 mmc1_clk: mmc1_clk@e6150244 {
1043 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1044 reg = <0 0xe6150244 0 4>;
1045 clocks = <&pll1_div2_clk>;
1046 #clock-cells = <0>;
1047 clock-output-names = "mmc1";
1048 };
1049 ssp_clk: ssp_clk@e6150248 {
1050 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1051 reg = <0 0xe6150248 0 4>;
1052 clocks = <&pll1_div2_clk>;
1053 #clock-cells = <0>;
1054 clock-output-names = "ssp";
1055 };
1056 ssprs_clk: ssprs_clk@e615024c {
1057 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1058 reg = <0 0xe615024c 0 4>;
1059 clocks = <&pll1_div2_clk>;
1060 #clock-cells = <0>;
1061 clock-output-names = "ssprs";
1062 };
1063
1064 /* Fixed factor clocks */
1065 pll1_div2_clk: pll1_div2_clk {
1066 compatible = "fixed-factor-clock";
1067 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1068 #clock-cells = <0>;
1069 clock-div = <2>;
1070 clock-mult = <1>;
1071 clock-output-names = "pll1_div2";
1072 };
1073 z2_clk: z2_clk {
1074 compatible = "fixed-factor-clock";
1075 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1076 #clock-cells = <0>;
1077 clock-div = <2>;
1078 clock-mult = <1>;
1079 clock-output-names = "z2";
1080 };
1081 zg_clk: zg_clk {
1082 compatible = "fixed-factor-clock";
1083 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1084 #clock-cells = <0>;
1085 clock-div = <3>;
1086 clock-mult = <1>;
1087 clock-output-names = "zg";
1088 };
1089 zx_clk: zx_clk {
1090 compatible = "fixed-factor-clock";
1091 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1092 #clock-cells = <0>;
1093 clock-div = <3>;
1094 clock-mult = <1>;
1095 clock-output-names = "zx";
1096 };
1097 zs_clk: zs_clk {
1098 compatible = "fixed-factor-clock";
1099 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1100 #clock-cells = <0>;
1101 clock-div = <6>;
1102 clock-mult = <1>;
1103 clock-output-names = "zs";
1104 };
1105 hp_clk: hp_clk {
1106 compatible = "fixed-factor-clock";
1107 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1108 #clock-cells = <0>;
1109 clock-div = <12>;
1110 clock-mult = <1>;
1111 clock-output-names = "hp";
1112 };
1113 i_clk: i_clk {
1114 compatible = "fixed-factor-clock";
1115 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1116 #clock-cells = <0>;
1117 clock-div = <2>;
1118 clock-mult = <1>;
1119 clock-output-names = "i";
1120 };
1121 b_clk: b_clk {
1122 compatible = "fixed-factor-clock";
1123 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1124 #clock-cells = <0>;
1125 clock-div = <12>;
1126 clock-mult = <1>;
1127 clock-output-names = "b";
1128 };
1129 p_clk: p_clk {
1130 compatible = "fixed-factor-clock";
1131 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1132 #clock-cells = <0>;
1133 clock-div = <24>;
1134 clock-mult = <1>;
1135 clock-output-names = "p";
1136 };
1137 cl_clk: cl_clk {
1138 compatible = "fixed-factor-clock";
1139 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1140 #clock-cells = <0>;
1141 clock-div = <48>;
1142 clock-mult = <1>;
1143 clock-output-names = "cl";
1144 };
1145 m2_clk: m2_clk {
1146 compatible = "fixed-factor-clock";
1147 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1148 #clock-cells = <0>;
1149 clock-div = <8>;
1150 clock-mult = <1>;
1151 clock-output-names = "m2";
1152 };
1153 imp_clk: imp_clk {
1154 compatible = "fixed-factor-clock";
1155 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1156 #clock-cells = <0>;
1157 clock-div = <4>;
1158 clock-mult = <1>;
1159 clock-output-names = "imp";
1160 };
1161 rclk_clk: rclk_clk {
1162 compatible = "fixed-factor-clock";
1163 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1164 #clock-cells = <0>;
1165 clock-div = <(48 * 1024)>;
1166 clock-mult = <1>;
1167 clock-output-names = "rclk";
1168 };
1169 oscclk_clk: oscclk_clk {
1170 compatible = "fixed-factor-clock";
1171 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1172 #clock-cells = <0>;
1173 clock-div = <(12 * 1024)>;
1174 clock-mult = <1>;
1175 clock-output-names = "oscclk";
1176 };
1177 zb3_clk: zb3_clk {
1178 compatible = "fixed-factor-clock";
1179 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1180 #clock-cells = <0>;
1181 clock-div = <4>;
1182 clock-mult = <1>;
1183 clock-output-names = "zb3";
1184 };
1185 zb3d2_clk: zb3d2_clk {
1186 compatible = "fixed-factor-clock";
1187 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1188 #clock-cells = <0>;
1189 clock-div = <8>;
1190 clock-mult = <1>;
1191 clock-output-names = "zb3d2";
1192 };
1193 ddr_clk: ddr_clk {
1194 compatible = "fixed-factor-clock";
1195 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1196 #clock-cells = <0>;
1197 clock-div = <8>;
1198 clock-mult = <1>;
1199 clock-output-names = "ddr";
1200 };
1201 mp_clk: mp_clk {
1202 compatible = "fixed-factor-clock";
1203 clocks = <&pll1_div2_clk>;
1204 #clock-cells = <0>;
1205 clock-div = <15>;
1206 clock-mult = <1>;
1207 clock-output-names = "mp";
1208 };
1209 cp_clk: cp_clk {
1210 compatible = "fixed-factor-clock";
1211 clocks = <&extal_clk>;
1212 #clock-cells = <0>;
1213 clock-div = <2>;
1214 clock-mult = <1>;
1215 clock-output-names = "cp";
1216 };
1217
1218 /* Gate clocks */
9d90951a
LP		 1219 mstp0_clks: mstp0_clks@e6150130 {
1220 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1221 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1222 clocks = <&mp_clk>;
1223 #clock-cells = <1>;
b54010af 1224 clock-indices = <R8A7790_CLK_MSIOF0>;
9d90951a
LP		 1225 clock-output-names = "msiof0";
1226 };
22a1f595
LP		 1227 mstp1_clks: mstp1_clks@e6150134 {
1228 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1229 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
4ba8f246
YH		 1230 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1231 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1232 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1233 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
22a1f595 1234 #clock-cells = <1>;
b54010af 1235 clock-indices = <
4ba8f246
YH		 1236 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1237 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1238 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1239 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1240 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1241 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1242 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
22a1f595
LP		 1243 >;
1244 clock-output-names =
4ba8f246
YH		 1245 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1246 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1247 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
2284ff5f 1248 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
22a1f595
LP		 1249 };
1250 mstp2_clks: mstp2_clks@e6150138 {
1251 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1252 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1253 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
c819acda
LP		 1254 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1255 <&zs_clk>;
22a1f595 1256 #clock-cells = <1>;
b54010af 1257 clock-indices = <
22a1f595 1258 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
9d90951a
LP		 1259 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1260 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
c819acda 1261 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
22a1f595
LP		 1262 >;
1263 clock-output-names =
9d90951a 1264 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
c819acda
LP		 1265 "scifb1", "msiof1", "msiof3", "scifb2",
1266 "sys-dmac1", "sys-dmac0";
22a1f595
LP		 1267 };
1268 mstp3_clks: mstp3_clks@e615013c {
1269 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1270 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
17465149
WS		 1271 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1272 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
b02ce79f
YS		 1273 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1274 <&hp_clk>, <&hp_clk>;
22a1f595 1275 #clock-cells = <1>;
b54010af 1276 clock-indices = <
17465149
WS		 1277 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1278 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
ecafea8c 1279 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
b02ce79f 1280 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
22a1f595
LP		 1281 >;
1282 clock-output-names =
17465149
WS		 1283 "iic2", "tpu0", "mmcif1", "sdhi3",
1284 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
b02ce79f
YS		 1285 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1286 "usbdmac0", "usbdmac1";
22a1f595 1287 };
61624caf
GU		 1288 mstp4_clks: mstp4_clks@e6150140 {
1289 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1290 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1291 clocks = <&cp_clk>;
1292 #clock-cells = <1>;
1293 clock-indices = <R8A7790_CLK_IRQC>;
1294 clock-output-names = "irqc";
1295 };
22a1f595
LP		 1296 mstp5_clks: mstp5_clks@e6150144 {
1297 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1298 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
3453ca9e
SS		 1299 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1300 <&extal_clk>, <&p_clk>;
22a1f595 1301 #clock-cells = <1>;
b54010af
BD		 1302 clock-indices = <
1303 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
3453ca9e
SS		 1304 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1305 R8A7790_CLK_PWM
b54010af 1306 >;
3453ca9e
SS		 1307 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1308 "thermal", "pwm";
22a1f595
LP		 1309 };
1310 mstp7_clks: mstp7_clks@e615014c {
1311 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1312 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
b621f6d4 1313 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
22a1f595
LP		 1314 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1315 <&zx_clk>;
1316 #clock-cells = <1>;
b54010af 1317 clock-indices = <
22a1f595
LP		 1318 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1319 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1320 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1321 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1322 >;
1323 clock-output-names =
1324 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1325 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1326 };
1327 mstp8_clks: mstp8_clks@e6150990 {
1328 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1329 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
f6b5dd40 1330 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
63d2d750
SS		 1331 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1332 <&zs_clk>;
22a1f595 1333 #clock-cells = <1>;
b54010af 1334 clock-indices = <
f6b5dd40 1335 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
63d2d750
SS		 1336 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1337 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
f6b5dd40 1338 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
3f2beaa9 1339 >;
bccccc3d 1340 clock-output-names =
63d2d750
SS		 1341 "mlb", "vin3", "vin2", "vin1", "vin0",
1342 "etheravb", "ether", "sata1", "sata0";
22a1f595
LP		 1343 };
1344 mstp9_clks: mstp9_clks@e6150994 {
1345 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1346 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
81f6883f
GU		 1347 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1348 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1349 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
3672b059 1350 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
22a1f595 1351 #clock-cells = <1>;
b54010af 1352 clock-indices = <
81f6883f
GU		 1353 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1354 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
17465149
WS		 1355 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1356 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
22a1f595 1357 >;
91b56ca1 1358 clock-output-names =
81f6883f 1359 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
17465149
WS		 1360 "rcan1", "rcan0", "qspi_mod", "iic3",
1361 "i2c3", "i2c2", "i2c1", "i2c0";
22a1f595 1362 };
bcde3722
KM		 1363 mstp10_clks: mstp10_clks@e6150998 {
1364 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1365 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1366 clocks = <&p_clk>,
1367 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1368 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1369 <&p_clk>,
1370 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1371 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1372 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1373 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1374 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
a7163784 1375 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
bcde3722
KM		 1376 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1377
1378 #clock-cells = <1>;
1379 clock-indices = <
1380 R8A7790_CLK_SSI_ALL
1381 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1382 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1383 R8A7790_CLK_SCU_ALL
1384 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
a7163784 1385 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
bcde3722
KM		 1386 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1387 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1388 >;
1389 clock-output-names =
1390 "ssi-all",
1391 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1392 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1393 "scu-all",
1394 "scu-dvc1", "scu-dvc0",
a7163784 1395 "scu-ctu1-mix1", "scu-ctu0-mix0",
bcde3722
KM		 1396 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1397 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1398 };
22a1f595 1399 };
7053e134 1400
fad6d45c 1401 qspi: spi@e6b10000 {
7053e134
GU		 1402 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1403 reg = <0 0xe6b10000 0 0x2c>;
7053e134
GU		 1404 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1405 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
37cf3d61
GU		 1406 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1407 dma-names = "tx", "rx";
484adb00 1408 power-domains = <&cpg_clocks>;
7053e134
GU		 1409 num-cs = <1>;
1410 #address-cells = <1>;
1411 #size-cells = <0>;
1412 status = "disabled";
1413 };
ae8a6146
GU		 1414
1415 msiof0: spi@e6e20000 {
1416 compatible = "renesas,msiof-r8a7790";
c7d1f08a 1417 reg = <0 0xe6e20000 0 0x0064>;
ae8a6146
GU		 1418 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
fbff6688
GU		 1420 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1421 dma-names = "tx", "rx";
484adb00 1422 power-domains = <&cpg_clocks>;
ae8a6146
GU		 1423 #address-cells = <1>;
1424 #size-cells = <0>;
1425 status = "disabled";
1426 };
1427
1428 msiof1: spi@e6e10000 {
1429 compatible = "renesas,msiof-r8a7790";
c7d1f08a 1430 reg = <0 0xe6e10000 0 0x0064>;
ae8a6146
GU		 1431 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1432 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
fbff6688
GU		 1433 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1434 dma-names = "tx", "rx";
484adb00 1435 power-domains = <&cpg_clocks>;
ae8a6146
GU		 1436 #address-cells = <1>;
1437 #size-cells = <0>;
1438 status = "disabled";
1439 };
1440
1441 msiof2: spi@e6e00000 {
1442 compatible = "renesas,msiof-r8a7790";
c7d1f08a 1443 reg = <0 0xe6e00000 0 0x0064>;
ae8a6146
GU		 1444 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1445 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
fbff6688
GU		 1446 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1447 dma-names = "tx", "rx";
484adb00 1448 power-domains = <&cpg_clocks>;
ae8a6146
GU		 1449 #address-cells = <1>;
1450 #size-cells = <0>;
1451 status = "disabled";
1452 };
1453
1454 msiof3: spi@e6c90000 {
1455 compatible = "renesas,msiof-r8a7790";
c7d1f08a 1456 reg = <0 0xe6c90000 0 0x0064>;
ae8a6146
GU		 1457 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
1458 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
fbff6688
GU		 1459 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1460 dma-names = "tx", "rx";
484adb00 1461 power-domains = <&cpg_clocks>;
ae8a6146
GU		 1462 #address-cells = <1>;
1463 #size-cells = <0>;
1464 status = "disabled";
1465 };
7df2fd57 1466
157fcd8a
YS		 1467 xhci: usb@ee000000 {
1468 compatible = "renesas,xhci-r8a7790";
1469 reg = <0 0xee000000 0 0xc00>;
1470 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1471 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
484adb00 1472 power-domains = <&cpg_clocks>;
157fcd8a
YS		 1473 phys = <&usb2 1>;
1474 phy-names = "usb";
1475 status = "disabled";
1476 };
1477
ff4f3eb8
BD		 1478 pci0: pci@ee090000 {
1479 compatible = "renesas,pci-r8a7790";
1480 device_type = "pci";
ff4f3eb8
BD		 1481 reg = <0 0xee090000 0 0xc00>,
1482 <0 0xee080000 0 0x1100>;
1483 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 1484 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1485 power-domains = <&cpg_clocks>;
ff4f3eb8
BD		 1486 status = "disabled";
1487
1488 bus-range = <0 0>;
1489 #address-cells = <3>;
1490 #size-cells = <2>;
1491 #interrupt-cells = <1>;
1492 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1493 interrupt-map-mask = <0xff00 0 0 0x7>;
1494 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
517ec80a
GU		 1495 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1496 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
538c40e5
SS		 1497
1498 usb@0,1 {
1499 reg = <0x800 0 0 0 0>;
1500 device_type = "pci";
1501 phys = <&usb0 0>;
1502 phy-names = "usb";
1503 };
1504
1505 usb@0,2 {
1506 reg = <0x1000 0 0 0 0>;
1507 device_type = "pci";
1508 phys = <&usb0 0>;
1509 phy-names = "usb";
1510 };
ff4f3eb8
BD		 1511 };
1512
1513 pci1: pci@ee0b0000 {
1514 compatible = "renesas,pci-r8a7790";
1515 device_type = "pci";
ff4f3eb8
BD		 1516 reg = <0 0xee0b0000 0 0xc00>,
1517 <0 0xee0a0000 0 0x1100>;
1518 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 1519 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1520 power-domains = <&cpg_clocks>;
ff4f3eb8
BD		 1521 status = "disabled";
1522
1523 bus-range = <1 1>;
1524 #address-cells = <3>;
1525 #size-cells = <2>;
1526 #interrupt-cells = <1>;
1527 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1528 interrupt-map-mask = <0xff00 0 0 0x7>;
1529 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
517ec80a
GU		 1530 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1531 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
ff4f3eb8
BD		 1532 };
1533
1534 pci2: pci@ee0d0000 {
1535 compatible = "renesas,pci-r8a7790";
1536 device_type = "pci";
1537 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
484adb00 1538 power-domains = <&cpg_clocks>;
ff4f3eb8
BD		 1539 reg = <0 0xee0d0000 0 0xc00>,
1540 <0 0xee0c0000 0 0x1100>;
1541 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1542 status = "disabled";
1543
1544 bus-range = <2 2>;
1545 #address-cells = <3>;
1546 #size-cells = <2>;
1547 #interrupt-cells = <1>;
1548 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1549 interrupt-map-mask = <0xff00 0 0 0x7>;
1550 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
517ec80a
GU		 1551 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1552 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
538c40e5
SS		 1553
1554 usb@0,1 {
1555 reg = <0x800 0 0 0 0>;
1556 device_type = "pci";
1557 phys = <&usb2 0>;
1558 phy-names = "usb";
1559 };
1560
1561 usb@0,2 {
1562 reg = <0x1000 0 0 0 0>;
1563 device_type = "pci";
1564 phys = <&usb2 0>;
1565 phy-names = "usb";
1566 };
ff4f3eb8
BD		 1567 };
1568
745329d2
PE		 1569 pciec: pcie@fe000000 {
1570 compatible = "renesas,pcie-r8a7790";
1571 reg = <0 0xfe000000 0 0x80000>;
1572 #address-cells = <3>;
1573 #size-cells = <2>;
1574 bus-range = <0x00 0xff>;
1575 device_type = "pci";
1576 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1577 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1578 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1579 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1580 /* Map all possible DDR as inbound ranges */
1581 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1582 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1583 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1584 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1585 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1586 #interrupt-cells = <1>;
1587 interrupt-map-mask = <0 0 0 0>;
1588 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1589 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1590 clock-names = "pcie", "pcie_bus";
484adb00 1591 power-domains = <&cpg_clocks>;
745329d2
PE		 1592 status = "disabled";
1593 };
1594
b694e380 1595 rcar_sound: sound@ec500000 {
ad63241c
KM		 1596 /*
1597 * #sound-dai-cells is required
1598 *
1599 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1600 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1601 */
31078ecd 1602 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
7df2fd57
KM		 1603 reg = <0 0xec500000 0 0x1000>, /* SCU */
1604 <0 0xec5a0000 0 0x100>, /* ADG */
1605 <0 0xec540000 0 0x1000>, /* SSIU */
4bc4a205 1606 <0 0xec541000 0 0x280>, /* SSI */
0c602677
KM		 1607 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1608 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
46a158f2 1609
7df2fd57
KM		 1610 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1611 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1612 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1613 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1614 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1615 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1616 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1617 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1618 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1619 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1620 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
a7163784 1621 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
fc67bf42 1622 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
334d69a2 1623 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
7df2fd57
KM		 1624 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1625 clock-names = "ssi-all",
1626 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1627 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1628 "src.9", "src.8", "src.7", "src.6", "src.5",
1629 "src.4", "src.3", "src.2", "src.1", "src.0",
a7163784 1630 "ctu.0", "ctu.1",
fc67bf42 1631 "mix.0", "mix.1",
334d69a2 1632 "dvc.0", "dvc.1",
7df2fd57 1633 "clk_a", "clk_b", "clk_c", "clk_i";
6507c4ef 1634 power-domains = <&cpg_clocks>;
7df2fd57
KM		 1635
1636 status = "disabled";
1637
334d69a2 1638 rcar_sound,dvc {
118a5093
KM		 1639 dvc0: dvc@0 {
1640 dmas = <&audma0 0xbc>;
1641 dma-names = "tx";
1642 };
1643 dvc1: dvc@1 {
1644 dmas = <&audma0 0xbe>;
1645 dma-names = "tx";
1646 };
334d69a2
KM		 1647 };
1648
fc67bf42
KM		 1649 rcar_sound,mix {
1650 mix0: mix@0 { };
1651 mix1: mix@1 { };
1652 };
1653
a7163784
KM		 1654 rcar_sound,ctu {
1655 ctu00: ctu@0 { };
1656 ctu01: ctu@1 { };
1657 ctu02: ctu@2 { };
1658 ctu03: ctu@3 { };
1659 ctu10: ctu@4 { };
1660 ctu11: ctu@5 { };
1661 ctu12: ctu@6 { };
1662 ctu13: ctu@7 { };
1663 };
1664
7df2fd57 1665 rcar_sound,src {
118a5093
KM		 1666 src0: src@0 {
1667 interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
1668 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1669 dma-names = "rx", "tx";
1670 };
1671 src1: src@1 {
1672 interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
1673 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1674 dma-names = "rx", "tx";
1675 };
1676 src2: src@2 {
1677 interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
1678 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1679 dma-names = "rx", "tx";
1680 };
1681 src3: src@3 {
1682 interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
1683 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1684 dma-names = "rx", "tx";
1685 };
1686 src4: src@4 {
1687 interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
1688 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1689 dma-names = "rx", "tx";
1690 };
1691 src5: src@5 {
1692 interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
1693 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1694 dma-names = "rx", "tx";
1695 };
1696 src6: src@6 {
1697 interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
1698 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1699 dma-names = "rx", "tx";
1700 };
1701 src7: src@7 {
1702 interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
1703 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1704 dma-names = "rx", "tx";
1705 };
1706 src8: src@8 {
1707 interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
1708 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1709 dma-names = "rx", "tx";
1710 };
1711 src9: src@9 {
1712 interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
1713 dmas = <&audma0 0x97>, <&audma1 0xba>;
1714 dma-names = "rx", "tx";
1715 };
7df2fd57
KM		 1716 };
1717
1718 rcar_sound,ssi {
118a5093
KM		 1719 ssi0: ssi@0 {
1720 interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
1721 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1722 dma-names = "rx", "tx", "rxu", "txu";
1723 };
1724 ssi1: ssi@1 {
1725 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
1726 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1727 dma-names = "rx", "tx", "rxu", "txu";
1728 };
1729 ssi2: ssi@2 {
1730 interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
1731 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1732 dma-names = "rx", "tx", "rxu", "txu";
1733 };
1734 ssi3: ssi@3 {
1735 interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
1736 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1737 dma-names = "rx", "tx", "rxu", "txu";
1738 };
1739 ssi4: ssi@4 {
1740 interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
1741 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1742 dma-names = "rx", "tx", "rxu", "txu";
1743 };
1744 ssi5: ssi@5 {
1745 interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
1746 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1747 dma-names = "rx", "tx", "rxu", "txu";
1748 };
1749 ssi6: ssi@6 {
1750 interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
1751 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1752 dma-names = "rx", "tx", "rxu", "txu";
1753 };
1754 ssi7: ssi@7 {
1755 interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
1756 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1757 dma-names = "rx", "tx", "rxu", "txu";
1758 };
1759 ssi8: ssi@8 {
1760 interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
1761 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1762 dma-names = "rx", "tx", "rxu", "txu";
1763 };
1764 ssi9: ssi@9 {
1765 interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
1766 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1767 dma-names = "rx", "tx", "rxu", "txu";
1768 };
7df2fd57
KM		 1769 };
1770 };
70496727
LP		 1771
1772 ipmmu_sy0: mmu@e6280000 {
c8d6686e 1773 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727
LP		 1774 reg = <0 0xe6280000 0 0x1000>;
1775 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1776 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1777 #iommu-cells = <1>;
1778 status = "disabled";
1779 };
1780
1781 ipmmu_sy1: mmu@e6290000 {
c8d6686e 1782 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727
LP		 1783 reg = <0 0xe6290000 0 0x1000>;
1784 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1785 #iommu-cells = <1>;
1786 status = "disabled";
1787 };
1788
1789 ipmmu_ds: mmu@e6740000 {
c8d6686e 1790 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727
LP		 1791 reg = <0 0xe6740000 0 0x1000>;
1792 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1793 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1794 #iommu-cells = <1>;
1795 status = "disabled";
1796 };
1797
1798 ipmmu_mp: mmu@ec680000 {
c8d6686e 1799 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727
LP		 1800 reg = <0 0xec680000 0 0x1000>;
1801 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1802 #iommu-cells = <1>;
1803 status = "disabled";
1804 };
1805
1806 ipmmu_mx: mmu@fe951000 {
c8d6686e 1807 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727
LP		 1808 reg = <0 0xfe951000 0 0x1000>;
1809 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1810 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1811 #iommu-cells = <1>;
1812 status = "disabled";
1813 };
1814
1815 ipmmu_rt: mmu@ffc80000 {
c8d6686e 1816 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727
LP		 1817 reg = <0 0xffc80000 0 0x1000>;
1818 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1819 #iommu-cells = <1>;
1820 status = "disabled";
1821 };
0468b2d6 1822};
Linux kernel - Deliverables
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