Commit | Line | Data |
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0468b2d6 MD |
1 | /* |
2 | * Device Tree Source for the r8a7790 SoC | |
3 | * | |
b621f6d4 | 4 | * Copyright (C) 2015 Renesas Electronics Corporation |
d8913c67 SS |
5 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
6 | * Copyright (C) 2014 Cogent Embedded Inc. | |
0468b2d6 MD |
7 | * |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
11 | */ | |
12 | ||
22a1f595 | 13 | #include <dt-bindings/clock/r8a7790-clock.h> |
5f75e73c LP |
14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
15 | #include <dt-bindings/interrupt-controller/irq.h> | |
16 | ||
0468b2d6 MD |
17 | / { |
18 | compatible = "renesas,r8a7790"; | |
19 | interrupt-parent = <&gic>; | |
8585deb1 TY |
20 | #address-cells = <2>; |
21 | #size-cells = <2>; | |
0468b2d6 | 22 | |
6b1d7c68 WS |
23 | aliases { |
24 | i2c0 = &i2c0; | |
25 | i2c1 = &i2c1; | |
26 | i2c2 = &i2c2; | |
27 | i2c3 = &i2c3; | |
05f39916 WS |
28 | i2c4 = &iic0; |
29 | i2c5 = &iic1; | |
30 | i2c6 = &iic2; | |
31 | i2c7 = &iic3; | |
fad6d45c | 32 | spi0 = &qspi; |
ae8a6146 GU |
33 | spi1 = &msiof0; |
34 | spi2 = &msiof1; | |
35 | spi3 = &msiof2; | |
36 | spi4 = &msiof3; | |
9f685bfc BD |
37 | vin0 = &vin0; |
38 | vin1 = &vin1; | |
39 | vin2 = &vin2; | |
40 | vin3 = &vin3; | |
6b1d7c68 WS |
41 | }; |
42 | ||
0468b2d6 MD |
43 | cpus { |
44 | #address-cells = <1>; | |
45 | #size-cells = <0>; | |
46 | ||
47 | cpu0: cpu@0 { | |
48 | device_type = "cpu"; | |
49 | compatible = "arm,cortex-a15"; | |
50 | reg = <0>; | |
51 | clock-frequency = <1300000000>; | |
b989e138 BC |
52 | voltage-tolerance = <1>; /* 1% */ |
53 | clocks = <&cpg_clocks R8A7790_CLK_Z>; | |
54 | clock-latency = <300000>; /* 300 us */ | |
55 | ||
56 | /* kHz - uV - OPPs unknown yet */ | |
57 | operating-points = <1400000 1000000>, | |
58 | <1225000 1000000>, | |
59 | <1050000 1000000>, | |
60 | < 875000 1000000>, | |
61 | < 700000 1000000>, | |
62 | < 350000 1000000>; | |
0468b2d6 | 63 | }; |
c1f95979 MD |
64 | |
65 | cpu1: cpu@1 { | |
66 | device_type = "cpu"; | |
67 | compatible = "arm,cortex-a15"; | |
68 | reg = <1>; | |
69 | clock-frequency = <1300000000>; | |
70 | }; | |
71 | ||
72 | cpu2: cpu@2 { | |
73 | device_type = "cpu"; | |
74 | compatible = "arm,cortex-a15"; | |
75 | reg = <2>; | |
76 | clock-frequency = <1300000000>; | |
77 | }; | |
78 | ||
79 | cpu3: cpu@3 { | |
80 | device_type = "cpu"; | |
81 | compatible = "arm,cortex-a15"; | |
82 | reg = <3>; | |
83 | clock-frequency = <1300000000>; | |
84 | }; | |
2007e74c MD |
85 | |
86 | cpu4: cpu@4 { | |
87 | device_type = "cpu"; | |
88 | compatible = "arm,cortex-a7"; | |
89 | reg = <0x100>; | |
90 | clock-frequency = <780000000>; | |
91 | }; | |
92 | ||
93 | cpu5: cpu@5 { | |
94 | device_type = "cpu"; | |
95 | compatible = "arm,cortex-a7"; | |
96 | reg = <0x101>; | |
97 | clock-frequency = <780000000>; | |
98 | }; | |
99 | ||
100 | cpu6: cpu@6 { | |
101 | device_type = "cpu"; | |
102 | compatible = "arm,cortex-a7"; | |
103 | reg = <0x102>; | |
104 | clock-frequency = <780000000>; | |
105 | }; | |
106 | ||
107 | cpu7: cpu@7 { | |
108 | device_type = "cpu"; | |
109 | compatible = "arm,cortex-a7"; | |
110 | reg = <0x103>; | |
111 | clock-frequency = <780000000>; | |
112 | }; | |
0468b2d6 MD |
113 | }; |
114 | ||
115 | gic: interrupt-controller@f1001000 { | |
e715e9c5 | 116 | compatible = "arm,gic-400"; |
0468b2d6 MD |
117 | #interrupt-cells = <3>; |
118 | #address-cells = <0>; | |
119 | interrupt-controller; | |
8585deb1 TY |
120 | reg = <0 0xf1001000 0 0x1000>, |
121 | <0 0xf1002000 0 0x1000>, | |
122 | <0 0xf1004000 0 0x2000>, | |
123 | <0 0xf1006000 0 0x2000>; | |
5f75e73c | 124 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
0468b2d6 MD |
125 | }; |
126 | ||
23de2278 | 127 | gpio0: gpio@e6050000 { |
f98e10c8 | 128 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
23de2278 | 129 | reg = <0 0xe6050000 0 0x50>; |
5f75e73c | 130 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; |
f98e10c8 LP |
131 | #gpio-cells = <2>; |
132 | gpio-controller; | |
133 | gpio-ranges = <&pfc 0 0 32>; | |
134 | #interrupt-cells = <2>; | |
135 | interrupt-controller; | |
81f6883f | 136 | clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; |
484adb00 | 137 | power-domains = <&cpg_clocks>; |
f98e10c8 LP |
138 | }; |
139 | ||
23de2278 | 140 | gpio1: gpio@e6051000 { |
f98e10c8 | 141 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
23de2278 | 142 | reg = <0 0xe6051000 0 0x50>; |
5f75e73c | 143 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
f98e10c8 LP |
144 | #gpio-cells = <2>; |
145 | gpio-controller; | |
146 | gpio-ranges = <&pfc 0 32 32>; | |
147 | #interrupt-cells = <2>; | |
148 | interrupt-controller; | |
81f6883f | 149 | clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; |
484adb00 | 150 | power-domains = <&cpg_clocks>; |
f98e10c8 LP |
151 | }; |
152 | ||
23de2278 | 153 | gpio2: gpio@e6052000 { |
f98e10c8 | 154 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
23de2278 | 155 | reg = <0 0xe6052000 0 0x50>; |
5f75e73c | 156 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
f98e10c8 LP |
157 | #gpio-cells = <2>; |
158 | gpio-controller; | |
159 | gpio-ranges = <&pfc 0 64 32>; | |
160 | #interrupt-cells = <2>; | |
161 | interrupt-controller; | |
81f6883f | 162 | clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; |
484adb00 | 163 | power-domains = <&cpg_clocks>; |
f98e10c8 LP |
164 | }; |
165 | ||
23de2278 | 166 | gpio3: gpio@e6053000 { |
f98e10c8 | 167 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
23de2278 | 168 | reg = <0 0xe6053000 0 0x50>; |
5f75e73c | 169 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
f98e10c8 LP |
170 | #gpio-cells = <2>; |
171 | gpio-controller; | |
172 | gpio-ranges = <&pfc 0 96 32>; | |
173 | #interrupt-cells = <2>; | |
174 | interrupt-controller; | |
81f6883f | 175 | clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; |
484adb00 | 176 | power-domains = <&cpg_clocks>; |
f98e10c8 LP |
177 | }; |
178 | ||
23de2278 | 179 | gpio4: gpio@e6054000 { |
f98e10c8 | 180 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
23de2278 | 181 | reg = <0 0xe6054000 0 0x50>; |
5f75e73c | 182 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
f98e10c8 LP |
183 | #gpio-cells = <2>; |
184 | gpio-controller; | |
185 | gpio-ranges = <&pfc 0 128 32>; | |
186 | #interrupt-cells = <2>; | |
187 | interrupt-controller; | |
81f6883f | 188 | clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; |
484adb00 | 189 | power-domains = <&cpg_clocks>; |
f98e10c8 LP |
190 | }; |
191 | ||
23de2278 | 192 | gpio5: gpio@e6055000 { |
f98e10c8 | 193 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
23de2278 | 194 | reg = <0 0xe6055000 0 0x50>; |
5f75e73c | 195 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
f98e10c8 LP |
196 | #gpio-cells = <2>; |
197 | gpio-controller; | |
198 | gpio-ranges = <&pfc 0 160 32>; | |
199 | #interrupt-cells = <2>; | |
200 | interrupt-controller; | |
81f6883f | 201 | clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; |
484adb00 | 202 | power-domains = <&cpg_clocks>; |
f98e10c8 LP |
203 | }; |
204 | ||
03e2f56b MD |
205 | thermal@e61f0000 { |
206 | compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; | |
207 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; | |
03e2f56b | 208 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
d3a439db | 209 | clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; |
484adb00 | 210 | power-domains = <&cpg_clocks>; |
03e2f56b MD |
211 | }; |
212 | ||
0468b2d6 MD |
213 | timer { |
214 | compatible = "arm,armv7-timer"; | |
5f75e73c LP |
215 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
216 | <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
217 | <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
218 | <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
0468b2d6 | 219 | }; |
8f5ec0a5 | 220 | |
39cf6d73 | 221 | cmt0: timer@ffca0000 { |
37757030 | 222 | compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; |
39cf6d73 LP |
223 | reg = <0 0xffca0000 0 0x1004>; |
224 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, | |
225 | <0 143 IRQ_TYPE_LEVEL_HIGH>; | |
226 | clocks = <&mstp1_clks R8A7790_CLK_CMT0>; | |
227 | clock-names = "fck"; | |
484adb00 | 228 | power-domains = <&cpg_clocks>; |
39cf6d73 LP |
229 | |
230 | renesas,channels-mask = <0x60>; | |
231 | ||
232 | status = "disabled"; | |
233 | }; | |
234 | ||
235 | cmt1: timer@e6130000 { | |
37757030 | 236 | compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; |
39cf6d73 LP |
237 | reg = <0 0xe6130000 0 0x1004>; |
238 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, | |
239 | <0 121 IRQ_TYPE_LEVEL_HIGH>, | |
240 | <0 122 IRQ_TYPE_LEVEL_HIGH>, | |
241 | <0 123 IRQ_TYPE_LEVEL_HIGH>, | |
242 | <0 124 IRQ_TYPE_LEVEL_HIGH>, | |
243 | <0 125 IRQ_TYPE_LEVEL_HIGH>, | |
244 | <0 126 IRQ_TYPE_LEVEL_HIGH>, | |
245 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
246 | clocks = <&mstp3_clks R8A7790_CLK_CMT1>; | |
247 | clock-names = "fck"; | |
484adb00 | 248 | power-domains = <&cpg_clocks>; |
39cf6d73 LP |
249 | |
250 | renesas,channels-mask = <0xff>; | |
251 | ||
252 | status = "disabled"; | |
253 | }; | |
254 | ||
8f5ec0a5 | 255 | irqc0: interrupt-controller@e61c0000 { |
220fc352 | 256 | compatible = "renesas,irqc-r8a7790", "renesas,irqc"; |
8f5ec0a5 MD |
257 | #interrupt-cells = <2>; |
258 | interrupt-controller; | |
8585deb1 | 259 | reg = <0 0xe61c0000 0 0x200>; |
5f75e73c LP |
260 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
261 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | |
262 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | |
263 | <0 3 IRQ_TYPE_LEVEL_HIGH>; | |
61624caf | 264 | clocks = <&mstp4_clks R8A7790_CLK_IRQC>; |
484adb00 | 265 | power-domains = <&cpg_clocks>; |
8f5ec0a5 | 266 | }; |
8c9b1aa4 | 267 | |
b9fea49c LP |
268 | dmac0: dma-controller@e6700000 { |
269 | compatible = "renesas,rcar-dmac"; | |
270 | reg = <0 0xe6700000 0 0x20000>; | |
271 | interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH | |
272 | 0 200 IRQ_TYPE_LEVEL_HIGH | |
273 | 0 201 IRQ_TYPE_LEVEL_HIGH | |
274 | 0 202 IRQ_TYPE_LEVEL_HIGH | |
275 | 0 203 IRQ_TYPE_LEVEL_HIGH | |
276 | 0 204 IRQ_TYPE_LEVEL_HIGH | |
277 | 0 205 IRQ_TYPE_LEVEL_HIGH | |
278 | 0 206 IRQ_TYPE_LEVEL_HIGH | |
279 | 0 207 IRQ_TYPE_LEVEL_HIGH | |
280 | 0 208 IRQ_TYPE_LEVEL_HIGH | |
281 | 0 209 IRQ_TYPE_LEVEL_HIGH | |
282 | 0 210 IRQ_TYPE_LEVEL_HIGH | |
283 | 0 211 IRQ_TYPE_LEVEL_HIGH | |
284 | 0 212 IRQ_TYPE_LEVEL_HIGH | |
285 | 0 213 IRQ_TYPE_LEVEL_HIGH | |
286 | 0 214 IRQ_TYPE_LEVEL_HIGH>; | |
287 | interrupt-names = "error", | |
288 | "ch0", "ch1", "ch2", "ch3", | |
289 | "ch4", "ch5", "ch6", "ch7", | |
290 | "ch8", "ch9", "ch10", "ch11", | |
291 | "ch12", "ch13", "ch14"; | |
292 | clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; | |
293 | clock-names = "fck"; | |
484adb00 | 294 | power-domains = <&cpg_clocks>; |
b9fea49c LP |
295 | #dma-cells = <1>; |
296 | dma-channels = <15>; | |
297 | }; | |
298 | ||
299 | dmac1: dma-controller@e6720000 { | |
300 | compatible = "renesas,rcar-dmac"; | |
301 | reg = <0 0xe6720000 0 0x20000>; | |
302 | interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH | |
303 | 0 216 IRQ_TYPE_LEVEL_HIGH | |
304 | 0 217 IRQ_TYPE_LEVEL_HIGH | |
305 | 0 218 IRQ_TYPE_LEVEL_HIGH | |
306 | 0 219 IRQ_TYPE_LEVEL_HIGH | |
307 | 0 308 IRQ_TYPE_LEVEL_HIGH | |
308 | 0 309 IRQ_TYPE_LEVEL_HIGH | |
309 | 0 310 IRQ_TYPE_LEVEL_HIGH | |
310 | 0 311 IRQ_TYPE_LEVEL_HIGH | |
311 | 0 312 IRQ_TYPE_LEVEL_HIGH | |
312 | 0 313 IRQ_TYPE_LEVEL_HIGH | |
313 | 0 314 IRQ_TYPE_LEVEL_HIGH | |
314 | 0 315 IRQ_TYPE_LEVEL_HIGH | |
315 | 0 316 IRQ_TYPE_LEVEL_HIGH | |
316 | 0 317 IRQ_TYPE_LEVEL_HIGH | |
317 | 0 318 IRQ_TYPE_LEVEL_HIGH>; | |
318 | interrupt-names = "error", | |
319 | "ch0", "ch1", "ch2", "ch3", | |
320 | "ch4", "ch5", "ch6", "ch7", | |
321 | "ch8", "ch9", "ch10", "ch11", | |
322 | "ch12", "ch13", "ch14"; | |
323 | clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; | |
324 | clock-names = "fck"; | |
484adb00 | 325 | power-domains = <&cpg_clocks>; |
b9fea49c LP |
326 | #dma-cells = <1>; |
327 | dma-channels = <15>; | |
328 | }; | |
ba3240be KM |
329 | |
330 | audma0: dma-controller@ec700000 { | |
331 | compatible = "renesas,rcar-dmac"; | |
332 | reg = <0 0xec700000 0 0x10000>; | |
333 | interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH | |
334 | 0 320 IRQ_TYPE_LEVEL_HIGH | |
335 | 0 321 IRQ_TYPE_LEVEL_HIGH | |
336 | 0 322 IRQ_TYPE_LEVEL_HIGH | |
337 | 0 323 IRQ_TYPE_LEVEL_HIGH | |
338 | 0 324 IRQ_TYPE_LEVEL_HIGH | |
339 | 0 325 IRQ_TYPE_LEVEL_HIGH | |
340 | 0 326 IRQ_TYPE_LEVEL_HIGH | |
341 | 0 327 IRQ_TYPE_LEVEL_HIGH | |
342 | 0 328 IRQ_TYPE_LEVEL_HIGH | |
343 | 0 329 IRQ_TYPE_LEVEL_HIGH | |
344 | 0 330 IRQ_TYPE_LEVEL_HIGH | |
345 | 0 331 IRQ_TYPE_LEVEL_HIGH | |
346 | 0 332 IRQ_TYPE_LEVEL_HIGH>; | |
347 | interrupt-names = "error", | |
348 | "ch0", "ch1", "ch2", "ch3", | |
349 | "ch4", "ch5", "ch6", "ch7", | |
350 | "ch8", "ch9", "ch10", "ch11", | |
351 | "ch12"; | |
352 | clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>; | |
353 | clock-names = "fck"; | |
484adb00 | 354 | power-domains = <&cpg_clocks>; |
ba3240be KM |
355 | #dma-cells = <1>; |
356 | dma-channels = <13>; | |
357 | }; | |
358 | ||
359 | audma1: dma-controller@ec720000 { | |
360 | compatible = "renesas,rcar-dmac"; | |
361 | reg = <0 0xec720000 0 0x10000>; | |
362 | interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH | |
363 | 0 333 IRQ_TYPE_LEVEL_HIGH | |
364 | 0 334 IRQ_TYPE_LEVEL_HIGH | |
365 | 0 335 IRQ_TYPE_LEVEL_HIGH | |
366 | 0 336 IRQ_TYPE_LEVEL_HIGH | |
367 | 0 337 IRQ_TYPE_LEVEL_HIGH | |
368 | 0 338 IRQ_TYPE_LEVEL_HIGH | |
369 | 0 339 IRQ_TYPE_LEVEL_HIGH | |
370 | 0 340 IRQ_TYPE_LEVEL_HIGH | |
371 | 0 341 IRQ_TYPE_LEVEL_HIGH | |
372 | 0 342 IRQ_TYPE_LEVEL_HIGH | |
373 | 0 343 IRQ_TYPE_LEVEL_HIGH | |
374 | 0 344 IRQ_TYPE_LEVEL_HIGH | |
375 | 0 345 IRQ_TYPE_LEVEL_HIGH>; | |
376 | interrupt-names = "error", | |
377 | "ch0", "ch1", "ch2", "ch3", | |
378 | "ch4", "ch5", "ch6", "ch7", | |
379 | "ch8", "ch9", "ch10", "ch11", | |
380 | "ch12"; | |
381 | clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>; | |
382 | clock-names = "fck"; | |
484adb00 | 383 | power-domains = <&cpg_clocks>; |
ba3240be KM |
384 | #dma-cells = <1>; |
385 | dma-channels = <13>; | |
386 | }; | |
387 | ||
a3ff2090 YS |
388 | usb_dmac0: dma-controller@e65a0000 { |
389 | compatible = "renesas,usb-dmac"; | |
390 | reg = <0 0xe65a0000 0 0x100>; | |
391 | interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH | |
392 | 0 109 IRQ_TYPE_LEVEL_HIGH>; | |
393 | interrupt-names = "ch0", "ch1"; | |
394 | clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>; | |
484adb00 | 395 | power-domains = <&cpg_clocks>; |
a3ff2090 YS |
396 | #dma-cells = <1>; |
397 | dma-channels = <2>; | |
398 | }; | |
399 | ||
400 | usb_dmac1: dma-controller@e65b0000 { | |
401 | compatible = "renesas,usb-dmac"; | |
402 | reg = <0 0xe65b0000 0 0x100>; | |
403 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH | |
404 | 0 110 IRQ_TYPE_LEVEL_HIGH>; | |
405 | interrupt-names = "ch0", "ch1"; | |
406 | clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>; | |
484adb00 | 407 | power-domains = <&cpg_clocks>; |
a3ff2090 YS |
408 | #dma-cells = <1>; |
409 | dma-channels = <2>; | |
410 | }; | |
411 | ||
edd2b9f4 GL |
412 | i2c0: i2c@e6508000 { |
413 | #address-cells = <1>; | |
414 | #size-cells = <0>; | |
415 | compatible = "renesas,i2c-r8a7790"; | |
416 | reg = <0 0xe6508000 0 0x40>; | |
5f75e73c | 417 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; |
2450badf | 418 | clocks = <&mstp9_clks R8A7790_CLK_I2C0>; |
484adb00 | 419 | power-domains = <&cpg_clocks>; |
edd2b9f4 GL |
420 | status = "disabled"; |
421 | }; | |
422 | ||
423 | i2c1: i2c@e6518000 { | |
424 | #address-cells = <1>; | |
425 | #size-cells = <0>; | |
426 | compatible = "renesas,i2c-r8a7790"; | |
427 | reg = <0 0xe6518000 0 0x40>; | |
5f75e73c | 428 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; |
2450badf | 429 | clocks = <&mstp9_clks R8A7790_CLK_I2C1>; |
484adb00 | 430 | power-domains = <&cpg_clocks>; |
edd2b9f4 GL |
431 | status = "disabled"; |
432 | }; | |
433 | ||
434 | i2c2: i2c@e6530000 { | |
435 | #address-cells = <1>; | |
436 | #size-cells = <0>; | |
437 | compatible = "renesas,i2c-r8a7790"; | |
438 | reg = <0 0xe6530000 0 0x40>; | |
5f75e73c | 439 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; |
2450badf | 440 | clocks = <&mstp9_clks R8A7790_CLK_I2C2>; |
484adb00 | 441 | power-domains = <&cpg_clocks>; |
edd2b9f4 GL |
442 | status = "disabled"; |
443 | }; | |
444 | ||
445 | i2c3: i2c@e6540000 { | |
446 | #address-cells = <1>; | |
447 | #size-cells = <0>; | |
448 | compatible = "renesas,i2c-r8a7790"; | |
449 | reg = <0 0xe6540000 0 0x40>; | |
5f75e73c | 450 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; |
2450badf | 451 | clocks = <&mstp9_clks R8A7790_CLK_I2C3>; |
484adb00 | 452 | power-domains = <&cpg_clocks>; |
edd2b9f4 GL |
453 | status = "disabled"; |
454 | }; | |
455 | ||
05f39916 WS |
456 | iic0: i2c@e6500000 { |
457 | #address-cells = <1>; | |
458 | #size-cells = <0>; | |
459 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | |
460 | reg = <0 0xe6500000 0 0x425>; | |
461 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; | |
462 | clocks = <&mstp3_clks R8A7790_CLK_IIC0>; | |
0d73ca41 WS |
463 | dmas = <&dmac0 0x61>, <&dmac0 0x62>; |
464 | dma-names = "tx", "rx"; | |
484adb00 | 465 | power-domains = <&cpg_clocks>; |
05f39916 WS |
466 | status = "disabled"; |
467 | }; | |
468 | ||
469 | iic1: i2c@e6510000 { | |
470 | #address-cells = <1>; | |
471 | #size-cells = <0>; | |
472 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | |
473 | reg = <0 0xe6510000 0 0x425>; | |
474 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; | |
475 | clocks = <&mstp3_clks R8A7790_CLK_IIC1>; | |
0d73ca41 WS |
476 | dmas = <&dmac0 0x65>, <&dmac0 0x66>; |
477 | dma-names = "tx", "rx"; | |
484adb00 | 478 | power-domains = <&cpg_clocks>; |
05f39916 WS |
479 | status = "disabled"; |
480 | }; | |
481 | ||
482 | iic2: i2c@e6520000 { | |
483 | #address-cells = <1>; | |
484 | #size-cells = <0>; | |
485 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | |
486 | reg = <0 0xe6520000 0 0x425>; | |
487 | interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; | |
488 | clocks = <&mstp3_clks R8A7790_CLK_IIC2>; | |
0d73ca41 WS |
489 | dmas = <&dmac0 0x69>, <&dmac0 0x6a>; |
490 | dma-names = "tx", "rx"; | |
484adb00 | 491 | power-domains = <&cpg_clocks>; |
05f39916 WS |
492 | status = "disabled"; |
493 | }; | |
494 | ||
495 | iic3: i2c@e60b0000 { | |
496 | #address-cells = <1>; | |
497 | #size-cells = <0>; | |
498 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | |
499 | reg = <0 0xe60b0000 0 0x425>; | |
500 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; | |
501 | clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; | |
0d73ca41 WS |
502 | dmas = <&dmac0 0x77>, <&dmac0 0x78>; |
503 | dma-names = "tx", "rx"; | |
484adb00 | 504 | power-domains = <&cpg_clocks>; |
05f39916 WS |
505 | status = "disabled"; |
506 | }; | |
507 | ||
22c2b78d | 508 | mmcif0: mmc@ee200000 { |
063e8560 | 509 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
8c9b1aa4 | 510 | reg = <0 0xee200000 0 0x80>; |
5f75e73c | 511 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; |
72197ca7 | 512 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; |
108216c1 LP |
513 | dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; |
514 | dma-names = "tx", "rx"; | |
484adb00 | 515 | power-domains = <&cpg_clocks>; |
8c9b1aa4 GL |
516 | reg-io-width = <4>; |
517 | status = "disabled"; | |
96370057 | 518 | max-frequency = <97500000>; |
8c9b1aa4 GL |
519 | }; |
520 | ||
b718aa44 | 521 | mmcif1: mmc@ee220000 { |
063e8560 | 522 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
8c9b1aa4 | 523 | reg = <0 0xee220000 0 0x80>; |
5f75e73c | 524 | interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; |
72197ca7 | 525 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; |
108216c1 LP |
526 | dmas = <&dmac0 0xe1>, <&dmac0 0xe2>; |
527 | dma-names = "tx", "rx"; | |
484adb00 | 528 | power-domains = <&cpg_clocks>; |
8c9b1aa4 GL |
529 | reg-io-width = <4>; |
530 | status = "disabled"; | |
96370057 | 531 | max-frequency = <97500000>; |
8c9b1aa4 GL |
532 | }; |
533 | ||
9694c778 LP |
534 | pfc: pfc@e6060000 { |
535 | compatible = "renesas,pfc-r8a7790"; | |
536 | reg = <0 0xe6060000 0 0x250>; | |
537 | }; | |
55689bfa | 538 | |
b718aa44 | 539 | sdhi0: sd@ee100000 { |
df1d0584 | 540 | compatible = "renesas,sdhi-r8a7790"; |
66f47ed0 | 541 | reg = <0 0xee100000 0 0x328>; |
5f75e73c | 542 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
72197ca7 | 543 | clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; |
941fe36b LP |
544 | dmas = <&dmac1 0xcd>, <&dmac1 0xce>; |
545 | dma-names = "tx", "rx"; | |
484adb00 | 546 | power-domains = <&cpg_clocks>; |
8c9b1aa4 GL |
547 | status = "disabled"; |
548 | }; | |
549 | ||
b718aa44 | 550 | sdhi1: sd@ee120000 { |
df1d0584 | 551 | compatible = "renesas,sdhi-r8a7790"; |
66f47ed0 | 552 | reg = <0 0xee120000 0 0x328>; |
5f75e73c | 553 | interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; |
72197ca7 | 554 | clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; |
941fe36b LP |
555 | dmas = <&dmac1 0xc9>, <&dmac1 0xca>; |
556 | dma-names = "tx", "rx"; | |
484adb00 | 557 | power-domains = <&cpg_clocks>; |
8c9b1aa4 GL |
558 | status = "disabled"; |
559 | }; | |
560 | ||
b718aa44 | 561 | sdhi2: sd@ee140000 { |
df1d0584 | 562 | compatible = "renesas,sdhi-r8a7790"; |
8c9b1aa4 | 563 | reg = <0 0xee140000 0 0x100>; |
5f75e73c | 564 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
72197ca7 | 565 | clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; |
941fe36b LP |
566 | dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; |
567 | dma-names = "tx", "rx"; | |
484adb00 | 568 | power-domains = <&cpg_clocks>; |
8c9b1aa4 GL |
569 | status = "disabled"; |
570 | }; | |
571 | ||
b718aa44 | 572 | sdhi3: sd@ee160000 { |
df1d0584 | 573 | compatible = "renesas,sdhi-r8a7790"; |
8c9b1aa4 | 574 | reg = <0 0xee160000 0 0x100>; |
5f75e73c | 575 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; |
72197ca7 | 576 | clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; |
941fe36b LP |
577 | dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; |
578 | dma-names = "tx", "rx"; | |
484adb00 | 579 | power-domains = <&cpg_clocks>; |
8c9b1aa4 GL |
580 | status = "disabled"; |
581 | }; | |
22a1f595 | 582 | |
597af20f | 583 | scifa0: serial@e6c40000 { |
59d2b517 | 584 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
597af20f | 585 | reg = <0 0xe6c40000 0 64>; |
1f4c745b | 586 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
587 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; |
588 | clock-names = "sci_ick"; | |
acea43fc GU |
589 | dmas = <&dmac0 0x21>, <&dmac0 0x22>; |
590 | dma-names = "tx", "rx"; | |
484adb00 | 591 | power-domains = <&cpg_clocks>; |
597af20f LP |
592 | status = "disabled"; |
593 | }; | |
594 | ||
595 | scifa1: serial@e6c50000 { | |
59d2b517 | 596 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
597af20f | 597 | reg = <0 0xe6c50000 0 64>; |
1f4c745b | 598 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
599 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; |
600 | clock-names = "sci_ick"; | |
acea43fc GU |
601 | dmas = <&dmac0 0x25>, <&dmac0 0x26>; |
602 | dma-names = "tx", "rx"; | |
484adb00 | 603 | power-domains = <&cpg_clocks>; |
597af20f LP |
604 | status = "disabled"; |
605 | }; | |
606 | ||
607 | scifa2: serial@e6c60000 { | |
59d2b517 | 608 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
597af20f | 609 | reg = <0 0xe6c60000 0 64>; |
1f4c745b | 610 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
611 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; |
612 | clock-names = "sci_ick"; | |
acea43fc GU |
613 | dmas = <&dmac0 0x27>, <&dmac0 0x28>; |
614 | dma-names = "tx", "rx"; | |
484adb00 | 615 | power-domains = <&cpg_clocks>; |
597af20f LP |
616 | status = "disabled"; |
617 | }; | |
618 | ||
619 | scifb0: serial@e6c20000 { | |
59d2b517 | 620 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
597af20f | 621 | reg = <0 0xe6c20000 0 64>; |
1f4c745b | 622 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
623 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; |
624 | clock-names = "sci_ick"; | |
acea43fc GU |
625 | dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; |
626 | dma-names = "tx", "rx"; | |
484adb00 | 627 | power-domains = <&cpg_clocks>; |
597af20f LP |
628 | status = "disabled"; |
629 | }; | |
630 | ||
631 | scifb1: serial@e6c30000 { | |
59d2b517 | 632 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
597af20f | 633 | reg = <0 0xe6c30000 0 64>; |
1f4c745b | 634 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
635 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; |
636 | clock-names = "sci_ick"; | |
acea43fc GU |
637 | dmas = <&dmac0 0x19>, <&dmac0 0x1a>; |
638 | dma-names = "tx", "rx"; | |
484adb00 | 639 | power-domains = <&cpg_clocks>; |
597af20f LP |
640 | status = "disabled"; |
641 | }; | |
642 | ||
643 | scifb2: serial@e6ce0000 { | |
59d2b517 | 644 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
597af20f | 645 | reg = <0 0xe6ce0000 0 64>; |
1f4c745b | 646 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
647 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; |
648 | clock-names = "sci_ick"; | |
acea43fc GU |
649 | dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; |
650 | dma-names = "tx", "rx"; | |
484adb00 | 651 | power-domains = <&cpg_clocks>; |
597af20f LP |
652 | status = "disabled"; |
653 | }; | |
654 | ||
655 | scif0: serial@e6e60000 { | |
59d2b517 | 656 | compatible = "renesas,scif-r8a7790", "renesas,scif"; |
597af20f | 657 | reg = <0 0xe6e60000 0 64>; |
1f4c745b | 658 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
659 | clocks = <&mstp7_clks R8A7790_CLK_SCIF0>; |
660 | clock-names = "sci_ick"; | |
acea43fc GU |
661 | dmas = <&dmac0 0x29>, <&dmac0 0x2a>; |
662 | dma-names = "tx", "rx"; | |
484adb00 | 663 | power-domains = <&cpg_clocks>; |
597af20f LP |
664 | status = "disabled"; |
665 | }; | |
666 | ||
667 | scif1: serial@e6e68000 { | |
59d2b517 | 668 | compatible = "renesas,scif-r8a7790", "renesas,scif"; |
597af20f | 669 | reg = <0 0xe6e68000 0 64>; |
1f4c745b | 670 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
671 | clocks = <&mstp7_clks R8A7790_CLK_SCIF1>; |
672 | clock-names = "sci_ick"; | |
acea43fc GU |
673 | dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; |
674 | dma-names = "tx", "rx"; | |
484adb00 | 675 | power-domains = <&cpg_clocks>; |
597af20f LP |
676 | status = "disabled"; |
677 | }; | |
678 | ||
679 | hscif0: serial@e62c0000 { | |
59d2b517 | 680 | compatible = "renesas,hscif-r8a7790", "renesas,hscif"; |
597af20f | 681 | reg = <0 0xe62c0000 0 96>; |
1f4c745b | 682 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
683 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>; |
684 | clock-names = "sci_ick"; | |
acea43fc GU |
685 | dmas = <&dmac0 0x39>, <&dmac0 0x3a>; |
686 | dma-names = "tx", "rx"; | |
484adb00 | 687 | power-domains = <&cpg_clocks>; |
597af20f LP |
688 | status = "disabled"; |
689 | }; | |
690 | ||
691 | hscif1: serial@e62c8000 { | |
59d2b517 | 692 | compatible = "renesas,hscif-r8a7790", "renesas,hscif"; |
597af20f | 693 | reg = <0 0xe62c8000 0 96>; |
1f4c745b | 694 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; |
597af20f LP |
695 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>; |
696 | clock-names = "sci_ick"; | |
acea43fc GU |
697 | dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; |
698 | dma-names = "tx", "rx"; | |
484adb00 | 699 | power-domains = <&cpg_clocks>; |
597af20f LP |
700 | status = "disabled"; |
701 | }; | |
702 | ||
d8913c67 SS |
703 | ether: ethernet@ee700000 { |
704 | compatible = "renesas,ether-r8a7790"; | |
705 | reg = <0 0xee700000 0 0x400>; | |
706 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; | |
707 | clocks = <&mstp8_clks R8A7790_CLK_ETHER>; | |
484adb00 | 708 | power-domains = <&cpg_clocks>; |
d8913c67 SS |
709 | phy-mode = "rmii"; |
710 | #address-cells = <1>; | |
711 | #size-cells = <0>; | |
712 | status = "disabled"; | |
713 | }; | |
714 | ||
f25d6b97 SS |
715 | avb: ethernet@e6800000 { |
716 | compatible = "renesas,etheravb-r8a7790"; | |
717 | reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; | |
718 | interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; | |
719 | clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>; | |
484adb00 | 720 | power-domains = <&cpg_clocks>; |
f25d6b97 SS |
721 | #address-cells = <1>; |
722 | #size-cells = <0>; | |
723 | status = "disabled"; | |
724 | }; | |
725 | ||
cde630f7 VB |
726 | sata0: sata@ee300000 { |
727 | compatible = "renesas,sata-r8a7790"; | |
728 | reg = <0 0xee300000 0 0x2000>; | |
cde630f7 VB |
729 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; |
730 | clocks = <&mstp8_clks R8A7790_CLK_SATA0>; | |
484adb00 | 731 | power-domains = <&cpg_clocks>; |
cde630f7 VB |
732 | status = "disabled"; |
733 | }; | |
734 | ||
735 | sata1: sata@ee500000 { | |
736 | compatible = "renesas,sata-r8a7790"; | |
737 | reg = <0 0xee500000 0 0x2000>; | |
cde630f7 VB |
738 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
739 | clocks = <&mstp8_clks R8A7790_CLK_SATA1>; | |
484adb00 | 740 | power-domains = <&cpg_clocks>; |
cde630f7 VB |
741 | status = "disabled"; |
742 | }; | |
743 | ||
ae0a555b YS |
744 | hsusb: usb@e6590000 { |
745 | compatible = "renesas,usbhs-r8a7790"; | |
746 | reg = <0 0xe6590000 0 0x100>; | |
747 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; | |
748 | clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; | |
e8295dc3 YS |
749 | dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, |
750 | <&usb_dmac1 0>, <&usb_dmac1 1>; | |
751 | dma-names = "ch0", "ch1", "ch2", "ch3"; | |
484adb00 GU |
752 | power-domains = <&cpg_clocks>; |
753 | renesas,buswait = <4>; | |
754 | phys = <&usb0 1>; | |
755 | phy-names = "usb"; | |
ae0a555b YS |
756 | status = "disabled"; |
757 | }; | |
758 | ||
e089f657 SS |
759 | usbphy: usb-phy@e6590100 { |
760 | compatible = "renesas,usb-phy-r8a7790"; | |
761 | reg = <0 0xe6590100 0 0x100>; | |
762 | #address-cells = <1>; | |
763 | #size-cells = <0>; | |
764 | clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; | |
765 | clock-names = "usbhs"; | |
484adb00 | 766 | power-domains = <&cpg_clocks>; |
e089f657 SS |
767 | status = "disabled"; |
768 | ||
769 | usb0: usb-channel@0 { | |
770 | reg = <0>; | |
771 | #phy-cells = <1>; | |
772 | }; | |
773 | usb2: usb-channel@2 { | |
774 | reg = <2>; | |
775 | #phy-cells = <1>; | |
776 | }; | |
777 | }; | |
778 | ||
9f685bfc BD |
779 | vin0: video@e6ef0000 { |
780 | compatible = "renesas,vin-r8a7790"; | |
9f685bfc BD |
781 | reg = <0 0xe6ef0000 0 0x1000>; |
782 | interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; | |
484adb00 GU |
783 | clocks = <&mstp8_clks R8A7790_CLK_VIN0>; |
784 | power-domains = <&cpg_clocks>; | |
9f685bfc BD |
785 | status = "disabled"; |
786 | }; | |
787 | ||
788 | vin1: video@e6ef1000 { | |
789 | compatible = "renesas,vin-r8a7790"; | |
9f685bfc BD |
790 | reg = <0 0xe6ef1000 0 0x1000>; |
791 | interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; | |
484adb00 GU |
792 | clocks = <&mstp8_clks R8A7790_CLK_VIN1>; |
793 | power-domains = <&cpg_clocks>; | |
9f685bfc BD |
794 | status = "disabled"; |
795 | }; | |
796 | ||
797 | vin2: video@e6ef2000 { | |
798 | compatible = "renesas,vin-r8a7790"; | |
9f685bfc BD |
799 | reg = <0 0xe6ef2000 0 0x1000>; |
800 | interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; | |
484adb00 GU |
801 | clocks = <&mstp8_clks R8A7790_CLK_VIN2>; |
802 | power-domains = <&cpg_clocks>; | |
9f685bfc BD |
803 | status = "disabled"; |
804 | }; | |
805 | ||
806 | vin3: video@e6ef3000 { | |
807 | compatible = "renesas,vin-r8a7790"; | |
9f685bfc BD |
808 | reg = <0 0xe6ef3000 0 0x1000>; |
809 | interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>; | |
484adb00 GU |
810 | clocks = <&mstp8_clks R8A7790_CLK_VIN3>; |
811 | power-domains = <&cpg_clocks>; | |
9f685bfc BD |
812 | status = "disabled"; |
813 | }; | |
814 | ||
3ac6a83c LP |
815 | vsp1@fe920000 { |
816 | compatible = "renesas,vsp1"; | |
817 | reg = <0 0xfe920000 0 0x8000>; | |
818 | interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>; | |
819 | clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; | |
484adb00 | 820 | power-domains = <&cpg_clocks>; |
3ac6a83c LP |
821 | |
822 | renesas,has-sru; | |
823 | renesas,#rpf = <5>; | |
824 | renesas,#uds = <1>; | |
825 | renesas,#wpf = <4>; | |
826 | }; | |
827 | ||
828 | vsp1@fe928000 { | |
829 | compatible = "renesas,vsp1"; | |
830 | reg = <0 0xfe928000 0 0x8000>; | |
831 | interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; | |
832 | clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; | |
484adb00 | 833 | power-domains = <&cpg_clocks>; |
3ac6a83c LP |
834 | |
835 | renesas,has-lut; | |
836 | renesas,has-sru; | |
837 | renesas,#rpf = <5>; | |
838 | renesas,#uds = <3>; | |
839 | renesas,#wpf = <4>; | |
840 | }; | |
841 | ||
842 | vsp1@fe930000 { | |
843 | compatible = "renesas,vsp1"; | |
844 | reg = <0 0xfe930000 0 0x8000>; | |
845 | interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; | |
846 | clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; | |
484adb00 | 847 | power-domains = <&cpg_clocks>; |
3ac6a83c LP |
848 | |
849 | renesas,has-lif; | |
850 | renesas,has-lut; | |
851 | renesas,#rpf = <4>; | |
852 | renesas,#uds = <1>; | |
853 | renesas,#wpf = <4>; | |
854 | }; | |
855 | ||
856 | vsp1@fe938000 { | |
857 | compatible = "renesas,vsp1"; | |
858 | reg = <0 0xfe938000 0 0x8000>; | |
859 | interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; | |
860 | clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; | |
484adb00 | 861 | power-domains = <&cpg_clocks>; |
3ac6a83c LP |
862 | |
863 | renesas,has-lif; | |
864 | renesas,has-lut; | |
865 | renesas,#rpf = <4>; | |
866 | renesas,#uds = <1>; | |
867 | renesas,#wpf = <4>; | |
868 | }; | |
869 | ||
870 | du: display@feb00000 { | |
871 | compatible = "renesas,du-r8a7790"; | |
872 | reg = <0 0xfeb00000 0 0x70000>, | |
873 | <0 0xfeb90000 0 0x1c>, | |
874 | <0 0xfeb94000 0 0x1c>; | |
875 | reg-names = "du", "lvds.0", "lvds.1"; | |
876 | interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, | |
877 | <0 268 IRQ_TYPE_LEVEL_HIGH>, | |
878 | <0 269 IRQ_TYPE_LEVEL_HIGH>; | |
879 | clocks = <&mstp7_clks R8A7790_CLK_DU0>, | |
880 | <&mstp7_clks R8A7790_CLK_DU1>, | |
881 | <&mstp7_clks R8A7790_CLK_DU2>, | |
882 | <&mstp7_clks R8A7790_CLK_LVDS0>, | |
883 | <&mstp7_clks R8A7790_CLK_LVDS1>; | |
884 | clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1"; | |
885 | status = "disabled"; | |
886 | ||
887 | ports { | |
888 | #address-cells = <1>; | |
889 | #size-cells = <0>; | |
890 | ||
891 | port@0 { | |
892 | reg = <0>; | |
893 | du_out_rgb: endpoint { | |
894 | }; | |
895 | }; | |
896 | port@1 { | |
897 | reg = <1>; | |
898 | du_out_lvds0: endpoint { | |
899 | }; | |
900 | }; | |
901 | port@2 { | |
902 | reg = <2>; | |
903 | du_out_lvds1: endpoint { | |
904 | }; | |
905 | }; | |
906 | }; | |
907 | }; | |
908 | ||
6a7742b4 SS |
909 | can0: can@e6e80000 { |
910 | compatible = "renesas,can-r8a7790"; | |
911 | reg = <0 0xe6e80000 0 0x1000>; | |
912 | interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; | |
913 | clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, | |
914 | <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; | |
915 | clock-names = "clkp1", "clkp2", "can_clk"; | |
484adb00 | 916 | power-domains = <&cpg_clocks>; |
6a7742b4 SS |
917 | status = "disabled"; |
918 | }; | |
919 | ||
920 | can1: can@e6e88000 { | |
921 | compatible = "renesas,can-r8a7790"; | |
922 | reg = <0 0xe6e88000 0 0x1000>; | |
923 | interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>; | |
924 | clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, | |
925 | <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; | |
926 | clock-names = "clkp1", "clkp2", "can_clk"; | |
484adb00 | 927 | power-domains = <&cpg_clocks>; |
6a7742b4 SS |
928 | status = "disabled"; |
929 | }; | |
930 | ||
fb847575 MU |
931 | jpu: jpeg-codec@fe980000 { |
932 | compatible = "renesas,jpu-r8a7790"; | |
933 | reg = <0 0xfe980000 0 0x10300>; | |
934 | interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>; | |
935 | clocks = <&mstp1_clks R8A7790_CLK_JPU>; | |
484adb00 | 936 | power-domains = <&cpg_clocks>; |
fb847575 MU |
937 | }; |
938 | ||
22a1f595 LP |
939 | clocks { |
940 | #address-cells = <2>; | |
941 | #size-cells = <2>; | |
942 | ranges; | |
943 | ||
944 | /* External root clock */ | |
945 | extal_clk: extal_clk { | |
946 | compatible = "fixed-clock"; | |
947 | #clock-cells = <0>; | |
948 | /* This value must be overriden by the board. */ | |
949 | clock-frequency = <0>; | |
950 | clock-output-names = "extal"; | |
951 | }; | |
952 | ||
51d17918 PE |
953 | /* External PCIe clock - can be overridden by the board */ |
954 | pcie_bus_clk: pcie_bus_clk { | |
955 | compatible = "fixed-clock"; | |
956 | #clock-cells = <0>; | |
957 | clock-frequency = <100000000>; | |
958 | clock-output-names = "pcie_bus"; | |
959 | status = "disabled"; | |
960 | }; | |
961 | ||
c7c2ec3a KM |
962 | /* |
963 | * The external audio clocks are configured as 0 Hz fixed frequency clocks by | |
964 | * default. Boards that provide audio clocks should override them. | |
965 | */ | |
966 | audio_clk_a: audio_clk_a { | |
967 | compatible = "fixed-clock"; | |
968 | #clock-cells = <0>; | |
969 | clock-frequency = <0>; | |
970 | clock-output-names = "audio_clk_a"; | |
971 | }; | |
972 | audio_clk_b: audio_clk_b { | |
973 | compatible = "fixed-clock"; | |
974 | #clock-cells = <0>; | |
975 | clock-frequency = <0>; | |
976 | clock-output-names = "audio_clk_b"; | |
977 | }; | |
978 | audio_clk_c: audio_clk_c { | |
979 | compatible = "fixed-clock"; | |
980 | #clock-cells = <0>; | |
981 | clock-frequency = <0>; | |
982 | clock-output-names = "audio_clk_c"; | |
983 | }; | |
984 | ||
41650f40 SS |
985 | /* External USB clock - can be overridden by the board */ |
986 | usb_extal_clk: usb_extal_clk { | |
987 | compatible = "fixed-clock"; | |
988 | #clock-cells = <0>; | |
989 | clock-frequency = <48000000>; | |
990 | clock-output-names = "usb_extal"; | |
991 | }; | |
992 | ||
993 | /* External CAN clock */ | |
994 | can_clk: can_clk { | |
995 | compatible = "fixed-clock"; | |
996 | #clock-cells = <0>; | |
997 | /* This value must be overridden by the board. */ | |
998 | clock-frequency = <0>; | |
999 | clock-output-names = "can_clk"; | |
1000 | status = "disabled"; | |
1001 | }; | |
1002 | ||
22a1f595 LP |
1003 | /* Special CPG clocks */ |
1004 | cpg_clocks: cpg_clocks@e6150000 { | |
1005 | compatible = "renesas,r8a7790-cpg-clocks", | |
1006 | "renesas,rcar-gen2-cpg-clocks"; | |
1007 | reg = <0 0xe6150000 0 0x1000>; | |
41650f40 | 1008 | clocks = <&extal_clk &usb_extal_clk>; |
22a1f595 LP |
1009 | #clock-cells = <1>; |
1010 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
1011 | "lb", "qspi", "sdh", "sd0", "sd1", | |
3453ca9e | 1012 | "z", "rcan", "adsp"; |
484adb00 | 1013 | #power-domain-cells = <0>; |
22a1f595 LP |
1014 | }; |
1015 | ||
1016 | /* Variable factor clocks */ | |
1017 | sd2_clk: sd2_clk@e6150078 { | |
1018 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
1019 | reg = <0 0xe6150078 0 4>; | |
1020 | clocks = <&pll1_div2_clk>; | |
1021 | #clock-cells = <0>; | |
1022 | clock-output-names = "sd2"; | |
1023 | }; | |
edd7b938 | 1024 | sd3_clk: sd3_clk@e615026c { |
22a1f595 | 1025 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
edd7b938 | 1026 | reg = <0 0xe615026c 0 4>; |
22a1f595 LP |
1027 | clocks = <&pll1_div2_clk>; |
1028 | #clock-cells = <0>; | |
1029 | clock-output-names = "sd3"; | |
1030 | }; | |
1031 | mmc0_clk: mmc0_clk@e6150240 { | |
1032 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
1033 | reg = <0 0xe6150240 0 4>; | |
1034 | clocks = <&pll1_div2_clk>; | |
1035 | #clock-cells = <0>; | |
1036 | clock-output-names = "mmc0"; | |
1037 | }; | |
1038 | mmc1_clk: mmc1_clk@e6150244 { | |
1039 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
1040 | reg = <0 0xe6150244 0 4>; | |
1041 | clocks = <&pll1_div2_clk>; | |
1042 | #clock-cells = <0>; | |
1043 | clock-output-names = "mmc1"; | |
1044 | }; | |
1045 | ssp_clk: ssp_clk@e6150248 { | |
1046 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
1047 | reg = <0 0xe6150248 0 4>; | |
1048 | clocks = <&pll1_div2_clk>; | |
1049 | #clock-cells = <0>; | |
1050 | clock-output-names = "ssp"; | |
1051 | }; | |
1052 | ssprs_clk: ssprs_clk@e615024c { | |
1053 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
1054 | reg = <0 0xe615024c 0 4>; | |
1055 | clocks = <&pll1_div2_clk>; | |
1056 | #clock-cells = <0>; | |
1057 | clock-output-names = "ssprs"; | |
1058 | }; | |
1059 | ||
1060 | /* Fixed factor clocks */ | |
1061 | pll1_div2_clk: pll1_div2_clk { | |
1062 | compatible = "fixed-factor-clock"; | |
1063 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
1064 | #clock-cells = <0>; | |
1065 | clock-div = <2>; | |
1066 | clock-mult = <1>; | |
1067 | clock-output-names = "pll1_div2"; | |
1068 | }; | |
1069 | z2_clk: z2_clk { | |
1070 | compatible = "fixed-factor-clock"; | |
1071 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
1072 | #clock-cells = <0>; | |
1073 | clock-div = <2>; | |
1074 | clock-mult = <1>; | |
1075 | clock-output-names = "z2"; | |
1076 | }; | |
1077 | zg_clk: zg_clk { | |
1078 | compatible = "fixed-factor-clock"; | |
1079 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
1080 | #clock-cells = <0>; | |
1081 | clock-div = <3>; | |
1082 | clock-mult = <1>; | |
1083 | clock-output-names = "zg"; | |
1084 | }; | |
1085 | zx_clk: zx_clk { | |
1086 | compatible = "fixed-factor-clock"; | |
1087 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
1088 | #clock-cells = <0>; | |
1089 | clock-div = <3>; | |
1090 | clock-mult = <1>; | |
1091 | clock-output-names = "zx"; | |
1092 | }; | |
1093 | zs_clk: zs_clk { | |
1094 | compatible = "fixed-factor-clock"; | |
1095 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
1096 | #clock-cells = <0>; | |
1097 | clock-div = <6>; | |
1098 | clock-mult = <1>; | |
1099 | clock-output-names = "zs"; | |
1100 | }; | |
1101 | hp_clk: hp_clk { | |
1102 | compatible = "fixed-factor-clock"; | |
1103 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
1104 | #clock-cells = <0>; | |
1105 | clock-div = <12>; | |
1106 | clock-mult = <1>; | |
1107 | clock-output-names = "hp"; | |
1108 | }; | |
1109 | i_clk: i_clk { | |
1110 | compatible = "fixed-factor-clock"; | |
1111 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
1112 | #clock-cells = <0>; | |
1113 | clock-div = <2>; | |
1114 | clock-mult = <1>; | |
1115 | clock-output-names = "i"; | |
1116 | }; | |
1117 | b_clk: b_clk { | |
1118 | compatible = "fixed-factor-clock"; | |
1119 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
1120 | #clock-cells = <0>; | |
1121 | clock-div = <12>; | |
1122 | clock-mult = <1>; | |
1123 | clock-output-names = "b"; | |
1124 | }; | |
1125 | p_clk: p_clk { | |
1126 | compatible = "fixed-factor-clock"; | |
1127 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
1128 | #clock-cells = <0>; | |
1129 | clock-div = <24>; | |
1130 | clock-mult = <1>; | |
1131 | clock-output-names = "p"; | |
1132 | }; | |
1133 | cl_clk: cl_clk { | |
1134 | compatible = "fixed-factor-clock"; | |
1135 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
1136 | #clock-cells = <0>; | |
1137 | clock-div = <48>; | |
1138 | clock-mult = <1>; | |
1139 | clock-output-names = "cl"; | |
1140 | }; | |
1141 | m2_clk: m2_clk { | |
1142 | compatible = "fixed-factor-clock"; | |
1143 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
1144 | #clock-cells = <0>; | |
1145 | clock-div = <8>; | |
1146 | clock-mult = <1>; | |
1147 | clock-output-names = "m2"; | |
1148 | }; | |
1149 | imp_clk: imp_clk { | |
1150 | compatible = "fixed-factor-clock"; | |
1151 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
1152 | #clock-cells = <0>; | |
1153 | clock-div = <4>; | |
1154 | clock-mult = <1>; | |
1155 | clock-output-names = "imp"; | |
1156 | }; | |
1157 | rclk_clk: rclk_clk { | |
1158 | compatible = "fixed-factor-clock"; | |
1159 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
1160 | #clock-cells = <0>; | |
1161 | clock-div = <(48 * 1024)>; | |
1162 | clock-mult = <1>; | |
1163 | clock-output-names = "rclk"; | |
1164 | }; | |
1165 | oscclk_clk: oscclk_clk { | |
1166 | compatible = "fixed-factor-clock"; | |
1167 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
1168 | #clock-cells = <0>; | |
1169 | clock-div = <(12 * 1024)>; | |
1170 | clock-mult = <1>; | |
1171 | clock-output-names = "oscclk"; | |
1172 | }; | |
1173 | zb3_clk: zb3_clk { | |
1174 | compatible = "fixed-factor-clock"; | |
1175 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; | |
1176 | #clock-cells = <0>; | |
1177 | clock-div = <4>; | |
1178 | clock-mult = <1>; | |
1179 | clock-output-names = "zb3"; | |
1180 | }; | |
1181 | zb3d2_clk: zb3d2_clk { | |
1182 | compatible = "fixed-factor-clock"; | |
1183 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; | |
1184 | #clock-cells = <0>; | |
1185 | clock-div = <8>; | |
1186 | clock-mult = <1>; | |
1187 | clock-output-names = "zb3d2"; | |
1188 | }; | |
1189 | ddr_clk: ddr_clk { | |
1190 | compatible = "fixed-factor-clock"; | |
1191 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; | |
1192 | #clock-cells = <0>; | |
1193 | clock-div = <8>; | |
1194 | clock-mult = <1>; | |
1195 | clock-output-names = "ddr"; | |
1196 | }; | |
1197 | mp_clk: mp_clk { | |
1198 | compatible = "fixed-factor-clock"; | |
1199 | clocks = <&pll1_div2_clk>; | |
1200 | #clock-cells = <0>; | |
1201 | clock-div = <15>; | |
1202 | clock-mult = <1>; | |
1203 | clock-output-names = "mp"; | |
1204 | }; | |
1205 | cp_clk: cp_clk { | |
1206 | compatible = "fixed-factor-clock"; | |
1207 | clocks = <&extal_clk>; | |
1208 | #clock-cells = <0>; | |
1209 | clock-div = <2>; | |
1210 | clock-mult = <1>; | |
1211 | clock-output-names = "cp"; | |
1212 | }; | |
1213 | ||
1214 | /* Gate clocks */ | |
9d90951a LP |
1215 | mstp0_clks: mstp0_clks@e6150130 { |
1216 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1217 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; | |
1218 | clocks = <&mp_clk>; | |
1219 | #clock-cells = <1>; | |
b54010af | 1220 | clock-indices = <R8A7790_CLK_MSIOF0>; |
9d90951a LP |
1221 | clock-output-names = "msiof0"; |
1222 | }; | |
22a1f595 LP |
1223 | mstp1_clks: mstp1_clks@e6150134 { |
1224 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1225 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
4ba8f246 YH |
1226 | clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>, |
1227 | <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>, | |
1228 | <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, | |
1229 | <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; | |
22a1f595 | 1230 | #clock-cells = <1>; |
b54010af | 1231 | clock-indices = < |
4ba8f246 YH |
1232 | R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 |
1233 | R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 | |
1234 | R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC | |
1235 | R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0 | |
1236 | R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 | |
1237 | R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0 | |
1238 | R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S | |
22a1f595 LP |
1239 | >; |
1240 | clock-output-names = | |
4ba8f246 YH |
1241 | "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1", |
1242 | "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1", | |
1243 | "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0", | |
2284ff5f | 1244 | "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy"; |
22a1f595 LP |
1245 | }; |
1246 | mstp2_clks: mstp2_clks@e6150138 { | |
1247 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1248 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
1249 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
c819acda LP |
1250 | <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, |
1251 | <&zs_clk>; | |
22a1f595 | 1252 | #clock-cells = <1>; |
b54010af | 1253 | clock-indices = < |
22a1f595 | 1254 | R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 |
9d90951a LP |
1255 | R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 |
1256 | R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 | |
c819acda | 1257 | R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0 |
22a1f595 LP |
1258 | >; |
1259 | clock-output-names = | |
9d90951a | 1260 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
c819acda LP |
1261 | "scifb1", "msiof1", "msiof3", "scifb2", |
1262 | "sys-dmac1", "sys-dmac0"; | |
22a1f595 LP |
1263 | }; |
1264 | mstp3_clks: mstp3_clks@e615013c { | |
1265 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1266 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
17465149 WS |
1267 | clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, |
1268 | <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, | |
b02ce79f YS |
1269 | <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, |
1270 | <&hp_clk>, <&hp_clk>; | |
22a1f595 | 1271 | #clock-cells = <1>; |
b54010af | 1272 | clock-indices = < |
17465149 WS |
1273 | R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 |
1274 | R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 | |
ecafea8c | 1275 | R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 |
b02ce79f | 1276 | R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1 |
22a1f595 LP |
1277 | >; |
1278 | clock-output-names = | |
17465149 WS |
1279 | "iic2", "tpu0", "mmcif1", "sdhi3", |
1280 | "sdhi2", "sdhi1", "sdhi0", "mmcif0", | |
b02ce79f YS |
1281 | "iic0", "pciec", "iic1", "ssusb", "cmt1", |
1282 | "usbdmac0", "usbdmac1"; | |
22a1f595 | 1283 | }; |
61624caf GU |
1284 | mstp4_clks: mstp4_clks@e6150140 { |
1285 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1286 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; | |
1287 | clocks = <&cp_clk>; | |
1288 | #clock-cells = <1>; | |
1289 | clock-indices = <R8A7790_CLK_IRQC>; | |
1290 | clock-output-names = "irqc"; | |
1291 | }; | |
22a1f595 LP |
1292 | mstp5_clks: mstp5_clks@e6150144 { |
1293 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1294 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; | |
3453ca9e SS |
1295 | clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>, |
1296 | <&extal_clk>, <&p_clk>; | |
22a1f595 | 1297 | #clock-cells = <1>; |
b54010af BD |
1298 | clock-indices = < |
1299 | R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 | |
3453ca9e SS |
1300 | R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL |
1301 | R8A7790_CLK_PWM | |
b54010af | 1302 | >; |
3453ca9e SS |
1303 | clock-output-names = "audmac0", "audmac1", "adsp_mod", |
1304 | "thermal", "pwm"; | |
22a1f595 LP |
1305 | }; |
1306 | mstp7_clks: mstp7_clks@e615014c { | |
1307 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1308 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
b621f6d4 | 1309 | clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, |
22a1f595 LP |
1310 | <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, |
1311 | <&zx_clk>; | |
1312 | #clock-cells = <1>; | |
b54010af | 1313 | clock-indices = < |
22a1f595 LP |
1314 | R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 |
1315 | R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 | |
1316 | R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 | |
1317 | R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 | |
1318 | >; | |
1319 | clock-output-names = | |
1320 | "ehci", "hsusb", "hscif1", "hscif0", "scif1", | |
1321 | "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; | |
1322 | }; | |
1323 | mstp8_clks: mstp8_clks@e6150990 { | |
1324 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1325 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
f6b5dd40 | 1326 | clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, |
63d2d750 SS |
1327 | <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, |
1328 | <&zs_clk>; | |
22a1f595 | 1329 | #clock-cells = <1>; |
b54010af | 1330 | clock-indices = < |
f6b5dd40 | 1331 | R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 |
63d2d750 SS |
1332 | R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 |
1333 | R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER | |
f6b5dd40 | 1334 | R8A7790_CLK_SATA1 R8A7790_CLK_SATA0 |
3f2beaa9 | 1335 | >; |
bccccc3d | 1336 | clock-output-names = |
63d2d750 SS |
1337 | "mlb", "vin3", "vin2", "vin1", "vin0", |
1338 | "etheravb", "ether", "sata1", "sata0"; | |
22a1f595 LP |
1339 | }; |
1340 | mstp9_clks: mstp9_clks@e6150994 { | |
1341 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1342 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
81f6883f GU |
1343 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, |
1344 | <&cp_clk>, <&cp_clk>, <&cp_clk>, | |
1345 | <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, | |
3672b059 | 1346 | <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; |
22a1f595 | 1347 | #clock-cells = <1>; |
b54010af | 1348 | clock-indices = < |
81f6883f GU |
1349 | R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 |
1350 | R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 | |
17465149 WS |
1351 | R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS |
1352 | R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 | |
22a1f595 | 1353 | >; |
91b56ca1 | 1354 | clock-output-names = |
81f6883f | 1355 | "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", |
17465149 WS |
1356 | "rcan1", "rcan0", "qspi_mod", "iic3", |
1357 | "i2c3", "i2c2", "i2c1", "i2c0"; | |
22a1f595 | 1358 | }; |
bcde3722 KM |
1359 | mstp10_clks: mstp10_clks@e6150998 { |
1360 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1361 | reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; | |
1362 | clocks = <&p_clk>, | |
1363 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
1364 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
1365 | <&p_clk>, | |
1366 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, | |
1367 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, | |
1368 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, | |
1369 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, | |
1370 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, | |
a7163784 | 1371 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, |
bcde3722 KM |
1372 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>; |
1373 | ||
1374 | #clock-cells = <1>; | |
1375 | clock-indices = < | |
1376 | R8A7790_CLK_SSI_ALL | |
1377 | R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5 | |
1378 | R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 | |
1379 | R8A7790_CLK_SCU_ALL | |
1380 | R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0 | |
a7163784 | 1381 | R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0 |
bcde3722 KM |
1382 | R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5 |
1383 | R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0 | |
1384 | >; | |
1385 | clock-output-names = | |
1386 | "ssi-all", | |
1387 | "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", | |
1388 | "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", | |
1389 | "scu-all", | |
1390 | "scu-dvc1", "scu-dvc0", | |
a7163784 | 1391 | "scu-ctu1-mix1", "scu-ctu0-mix0", |
bcde3722 KM |
1392 | "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", |
1393 | "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; | |
1394 | }; | |
22a1f595 | 1395 | }; |
7053e134 | 1396 | |
fad6d45c | 1397 | qspi: spi@e6b10000 { |
7053e134 GU |
1398 | compatible = "renesas,qspi-r8a7790", "renesas,qspi"; |
1399 | reg = <0 0xe6b10000 0 0x2c>; | |
7053e134 GU |
1400 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
1401 | clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; | |
37cf3d61 GU |
1402 | dmas = <&dmac0 0x17>, <&dmac0 0x18>; |
1403 | dma-names = "tx", "rx"; | |
484adb00 | 1404 | power-domains = <&cpg_clocks>; |
7053e134 GU |
1405 | num-cs = <1>; |
1406 | #address-cells = <1>; | |
1407 | #size-cells = <0>; | |
1408 | status = "disabled"; | |
1409 | }; | |
ae8a6146 GU |
1410 | |
1411 | msiof0: spi@e6e20000 { | |
1412 | compatible = "renesas,msiof-r8a7790"; | |
c7d1f08a | 1413 | reg = <0 0xe6e20000 0 0x0064>; |
ae8a6146 GU |
1414 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; |
1415 | clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; | |
fbff6688 GU |
1416 | dmas = <&dmac0 0x51>, <&dmac0 0x52>; |
1417 | dma-names = "tx", "rx"; | |
484adb00 | 1418 | power-domains = <&cpg_clocks>; |
ae8a6146 GU |
1419 | #address-cells = <1>; |
1420 | #size-cells = <0>; | |
1421 | status = "disabled"; | |
1422 | }; | |
1423 | ||
1424 | msiof1: spi@e6e10000 { | |
1425 | compatible = "renesas,msiof-r8a7790"; | |
c7d1f08a | 1426 | reg = <0 0xe6e10000 0 0x0064>; |
ae8a6146 GU |
1427 | interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; |
1428 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; | |
fbff6688 GU |
1429 | dmas = <&dmac0 0x55>, <&dmac0 0x56>; |
1430 | dma-names = "tx", "rx"; | |
484adb00 | 1431 | power-domains = <&cpg_clocks>; |
ae8a6146 GU |
1432 | #address-cells = <1>; |
1433 | #size-cells = <0>; | |
1434 | status = "disabled"; | |
1435 | }; | |
1436 | ||
1437 | msiof2: spi@e6e00000 { | |
1438 | compatible = "renesas,msiof-r8a7790"; | |
c7d1f08a | 1439 | reg = <0 0xe6e00000 0 0x0064>; |
ae8a6146 GU |
1440 | interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; |
1441 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; | |
fbff6688 GU |
1442 | dmas = <&dmac0 0x41>, <&dmac0 0x42>; |
1443 | dma-names = "tx", "rx"; | |
484adb00 | 1444 | power-domains = <&cpg_clocks>; |
ae8a6146 GU |
1445 | #address-cells = <1>; |
1446 | #size-cells = <0>; | |
1447 | status = "disabled"; | |
1448 | }; | |
1449 | ||
1450 | msiof3: spi@e6c90000 { | |
1451 | compatible = "renesas,msiof-r8a7790"; | |
c7d1f08a | 1452 | reg = <0 0xe6c90000 0 0x0064>; |
ae8a6146 GU |
1453 | interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; |
1454 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; | |
fbff6688 GU |
1455 | dmas = <&dmac0 0x45>, <&dmac0 0x46>; |
1456 | dma-names = "tx", "rx"; | |
484adb00 | 1457 | power-domains = <&cpg_clocks>; |
ae8a6146 GU |
1458 | #address-cells = <1>; |
1459 | #size-cells = <0>; | |
1460 | status = "disabled"; | |
1461 | }; | |
7df2fd57 | 1462 | |
157fcd8a YS |
1463 | xhci: usb@ee000000 { |
1464 | compatible = "renesas,xhci-r8a7790"; | |
1465 | reg = <0 0xee000000 0 0xc00>; | |
1466 | interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; | |
1467 | clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; | |
484adb00 | 1468 | power-domains = <&cpg_clocks>; |
157fcd8a YS |
1469 | phys = <&usb2 1>; |
1470 | phy-names = "usb"; | |
1471 | status = "disabled"; | |
1472 | }; | |
1473 | ||
ff4f3eb8 BD |
1474 | pci0: pci@ee090000 { |
1475 | compatible = "renesas,pci-r8a7790"; | |
1476 | device_type = "pci"; | |
ff4f3eb8 BD |
1477 | reg = <0 0xee090000 0 0xc00>, |
1478 | <0 0xee080000 0 0x1100>; | |
1479 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | |
484adb00 GU |
1480 | clocks = <&mstp7_clks R8A7790_CLK_EHCI>; |
1481 | power-domains = <&cpg_clocks>; | |
ff4f3eb8 BD |
1482 | status = "disabled"; |
1483 | ||
1484 | bus-range = <0 0>; | |
1485 | #address-cells = <3>; | |
1486 | #size-cells = <2>; | |
1487 | #interrupt-cells = <1>; | |
1488 | ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; | |
1489 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
1490 | interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH | |
517ec80a GU |
1491 | 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH |
1492 | 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; | |
538c40e5 SS |
1493 | |
1494 | usb@0,1 { | |
1495 | reg = <0x800 0 0 0 0>; | |
1496 | device_type = "pci"; | |
1497 | phys = <&usb0 0>; | |
1498 | phy-names = "usb"; | |
1499 | }; | |
1500 | ||
1501 | usb@0,2 { | |
1502 | reg = <0x1000 0 0 0 0>; | |
1503 | device_type = "pci"; | |
1504 | phys = <&usb0 0>; | |
1505 | phy-names = "usb"; | |
1506 | }; | |
ff4f3eb8 BD |
1507 | }; |
1508 | ||
1509 | pci1: pci@ee0b0000 { | |
1510 | compatible = "renesas,pci-r8a7790"; | |
1511 | device_type = "pci"; | |
ff4f3eb8 BD |
1512 | reg = <0 0xee0b0000 0 0xc00>, |
1513 | <0 0xee0a0000 0 0x1100>; | |
1514 | interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; | |
484adb00 GU |
1515 | clocks = <&mstp7_clks R8A7790_CLK_EHCI>; |
1516 | power-domains = <&cpg_clocks>; | |
ff4f3eb8 BD |
1517 | status = "disabled"; |
1518 | ||
1519 | bus-range = <1 1>; | |
1520 | #address-cells = <3>; | |
1521 | #size-cells = <2>; | |
1522 | #interrupt-cells = <1>; | |
1523 | ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; | |
1524 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
1525 | interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH | |
517ec80a GU |
1526 | 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH |
1527 | 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>; | |
ff4f3eb8 BD |
1528 | }; |
1529 | ||
1530 | pci2: pci@ee0d0000 { | |
1531 | compatible = "renesas,pci-r8a7790"; | |
1532 | device_type = "pci"; | |
1533 | clocks = <&mstp7_clks R8A7790_CLK_EHCI>; | |
484adb00 | 1534 | power-domains = <&cpg_clocks>; |
ff4f3eb8 BD |
1535 | reg = <0 0xee0d0000 0 0xc00>, |
1536 | <0 0xee0c0000 0 0x1100>; | |
1537 | interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; | |
1538 | status = "disabled"; | |
1539 | ||
1540 | bus-range = <2 2>; | |
1541 | #address-cells = <3>; | |
1542 | #size-cells = <2>; | |
1543 | #interrupt-cells = <1>; | |
1544 | ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; | |
1545 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
1546 | interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH | |
517ec80a GU |
1547 | 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH |
1548 | 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; | |
538c40e5 SS |
1549 | |
1550 | usb@0,1 { | |
1551 | reg = <0x800 0 0 0 0>; | |
1552 | device_type = "pci"; | |
1553 | phys = <&usb2 0>; | |
1554 | phy-names = "usb"; | |
1555 | }; | |
1556 | ||
1557 | usb@0,2 { | |
1558 | reg = <0x1000 0 0 0 0>; | |
1559 | device_type = "pci"; | |
1560 | phys = <&usb2 0>; | |
1561 | phy-names = "usb"; | |
1562 | }; | |
ff4f3eb8 BD |
1563 | }; |
1564 | ||
745329d2 PE |
1565 | pciec: pcie@fe000000 { |
1566 | compatible = "renesas,pcie-r8a7790"; | |
1567 | reg = <0 0xfe000000 0 0x80000>; | |
1568 | #address-cells = <3>; | |
1569 | #size-cells = <2>; | |
1570 | bus-range = <0x00 0xff>; | |
1571 | device_type = "pci"; | |
1572 | ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 | |
1573 | 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 | |
1574 | 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 | |
1575 | 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; | |
1576 | /* Map all possible DDR as inbound ranges */ | |
1577 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 | |
1578 | 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; | |
1579 | interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, | |
1580 | <0 117 IRQ_TYPE_LEVEL_HIGH>, | |
1581 | <0 118 IRQ_TYPE_LEVEL_HIGH>; | |
1582 | #interrupt-cells = <1>; | |
1583 | interrupt-map-mask = <0 0 0 0>; | |
1584 | interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; | |
1585 | clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>; | |
1586 | clock-names = "pcie", "pcie_bus"; | |
484adb00 | 1587 | power-domains = <&cpg_clocks>; |
745329d2 PE |
1588 | status = "disabled"; |
1589 | }; | |
1590 | ||
b694e380 | 1591 | rcar_sound: sound@ec500000 { |
ad63241c KM |
1592 | /* |
1593 | * #sound-dai-cells is required | |
1594 | * | |
1595 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; | |
1596 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; | |
1597 | */ | |
31078ecd | 1598 | compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2"; |
7df2fd57 KM |
1599 | reg = <0 0xec500000 0 0x1000>, /* SCU */ |
1600 | <0 0xec5a0000 0 0x100>, /* ADG */ | |
1601 | <0 0xec540000 0 0x1000>, /* SSIU */ | |
4bc4a205 | 1602 | <0 0xec541000 0 0x280>, /* SSI */ |
0c602677 KM |
1603 | <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ |
1604 | reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; | |
46a158f2 | 1605 | |
7df2fd57 KM |
1606 | clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>, |
1607 | <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>, | |
1608 | <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>, | |
1609 | <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>, | |
1610 | <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>, | |
1611 | <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>, | |
1612 | <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>, | |
1613 | <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>, | |
1614 | <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, | |
1615 | <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, | |
1616 | <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, | |
a7163784 | 1617 | <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, |
fc67bf42 | 1618 | <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, |
334d69a2 | 1619 | <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, |
7df2fd57 KM |
1620 | <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; |
1621 | clock-names = "ssi-all", | |
1622 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", | |
1623 | "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", | |
1624 | "src.9", "src.8", "src.7", "src.6", "src.5", | |
1625 | "src.4", "src.3", "src.2", "src.1", "src.0", | |
a7163784 | 1626 | "ctu.0", "ctu.1", |
fc67bf42 | 1627 | "mix.0", "mix.1", |
334d69a2 | 1628 | "dvc.0", "dvc.1", |
7df2fd57 | 1629 | "clk_a", "clk_b", "clk_c", "clk_i"; |
6507c4ef | 1630 | power-domains = <&cpg_clocks>; |
7df2fd57 KM |
1631 | |
1632 | status = "disabled"; | |
1633 | ||
334d69a2 | 1634 | rcar_sound,dvc { |
118a5093 KM |
1635 | dvc0: dvc@0 { |
1636 | dmas = <&audma0 0xbc>; | |
1637 | dma-names = "tx"; | |
1638 | }; | |
1639 | dvc1: dvc@1 { | |
1640 | dmas = <&audma0 0xbe>; | |
1641 | dma-names = "tx"; | |
1642 | }; | |
334d69a2 KM |
1643 | }; |
1644 | ||
fc67bf42 KM |
1645 | rcar_sound,mix { |
1646 | mix0: mix@0 { }; | |
1647 | mix1: mix@1 { }; | |
1648 | }; | |
1649 | ||
a7163784 KM |
1650 | rcar_sound,ctu { |
1651 | ctu00: ctu@0 { }; | |
1652 | ctu01: ctu@1 { }; | |
1653 | ctu02: ctu@2 { }; | |
1654 | ctu03: ctu@3 { }; | |
1655 | ctu10: ctu@4 { }; | |
1656 | ctu11: ctu@5 { }; | |
1657 | ctu12: ctu@6 { }; | |
1658 | ctu13: ctu@7 { }; | |
1659 | }; | |
1660 | ||
7df2fd57 | 1661 | rcar_sound,src { |
118a5093 KM |
1662 | src0: src@0 { |
1663 | interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; | |
1664 | dmas = <&audma0 0x85>, <&audma1 0x9a>; | |
1665 | dma-names = "rx", "tx"; | |
1666 | }; | |
1667 | src1: src@1 { | |
1668 | interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; | |
1669 | dmas = <&audma0 0x87>, <&audma1 0x9c>; | |
1670 | dma-names = "rx", "tx"; | |
1671 | }; | |
1672 | src2: src@2 { | |
1673 | interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; | |
1674 | dmas = <&audma0 0x89>, <&audma1 0x9e>; | |
1675 | dma-names = "rx", "tx"; | |
1676 | }; | |
1677 | src3: src@3 { | |
1678 | interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; | |
1679 | dmas = <&audma0 0x8b>, <&audma1 0xa0>; | |
1680 | dma-names = "rx", "tx"; | |
1681 | }; | |
1682 | src4: src@4 { | |
1683 | interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; | |
1684 | dmas = <&audma0 0x8d>, <&audma1 0xb0>; | |
1685 | dma-names = "rx", "tx"; | |
1686 | }; | |
1687 | src5: src@5 { | |
1688 | interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; | |
1689 | dmas = <&audma0 0x8f>, <&audma1 0xb2>; | |
1690 | dma-names = "rx", "tx"; | |
1691 | }; | |
1692 | src6: src@6 { | |
1693 | interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; | |
1694 | dmas = <&audma0 0x91>, <&audma1 0xb4>; | |
1695 | dma-names = "rx", "tx"; | |
1696 | }; | |
1697 | src7: src@7 { | |
1698 | interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; | |
1699 | dmas = <&audma0 0x93>, <&audma1 0xb6>; | |
1700 | dma-names = "rx", "tx"; | |
1701 | }; | |
1702 | src8: src@8 { | |
1703 | interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; | |
1704 | dmas = <&audma0 0x95>, <&audma1 0xb8>; | |
1705 | dma-names = "rx", "tx"; | |
1706 | }; | |
1707 | src9: src@9 { | |
1708 | interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; | |
1709 | dmas = <&audma0 0x97>, <&audma1 0xba>; | |
1710 | dma-names = "rx", "tx"; | |
1711 | }; | |
7df2fd57 KM |
1712 | }; |
1713 | ||
1714 | rcar_sound,ssi { | |
118a5093 KM |
1715 | ssi0: ssi@0 { |
1716 | interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; | |
1717 | dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; | |
1718 | dma-names = "rx", "tx", "rxu", "txu"; | |
1719 | }; | |
1720 | ssi1: ssi@1 { | |
1721 | interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; | |
1722 | dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; | |
1723 | dma-names = "rx", "tx", "rxu", "txu"; | |
1724 | }; | |
1725 | ssi2: ssi@2 { | |
1726 | interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; | |
1727 | dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; | |
1728 | dma-names = "rx", "tx", "rxu", "txu"; | |
1729 | }; | |
1730 | ssi3: ssi@3 { | |
1731 | interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; | |
1732 | dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; | |
1733 | dma-names = "rx", "tx", "rxu", "txu"; | |
1734 | }; | |
1735 | ssi4: ssi@4 { | |
1736 | interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; | |
1737 | dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; | |
1738 | dma-names = "rx", "tx", "rxu", "txu"; | |
1739 | }; | |
1740 | ssi5: ssi@5 { | |
1741 | interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; | |
1742 | dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; | |
1743 | dma-names = "rx", "tx", "rxu", "txu"; | |
1744 | }; | |
1745 | ssi6: ssi@6 { | |
1746 | interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; | |
1747 | dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; | |
1748 | dma-names = "rx", "tx", "rxu", "txu"; | |
1749 | }; | |
1750 | ssi7: ssi@7 { | |
1751 | interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; | |
1752 | dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; | |
1753 | dma-names = "rx", "tx", "rxu", "txu"; | |
1754 | }; | |
1755 | ssi8: ssi@8 { | |
1756 | interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; | |
1757 | dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; | |
1758 | dma-names = "rx", "tx", "rxu", "txu"; | |
1759 | }; | |
1760 | ssi9: ssi@9 { | |
1761 | interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; | |
1762 | dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; | |
1763 | dma-names = "rx", "tx", "rxu", "txu"; | |
1764 | }; | |
7df2fd57 KM |
1765 | }; |
1766 | }; | |
70496727 LP |
1767 | |
1768 | ipmmu_sy0: mmu@e6280000 { | |
1769 | compatible = "renesas,ipmmu-vmsa"; | |
1770 | reg = <0 0xe6280000 0 0x1000>; | |
1771 | interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, | |
1772 | <0 224 IRQ_TYPE_LEVEL_HIGH>; | |
1773 | #iommu-cells = <1>; | |
1774 | status = "disabled"; | |
1775 | }; | |
1776 | ||
1777 | ipmmu_sy1: mmu@e6290000 { | |
1778 | compatible = "renesas,ipmmu-vmsa"; | |
1779 | reg = <0 0xe6290000 0 0x1000>; | |
1780 | interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; | |
1781 | #iommu-cells = <1>; | |
1782 | status = "disabled"; | |
1783 | }; | |
1784 | ||
1785 | ipmmu_ds: mmu@e6740000 { | |
1786 | compatible = "renesas,ipmmu-vmsa"; | |
1787 | reg = <0 0xe6740000 0 0x1000>; | |
1788 | interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, | |
1789 | <0 199 IRQ_TYPE_LEVEL_HIGH>; | |
1790 | #iommu-cells = <1>; | |
1791 | status = "disabled"; | |
1792 | }; | |
1793 | ||
1794 | ipmmu_mp: mmu@ec680000 { | |
1795 | compatible = "renesas,ipmmu-vmsa"; | |
1796 | reg = <0 0xec680000 0 0x1000>; | |
1797 | interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; | |
1798 | #iommu-cells = <1>; | |
1799 | status = "disabled"; | |
1800 | }; | |
1801 | ||
1802 | ipmmu_mx: mmu@fe951000 { | |
1803 | compatible = "renesas,ipmmu-vmsa"; | |
1804 | reg = <0 0xfe951000 0 0x1000>; | |
1805 | interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, | |
1806 | <0 221 IRQ_TYPE_LEVEL_HIGH>; | |
1807 | #iommu-cells = <1>; | |
1808 | status = "disabled"; | |
1809 | }; | |
1810 | ||
1811 | ipmmu_rt: mmu@ffc80000 { | |
1812 | compatible = "renesas,ipmmu-vmsa"; | |
1813 | reg = <0 0xffc80000 0 0x1000>; | |
1814 | interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>; | |
1815 | #iommu-cells = <1>; | |
1816 | status = "disabled"; | |
1817 | }; | |
0468b2d6 | 1818 | }; |