Commit | Line | Data |
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0d0771ab HN |
1 | /* |
2 | * Device Tree Source for the r8a7791 SoC | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Electronics Corporation | |
2e5d55ce SS |
5 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
6 | * Copyright (C) 2014 Cogent Embedded Inc. | |
0d0771ab HN |
7 | * |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
11 | */ | |
12 | ||
59e79895 | 13 | #include <dt-bindings/clock/r8a7791-clock.h> |
5f75e73c LP |
14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
15 | #include <dt-bindings/interrupt-controller/irq.h> | |
16 | ||
0d0771ab HN |
17 | / { |
18 | compatible = "renesas,r8a7791"; | |
19 | interrupt-parent = <&gic>; | |
20 | #address-cells = <2>; | |
21 | #size-cells = <2>; | |
22 | ||
5bd3de7b WS |
23 | aliases { |
24 | i2c0 = &i2c0; | |
25 | i2c1 = &i2c1; | |
26 | i2c2 = &i2c2; | |
27 | i2c3 = &i2c3; | |
28 | i2c4 = &i2c4; | |
29 | i2c5 = &i2c5; | |
36408d9d WS |
30 | i2c6 = &i2c6; |
31 | i2c7 = &i2c7; | |
32 | i2c8 = &i2c8; | |
6f3e4ee3 | 33 | spi0 = &qspi; |
7713d3ab GU |
34 | spi1 = &msiof0; |
35 | spi2 = &msiof1; | |
36 | spi3 = &msiof2; | |
5bd3de7b WS |
37 | }; |
38 | ||
0d0771ab HN |
39 | cpus { |
40 | #address-cells = <1>; | |
41 | #size-cells = <0>; | |
42 | ||
43 | cpu0: cpu@0 { | |
44 | device_type = "cpu"; | |
45 | compatible = "arm,cortex-a15"; | |
46 | reg = <0>; | |
896b79df | 47 | clock-frequency = <1500000000>; |
0d0771ab | 48 | }; |
15ab426c MD |
49 | |
50 | cpu1: cpu@1 { | |
51 | device_type = "cpu"; | |
52 | compatible = "arm,cortex-a15"; | |
53 | reg = <1>; | |
896b79df | 54 | clock-frequency = <1500000000>; |
15ab426c | 55 | }; |
0d0771ab HN |
56 | }; |
57 | ||
58 | gic: interrupt-controller@f1001000 { | |
59 | compatible = "arm,cortex-a15-gic"; | |
60 | #interrupt-cells = <3>; | |
61 | #address-cells = <0>; | |
62 | interrupt-controller; | |
63 | reg = <0 0xf1001000 0 0x1000>, | |
64 | <0 0xf1002000 0 0x1000>, | |
65 | <0 0xf1004000 0 0x2000>, | |
66 | <0 0xf1006000 0 0x2000>; | |
5f75e73c | 67 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
0d0771ab | 68 | }; |
d77db73e | 69 | |
89fbba12 | 70 | gpio0: gpio@e6050000 { |
ab87e3fc | 71 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 72 | reg = <0 0xe6050000 0 0x50>; |
5f75e73c | 73 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
74 | #gpio-cells = <2>; |
75 | gpio-controller; | |
76 | gpio-ranges = <&pfc 0 0 32>; | |
77 | #interrupt-cells = <2>; | |
78 | interrupt-controller; | |
4faf9c5e | 79 | clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; |
ab87e3fc MD |
80 | }; |
81 | ||
89fbba12 | 82 | gpio1: gpio@e6051000 { |
ab87e3fc | 83 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 84 | reg = <0 0xe6051000 0 0x50>; |
5f75e73c | 85 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
86 | #gpio-cells = <2>; |
87 | gpio-controller; | |
88 | gpio-ranges = <&pfc 0 32 32>; | |
89 | #interrupt-cells = <2>; | |
90 | interrupt-controller; | |
4faf9c5e | 91 | clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; |
ab87e3fc MD |
92 | }; |
93 | ||
89fbba12 | 94 | gpio2: gpio@e6052000 { |
ab87e3fc | 95 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 96 | reg = <0 0xe6052000 0 0x50>; |
5f75e73c | 97 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
98 | #gpio-cells = <2>; |
99 | gpio-controller; | |
100 | gpio-ranges = <&pfc 0 64 32>; | |
101 | #interrupt-cells = <2>; | |
102 | interrupt-controller; | |
4faf9c5e | 103 | clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; |
ab87e3fc MD |
104 | }; |
105 | ||
89fbba12 | 106 | gpio3: gpio@e6053000 { |
ab87e3fc | 107 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 108 | reg = <0 0xe6053000 0 0x50>; |
5f75e73c | 109 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
110 | #gpio-cells = <2>; |
111 | gpio-controller; | |
112 | gpio-ranges = <&pfc 0 96 32>; | |
113 | #interrupt-cells = <2>; | |
114 | interrupt-controller; | |
4faf9c5e | 115 | clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; |
ab87e3fc MD |
116 | }; |
117 | ||
89fbba12 | 118 | gpio4: gpio@e6054000 { |
ab87e3fc | 119 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 120 | reg = <0 0xe6054000 0 0x50>; |
5f75e73c | 121 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
122 | #gpio-cells = <2>; |
123 | gpio-controller; | |
124 | gpio-ranges = <&pfc 0 128 32>; | |
125 | #interrupt-cells = <2>; | |
126 | interrupt-controller; | |
4faf9c5e | 127 | clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; |
ab87e3fc MD |
128 | }; |
129 | ||
89fbba12 | 130 | gpio5: gpio@e6055000 { |
ab87e3fc | 131 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 132 | reg = <0 0xe6055000 0 0x50>; |
5f75e73c | 133 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
134 | #gpio-cells = <2>; |
135 | gpio-controller; | |
136 | gpio-ranges = <&pfc 0 160 32>; | |
137 | #interrupt-cells = <2>; | |
138 | interrupt-controller; | |
4faf9c5e | 139 | clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; |
ab87e3fc MD |
140 | }; |
141 | ||
89fbba12 | 142 | gpio6: gpio@e6055400 { |
ab87e3fc | 143 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 144 | reg = <0 0xe6055400 0 0x50>; |
5f75e73c | 145 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
146 | #gpio-cells = <2>; |
147 | gpio-controller; | |
148 | gpio-ranges = <&pfc 0 192 32>; | |
149 | #interrupt-cells = <2>; | |
150 | interrupt-controller; | |
4faf9c5e | 151 | clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; |
ab87e3fc MD |
152 | }; |
153 | ||
89fbba12 | 154 | gpio7: gpio@e6055800 { |
ab87e3fc | 155 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 156 | reg = <0 0xe6055800 0 0x50>; |
5f75e73c | 157 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
158 | #gpio-cells = <2>; |
159 | gpio-controller; | |
160 | gpio-ranges = <&pfc 0 224 26>; | |
161 | #interrupt-cells = <2>; | |
162 | interrupt-controller; | |
4faf9c5e | 163 | clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; |
ab87e3fc MD |
164 | }; |
165 | ||
d103f4d3 MD |
166 | thermal@e61f0000 { |
167 | compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal"; | |
168 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; | |
d103f4d3 | 169 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
563bc8eb | 170 | clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; |
d103f4d3 MD |
171 | }; |
172 | ||
03586acf MD |
173 | timer { |
174 | compatible = "arm,armv7-timer"; | |
5f75e73c LP |
175 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
176 | <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
177 | <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
178 | <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
03586acf MD |
179 | }; |
180 | ||
d77db73e | 181 | irqc0: interrupt-controller@e61c0000 { |
26041b06 | 182 | compatible = "renesas,irqc-r8a7791", "renesas,irqc"; |
d77db73e MD |
183 | #interrupt-cells = <2>; |
184 | interrupt-controller; | |
185 | reg = <0 0xe61c0000 0 0x200>; | |
5f75e73c LP |
186 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
187 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | |
188 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | |
189 | <0 3 IRQ_TYPE_LEVEL_HIGH>, | |
190 | <0 12 IRQ_TYPE_LEVEL_HIGH>, | |
191 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
192 | <0 14 IRQ_TYPE_LEVEL_HIGH>, | |
193 | <0 15 IRQ_TYPE_LEVEL_HIGH>, | |
194 | <0 16 IRQ_TYPE_LEVEL_HIGH>, | |
195 | <0 17 IRQ_TYPE_LEVEL_HIGH>; | |
d77db73e | 196 | }; |
55146927 | 197 | |
36408d9d | 198 | /* The memory map in the User's Manual maps the cores to bus numbers */ |
5bd3de7b WS |
199 | i2c0: i2c@e6508000 { |
200 | #address-cells = <1>; | |
201 | #size-cells = <0>; | |
202 | compatible = "renesas,i2c-r8a7791"; | |
203 | reg = <0 0xe6508000 0 0x40>; | |
204 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; | |
205 | clocks = <&mstp9_clks R8A7791_CLK_I2C0>; | |
206 | status = "disabled"; | |
207 | }; | |
208 | ||
209 | i2c1: i2c@e6518000 { | |
210 | #address-cells = <1>; | |
211 | #size-cells = <0>; | |
212 | compatible = "renesas,i2c-r8a7791"; | |
213 | reg = <0 0xe6518000 0 0x40>; | |
214 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; | |
215 | clocks = <&mstp9_clks R8A7791_CLK_I2C1>; | |
216 | status = "disabled"; | |
217 | }; | |
218 | ||
219 | i2c2: i2c@e6530000 { | |
220 | #address-cells = <1>; | |
221 | #size-cells = <0>; | |
222 | compatible = "renesas,i2c-r8a7791"; | |
223 | reg = <0 0xe6530000 0 0x40>; | |
224 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; | |
225 | clocks = <&mstp9_clks R8A7791_CLK_I2C2>; | |
226 | status = "disabled"; | |
227 | }; | |
228 | ||
229 | i2c3: i2c@e6540000 { | |
230 | #address-cells = <1>; | |
231 | #size-cells = <0>; | |
232 | compatible = "renesas,i2c-r8a7791"; | |
233 | reg = <0 0xe6540000 0 0x40>; | |
234 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; | |
235 | clocks = <&mstp9_clks R8A7791_CLK_I2C3>; | |
236 | status = "disabled"; | |
237 | }; | |
238 | ||
239 | i2c4: i2c@e6520000 { | |
240 | #address-cells = <1>; | |
241 | #size-cells = <0>; | |
242 | compatible = "renesas,i2c-r8a7791"; | |
243 | reg = <0 0xe6520000 0 0x40>; | |
244 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; | |
245 | clocks = <&mstp9_clks R8A7791_CLK_I2C4>; | |
246 | status = "disabled"; | |
247 | }; | |
248 | ||
249 | i2c5: i2c@e6528000 { | |
36408d9d | 250 | /* doesn't need pinmux */ |
5bd3de7b WS |
251 | #address-cells = <1>; |
252 | #size-cells = <0>; | |
253 | compatible = "renesas,i2c-r8a7791"; | |
254 | reg = <0 0xe6528000 0 0x40>; | |
255 | interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
256 | clocks = <&mstp9_clks R8A7791_CLK_I2C5>; | |
257 | status = "disabled"; | |
258 | }; | |
259 | ||
36408d9d WS |
260 | i2c6: i2c@e60b0000 { |
261 | /* doesn't need pinmux */ | |
262 | #address-cells = <1>; | |
263 | #size-cells = <0>; | |
264 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
265 | reg = <0 0xe60b0000 0 0x425>; | |
266 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; | |
267 | clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; | |
268 | status = "disabled"; | |
269 | }; | |
270 | ||
271 | i2c7: i2c@e6500000 { | |
272 | #address-cells = <1>; | |
273 | #size-cells = <0>; | |
274 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
275 | reg = <0 0xe6500000 0 0x425>; | |
276 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; | |
277 | clocks = <&mstp3_clks R8A7791_CLK_IIC0>; | |
278 | status = "disabled"; | |
279 | }; | |
280 | ||
281 | i2c8: i2c@e6510000 { | |
282 | #address-cells = <1>; | |
283 | #size-cells = <0>; | |
284 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
285 | reg = <0 0xe6510000 0 0x425>; | |
286 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; | |
287 | clocks = <&mstp3_clks R8A7791_CLK_IIC1>; | |
288 | status = "disabled"; | |
289 | }; | |
290 | ||
55146927 MD |
291 | pfc: pfc@e6060000 { |
292 | compatible = "renesas,pfc-r8a7791"; | |
293 | reg = <0 0xe6060000 0 0x250>; | |
294 | #gpio-range-cells = <3>; | |
295 | }; | |
59e79895 | 296 | |
b7ed8a0d MD |
297 | sdhi0: sd@ee100000 { |
298 | compatible = "renesas,sdhi-r8a7791"; | |
299 | reg = <0 0xee100000 0 0x200>; | |
b7ed8a0d MD |
300 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
301 | clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; | |
302 | status = "disabled"; | |
303 | }; | |
304 | ||
305 | sdhi1: sd@ee140000 { | |
306 | compatible = "renesas,sdhi-r8a7791"; | |
307 | reg = <0 0xee140000 0 0x100>; | |
b7ed8a0d MD |
308 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
309 | clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; | |
310 | status = "disabled"; | |
311 | }; | |
312 | ||
313 | sdhi2: sd@ee160000 { | |
314 | compatible = "renesas,sdhi-r8a7791"; | |
315 | reg = <0 0xee160000 0 0x100>; | |
b7ed8a0d MD |
316 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; |
317 | clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; | |
318 | status = "disabled"; | |
319 | }; | |
320 | ||
9640cf25 LP |
321 | scifa0: serial@e6c40000 { |
322 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
323 | reg = <0 0xe6c40000 0 64>; | |
9640cf25 LP |
324 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; |
325 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; | |
326 | clock-names = "sci_ick"; | |
327 | status = "disabled"; | |
328 | }; | |
329 | ||
330 | scifa1: serial@e6c50000 { | |
331 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
332 | reg = <0 0xe6c50000 0 64>; |
333 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; | |
334 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; | |
335 | clock-names = "sci_ick"; | |
336 | status = "disabled"; | |
337 | }; | |
338 | ||
339 | scifa2: serial@e6c60000 { | |
340 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
341 | reg = <0 0xe6c60000 0 64>; |
342 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; | |
343 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; | |
344 | clock-names = "sci_ick"; | |
345 | status = "disabled"; | |
346 | }; | |
347 | ||
348 | scifa3: serial@e6c70000 { | |
349 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
350 | reg = <0 0xe6c70000 0 64>; |
351 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; | |
352 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; | |
353 | clock-names = "sci_ick"; | |
354 | status = "disabled"; | |
355 | }; | |
356 | ||
357 | scifa4: serial@e6c78000 { | |
358 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
359 | reg = <0 0xe6c78000 0 64>; |
360 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; | |
361 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; | |
362 | clock-names = "sci_ick"; | |
363 | status = "disabled"; | |
364 | }; | |
365 | ||
366 | scifa5: serial@e6c80000 { | |
367 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
368 | reg = <0 0xe6c80000 0 64>; |
369 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; | |
370 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; | |
371 | clock-names = "sci_ick"; | |
372 | status = "disabled"; | |
373 | }; | |
374 | ||
375 | scifb0: serial@e6c20000 { | |
376 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
9640cf25 LP |
377 | reg = <0 0xe6c20000 0 64>; |
378 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; | |
379 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; | |
380 | clock-names = "sci_ick"; | |
381 | status = "disabled"; | |
382 | }; | |
383 | ||
384 | scifb1: serial@e6c30000 { | |
385 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
9640cf25 LP |
386 | reg = <0 0xe6c30000 0 64>; |
387 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; | |
388 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; | |
389 | clock-names = "sci_ick"; | |
390 | status = "disabled"; | |
391 | }; | |
392 | ||
393 | scifb2: serial@e6ce0000 { | |
394 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
9640cf25 LP |
395 | reg = <0 0xe6ce0000 0 64>; |
396 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; | |
397 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; | |
398 | clock-names = "sci_ick"; | |
399 | status = "disabled"; | |
400 | }; | |
401 | ||
402 | scif0: serial@e6e60000 { | |
403 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
404 | reg = <0 0xe6e60000 0 64>; |
405 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; | |
406 | clocks = <&mstp7_clks R8A7791_CLK_SCIF0>; | |
407 | clock-names = "sci_ick"; | |
408 | status = "disabled"; | |
409 | }; | |
410 | ||
411 | scif1: serial@e6e68000 { | |
412 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
413 | reg = <0 0xe6e68000 0 64>; |
414 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; | |
415 | clocks = <&mstp7_clks R8A7791_CLK_SCIF1>; | |
416 | clock-names = "sci_ick"; | |
417 | status = "disabled"; | |
418 | }; | |
419 | ||
420 | scif2: serial@e6e58000 { | |
421 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
422 | reg = <0 0xe6e58000 0 64>; |
423 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; | |
424 | clocks = <&mstp7_clks R8A7791_CLK_SCIF2>; | |
425 | clock-names = "sci_ick"; | |
426 | status = "disabled"; | |
427 | }; | |
428 | ||
429 | scif3: serial@e6ea8000 { | |
430 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
431 | reg = <0 0xe6ea8000 0 64>; |
432 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; | |
433 | clocks = <&mstp7_clks R8A7791_CLK_SCIF3>; | |
434 | clock-names = "sci_ick"; | |
435 | status = "disabled"; | |
436 | }; | |
437 | ||
438 | scif4: serial@e6ee0000 { | |
439 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
440 | reg = <0 0xe6ee0000 0 64>; |
441 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; | |
442 | clocks = <&mstp7_clks R8A7791_CLK_SCIF4>; | |
443 | clock-names = "sci_ick"; | |
444 | status = "disabled"; | |
445 | }; | |
446 | ||
447 | scif5: serial@e6ee8000 { | |
448 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
449 | reg = <0 0xe6ee8000 0 64>; |
450 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; | |
451 | clocks = <&mstp7_clks R8A7791_CLK_SCIF5>; | |
452 | clock-names = "sci_ick"; | |
453 | status = "disabled"; | |
454 | }; | |
455 | ||
456 | hscif0: serial@e62c0000 { | |
457 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
9640cf25 LP |
458 | reg = <0 0xe62c0000 0 96>; |
459 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; | |
460 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>; | |
461 | clock-names = "sci_ick"; | |
462 | status = "disabled"; | |
463 | }; | |
464 | ||
465 | hscif1: serial@e62c8000 { | |
466 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
9640cf25 LP |
467 | reg = <0 0xe62c8000 0 96>; |
468 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; | |
469 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>; | |
470 | clock-names = "sci_ick"; | |
471 | status = "disabled"; | |
472 | }; | |
473 | ||
474 | hscif2: serial@e62d0000 { | |
475 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
9640cf25 LP |
476 | reg = <0 0xe62d0000 0 96>; |
477 | interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; | |
478 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>; | |
479 | clock-names = "sci_ick"; | |
480 | status = "disabled"; | |
481 | }; | |
482 | ||
2e5d55ce SS |
483 | ether: ethernet@ee700000 { |
484 | compatible = "renesas,ether-r8a7791"; | |
485 | reg = <0 0xee700000 0 0x400>; | |
486 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; | |
487 | clocks = <&mstp8_clks R8A7791_CLK_ETHER>; | |
488 | phy-mode = "rmii"; | |
489 | #address-cells = <1>; | |
490 | #size-cells = <0>; | |
491 | status = "disabled"; | |
492 | }; | |
493 | ||
b8532c69 VB |
494 | sata0: sata@ee300000 { |
495 | compatible = "renesas,sata-r8a7791"; | |
496 | reg = <0 0xee300000 0 0x2000>; | |
b8532c69 VB |
497 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; |
498 | clocks = <&mstp8_clks R8A7791_CLK_SATA0>; | |
499 | status = "disabled"; | |
500 | }; | |
501 | ||
502 | sata1: sata@ee500000 { | |
503 | compatible = "renesas,sata-r8a7791"; | |
504 | reg = <0 0xee500000 0 0x2000>; | |
b8532c69 VB |
505 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
506 | clocks = <&mstp8_clks R8A7791_CLK_SATA1>; | |
507 | status = "disabled"; | |
508 | }; | |
509 | ||
59e79895 LP |
510 | clocks { |
511 | #address-cells = <2>; | |
512 | #size-cells = <2>; | |
513 | ranges; | |
514 | ||
515 | /* External root clock */ | |
516 | extal_clk: extal_clk { | |
517 | compatible = "fixed-clock"; | |
518 | #clock-cells = <0>; | |
519 | /* This value must be overriden by the board. */ | |
520 | clock-frequency = <0>; | |
521 | clock-output-names = "extal"; | |
522 | }; | |
523 | ||
524 | /* Special CPG clocks */ | |
525 | cpg_clocks: cpg_clocks@e6150000 { | |
526 | compatible = "renesas,r8a7791-cpg-clocks", | |
527 | "renesas,rcar-gen2-cpg-clocks"; | |
528 | reg = <0 0xe6150000 0 0x1000>; | |
529 | clocks = <&extal_clk>; | |
530 | #clock-cells = <1>; | |
531 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
532 | "lb", "qspi", "sdh", "sd0", "z"; | |
533 | }; | |
534 | ||
535 | /* Variable factor clocks */ | |
536 | sd1_clk: sd2_clk@e6150078 { | |
537 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
538 | reg = <0 0xe6150078 0 4>; | |
539 | clocks = <&pll1_div2_clk>; | |
540 | #clock-cells = <0>; | |
541 | clock-output-names = "sd1"; | |
542 | }; | |
543 | sd2_clk: sd3_clk@e615007c { | |
544 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
545 | reg = <0 0xe615007c 0 4>; | |
546 | clocks = <&pll1_div2_clk>; | |
547 | #clock-cells = <0>; | |
548 | clock-output-names = "sd2"; | |
549 | }; | |
550 | mmc0_clk: mmc0_clk@e6150240 { | |
551 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
552 | reg = <0 0xe6150240 0 4>; | |
553 | clocks = <&pll1_div2_clk>; | |
554 | #clock-cells = <0>; | |
555 | clock-output-names = "mmc0"; | |
556 | }; | |
557 | ssp_clk: ssp_clk@e6150248 { | |
558 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
559 | reg = <0 0xe6150248 0 4>; | |
560 | clocks = <&pll1_div2_clk>; | |
561 | #clock-cells = <0>; | |
562 | clock-output-names = "ssp"; | |
563 | }; | |
564 | ssprs_clk: ssprs_clk@e615024c { | |
565 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
566 | reg = <0 0xe615024c 0 4>; | |
567 | clocks = <&pll1_div2_clk>; | |
568 | #clock-cells = <0>; | |
569 | clock-output-names = "ssprs"; | |
570 | }; | |
571 | ||
572 | /* Fixed factor clocks */ | |
573 | pll1_div2_clk: pll1_div2_clk { | |
574 | compatible = "fixed-factor-clock"; | |
575 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
576 | #clock-cells = <0>; | |
577 | clock-div = <2>; | |
578 | clock-mult = <1>; | |
579 | clock-output-names = "pll1_div2"; | |
580 | }; | |
581 | zg_clk: zg_clk { | |
582 | compatible = "fixed-factor-clock"; | |
583 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
584 | #clock-cells = <0>; | |
585 | clock-div = <3>; | |
586 | clock-mult = <1>; | |
587 | clock-output-names = "zg"; | |
588 | }; | |
589 | zx_clk: zx_clk { | |
590 | compatible = "fixed-factor-clock"; | |
591 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
592 | #clock-cells = <0>; | |
593 | clock-div = <3>; | |
594 | clock-mult = <1>; | |
595 | clock-output-names = "zx"; | |
596 | }; | |
597 | zs_clk: zs_clk { | |
598 | compatible = "fixed-factor-clock"; | |
599 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
600 | #clock-cells = <0>; | |
601 | clock-div = <6>; | |
602 | clock-mult = <1>; | |
603 | clock-output-names = "zs"; | |
604 | }; | |
605 | hp_clk: hp_clk { | |
606 | compatible = "fixed-factor-clock"; | |
607 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
608 | #clock-cells = <0>; | |
609 | clock-div = <12>; | |
610 | clock-mult = <1>; | |
611 | clock-output-names = "hp"; | |
612 | }; | |
613 | i_clk: i_clk { | |
614 | compatible = "fixed-factor-clock"; | |
615 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
616 | #clock-cells = <0>; | |
617 | clock-div = <2>; | |
618 | clock-mult = <1>; | |
619 | clock-output-names = "i"; | |
620 | }; | |
621 | b_clk: b_clk { | |
622 | compatible = "fixed-factor-clock"; | |
623 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
624 | #clock-cells = <0>; | |
625 | clock-div = <12>; | |
626 | clock-mult = <1>; | |
627 | clock-output-names = "b"; | |
628 | }; | |
629 | p_clk: p_clk { | |
630 | compatible = "fixed-factor-clock"; | |
631 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
632 | #clock-cells = <0>; | |
633 | clock-div = <24>; | |
634 | clock-mult = <1>; | |
635 | clock-output-names = "p"; | |
636 | }; | |
637 | cl_clk: cl_clk { | |
638 | compatible = "fixed-factor-clock"; | |
639 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
640 | #clock-cells = <0>; | |
641 | clock-div = <48>; | |
642 | clock-mult = <1>; | |
643 | clock-output-names = "cl"; | |
644 | }; | |
645 | m2_clk: m2_clk { | |
646 | compatible = "fixed-factor-clock"; | |
647 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
648 | #clock-cells = <0>; | |
649 | clock-div = <8>; | |
650 | clock-mult = <1>; | |
651 | clock-output-names = "m2"; | |
652 | }; | |
653 | imp_clk: imp_clk { | |
654 | compatible = "fixed-factor-clock"; | |
655 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
656 | #clock-cells = <0>; | |
657 | clock-div = <4>; | |
658 | clock-mult = <1>; | |
659 | clock-output-names = "imp"; | |
660 | }; | |
661 | rclk_clk: rclk_clk { | |
662 | compatible = "fixed-factor-clock"; | |
663 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
664 | #clock-cells = <0>; | |
665 | clock-div = <(48 * 1024)>; | |
666 | clock-mult = <1>; | |
667 | clock-output-names = "rclk"; | |
668 | }; | |
669 | oscclk_clk: oscclk_clk { | |
670 | compatible = "fixed-factor-clock"; | |
671 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
672 | #clock-cells = <0>; | |
673 | clock-div = <(12 * 1024)>; | |
674 | clock-mult = <1>; | |
675 | clock-output-names = "oscclk"; | |
676 | }; | |
677 | zb3_clk: zb3_clk { | |
678 | compatible = "fixed-factor-clock"; | |
679 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
680 | #clock-cells = <0>; | |
681 | clock-div = <4>; | |
682 | clock-mult = <1>; | |
683 | clock-output-names = "zb3"; | |
684 | }; | |
685 | zb3d2_clk: zb3d2_clk { | |
686 | compatible = "fixed-factor-clock"; | |
687 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
688 | #clock-cells = <0>; | |
689 | clock-div = <8>; | |
690 | clock-mult = <1>; | |
691 | clock-output-names = "zb3d2"; | |
692 | }; | |
693 | ddr_clk: ddr_clk { | |
694 | compatible = "fixed-factor-clock"; | |
695 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
696 | #clock-cells = <0>; | |
697 | clock-div = <8>; | |
698 | clock-mult = <1>; | |
699 | clock-output-names = "ddr"; | |
700 | }; | |
701 | mp_clk: mp_clk { | |
702 | compatible = "fixed-factor-clock"; | |
703 | clocks = <&pll1_div2_clk>; | |
704 | #clock-cells = <0>; | |
705 | clock-div = <15>; | |
706 | clock-mult = <1>; | |
707 | clock-output-names = "mp"; | |
708 | }; | |
709 | cp_clk: cp_clk { | |
710 | compatible = "fixed-factor-clock"; | |
711 | clocks = <&extal_clk>; | |
712 | #clock-cells = <0>; | |
713 | clock-div = <2>; | |
714 | clock-mult = <1>; | |
715 | clock-output-names = "cp"; | |
716 | }; | |
717 | ||
718 | /* Gate clocks */ | |
cded80f8 LP |
719 | mstp0_clks: mstp0_clks@e6150130 { |
720 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
721 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; | |
722 | clocks = <&mp_clk>; | |
723 | #clock-cells = <1>; | |
724 | renesas,clock-indices = <R8A7791_CLK_MSIOF0>; | |
725 | clock-output-names = "msiof0"; | |
726 | }; | |
59e79895 LP |
727 | mstp1_clks: mstp1_clks@e6150134 { |
728 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
729 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
730 | clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, | |
731 | <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; | |
732 | #clock-cells = <1>; | |
733 | renesas,clock-indices = < | |
734 | R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 | |
735 | R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 | |
58ea1d53 | 736 | R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S |
59e79895 LP |
737 | >; |
738 | clock-output-names = | |
739 | "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", | |
740 | "vsp1-du0", "vsp1-sy"; | |
741 | }; | |
742 | mstp2_clks: mstp2_clks@e6150138 { | |
743 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
744 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
745 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
cded80f8 | 746 | <&mp_clk>, <&mp_clk>, <&mp_clk>; |
59e79895 LP |
747 | #clock-cells = <1>; |
748 | renesas,clock-indices = < | |
749 | R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 | |
cded80f8 LP |
750 | R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 |
751 | R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 | |
59e79895 LP |
752 | >; |
753 | clock-output-names = | |
0c002ef8 | 754 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
cded80f8 | 755 | "scifb1", "msiof1", "scifb2"; |
59e79895 LP |
756 | }; |
757 | mstp3_clks: mstp3_clks@e615013c { | |
758 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
759 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
c08691b5 | 760 | clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, |
308f3062 | 761 | <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; |
59e79895 LP |
762 | #clock-cells = <1>; |
763 | renesas,clock-indices = < | |
c08691b5 | 764 | R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 |
308f3062 | 765 | R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 |
59e79895 LP |
766 | >; |
767 | clock-output-names = | |
c08691b5 | 768 | "tpu0", "sdhi2", "sdhi1", "sdhi0", |
308f3062 | 769 | "mmcif0", "i2c7", "i2c8", "ssusb", "cmt1"; |
59e79895 LP |
770 | }; |
771 | mstp5_clks: mstp5_clks@e6150144 { | |
772 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
773 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; | |
774 | clocks = <&extal_clk>, <&p_clk>; | |
775 | #clock-cells = <1>; | |
776 | renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; | |
777 | clock-output-names = "thermal", "pwm"; | |
778 | }; | |
779 | mstp7_clks: mstp7_clks@e615014c { | |
780 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
781 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
6225b99a | 782 | clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, |
59e79895 LP |
783 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
784 | <&zx_clk>, <&zx_clk>, <&zx_clk>; | |
785 | #clock-cells = <1>; | |
786 | renesas,clock-indices = < | |
6225b99a | 787 | R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 |
59e79895 LP |
788 | R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 |
789 | R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 | |
790 | R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 | |
791 | R8A7791_CLK_LVDS0 | |
792 | >; | |
793 | clock-output-names = | |
6225b99a | 794 | "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", |
59e79895 LP |
795 | "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; |
796 | }; | |
797 | mstp8_clks: mstp8_clks@e6150990 { | |
798 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
799 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
65f05c38 LP |
800 | clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, |
801 | <&zs_clk>; | |
59e79895 | 802 | #clock-cells = <1>; |
09c98346 LP |
803 | renesas,clock-indices = < |
804 | R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 | |
65f05c38 | 805 | R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 |
09c98346 | 806 | >; |
65f05c38 LP |
807 | clock-output-names = |
808 | "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; | |
59e79895 LP |
809 | }; |
810 | mstp9_clks: mstp9_clks@e6150994 { | |
811 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
812 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
4faf9c5e GU |
813 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
814 | <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, | |
815 | <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, | |
11b48db9 LP |
816 | <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, |
817 | <&hp_clk>, <&hp_clk>; | |
59e79895 LP |
818 | #clock-cells = <1>; |
819 | renesas,clock-indices = < | |
4faf9c5e GU |
820 | R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 |
821 | R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 | |
c08691b5 WS |
822 | R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 |
823 | R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 | |
824 | R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 | |
59e79895 LP |
825 | >; |
826 | clock-output-names = | |
4faf9c5e GU |
827 | "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", |
828 | "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", | |
829 | "i2c1", "i2c0"; | |
59e79895 LP |
830 | }; |
831 | mstp11_clks: mstp11_clks@e615099c { | |
832 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
833 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; | |
834 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; | |
835 | #clock-cells = <1>; | |
836 | renesas,clock-indices = < | |
837 | R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 | |
838 | >; | |
839 | clock-output-names = "scifa3", "scifa4", "scifa5"; | |
840 | }; | |
841 | }; | |
4d5b59cd | 842 | |
6f3e4ee3 | 843 | qspi: spi@e6b10000 { |
4d5b59cd GU |
844 | compatible = "renesas,qspi-r8a7791", "renesas,qspi"; |
845 | reg = <0 0xe6b10000 0 0x2c>; | |
4d5b59cd GU |
846 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
847 | clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; | |
848 | num-cs = <1>; | |
849 | #address-cells = <1>; | |
850 | #size-cells = <0>; | |
851 | status = "disabled"; | |
852 | }; | |
7713d3ab GU |
853 | |
854 | msiof0: spi@e6e20000 { | |
855 | compatible = "renesas,msiof-r8a7791"; | |
856 | reg = <0 0xe6e20000 0 0x0064>; | |
857 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; | |
858 | clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; | |
859 | #address-cells = <1>; | |
860 | #size-cells = <0>; | |
861 | status = "disabled"; | |
862 | }; | |
863 | ||
864 | msiof1: spi@e6e10000 { | |
865 | compatible = "renesas,msiof-r8a7791"; | |
866 | reg = <0 0xe6e10000 0 0x0064>; | |
867 | interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; | |
868 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; | |
869 | #address-cells = <1>; | |
870 | #size-cells = <0>; | |
871 | status = "disabled"; | |
872 | }; | |
873 | ||
874 | msiof2: spi@e6e00000 { | |
875 | compatible = "renesas,msiof-r8a7791"; | |
876 | reg = <0 0xe6e00000 0 0x0064>; | |
877 | interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; | |
878 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; | |
879 | #address-cells = <1>; | |
880 | #size-cells = <0>; | |
881 | status = "disabled"; | |
882 | }; | |
0d0771ab | 883 | }; |