Commit | Line | Data |
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0d0771ab HN |
1 | /* |
2 | * Device Tree Source for the r8a7791 SoC | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Electronics Corporation | |
2e5d55ce SS |
5 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
6 | * Copyright (C) 2014 Cogent Embedded Inc. | |
0d0771ab HN |
7 | * |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
11 | */ | |
12 | ||
59e79895 | 13 | #include <dt-bindings/clock/r8a7791-clock.h> |
5f75e73c LP |
14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
15 | #include <dt-bindings/interrupt-controller/irq.h> | |
16 | ||
0d0771ab HN |
17 | / { |
18 | compatible = "renesas,r8a7791"; | |
19 | interrupt-parent = <&gic>; | |
20 | #address-cells = <2>; | |
21 | #size-cells = <2>; | |
22 | ||
5bd3de7b WS |
23 | aliases { |
24 | i2c0 = &i2c0; | |
25 | i2c1 = &i2c1; | |
26 | i2c2 = &i2c2; | |
27 | i2c3 = &i2c3; | |
28 | i2c4 = &i2c4; | |
29 | i2c5 = &i2c5; | |
36408d9d WS |
30 | i2c6 = &i2c6; |
31 | i2c7 = &i2c7; | |
32 | i2c8 = &i2c8; | |
6f3e4ee3 | 33 | spi0 = &qspi; |
7713d3ab GU |
34 | spi1 = &msiof0; |
35 | spi2 = &msiof1; | |
36 | spi3 = &msiof2; | |
0b8d1d57 SS |
37 | vin0 = &vin0; |
38 | vin1 = &vin1; | |
39 | vin2 = &vin2; | |
5bd3de7b WS |
40 | }; |
41 | ||
0d0771ab HN |
42 | cpus { |
43 | #address-cells = <1>; | |
44 | #size-cells = <0>; | |
45 | ||
46 | cpu0: cpu@0 { | |
47 | device_type = "cpu"; | |
48 | compatible = "arm,cortex-a15"; | |
49 | reg = <0>; | |
896b79df | 50 | clock-frequency = <1500000000>; |
a57004ec GI |
51 | voltage-tolerance = <1>; /* 1% */ |
52 | clocks = <&cpg_clocks R8A7791_CLK_Z>; | |
53 | clock-latency = <300000>; /* 300 us */ | |
54 | ||
55 | /* kHz - uV - OPPs unknown yet */ | |
56 | operating-points = <1500000 1000000>, | |
57 | <1312500 1000000>, | |
58 | <1125000 1000000>, | |
59 | < 937500 1000000>, | |
60 | < 750000 1000000>, | |
61 | < 375000 1000000>; | |
0d0771ab | 62 | }; |
15ab426c MD |
63 | |
64 | cpu1: cpu@1 { | |
65 | device_type = "cpu"; | |
66 | compatible = "arm,cortex-a15"; | |
67 | reg = <1>; | |
896b79df | 68 | clock-frequency = <1500000000>; |
15ab426c | 69 | }; |
0d0771ab HN |
70 | }; |
71 | ||
72 | gic: interrupt-controller@f1001000 { | |
73 | compatible = "arm,cortex-a15-gic"; | |
74 | #interrupt-cells = <3>; | |
75 | #address-cells = <0>; | |
76 | interrupt-controller; | |
77 | reg = <0 0xf1001000 0 0x1000>, | |
78 | <0 0xf1002000 0 0x1000>, | |
79 | <0 0xf1004000 0 0x2000>, | |
80 | <0 0xf1006000 0 0x2000>; | |
5f75e73c | 81 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
0d0771ab | 82 | }; |
d77db73e | 83 | |
89fbba12 | 84 | gpio0: gpio@e6050000 { |
ab87e3fc | 85 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 86 | reg = <0 0xe6050000 0 0x50>; |
5f75e73c | 87 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
88 | #gpio-cells = <2>; |
89 | gpio-controller; | |
90 | gpio-ranges = <&pfc 0 0 32>; | |
91 | #interrupt-cells = <2>; | |
92 | interrupt-controller; | |
4faf9c5e | 93 | clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; |
ab87e3fc MD |
94 | }; |
95 | ||
89fbba12 | 96 | gpio1: gpio@e6051000 { |
ab87e3fc | 97 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 98 | reg = <0 0xe6051000 0 0x50>; |
5f75e73c | 99 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
100 | #gpio-cells = <2>; |
101 | gpio-controller; | |
102 | gpio-ranges = <&pfc 0 32 32>; | |
103 | #interrupt-cells = <2>; | |
104 | interrupt-controller; | |
4faf9c5e | 105 | clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; |
ab87e3fc MD |
106 | }; |
107 | ||
89fbba12 | 108 | gpio2: gpio@e6052000 { |
ab87e3fc | 109 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 110 | reg = <0 0xe6052000 0 0x50>; |
5f75e73c | 111 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
112 | #gpio-cells = <2>; |
113 | gpio-controller; | |
114 | gpio-ranges = <&pfc 0 64 32>; | |
115 | #interrupt-cells = <2>; | |
116 | interrupt-controller; | |
4faf9c5e | 117 | clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; |
ab87e3fc MD |
118 | }; |
119 | ||
89fbba12 | 120 | gpio3: gpio@e6053000 { |
ab87e3fc | 121 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 122 | reg = <0 0xe6053000 0 0x50>; |
5f75e73c | 123 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
124 | #gpio-cells = <2>; |
125 | gpio-controller; | |
126 | gpio-ranges = <&pfc 0 96 32>; | |
127 | #interrupt-cells = <2>; | |
128 | interrupt-controller; | |
4faf9c5e | 129 | clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; |
ab87e3fc MD |
130 | }; |
131 | ||
89fbba12 | 132 | gpio4: gpio@e6054000 { |
ab87e3fc | 133 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 134 | reg = <0 0xe6054000 0 0x50>; |
5f75e73c | 135 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
136 | #gpio-cells = <2>; |
137 | gpio-controller; | |
138 | gpio-ranges = <&pfc 0 128 32>; | |
139 | #interrupt-cells = <2>; | |
140 | interrupt-controller; | |
4faf9c5e | 141 | clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; |
ab87e3fc MD |
142 | }; |
143 | ||
89fbba12 | 144 | gpio5: gpio@e6055000 { |
ab87e3fc | 145 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 146 | reg = <0 0xe6055000 0 0x50>; |
5f75e73c | 147 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
148 | #gpio-cells = <2>; |
149 | gpio-controller; | |
150 | gpio-ranges = <&pfc 0 160 32>; | |
151 | #interrupt-cells = <2>; | |
152 | interrupt-controller; | |
4faf9c5e | 153 | clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; |
ab87e3fc MD |
154 | }; |
155 | ||
89fbba12 | 156 | gpio6: gpio@e6055400 { |
ab87e3fc | 157 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 158 | reg = <0 0xe6055400 0 0x50>; |
5f75e73c | 159 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
160 | #gpio-cells = <2>; |
161 | gpio-controller; | |
162 | gpio-ranges = <&pfc 0 192 32>; | |
163 | #interrupt-cells = <2>; | |
164 | interrupt-controller; | |
4faf9c5e | 165 | clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; |
ab87e3fc MD |
166 | }; |
167 | ||
89fbba12 | 168 | gpio7: gpio@e6055800 { |
ab87e3fc | 169 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 170 | reg = <0 0xe6055800 0 0x50>; |
5f75e73c | 171 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
172 | #gpio-cells = <2>; |
173 | gpio-controller; | |
174 | gpio-ranges = <&pfc 0 224 26>; | |
175 | #interrupt-cells = <2>; | |
176 | interrupt-controller; | |
4faf9c5e | 177 | clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; |
ab87e3fc MD |
178 | }; |
179 | ||
d103f4d3 MD |
180 | thermal@e61f0000 { |
181 | compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal"; | |
182 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; | |
d103f4d3 | 183 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
563bc8eb | 184 | clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; |
d103f4d3 MD |
185 | }; |
186 | ||
03586acf MD |
187 | timer { |
188 | compatible = "arm,armv7-timer"; | |
5f75e73c LP |
189 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
190 | <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
191 | <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
192 | <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
03586acf MD |
193 | }; |
194 | ||
ceaa1894 | 195 | cmt0: timer@ffca0000 { |
4217f323 | 196 | compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; |
ceaa1894 LP |
197 | reg = <0 0xffca0000 0 0x1004>; |
198 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, | |
199 | <0 143 IRQ_TYPE_LEVEL_HIGH>; | |
200 | clocks = <&mstp1_clks R8A7791_CLK_CMT0>; | |
201 | clock-names = "fck"; | |
202 | ||
203 | renesas,channels-mask = <0x60>; | |
204 | ||
205 | status = "disabled"; | |
206 | }; | |
207 | ||
208 | cmt1: timer@e6130000 { | |
4217f323 | 209 | compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; |
ceaa1894 LP |
210 | reg = <0 0xe6130000 0 0x1004>; |
211 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, | |
212 | <0 121 IRQ_TYPE_LEVEL_HIGH>, | |
213 | <0 122 IRQ_TYPE_LEVEL_HIGH>, | |
214 | <0 123 IRQ_TYPE_LEVEL_HIGH>, | |
215 | <0 124 IRQ_TYPE_LEVEL_HIGH>, | |
216 | <0 125 IRQ_TYPE_LEVEL_HIGH>, | |
217 | <0 126 IRQ_TYPE_LEVEL_HIGH>, | |
218 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
219 | clocks = <&mstp3_clks R8A7791_CLK_CMT1>; | |
220 | clock-names = "fck"; | |
221 | ||
222 | renesas,channels-mask = <0xff>; | |
223 | ||
224 | status = "disabled"; | |
225 | }; | |
226 | ||
d77db73e | 227 | irqc0: interrupt-controller@e61c0000 { |
26041b06 | 228 | compatible = "renesas,irqc-r8a7791", "renesas,irqc"; |
d77db73e MD |
229 | #interrupt-cells = <2>; |
230 | interrupt-controller; | |
231 | reg = <0 0xe61c0000 0 0x200>; | |
5f75e73c LP |
232 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
233 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | |
234 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | |
235 | <0 3 IRQ_TYPE_LEVEL_HIGH>, | |
236 | <0 12 IRQ_TYPE_LEVEL_HIGH>, | |
237 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
238 | <0 14 IRQ_TYPE_LEVEL_HIGH>, | |
239 | <0 15 IRQ_TYPE_LEVEL_HIGH>, | |
240 | <0 16 IRQ_TYPE_LEVEL_HIGH>, | |
241 | <0 17 IRQ_TYPE_LEVEL_HIGH>; | |
d77db73e | 242 | }; |
55146927 | 243 | |
fde8feef LP |
244 | dmac0: dma-controller@e6700000 { |
245 | compatible = "renesas,rcar-dmac"; | |
246 | reg = <0 0xe6700000 0 0x20000>; | |
247 | interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH | |
248 | 0 200 IRQ_TYPE_LEVEL_HIGH | |
249 | 0 201 IRQ_TYPE_LEVEL_HIGH | |
250 | 0 202 IRQ_TYPE_LEVEL_HIGH | |
251 | 0 203 IRQ_TYPE_LEVEL_HIGH | |
252 | 0 204 IRQ_TYPE_LEVEL_HIGH | |
253 | 0 205 IRQ_TYPE_LEVEL_HIGH | |
254 | 0 206 IRQ_TYPE_LEVEL_HIGH | |
255 | 0 207 IRQ_TYPE_LEVEL_HIGH | |
256 | 0 208 IRQ_TYPE_LEVEL_HIGH | |
257 | 0 209 IRQ_TYPE_LEVEL_HIGH | |
258 | 0 210 IRQ_TYPE_LEVEL_HIGH | |
259 | 0 211 IRQ_TYPE_LEVEL_HIGH | |
260 | 0 212 IRQ_TYPE_LEVEL_HIGH | |
261 | 0 213 IRQ_TYPE_LEVEL_HIGH | |
262 | 0 214 IRQ_TYPE_LEVEL_HIGH>; | |
263 | interrupt-names = "error", | |
264 | "ch0", "ch1", "ch2", "ch3", | |
265 | "ch4", "ch5", "ch6", "ch7", | |
266 | "ch8", "ch9", "ch10", "ch11", | |
267 | "ch12", "ch13", "ch14"; | |
268 | clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; | |
269 | clock-names = "fck"; | |
270 | #dma-cells = <1>; | |
271 | dma-channels = <15>; | |
272 | }; | |
273 | ||
274 | dmac1: dma-controller@e6720000 { | |
275 | compatible = "renesas,rcar-dmac"; | |
276 | reg = <0 0xe6720000 0 0x20000>; | |
277 | interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH | |
278 | 0 216 IRQ_TYPE_LEVEL_HIGH | |
279 | 0 217 IRQ_TYPE_LEVEL_HIGH | |
280 | 0 218 IRQ_TYPE_LEVEL_HIGH | |
281 | 0 219 IRQ_TYPE_LEVEL_HIGH | |
282 | 0 308 IRQ_TYPE_LEVEL_HIGH | |
283 | 0 309 IRQ_TYPE_LEVEL_HIGH | |
284 | 0 310 IRQ_TYPE_LEVEL_HIGH | |
285 | 0 311 IRQ_TYPE_LEVEL_HIGH | |
286 | 0 312 IRQ_TYPE_LEVEL_HIGH | |
287 | 0 313 IRQ_TYPE_LEVEL_HIGH | |
288 | 0 314 IRQ_TYPE_LEVEL_HIGH | |
289 | 0 315 IRQ_TYPE_LEVEL_HIGH | |
290 | 0 316 IRQ_TYPE_LEVEL_HIGH | |
291 | 0 317 IRQ_TYPE_LEVEL_HIGH | |
292 | 0 318 IRQ_TYPE_LEVEL_HIGH>; | |
293 | interrupt-names = "error", | |
294 | "ch0", "ch1", "ch2", "ch3", | |
295 | "ch4", "ch5", "ch6", "ch7", | |
296 | "ch8", "ch9", "ch10", "ch11", | |
297 | "ch12", "ch13", "ch14"; | |
298 | clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; | |
299 | clock-names = "fck"; | |
300 | #dma-cells = <1>; | |
301 | dma-channels = <15>; | |
302 | }; | |
303 | ||
36408d9d | 304 | /* The memory map in the User's Manual maps the cores to bus numbers */ |
5bd3de7b WS |
305 | i2c0: i2c@e6508000 { |
306 | #address-cells = <1>; | |
307 | #size-cells = <0>; | |
308 | compatible = "renesas,i2c-r8a7791"; | |
309 | reg = <0 0xe6508000 0 0x40>; | |
310 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; | |
311 | clocks = <&mstp9_clks R8A7791_CLK_I2C0>; | |
312 | status = "disabled"; | |
313 | }; | |
314 | ||
315 | i2c1: i2c@e6518000 { | |
316 | #address-cells = <1>; | |
317 | #size-cells = <0>; | |
318 | compatible = "renesas,i2c-r8a7791"; | |
319 | reg = <0 0xe6518000 0 0x40>; | |
320 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; | |
321 | clocks = <&mstp9_clks R8A7791_CLK_I2C1>; | |
322 | status = "disabled"; | |
323 | }; | |
324 | ||
325 | i2c2: i2c@e6530000 { | |
326 | #address-cells = <1>; | |
327 | #size-cells = <0>; | |
328 | compatible = "renesas,i2c-r8a7791"; | |
329 | reg = <0 0xe6530000 0 0x40>; | |
330 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; | |
331 | clocks = <&mstp9_clks R8A7791_CLK_I2C2>; | |
332 | status = "disabled"; | |
333 | }; | |
334 | ||
335 | i2c3: i2c@e6540000 { | |
336 | #address-cells = <1>; | |
337 | #size-cells = <0>; | |
338 | compatible = "renesas,i2c-r8a7791"; | |
339 | reg = <0 0xe6540000 0 0x40>; | |
340 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; | |
341 | clocks = <&mstp9_clks R8A7791_CLK_I2C3>; | |
342 | status = "disabled"; | |
343 | }; | |
344 | ||
345 | i2c4: i2c@e6520000 { | |
346 | #address-cells = <1>; | |
347 | #size-cells = <0>; | |
348 | compatible = "renesas,i2c-r8a7791"; | |
349 | reg = <0 0xe6520000 0 0x40>; | |
350 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; | |
351 | clocks = <&mstp9_clks R8A7791_CLK_I2C4>; | |
352 | status = "disabled"; | |
353 | }; | |
354 | ||
355 | i2c5: i2c@e6528000 { | |
36408d9d | 356 | /* doesn't need pinmux */ |
5bd3de7b WS |
357 | #address-cells = <1>; |
358 | #size-cells = <0>; | |
359 | compatible = "renesas,i2c-r8a7791"; | |
360 | reg = <0 0xe6528000 0 0x40>; | |
361 | interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
362 | clocks = <&mstp9_clks R8A7791_CLK_I2C5>; | |
363 | status = "disabled"; | |
364 | }; | |
365 | ||
36408d9d WS |
366 | i2c6: i2c@e60b0000 { |
367 | /* doesn't need pinmux */ | |
368 | #address-cells = <1>; | |
369 | #size-cells = <0>; | |
370 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
371 | reg = <0 0xe60b0000 0 0x425>; | |
372 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; | |
373 | clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; | |
374 | status = "disabled"; | |
375 | }; | |
376 | ||
377 | i2c7: i2c@e6500000 { | |
378 | #address-cells = <1>; | |
379 | #size-cells = <0>; | |
380 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
381 | reg = <0 0xe6500000 0 0x425>; | |
382 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; | |
383 | clocks = <&mstp3_clks R8A7791_CLK_IIC0>; | |
384 | status = "disabled"; | |
385 | }; | |
386 | ||
387 | i2c8: i2c@e6510000 { | |
388 | #address-cells = <1>; | |
389 | #size-cells = <0>; | |
390 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
391 | reg = <0 0xe6510000 0 0x425>; | |
392 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; | |
393 | clocks = <&mstp3_clks R8A7791_CLK_IIC1>; | |
394 | status = "disabled"; | |
395 | }; | |
396 | ||
55146927 MD |
397 | pfc: pfc@e6060000 { |
398 | compatible = "renesas,pfc-r8a7791"; | |
399 | reg = <0 0xe6060000 0 0x250>; | |
400 | #gpio-range-cells = <3>; | |
401 | }; | |
59e79895 | 402 | |
b7ed8a0d MD |
403 | sdhi0: sd@ee100000 { |
404 | compatible = "renesas,sdhi-r8a7791"; | |
405 | reg = <0 0xee100000 0 0x200>; | |
b7ed8a0d MD |
406 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
407 | clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; | |
408 | status = "disabled"; | |
409 | }; | |
410 | ||
411 | sdhi1: sd@ee140000 { | |
412 | compatible = "renesas,sdhi-r8a7791"; | |
413 | reg = <0 0xee140000 0 0x100>; | |
b7ed8a0d MD |
414 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
415 | clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; | |
416 | status = "disabled"; | |
417 | }; | |
418 | ||
419 | sdhi2: sd@ee160000 { | |
420 | compatible = "renesas,sdhi-r8a7791"; | |
421 | reg = <0 0xee160000 0 0x100>; | |
b7ed8a0d MD |
422 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; |
423 | clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; | |
424 | status = "disabled"; | |
425 | }; | |
426 | ||
9640cf25 LP |
427 | scifa0: serial@e6c40000 { |
428 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
429 | reg = <0 0xe6c40000 0 64>; | |
9640cf25 LP |
430 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; |
431 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; | |
432 | clock-names = "sci_ick"; | |
433 | status = "disabled"; | |
434 | }; | |
435 | ||
436 | scifa1: serial@e6c50000 { | |
437 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
438 | reg = <0 0xe6c50000 0 64>; |
439 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; | |
440 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; | |
441 | clock-names = "sci_ick"; | |
442 | status = "disabled"; | |
443 | }; | |
444 | ||
445 | scifa2: serial@e6c60000 { | |
446 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
447 | reg = <0 0xe6c60000 0 64>; |
448 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; | |
449 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; | |
450 | clock-names = "sci_ick"; | |
451 | status = "disabled"; | |
452 | }; | |
453 | ||
454 | scifa3: serial@e6c70000 { | |
455 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
456 | reg = <0 0xe6c70000 0 64>; |
457 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; | |
458 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; | |
459 | clock-names = "sci_ick"; | |
460 | status = "disabled"; | |
461 | }; | |
462 | ||
463 | scifa4: serial@e6c78000 { | |
464 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
465 | reg = <0 0xe6c78000 0 64>; |
466 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; | |
467 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; | |
468 | clock-names = "sci_ick"; | |
469 | status = "disabled"; | |
470 | }; | |
471 | ||
472 | scifa5: serial@e6c80000 { | |
473 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
474 | reg = <0 0xe6c80000 0 64>; |
475 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; | |
476 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; | |
477 | clock-names = "sci_ick"; | |
478 | status = "disabled"; | |
479 | }; | |
480 | ||
481 | scifb0: serial@e6c20000 { | |
482 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
9640cf25 LP |
483 | reg = <0 0xe6c20000 0 64>; |
484 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; | |
485 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; | |
486 | clock-names = "sci_ick"; | |
487 | status = "disabled"; | |
488 | }; | |
489 | ||
490 | scifb1: serial@e6c30000 { | |
491 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
9640cf25 LP |
492 | reg = <0 0xe6c30000 0 64>; |
493 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; | |
494 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; | |
495 | clock-names = "sci_ick"; | |
496 | status = "disabled"; | |
497 | }; | |
498 | ||
499 | scifb2: serial@e6ce0000 { | |
500 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
9640cf25 LP |
501 | reg = <0 0xe6ce0000 0 64>; |
502 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; | |
503 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; | |
504 | clock-names = "sci_ick"; | |
505 | status = "disabled"; | |
506 | }; | |
507 | ||
508 | scif0: serial@e6e60000 { | |
509 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
510 | reg = <0 0xe6e60000 0 64>; |
511 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; | |
512 | clocks = <&mstp7_clks R8A7791_CLK_SCIF0>; | |
513 | clock-names = "sci_ick"; | |
514 | status = "disabled"; | |
515 | }; | |
516 | ||
517 | scif1: serial@e6e68000 { | |
518 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
519 | reg = <0 0xe6e68000 0 64>; |
520 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; | |
521 | clocks = <&mstp7_clks R8A7791_CLK_SCIF1>; | |
522 | clock-names = "sci_ick"; | |
523 | status = "disabled"; | |
524 | }; | |
525 | ||
526 | scif2: serial@e6e58000 { | |
527 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
528 | reg = <0 0xe6e58000 0 64>; |
529 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; | |
530 | clocks = <&mstp7_clks R8A7791_CLK_SCIF2>; | |
531 | clock-names = "sci_ick"; | |
532 | status = "disabled"; | |
533 | }; | |
534 | ||
535 | scif3: serial@e6ea8000 { | |
536 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
537 | reg = <0 0xe6ea8000 0 64>; |
538 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; | |
539 | clocks = <&mstp7_clks R8A7791_CLK_SCIF3>; | |
540 | clock-names = "sci_ick"; | |
541 | status = "disabled"; | |
542 | }; | |
543 | ||
544 | scif4: serial@e6ee0000 { | |
545 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
546 | reg = <0 0xe6ee0000 0 64>; |
547 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; | |
548 | clocks = <&mstp7_clks R8A7791_CLK_SCIF4>; | |
549 | clock-names = "sci_ick"; | |
550 | status = "disabled"; | |
551 | }; | |
552 | ||
553 | scif5: serial@e6ee8000 { | |
554 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
555 | reg = <0 0xe6ee8000 0 64>; |
556 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; | |
557 | clocks = <&mstp7_clks R8A7791_CLK_SCIF5>; | |
558 | clock-names = "sci_ick"; | |
559 | status = "disabled"; | |
560 | }; | |
561 | ||
562 | hscif0: serial@e62c0000 { | |
563 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
9640cf25 LP |
564 | reg = <0 0xe62c0000 0 96>; |
565 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; | |
566 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>; | |
567 | clock-names = "sci_ick"; | |
568 | status = "disabled"; | |
569 | }; | |
570 | ||
571 | hscif1: serial@e62c8000 { | |
572 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
9640cf25 LP |
573 | reg = <0 0xe62c8000 0 96>; |
574 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; | |
575 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>; | |
576 | clock-names = "sci_ick"; | |
577 | status = "disabled"; | |
578 | }; | |
579 | ||
580 | hscif2: serial@e62d0000 { | |
581 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
9640cf25 LP |
582 | reg = <0 0xe62d0000 0 96>; |
583 | interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; | |
584 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>; | |
585 | clock-names = "sci_ick"; | |
586 | status = "disabled"; | |
587 | }; | |
588 | ||
2e5d55ce SS |
589 | ether: ethernet@ee700000 { |
590 | compatible = "renesas,ether-r8a7791"; | |
591 | reg = <0 0xee700000 0 0x400>; | |
592 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; | |
593 | clocks = <&mstp8_clks R8A7791_CLK_ETHER>; | |
594 | phy-mode = "rmii"; | |
595 | #address-cells = <1>; | |
596 | #size-cells = <0>; | |
597 | status = "disabled"; | |
598 | }; | |
599 | ||
b8532c69 VB |
600 | sata0: sata@ee300000 { |
601 | compatible = "renesas,sata-r8a7791"; | |
602 | reg = <0 0xee300000 0 0x2000>; | |
b8532c69 VB |
603 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; |
604 | clocks = <&mstp8_clks R8A7791_CLK_SATA0>; | |
605 | status = "disabled"; | |
606 | }; | |
607 | ||
608 | sata1: sata@ee500000 { | |
609 | compatible = "renesas,sata-r8a7791"; | |
610 | reg = <0 0xee500000 0 0x2000>; | |
b8532c69 VB |
611 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
612 | clocks = <&mstp8_clks R8A7791_CLK_SATA1>; | |
613 | status = "disabled"; | |
614 | }; | |
615 | ||
3b7e530d SS |
616 | usbphy: usb-phy@e6590100 { |
617 | compatible = "renesas,usb-phy-r8a7791"; | |
618 | reg = <0 0xe6590100 0 0x100>; | |
619 | #address-cells = <1>; | |
620 | #size-cells = <0>; | |
621 | clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; | |
622 | clock-names = "usbhs"; | |
623 | status = "disabled"; | |
624 | ||
625 | usb0: usb-channel@0 { | |
626 | reg = <0>; | |
627 | #phy-cells = <1>; | |
628 | }; | |
629 | usb2: usb-channel@2 { | |
630 | reg = <2>; | |
631 | #phy-cells = <1>; | |
632 | }; | |
633 | }; | |
634 | ||
0b8d1d57 SS |
635 | vin0: video@e6ef0000 { |
636 | compatible = "renesas,vin-r8a7791"; | |
637 | clocks = <&mstp8_clks R8A7791_CLK_VIN0>; | |
638 | reg = <0 0xe6ef0000 0 0x1000>; | |
639 | interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; | |
640 | status = "disabled"; | |
641 | }; | |
642 | ||
643 | vin1: video@e6ef1000 { | |
644 | compatible = "renesas,vin-r8a7791"; | |
645 | clocks = <&mstp8_clks R8A7791_CLK_VIN1>; | |
646 | reg = <0 0xe6ef1000 0 0x1000>; | |
647 | interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; | |
648 | status = "disabled"; | |
649 | }; | |
650 | ||
651 | vin2: video@e6ef2000 { | |
652 | compatible = "renesas,vin-r8a7791"; | |
653 | clocks = <&mstp8_clks R8A7791_CLK_VIN2>; | |
654 | reg = <0 0xe6ef2000 0 0x1000>; | |
655 | interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; | |
656 | status = "disabled"; | |
657 | }; | |
658 | ||
8eefac2d LP |
659 | vsp1@fe928000 { |
660 | compatible = "renesas,vsp1"; | |
661 | reg = <0 0xfe928000 0 0x8000>; | |
662 | interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; | |
663 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; | |
664 | ||
665 | renesas,has-lut; | |
666 | renesas,has-sru; | |
667 | renesas,#rpf = <5>; | |
668 | renesas,#uds = <3>; | |
669 | renesas,#wpf = <4>; | |
670 | }; | |
671 | ||
672 | vsp1@fe930000 { | |
673 | compatible = "renesas,vsp1"; | |
674 | reg = <0 0xfe930000 0 0x8000>; | |
675 | interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; | |
676 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; | |
677 | ||
678 | renesas,has-lif; | |
679 | renesas,has-lut; | |
680 | renesas,#rpf = <4>; | |
681 | renesas,#uds = <1>; | |
682 | renesas,#wpf = <4>; | |
683 | }; | |
684 | ||
685 | vsp1@fe938000 { | |
686 | compatible = "renesas,vsp1"; | |
687 | reg = <0 0xfe938000 0 0x8000>; | |
688 | interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; | |
689 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; | |
690 | ||
691 | renesas,has-lif; | |
692 | renesas,has-lut; | |
693 | renesas,#rpf = <4>; | |
694 | renesas,#uds = <1>; | |
695 | renesas,#wpf = <4>; | |
696 | }; | |
697 | ||
698 | du: display@feb00000 { | |
699 | compatible = "renesas,du-r8a7791"; | |
700 | reg = <0 0xfeb00000 0 0x40000>, | |
701 | <0 0xfeb90000 0 0x1c>; | |
702 | reg-names = "du", "lvds.0"; | |
703 | interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, | |
704 | <0 268 IRQ_TYPE_LEVEL_HIGH>; | |
705 | clocks = <&mstp7_clks R8A7791_CLK_DU0>, | |
706 | <&mstp7_clks R8A7791_CLK_DU1>, | |
707 | <&mstp7_clks R8A7791_CLK_LVDS0>; | |
708 | clock-names = "du.0", "du.1", "lvds.0"; | |
709 | status = "disabled"; | |
710 | ||
711 | ports { | |
712 | #address-cells = <1>; | |
713 | #size-cells = <0>; | |
714 | ||
715 | port@0 { | |
716 | reg = <0>; | |
717 | du_out_rgb: endpoint { | |
718 | }; | |
719 | }; | |
720 | port@1 { | |
721 | reg = <1>; | |
722 | du_out_lvds0: endpoint { | |
723 | }; | |
724 | }; | |
725 | }; | |
726 | }; | |
727 | ||
59e79895 LP |
728 | clocks { |
729 | #address-cells = <2>; | |
730 | #size-cells = <2>; | |
731 | ranges; | |
732 | ||
733 | /* External root clock */ | |
734 | extal_clk: extal_clk { | |
735 | compatible = "fixed-clock"; | |
736 | #clock-cells = <0>; | |
737 | /* This value must be overriden by the board. */ | |
738 | clock-frequency = <0>; | |
739 | clock-output-names = "extal"; | |
740 | }; | |
741 | ||
0d3dbde8 KM |
742 | /* |
743 | * The external audio clocks are configured as 0 Hz fixed frequency clocks by | |
744 | * default. Boards that provide audio clocks should override them. | |
745 | */ | |
746 | audio_clk_a: audio_clk_a { | |
747 | compatible = "fixed-clock"; | |
748 | #clock-cells = <0>; | |
749 | clock-frequency = <0>; | |
750 | clock-output-names = "audio_clk_a"; | |
751 | }; | |
752 | audio_clk_b: audio_clk_b { | |
753 | compatible = "fixed-clock"; | |
754 | #clock-cells = <0>; | |
755 | clock-frequency = <0>; | |
756 | clock-output-names = "audio_clk_b"; | |
757 | }; | |
758 | audio_clk_c: audio_clk_c { | |
759 | compatible = "fixed-clock"; | |
760 | #clock-cells = <0>; | |
761 | clock-frequency = <0>; | |
762 | clock-output-names = "audio_clk_c"; | |
763 | }; | |
764 | ||
66c405e7 PE |
765 | /* External PCIe clock - can be overridden by the board */ |
766 | pcie_bus_clk: pcie_bus_clk { | |
767 | compatible = "fixed-clock"; | |
768 | #clock-cells = <0>; | |
769 | clock-frequency = <100000000>; | |
770 | clock-output-names = "pcie_bus"; | |
771 | status = "disabled"; | |
772 | }; | |
773 | ||
59e79895 LP |
774 | /* Special CPG clocks */ |
775 | cpg_clocks: cpg_clocks@e6150000 { | |
776 | compatible = "renesas,r8a7791-cpg-clocks", | |
777 | "renesas,rcar-gen2-cpg-clocks"; | |
778 | reg = <0 0xe6150000 0 0x1000>; | |
779 | clocks = <&extal_clk>; | |
780 | #clock-cells = <1>; | |
781 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
782 | "lb", "qspi", "sdh", "sd0", "z"; | |
783 | }; | |
784 | ||
785 | /* Variable factor clocks */ | |
786 | sd1_clk: sd2_clk@e6150078 { | |
787 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
788 | reg = <0 0xe6150078 0 4>; | |
789 | clocks = <&pll1_div2_clk>; | |
790 | #clock-cells = <0>; | |
791 | clock-output-names = "sd1"; | |
792 | }; | |
c9b22772 | 793 | sd2_clk: sd3_clk@e615026c { |
59e79895 | 794 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; |
c9b22772 | 795 | reg = <0 0xe615026c 0 4>; |
59e79895 LP |
796 | clocks = <&pll1_div2_clk>; |
797 | #clock-cells = <0>; | |
798 | clock-output-names = "sd2"; | |
799 | }; | |
800 | mmc0_clk: mmc0_clk@e6150240 { | |
801 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
802 | reg = <0 0xe6150240 0 4>; | |
803 | clocks = <&pll1_div2_clk>; | |
804 | #clock-cells = <0>; | |
805 | clock-output-names = "mmc0"; | |
806 | }; | |
807 | ssp_clk: ssp_clk@e6150248 { | |
808 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
809 | reg = <0 0xe6150248 0 4>; | |
810 | clocks = <&pll1_div2_clk>; | |
811 | #clock-cells = <0>; | |
812 | clock-output-names = "ssp"; | |
813 | }; | |
814 | ssprs_clk: ssprs_clk@e615024c { | |
815 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
816 | reg = <0 0xe615024c 0 4>; | |
817 | clocks = <&pll1_div2_clk>; | |
818 | #clock-cells = <0>; | |
819 | clock-output-names = "ssprs"; | |
820 | }; | |
821 | ||
822 | /* Fixed factor clocks */ | |
823 | pll1_div2_clk: pll1_div2_clk { | |
824 | compatible = "fixed-factor-clock"; | |
825 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
826 | #clock-cells = <0>; | |
827 | clock-div = <2>; | |
828 | clock-mult = <1>; | |
829 | clock-output-names = "pll1_div2"; | |
830 | }; | |
831 | zg_clk: zg_clk { | |
832 | compatible = "fixed-factor-clock"; | |
833 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
834 | #clock-cells = <0>; | |
835 | clock-div = <3>; | |
836 | clock-mult = <1>; | |
837 | clock-output-names = "zg"; | |
838 | }; | |
839 | zx_clk: zx_clk { | |
840 | compatible = "fixed-factor-clock"; | |
841 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
842 | #clock-cells = <0>; | |
843 | clock-div = <3>; | |
844 | clock-mult = <1>; | |
845 | clock-output-names = "zx"; | |
846 | }; | |
847 | zs_clk: zs_clk { | |
848 | compatible = "fixed-factor-clock"; | |
849 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
850 | #clock-cells = <0>; | |
851 | clock-div = <6>; | |
852 | clock-mult = <1>; | |
853 | clock-output-names = "zs"; | |
854 | }; | |
855 | hp_clk: hp_clk { | |
856 | compatible = "fixed-factor-clock"; | |
857 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
858 | #clock-cells = <0>; | |
859 | clock-div = <12>; | |
860 | clock-mult = <1>; | |
861 | clock-output-names = "hp"; | |
862 | }; | |
863 | i_clk: i_clk { | |
864 | compatible = "fixed-factor-clock"; | |
865 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
866 | #clock-cells = <0>; | |
867 | clock-div = <2>; | |
868 | clock-mult = <1>; | |
869 | clock-output-names = "i"; | |
870 | }; | |
871 | b_clk: b_clk { | |
872 | compatible = "fixed-factor-clock"; | |
873 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
874 | #clock-cells = <0>; | |
875 | clock-div = <12>; | |
876 | clock-mult = <1>; | |
877 | clock-output-names = "b"; | |
878 | }; | |
879 | p_clk: p_clk { | |
880 | compatible = "fixed-factor-clock"; | |
881 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
882 | #clock-cells = <0>; | |
883 | clock-div = <24>; | |
884 | clock-mult = <1>; | |
885 | clock-output-names = "p"; | |
886 | }; | |
887 | cl_clk: cl_clk { | |
888 | compatible = "fixed-factor-clock"; | |
889 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
890 | #clock-cells = <0>; | |
891 | clock-div = <48>; | |
892 | clock-mult = <1>; | |
893 | clock-output-names = "cl"; | |
894 | }; | |
895 | m2_clk: m2_clk { | |
896 | compatible = "fixed-factor-clock"; | |
897 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
898 | #clock-cells = <0>; | |
899 | clock-div = <8>; | |
900 | clock-mult = <1>; | |
901 | clock-output-names = "m2"; | |
902 | }; | |
903 | imp_clk: imp_clk { | |
904 | compatible = "fixed-factor-clock"; | |
905 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
906 | #clock-cells = <0>; | |
907 | clock-div = <4>; | |
908 | clock-mult = <1>; | |
909 | clock-output-names = "imp"; | |
910 | }; | |
911 | rclk_clk: rclk_clk { | |
912 | compatible = "fixed-factor-clock"; | |
913 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
914 | #clock-cells = <0>; | |
915 | clock-div = <(48 * 1024)>; | |
916 | clock-mult = <1>; | |
917 | clock-output-names = "rclk"; | |
918 | }; | |
919 | oscclk_clk: oscclk_clk { | |
920 | compatible = "fixed-factor-clock"; | |
921 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
922 | #clock-cells = <0>; | |
923 | clock-div = <(12 * 1024)>; | |
924 | clock-mult = <1>; | |
925 | clock-output-names = "oscclk"; | |
926 | }; | |
927 | zb3_clk: zb3_clk { | |
928 | compatible = "fixed-factor-clock"; | |
929 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
930 | #clock-cells = <0>; | |
931 | clock-div = <4>; | |
932 | clock-mult = <1>; | |
933 | clock-output-names = "zb3"; | |
934 | }; | |
935 | zb3d2_clk: zb3d2_clk { | |
936 | compatible = "fixed-factor-clock"; | |
937 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
938 | #clock-cells = <0>; | |
939 | clock-div = <8>; | |
940 | clock-mult = <1>; | |
941 | clock-output-names = "zb3d2"; | |
942 | }; | |
943 | ddr_clk: ddr_clk { | |
944 | compatible = "fixed-factor-clock"; | |
945 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
946 | #clock-cells = <0>; | |
947 | clock-div = <8>; | |
948 | clock-mult = <1>; | |
949 | clock-output-names = "ddr"; | |
950 | }; | |
951 | mp_clk: mp_clk { | |
952 | compatible = "fixed-factor-clock"; | |
953 | clocks = <&pll1_div2_clk>; | |
954 | #clock-cells = <0>; | |
955 | clock-div = <15>; | |
956 | clock-mult = <1>; | |
957 | clock-output-names = "mp"; | |
958 | }; | |
959 | cp_clk: cp_clk { | |
960 | compatible = "fixed-factor-clock"; | |
961 | clocks = <&extal_clk>; | |
962 | #clock-cells = <0>; | |
963 | clock-div = <2>; | |
964 | clock-mult = <1>; | |
965 | clock-output-names = "cp"; | |
966 | }; | |
967 | ||
968 | /* Gate clocks */ | |
cded80f8 LP |
969 | mstp0_clks: mstp0_clks@e6150130 { |
970 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
971 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; | |
972 | clocks = <&mp_clk>; | |
973 | #clock-cells = <1>; | |
974 | renesas,clock-indices = <R8A7791_CLK_MSIOF0>; | |
975 | clock-output-names = "msiof0"; | |
976 | }; | |
59e79895 LP |
977 | mstp1_clks: mstp1_clks@e6150134 { |
978 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
979 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
ed48b5d6 | 980 | clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, |
59e79895 LP |
981 | <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; |
982 | #clock-cells = <1>; | |
983 | renesas,clock-indices = < | |
ed48b5d6 | 984 | R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 |
59e79895 | 985 | R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 |
58ea1d53 | 986 | R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S |
59e79895 LP |
987 | >; |
988 | clock-output-names = | |
ed48b5d6 | 989 | "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", |
59e79895 LP |
990 | "vsp1-du0", "vsp1-sy"; |
991 | }; | |
992 | mstp2_clks: mstp2_clks@e6150138 { | |
993 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
994 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
995 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
4e074bc8 GU |
996 | <&mp_clk>, <&mp_clk>, <&mp_clk>, |
997 | <&zs_clk>, <&zs_clk>; | |
59e79895 LP |
998 | #clock-cells = <1>; |
999 | renesas,clock-indices = < | |
1000 | R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 | |
cded80f8 LP |
1001 | R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 |
1002 | R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 | |
4e074bc8 | 1003 | R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 |
59e79895 LP |
1004 | >; |
1005 | clock-output-names = | |
0c002ef8 | 1006 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
4e074bc8 GU |
1007 | "scifb1", "msiof1", "scifb2", |
1008 | "sys-dmac1", "sys-dmac0"; | |
59e79895 LP |
1009 | }; |
1010 | mstp3_clks: mstp3_clks@e615013c { | |
1011 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1012 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
c08691b5 | 1013 | clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, |
4bfb3767 | 1014 | <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; |
59e79895 LP |
1015 | #clock-cells = <1>; |
1016 | renesas,clock-indices = < | |
c08691b5 | 1017 | R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 |
4bfb3767 PE |
1018 | R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 |
1019 | R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 | |
59e79895 LP |
1020 | >; |
1021 | clock-output-names = | |
c08691b5 | 1022 | "tpu0", "sdhi2", "sdhi1", "sdhi0", |
4bfb3767 | 1023 | "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1"; |
59e79895 LP |
1024 | }; |
1025 | mstp5_clks: mstp5_clks@e6150144 { | |
1026 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1027 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; | |
1028 | clocks = <&extal_clk>, <&p_clk>; | |
1029 | #clock-cells = <1>; | |
1030 | renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; | |
1031 | clock-output-names = "thermal", "pwm"; | |
1032 | }; | |
1033 | mstp7_clks: mstp7_clks@e615014c { | |
1034 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1035 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
6225b99a | 1036 | clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, |
59e79895 LP |
1037 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
1038 | <&zx_clk>, <&zx_clk>, <&zx_clk>; | |
1039 | #clock-cells = <1>; | |
1040 | renesas,clock-indices = < | |
6225b99a | 1041 | R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 |
59e79895 LP |
1042 | R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 |
1043 | R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 | |
1044 | R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 | |
1045 | R8A7791_CLK_LVDS0 | |
1046 | >; | |
1047 | clock-output-names = | |
6225b99a | 1048 | "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", |
59e79895 LP |
1049 | "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; |
1050 | }; | |
1051 | mstp8_clks: mstp8_clks@e6150990 { | |
1052 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1053 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
65f05c38 LP |
1054 | clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, |
1055 | <&zs_clk>; | |
59e79895 | 1056 | #clock-cells = <1>; |
09c98346 LP |
1057 | renesas,clock-indices = < |
1058 | R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 | |
65f05c38 | 1059 | R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 |
09c98346 | 1060 | >; |
65f05c38 LP |
1061 | clock-output-names = |
1062 | "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; | |
59e79895 LP |
1063 | }; |
1064 | mstp9_clks: mstp9_clks@e6150994 { | |
1065 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1066 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
4faf9c5e GU |
1067 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
1068 | <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, | |
1069 | <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, | |
11b48db9 LP |
1070 | <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, |
1071 | <&hp_clk>, <&hp_clk>; | |
59e79895 LP |
1072 | #clock-cells = <1>; |
1073 | renesas,clock-indices = < | |
4faf9c5e GU |
1074 | R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 |
1075 | R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 | |
c08691b5 WS |
1076 | R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 |
1077 | R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 | |
1078 | R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 | |
59e79895 LP |
1079 | >; |
1080 | clock-output-names = | |
4faf9c5e GU |
1081 | "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", |
1082 | "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", | |
1083 | "i2c1", "i2c0"; | |
59e79895 | 1084 | }; |
ee914152 KM |
1085 | mstp10_clks: mstp10_clks@e6150998 { |
1086 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1087 | reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; | |
1088 | clocks = <&p_clk>, | |
1089 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
1090 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
1091 | <&p_clk>, | |
1092 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
1093 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
1094 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
1095 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
1096 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
1097 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; | |
1098 | ||
1099 | #clock-cells = <1>; | |
1100 | clock-indices = < | |
1101 | R8A7791_CLK_SSI_ALL | |
1102 | R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 | |
1103 | R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 | |
1104 | R8A7791_CLK_SCU_ALL | |
1105 | R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 | |
1106 | R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 | |
1107 | R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 | |
1108 | >; | |
1109 | clock-output-names = | |
1110 | "ssi-all", | |
1111 | "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", | |
1112 | "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", | |
1113 | "scu-all", | |
1114 | "scu-dvc1", "scu-dvc0", | |
1115 | "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", | |
1116 | "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; | |
1117 | }; | |
59e79895 LP |
1118 | mstp11_clks: mstp11_clks@e615099c { |
1119 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1120 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; | |
1121 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; | |
1122 | #clock-cells = <1>; | |
1123 | renesas,clock-indices = < | |
1124 | R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 | |
1125 | >; | |
1126 | clock-output-names = "scifa3", "scifa4", "scifa5"; | |
1127 | }; | |
1128 | }; | |
4d5b59cd | 1129 | |
6f3e4ee3 | 1130 | qspi: spi@e6b10000 { |
4d5b59cd GU |
1131 | compatible = "renesas,qspi-r8a7791", "renesas,qspi"; |
1132 | reg = <0 0xe6b10000 0 0x2c>; | |
4d5b59cd GU |
1133 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
1134 | clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; | |
591f2fa4 GU |
1135 | dmas = <&dmac0 0x17>, <&dmac0 0x18>; |
1136 | dma-names = "tx", "rx"; | |
4d5b59cd GU |
1137 | num-cs = <1>; |
1138 | #address-cells = <1>; | |
1139 | #size-cells = <0>; | |
1140 | status = "disabled"; | |
1141 | }; | |
7713d3ab GU |
1142 | |
1143 | msiof0: spi@e6e20000 { | |
1144 | compatible = "renesas,msiof-r8a7791"; | |
a5ce27f5 | 1145 | reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; |
7713d3ab GU |
1146 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; |
1147 | clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; | |
a5ce27f5 GU |
1148 | dmas = <&dmac0 0x51>, <&dmac0 0x52>; |
1149 | dma-names = "tx", "rx"; | |
7713d3ab GU |
1150 | #address-cells = <1>; |
1151 | #size-cells = <0>; | |
1152 | status = "disabled"; | |
1153 | }; | |
1154 | ||
1155 | msiof1: spi@e6e10000 { | |
1156 | compatible = "renesas,msiof-r8a7791"; | |
a5ce27f5 | 1157 | reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>; |
7713d3ab GU |
1158 | interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; |
1159 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; | |
a5ce27f5 GU |
1160 | dmas = <&dmac0 0x55>, <&dmac0 0x56>; |
1161 | dma-names = "tx", "rx"; | |
7713d3ab GU |
1162 | #address-cells = <1>; |
1163 | #size-cells = <0>; | |
1164 | status = "disabled"; | |
1165 | }; | |
1166 | ||
1167 | msiof2: spi@e6e00000 { | |
1168 | compatible = "renesas,msiof-r8a7791"; | |
a5ce27f5 | 1169 | reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>; |
7713d3ab GU |
1170 | interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; |
1171 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; | |
a5ce27f5 GU |
1172 | dmas = <&dmac0 0x41>, <&dmac0 0x42>; |
1173 | dma-names = "tx", "rx"; | |
7713d3ab GU |
1174 | #address-cells = <1>; |
1175 | #size-cells = <0>; | |
1176 | status = "disabled"; | |
1177 | }; | |
811cdfae | 1178 | |
aace0809 SS |
1179 | pci0: pci@ee090000 { |
1180 | compatible = "renesas,pci-r8a7791"; | |
1181 | device_type = "pci"; | |
1182 | clocks = <&mstp7_clks R8A7791_CLK_EHCI>; | |
1183 | reg = <0 0xee090000 0 0xc00>, | |
1184 | <0 0xee080000 0 0x1100>; | |
1185 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | |
1186 | status = "disabled"; | |
1187 | ||
1188 | bus-range = <0 0>; | |
1189 | #address-cells = <3>; | |
1190 | #size-cells = <2>; | |
1191 | #interrupt-cells = <1>; | |
1192 | ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; | |
1193 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
1194 | interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH | |
1195 | 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH | |
1196 | 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; | |
1197 | }; | |
1198 | ||
1199 | pci1: pci@ee0d0000 { | |
1200 | compatible = "renesas,pci-r8a7791"; | |
1201 | device_type = "pci"; | |
1202 | clocks = <&mstp7_clks R8A7791_CLK_EHCI>; | |
1203 | reg = <0 0xee0d0000 0 0xc00>, | |
1204 | <0 0xee0c0000 0 0x1100>; | |
1205 | interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; | |
1206 | status = "disabled"; | |
1207 | ||
1208 | bus-range = <1 1>; | |
1209 | #address-cells = <3>; | |
1210 | #size-cells = <2>; | |
1211 | #interrupt-cells = <1>; | |
1212 | ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; | |
1213 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
1214 | interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH | |
1215 | 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH | |
1216 | 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; | |
1217 | }; | |
1218 | ||
811cdfae PE |
1219 | pciec: pcie@fe000000 { |
1220 | compatible = "renesas,pcie-r8a7791"; | |
1221 | reg = <0 0xfe000000 0 0x80000>; | |
1222 | #address-cells = <3>; | |
1223 | #size-cells = <2>; | |
1224 | bus-range = <0x00 0xff>; | |
1225 | device_type = "pci"; | |
1226 | ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 | |
1227 | 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 | |
1228 | 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 | |
1229 | 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; | |
1230 | /* Map all possible DDR as inbound ranges */ | |
1231 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 | |
1232 | 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; | |
1233 | interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, | |
1234 | <0 117 IRQ_TYPE_LEVEL_HIGH>, | |
1235 | <0 118 IRQ_TYPE_LEVEL_HIGH>; | |
1236 | #interrupt-cells = <1>; | |
1237 | interrupt-map-mask = <0 0 0 0>; | |
1238 | interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; | |
1239 | clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; | |
1240 | clock-names = "pcie", "pcie_bus"; | |
1241 | status = "disabled"; | |
1242 | }; | |
09abd1fd KM |
1243 | |
1244 | rcar_sound: rcar_sound@0xec500000 { | |
1245 | #sound-dai-cells = <1>; | |
1246 | compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; | |
09abd1fd KM |
1247 | reg = <0 0xec500000 0 0x1000>, /* SCU */ |
1248 | <0 0xec5a0000 0 0x100>, /* ADG */ | |
1249 | <0 0xec540000 0 0x1000>, /* SSIU */ | |
1250 | <0 0xec541000 0 0x1280>; /* SSI */ | |
1251 | clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, | |
1252 | <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, | |
1253 | <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>, | |
1254 | <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>, | |
1255 | <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>, | |
1256 | <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>, | |
1257 | <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>, | |
1258 | <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>, | |
1259 | <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, | |
1260 | <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, | |
1261 | <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, | |
150c8ad4 | 1262 | <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, |
09abd1fd KM |
1263 | <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; |
1264 | clock-names = "ssi-all", | |
1265 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", | |
1266 | "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", | |
1267 | "src.9", "src.8", "src.7", "src.6", "src.5", | |
1268 | "src.4", "src.3", "src.2", "src.1", "src.0", | |
150c8ad4 | 1269 | "dvc.0", "dvc.1", |
09abd1fd KM |
1270 | "clk_a", "clk_b", "clk_c", "clk_i"; |
1271 | ||
1272 | status = "disabled"; | |
1273 | ||
150c8ad4 KM |
1274 | rcar_sound,dvc { |
1275 | dvc0: dvc@0 { }; | |
1276 | dvc1: dvc@1 { }; | |
1277 | }; | |
1278 | ||
09abd1fd KM |
1279 | rcar_sound,src { |
1280 | src0: src@0 { }; | |
1281 | src1: src@1 { }; | |
1282 | src2: src@2 { }; | |
1283 | src3: src@3 { }; | |
1284 | src4: src@4 { }; | |
1285 | src5: src@5 { }; | |
1286 | src6: src@6 { }; | |
1287 | src7: src@7 { }; | |
1288 | src8: src@8 { }; | |
1289 | src9: src@9 { }; | |
1290 | }; | |
1291 | ||
1292 | rcar_sound,ssi { | |
1293 | ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; }; | |
1294 | ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; }; | |
1295 | ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; }; | |
1296 | ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; }; | |
1297 | ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; }; | |
1298 | ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; }; | |
1299 | ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; }; | |
1300 | ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; }; | |
1301 | ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; }; | |
1302 | ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; }; | |
1303 | }; | |
1304 | }; | |
0d0771ab | 1305 | }; |