projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 0d0771ab HN |
1 | /* |
| 2 | * Device Tree Source for the r8a7791 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2013 Renesas Electronics Corporation | |
| 2e5d55ce SS |
5 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
| 6 | * Copyright (C) 2014 Cogent Embedded Inc. | |
| 0d0771ab HN |
7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public License | |
| 9 | * version 2. This program is licensed "as is" without any warranty of any | |
| 10 | * kind, whether express or implied. | |
| 11 | */ | |
| 12 | ||
| 59e79895 | 13 | #include <dt-bindings/clock/r8a7791-clock.h> |
| 5f75e73c LP |
14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 16 | ||
| 0d0771ab HN |
17 | / { |
| 18 | compatible = "renesas,r8a7791"; | |
| 19 | interrupt-parent = <&gic>; | |
| 20 | #address-cells = <2>; | |
| 21 | #size-cells = <2>; | |
| 22 | ||
| 5bd3de7b WS |
23 | aliases { |
| 24 | i2c0 = &i2c0; | |
| 25 | i2c1 = &i2c1; | |
| 26 | i2c2 = &i2c2; | |
| 27 | i2c3 = &i2c3; | |
| 28 | i2c4 = &i2c4; | |
| 29 | i2c5 = &i2c5; | |
| 36408d9d WS |
30 | i2c6 = &i2c6; |
| 31 | i2c7 = &i2c7; | |
| 32 | i2c8 = &i2c8; | |
| 6f3e4ee3 | 33 | spi0 = &qspi; |
| 7713d3ab GU |
34 | spi1 = &msiof0; |
| 35 | spi2 = &msiof1; | |
| 36 | spi3 = &msiof2; | |
| 5bd3de7b WS |
37 | }; |
| 38 | ||
| 0d0771ab HN |
39 | cpus { |
| 40 | #address-cells = <1>; | |
| 41 | #size-cells = <0>; | |
| 42 | ||
| 43 | cpu0: cpu@0 { | |
| 44 | device_type = "cpu"; | |
| 45 | compatible = "arm,cortex-a15"; | |
| 46 | reg = <0>; | |
| 896b79df | 47 | clock-frequency = <1500000000>; |
| a57004ec GI |
48 | voltage-tolerance = <1>; /* 1% */ |
| 49 | clocks = <&cpg_clocks R8A7791_CLK_Z>; | |
| 50 | clock-latency = <300000>; /* 300 us */ | |
| 51 | ||
| 52 | /* kHz - uV - OPPs unknown yet */ | |
| 53 | operating-points = <1500000 1000000>, | |
| 54 | <1312500 1000000>, | |
| 55 | <1125000 1000000>, | |
| 56 | < 937500 1000000>, | |
| 57 | < 750000 1000000>, | |
| 58 | < 375000 1000000>; | |
| 0d0771ab | 59 | }; |
| 15ab426c MD |
60 | |
| 61 | cpu1: cpu@1 { | |
| 62 | device_type = "cpu"; | |
| 63 | compatible = "arm,cortex-a15"; | |
| 64 | reg = <1>; | |
| 896b79df | 65 | clock-frequency = <1500000000>; |
| 15ab426c | 66 | }; |
| 0d0771ab HN |
67 | }; |
| 68 | ||
| 69 | gic: interrupt-controller@f1001000 { | |
| 70 | compatible = "arm,cortex-a15-gic"; | |
| 71 | #interrupt-cells = <3>; | |
| 72 | #address-cells = <0>; | |
| 73 | interrupt-controller; | |
| 74 | reg = <0 0xf1001000 0 0x1000>, | |
| 75 | <0 0xf1002000 0 0x1000>, | |
| 76 | <0 0xf1004000 0 0x2000>, | |
| 77 | <0 0xf1006000 0 0x2000>; | |
| 5f75e73c | 78 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| 0d0771ab | 79 | }; |
| d77db73e | 80 | |
| 89fbba12 | 81 | gpio0: gpio@e6050000 { |
| ab87e3fc | 82 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 83 | reg = <0 0xe6050000 0 0x50>; |
| 5f75e73c | 84 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
85 | #gpio-cells = <2>; |
| 86 | gpio-controller; | |
| 87 | gpio-ranges = <&pfc 0 0 32>; | |
| 88 | #interrupt-cells = <2>; | |
| 89 | interrupt-controller; | |
| 4faf9c5e | 90 | clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; |
| ab87e3fc MD |
91 | }; |
| 92 | ||
| 89fbba12 | 93 | gpio1: gpio@e6051000 { |
| ab87e3fc | 94 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 95 | reg = <0 0xe6051000 0 0x50>; |
| 5f75e73c | 96 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
97 | #gpio-cells = <2>; |
| 98 | gpio-controller; | |
| 99 | gpio-ranges = <&pfc 0 32 32>; | |
| 100 | #interrupt-cells = <2>; | |
| 101 | interrupt-controller; | |
| 4faf9c5e | 102 | clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; |
| ab87e3fc MD |
103 | }; |
| 104 | ||
| 89fbba12 | 105 | gpio2: gpio@e6052000 { |
| ab87e3fc | 106 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 107 | reg = <0 0xe6052000 0 0x50>; |
| 5f75e73c | 108 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
109 | #gpio-cells = <2>; |
| 110 | gpio-controller; | |
| 111 | gpio-ranges = <&pfc 0 64 32>; | |
| 112 | #interrupt-cells = <2>; | |
| 113 | interrupt-controller; | |
| 4faf9c5e | 114 | clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; |
| ab87e3fc MD |
115 | }; |
| 116 | ||
| 89fbba12 | 117 | gpio3: gpio@e6053000 { |
| ab87e3fc | 118 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 119 | reg = <0 0xe6053000 0 0x50>; |
| 5f75e73c | 120 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
121 | #gpio-cells = <2>; |
| 122 | gpio-controller; | |
| 123 | gpio-ranges = <&pfc 0 96 32>; | |
| 124 | #interrupt-cells = <2>; | |
| 125 | interrupt-controller; | |
| 4faf9c5e | 126 | clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; |
| ab87e3fc MD |
127 | }; |
| 128 | ||
| 89fbba12 | 129 | gpio4: gpio@e6054000 { |
| ab87e3fc | 130 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 131 | reg = <0 0xe6054000 0 0x50>; |
| 5f75e73c | 132 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
133 | #gpio-cells = <2>; |
| 134 | gpio-controller; | |
| 135 | gpio-ranges = <&pfc 0 128 32>; | |
| 136 | #interrupt-cells = <2>; | |
| 137 | interrupt-controller; | |
| 4faf9c5e | 138 | clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; |
| ab87e3fc MD |
139 | }; |
| 140 | ||
| 89fbba12 | 141 | gpio5: gpio@e6055000 { |
| ab87e3fc | 142 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 143 | reg = <0 0xe6055000 0 0x50>; |
| 5f75e73c | 144 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
145 | #gpio-cells = <2>; |
| 146 | gpio-controller; | |
| 147 | gpio-ranges = <&pfc 0 160 32>; | |
| 148 | #interrupt-cells = <2>; | |
| 149 | interrupt-controller; | |
| 4faf9c5e | 150 | clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; |
| ab87e3fc MD |
151 | }; |
| 152 | ||
| 89fbba12 | 153 | gpio6: gpio@e6055400 { |
| ab87e3fc | 154 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 155 | reg = <0 0xe6055400 0 0x50>; |
| 5f75e73c | 156 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
157 | #gpio-cells = <2>; |
| 158 | gpio-controller; | |
| 159 | gpio-ranges = <&pfc 0 192 32>; | |
| 160 | #interrupt-cells = <2>; | |
| 161 | interrupt-controller; | |
| 4faf9c5e | 162 | clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; |
| ab87e3fc MD |
163 | }; |
| 164 | ||
| 89fbba12 | 165 | gpio7: gpio@e6055800 { |
| ab87e3fc | 166 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 167 | reg = <0 0xe6055800 0 0x50>; |
| 5f75e73c | 168 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
169 | #gpio-cells = <2>; |
| 170 | gpio-controller; | |
| 171 | gpio-ranges = <&pfc 0 224 26>; | |
| 172 | #interrupt-cells = <2>; | |
| 173 | interrupt-controller; | |
| 4faf9c5e | 174 | clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; |
| ab87e3fc MD |
175 | }; |
| 176 | ||
| d103f4d3 MD |
177 | thermal@e61f0000 { |
| 178 | compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal"; | |
| 179 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; | |
| d103f4d3 | 180 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
| 563bc8eb | 181 | clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; |
| d103f4d3 MD |
182 | }; |
| 183 | ||
| 03586acf MD |
184 | timer { |
| 185 | compatible = "arm,armv7-timer"; | |
| 5f75e73c LP |
186 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 187 | <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 188 | <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 189 | <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
| 03586acf MD |
190 | }; |
| 191 | ||
| d77db73e | 192 | irqc0: interrupt-controller@e61c0000 { |
| 26041b06 | 193 | compatible = "renesas,irqc-r8a7791", "renesas,irqc"; |
| d77db73e MD |
194 | #interrupt-cells = <2>; |
| 195 | interrupt-controller; | |
| 196 | reg = <0 0xe61c0000 0 0x200>; | |
| 5f75e73c LP |
197 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
| 198 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | |
| 199 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | |
| 200 | <0 3 IRQ_TYPE_LEVEL_HIGH>, | |
| 201 | <0 12 IRQ_TYPE_LEVEL_HIGH>, | |
| 202 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
| 203 | <0 14 IRQ_TYPE_LEVEL_HIGH>, | |
| 204 | <0 15 IRQ_TYPE_LEVEL_HIGH>, | |
| 205 | <0 16 IRQ_TYPE_LEVEL_HIGH>, | |
| 206 | <0 17 IRQ_TYPE_LEVEL_HIGH>; | |
| d77db73e | 207 | }; |
| 55146927 | 208 | |
| 36408d9d | 209 | /* The memory map in the User's Manual maps the cores to bus numbers */ |
| 5bd3de7b WS |
210 | i2c0: i2c@e6508000 { |
| 211 | #address-cells = <1>; | |
| 212 | #size-cells = <0>; | |
| 213 | compatible = "renesas,i2c-r8a7791"; | |
| 214 | reg = <0 0xe6508000 0 0x40>; | |
| 215 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; | |
| 216 | clocks = <&mstp9_clks R8A7791_CLK_I2C0>; | |
| 217 | status = "disabled"; | |
| 218 | }; | |
| 219 | ||
| 220 | i2c1: i2c@e6518000 { | |
| 221 | #address-cells = <1>; | |
| 222 | #size-cells = <0>; | |
| 223 | compatible = "renesas,i2c-r8a7791"; | |
| 224 | reg = <0 0xe6518000 0 0x40>; | |
| 225 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; | |
| 226 | clocks = <&mstp9_clks R8A7791_CLK_I2C1>; | |
| 227 | status = "disabled"; | |
| 228 | }; | |
| 229 | ||
| 230 | i2c2: i2c@e6530000 { | |
| 231 | #address-cells = <1>; | |
| 232 | #size-cells = <0>; | |
| 233 | compatible = "renesas,i2c-r8a7791"; | |
| 234 | reg = <0 0xe6530000 0 0x40>; | |
| 235 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; | |
| 236 | clocks = <&mstp9_clks R8A7791_CLK_I2C2>; | |
| 237 | status = "disabled"; | |
| 238 | }; | |
| 239 | ||
| 240 | i2c3: i2c@e6540000 { | |
| 241 | #address-cells = <1>; | |
| 242 | #size-cells = <0>; | |
| 243 | compatible = "renesas,i2c-r8a7791"; | |
| 244 | reg = <0 0xe6540000 0 0x40>; | |
| 245 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; | |
| 246 | clocks = <&mstp9_clks R8A7791_CLK_I2C3>; | |
| 247 | status = "disabled"; | |
| 248 | }; | |
| 249 | ||
| 250 | i2c4: i2c@e6520000 { | |
| 251 | #address-cells = <1>; | |
| 252 | #size-cells = <0>; | |
| 253 | compatible = "renesas,i2c-r8a7791"; | |
| 254 | reg = <0 0xe6520000 0 0x40>; | |
| 255 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; | |
| 256 | clocks = <&mstp9_clks R8A7791_CLK_I2C4>; | |
| 257 | status = "disabled"; | |
| 258 | }; | |
| 259 | ||
| 260 | i2c5: i2c@e6528000 { | |
| 36408d9d | 261 | /* doesn't need pinmux */ |
| 5bd3de7b WS |
262 | #address-cells = <1>; |
| 263 | #size-cells = <0>; | |
| 264 | compatible = "renesas,i2c-r8a7791"; | |
| 265 | reg = <0 0xe6528000 0 0x40>; | |
| 266 | interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
| 267 | clocks = <&mstp9_clks R8A7791_CLK_I2C5>; | |
| 268 | status = "disabled"; | |
| 269 | }; | |
| 270 | ||
| 36408d9d WS |
271 | i2c6: i2c@e60b0000 { |
| 272 | /* doesn't need pinmux */ | |
| 273 | #address-cells = <1>; | |
| 274 | #size-cells = <0>; | |
| 275 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
| 276 | reg = <0 0xe60b0000 0 0x425>; | |
| 277 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; | |
| 278 | clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; | |
| 279 | status = "disabled"; | |
| 280 | }; | |
| 281 | ||
| 282 | i2c7: i2c@e6500000 { | |
| 283 | #address-cells = <1>; | |
| 284 | #size-cells = <0>; | |
| 285 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
| 286 | reg = <0 0xe6500000 0 0x425>; | |
| 287 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; | |
| 288 | clocks = <&mstp3_clks R8A7791_CLK_IIC0>; | |
| 289 | status = "disabled"; | |
| 290 | }; | |
| 291 | ||
| 292 | i2c8: i2c@e6510000 { | |
| 293 | #address-cells = <1>; | |
| 294 | #size-cells = <0>; | |
| 295 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
| 296 | reg = <0 0xe6510000 0 0x425>; | |
| 297 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; | |
| 298 | clocks = <&mstp3_clks R8A7791_CLK_IIC1>; | |
| 299 | status = "disabled"; | |
| 300 | }; | |
| 301 | ||
| 55146927 MD |
302 | pfc: pfc@e6060000 { |
| 303 | compatible = "renesas,pfc-r8a7791"; | |
| 304 | reg = <0 0xe6060000 0 0x250>; | |
| 305 | #gpio-range-cells = <3>; | |
| 306 | }; | |
| 59e79895 | 307 | |
| b7ed8a0d MD |
308 | sdhi0: sd@ee100000 { |
| 309 | compatible = "renesas,sdhi-r8a7791"; | |
| 310 | reg = <0 0xee100000 0 0x200>; | |
| b7ed8a0d MD |
311 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
| 312 | clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; | |
| 313 | status = "disabled"; | |
| 314 | }; | |
| 315 | ||
| 316 | sdhi1: sd@ee140000 { | |
| 317 | compatible = "renesas,sdhi-r8a7791"; | |
| 318 | reg = <0 0xee140000 0 0x100>; | |
| b7ed8a0d MD |
319 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
| 320 | clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; | |
| 321 | status = "disabled"; | |
| 322 | }; | |
| 323 | ||
| 324 | sdhi2: sd@ee160000 { | |
| 325 | compatible = "renesas,sdhi-r8a7791"; | |
| 326 | reg = <0 0xee160000 0 0x100>; | |
| b7ed8a0d MD |
327 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; |
| 328 | clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; | |
| 329 | status = "disabled"; | |
| 330 | }; | |
| 331 | ||
| 9640cf25 LP |
332 | scifa0: serial@e6c40000 { |
| 333 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
| 334 | reg = <0 0xe6c40000 0 64>; | |
| 9640cf25 LP |
335 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; |
| 336 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; | |
| 337 | clock-names = "sci_ick"; | |
| 338 | status = "disabled"; | |
| 339 | }; | |
| 340 | ||
| 341 | scifa1: serial@e6c50000 { | |
| 342 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
| 9640cf25 LP |
343 | reg = <0 0xe6c50000 0 64>; |
| 344 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; | |
| 345 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; | |
| 346 | clock-names = "sci_ick"; | |
| 347 | status = "disabled"; | |
| 348 | }; | |
| 349 | ||
| 350 | scifa2: serial@e6c60000 { | |
| 351 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
| 9640cf25 LP |
352 | reg = <0 0xe6c60000 0 64>; |
| 353 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; | |
| 354 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; | |
| 355 | clock-names = "sci_ick"; | |
| 356 | status = "disabled"; | |
| 357 | }; | |
| 358 | ||
| 359 | scifa3: serial@e6c70000 { | |
| 360 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
| 9640cf25 LP |
361 | reg = <0 0xe6c70000 0 64>; |
| 362 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; | |
| 363 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; | |
| 364 | clock-names = "sci_ick"; | |
| 365 | status = "disabled"; | |
| 366 | }; | |
| 367 | ||
| 368 | scifa4: serial@e6c78000 { | |
| 369 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
| 9640cf25 LP |
370 | reg = <0 0xe6c78000 0 64>; |
| 371 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; | |
| 372 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; | |
| 373 | clock-names = "sci_ick"; | |
| 374 | status = "disabled"; | |
| 375 | }; | |
| 376 | ||
| 377 | scifa5: serial@e6c80000 { | |
| 378 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
| 9640cf25 LP |
379 | reg = <0 0xe6c80000 0 64>; |
| 380 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; | |
| 381 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; | |
| 382 | clock-names = "sci_ick"; | |
| 383 | status = "disabled"; | |
| 384 | }; | |
| 385 | ||
| 386 | scifb0: serial@e6c20000 { | |
| 387 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
| 9640cf25 LP |
388 | reg = <0 0xe6c20000 0 64>; |
| 389 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; | |
| 390 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; | |
| 391 | clock-names = "sci_ick"; | |
| 392 | status = "disabled"; | |
| 393 | }; | |
| 394 | ||
| 395 | scifb1: serial@e6c30000 { | |
| 396 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
| 9640cf25 LP |
397 | reg = <0 0xe6c30000 0 64>; |
| 398 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; | |
| 399 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; | |
| 400 | clock-names = "sci_ick"; | |
| 401 | status = "disabled"; | |
| 402 | }; | |
| 403 | ||
| 404 | scifb2: serial@e6ce0000 { | |
| 405 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
| 9640cf25 LP |
406 | reg = <0 0xe6ce0000 0 64>; |
| 407 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; | |
| 408 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; | |
| 409 | clock-names = "sci_ick"; | |
| 410 | status = "disabled"; | |
| 411 | }; | |
| 412 | ||
| 413 | scif0: serial@e6e60000 { | |
| 414 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
| 9640cf25 LP |
415 | reg = <0 0xe6e60000 0 64>; |
| 416 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; | |
| 417 | clocks = <&mstp7_clks R8A7791_CLK_SCIF0>; | |
| 418 | clock-names = "sci_ick"; | |
| 419 | status = "disabled"; | |
| 420 | }; | |
| 421 | ||
| 422 | scif1: serial@e6e68000 { | |
| 423 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
| 9640cf25 LP |
424 | reg = <0 0xe6e68000 0 64>; |
| 425 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; | |
| 426 | clocks = <&mstp7_clks R8A7791_CLK_SCIF1>; | |
| 427 | clock-names = "sci_ick"; | |
| 428 | status = "disabled"; | |
| 429 | }; | |
| 430 | ||
| 431 | scif2: serial@e6e58000 { | |
| 432 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
| 9640cf25 LP |
433 | reg = <0 0xe6e58000 0 64>; |
| 434 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; | |
| 435 | clocks = <&mstp7_clks R8A7791_CLK_SCIF2>; | |
| 436 | clock-names = "sci_ick"; | |
| 437 | status = "disabled"; | |
| 438 | }; | |
| 439 | ||
| 440 | scif3: serial@e6ea8000 { | |
| 441 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
| 9640cf25 LP |
442 | reg = <0 0xe6ea8000 0 64>; |
| 443 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; | |
| 444 | clocks = <&mstp7_clks R8A7791_CLK_SCIF3>; | |
| 445 | clock-names = "sci_ick"; | |
| 446 | status = "disabled"; | |
| 447 | }; | |
| 448 | ||
| 449 | scif4: serial@e6ee0000 { | |
| 450 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
| 9640cf25 LP |
451 | reg = <0 0xe6ee0000 0 64>; |
| 452 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; | |
| 453 | clocks = <&mstp7_clks R8A7791_CLK_SCIF4>; | |
| 454 | clock-names = "sci_ick"; | |
| 455 | status = "disabled"; | |
| 456 | }; | |
| 457 | ||
| 458 | scif5: serial@e6ee8000 { | |
| 459 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
| 9640cf25 LP |
460 | reg = <0 0xe6ee8000 0 64>; |
| 461 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; | |
| 462 | clocks = <&mstp7_clks R8A7791_CLK_SCIF5>; | |
| 463 | clock-names = "sci_ick"; | |
| 464 | status = "disabled"; | |
| 465 | }; | |
| 466 | ||
| 467 | hscif0: serial@e62c0000 { | |
| 468 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
| 9640cf25 LP |
469 | reg = <0 0xe62c0000 0 96>; |
| 470 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; | |
| 471 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>; | |
| 472 | clock-names = "sci_ick"; | |
| 473 | status = "disabled"; | |
| 474 | }; | |
| 475 | ||
| 476 | hscif1: serial@e62c8000 { | |
| 477 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
| 9640cf25 LP |
478 | reg = <0 0xe62c8000 0 96>; |
| 479 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; | |
| 480 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>; | |
| 481 | clock-names = "sci_ick"; | |
| 482 | status = "disabled"; | |
| 483 | }; | |
| 484 | ||
| 485 | hscif2: serial@e62d0000 { | |
| 486 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
| 9640cf25 LP |
487 | reg = <0 0xe62d0000 0 96>; |
| 488 | interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; | |
| 489 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>; | |
| 490 | clock-names = "sci_ick"; | |
| 491 | status = "disabled"; | |
| 492 | }; | |
| 493 | ||
| 2e5d55ce SS |
494 | ether: ethernet@ee700000 { |
| 495 | compatible = "renesas,ether-r8a7791"; | |
| 496 | reg = <0 0xee700000 0 0x400>; | |
| 497 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; | |
| 498 | clocks = <&mstp8_clks R8A7791_CLK_ETHER>; | |
| 499 | phy-mode = "rmii"; | |
| 500 | #address-cells = <1>; | |
| 501 | #size-cells = <0>; | |
| 502 | status = "disabled"; | |
| 503 | }; | |
| 504 | ||
| b8532c69 VB |
505 | sata0: sata@ee300000 { |
| 506 | compatible = "renesas,sata-r8a7791"; | |
| 507 | reg = <0 0xee300000 0 0x2000>; | |
| b8532c69 VB |
508 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; |
| 509 | clocks = <&mstp8_clks R8A7791_CLK_SATA0>; | |
| 510 | status = "disabled"; | |
| 511 | }; | |
| 512 | ||
| 513 | sata1: sata@ee500000 { | |
| 514 | compatible = "renesas,sata-r8a7791"; | |
| 515 | reg = <0 0xee500000 0 0x2000>; | |
| b8532c69 VB |
516 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
| 517 | clocks = <&mstp8_clks R8A7791_CLK_SATA1>; | |
| 518 | status = "disabled"; | |
| 519 | }; | |
| 520 | ||
| 59e79895 LP |
521 | clocks { |
| 522 | #address-cells = <2>; | |
| 523 | #size-cells = <2>; | |
| 524 | ranges; | |
| 525 | ||
| 526 | /* External root clock */ | |
| 527 | extal_clk: extal_clk { | |
| 528 | compatible = "fixed-clock"; | |
| 529 | #clock-cells = <0>; | |
| 530 | /* This value must be overriden by the board. */ | |
| 531 | clock-frequency = <0>; | |
| 532 | clock-output-names = "extal"; | |
| 533 | }; | |
| 534 | ||
| 0d3dbde8 KM |
535 | /* |
| 536 | * The external audio clocks are configured as 0 Hz fixed frequency clocks by | |
| 537 | * default. Boards that provide audio clocks should override them. | |
| 538 | */ | |
| 539 | audio_clk_a: audio_clk_a { | |
| 540 | compatible = "fixed-clock"; | |
| 541 | #clock-cells = <0>; | |
| 542 | clock-frequency = <0>; | |
| 543 | clock-output-names = "audio_clk_a"; | |
| 544 | }; | |
| 545 | audio_clk_b: audio_clk_b { | |
| 546 | compatible = "fixed-clock"; | |
| 547 | #clock-cells = <0>; | |
| 548 | clock-frequency = <0>; | |
| 549 | clock-output-names = "audio_clk_b"; | |
| 550 | }; | |
| 551 | audio_clk_c: audio_clk_c { | |
| 552 | compatible = "fixed-clock"; | |
| 553 | #clock-cells = <0>; | |
| 554 | clock-frequency = <0>; | |
| 555 | clock-output-names = "audio_clk_c"; | |
| 556 | }; | |
| 557 | ||
| 59e79895 LP |
558 | /* Special CPG clocks */ |
| 559 | cpg_clocks: cpg_clocks@e6150000 { | |
| 560 | compatible = "renesas,r8a7791-cpg-clocks", | |
| 561 | "renesas,rcar-gen2-cpg-clocks"; | |
| 562 | reg = <0 0xe6150000 0 0x1000>; | |
| 563 | clocks = <&extal_clk>; | |
| 564 | #clock-cells = <1>; | |
| 565 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
| 566 | "lb", "qspi", "sdh", "sd0", "z"; | |
| 567 | }; | |
| 568 | ||
| 569 | /* Variable factor clocks */ | |
| 570 | sd1_clk: sd2_clk@e6150078 { | |
| 571 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
| 572 | reg = <0 0xe6150078 0 4>; | |
| 573 | clocks = <&pll1_div2_clk>; | |
| 574 | #clock-cells = <0>; | |
| 575 | clock-output-names = "sd1"; | |
| 576 | }; | |
| 577 | sd2_clk: sd3_clk@e615007c { | |
| 578 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
| 579 | reg = <0 0xe615007c 0 4>; | |
| 580 | clocks = <&pll1_div2_clk>; | |
| 581 | #clock-cells = <0>; | |
| 582 | clock-output-names = "sd2"; | |
| 583 | }; | |
| 584 | mmc0_clk: mmc0_clk@e6150240 { | |
| 585 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
| 586 | reg = <0 0xe6150240 0 4>; | |
| 587 | clocks = <&pll1_div2_clk>; | |
| 588 | #clock-cells = <0>; | |
| 589 | clock-output-names = "mmc0"; | |
| 590 | }; | |
| 591 | ssp_clk: ssp_clk@e6150248 { | |
| 592 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
| 593 | reg = <0 0xe6150248 0 4>; | |
| 594 | clocks = <&pll1_div2_clk>; | |
| 595 | #clock-cells = <0>; | |
| 596 | clock-output-names = "ssp"; | |
| 597 | }; | |
| 598 | ssprs_clk: ssprs_clk@e615024c { | |
| 599 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
| 600 | reg = <0 0xe615024c 0 4>; | |
| 601 | clocks = <&pll1_div2_clk>; | |
| 602 | #clock-cells = <0>; | |
| 603 | clock-output-names = "ssprs"; | |
| 604 | }; | |
| 605 | ||
| 606 | /* Fixed factor clocks */ | |
| 607 | pll1_div2_clk: pll1_div2_clk { | |
| 608 | compatible = "fixed-factor-clock"; | |
| 609 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 610 | #clock-cells = <0>; | |
| 611 | clock-div = <2>; | |
| 612 | clock-mult = <1>; | |
| 613 | clock-output-names = "pll1_div2"; | |
| 614 | }; | |
| 615 | zg_clk: zg_clk { | |
| 616 | compatible = "fixed-factor-clock"; | |
| 617 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 618 | #clock-cells = <0>; | |
| 619 | clock-div = <3>; | |
| 620 | clock-mult = <1>; | |
| 621 | clock-output-names = "zg"; | |
| 622 | }; | |
| 623 | zx_clk: zx_clk { | |
| 624 | compatible = "fixed-factor-clock"; | |
| 625 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 626 | #clock-cells = <0>; | |
| 627 | clock-div = <3>; | |
| 628 | clock-mult = <1>; | |
| 629 | clock-output-names = "zx"; | |
| 630 | }; | |
| 631 | zs_clk: zs_clk { | |
| 632 | compatible = "fixed-factor-clock"; | |
| 633 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 634 | #clock-cells = <0>; | |
| 635 | clock-div = <6>; | |
| 636 | clock-mult = <1>; | |
| 637 | clock-output-names = "zs"; | |
| 638 | }; | |
| 639 | hp_clk: hp_clk { | |
| 640 | compatible = "fixed-factor-clock"; | |
| 641 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 642 | #clock-cells = <0>; | |
| 643 | clock-div = <12>; | |
| 644 | clock-mult = <1>; | |
| 645 | clock-output-names = "hp"; | |
| 646 | }; | |
| 647 | i_clk: i_clk { | |
| 648 | compatible = "fixed-factor-clock"; | |
| 649 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 650 | #clock-cells = <0>; | |
| 651 | clock-div = <2>; | |
| 652 | clock-mult = <1>; | |
| 653 | clock-output-names = "i"; | |
| 654 | }; | |
| 655 | b_clk: b_clk { | |
| 656 | compatible = "fixed-factor-clock"; | |
| 657 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 658 | #clock-cells = <0>; | |
| 659 | clock-div = <12>; | |
| 660 | clock-mult = <1>; | |
| 661 | clock-output-names = "b"; | |
| 662 | }; | |
| 663 | p_clk: p_clk { | |
| 664 | compatible = "fixed-factor-clock"; | |
| 665 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 666 | #clock-cells = <0>; | |
| 667 | clock-div = <24>; | |
| 668 | clock-mult = <1>; | |
| 669 | clock-output-names = "p"; | |
| 670 | }; | |
| 671 | cl_clk: cl_clk { | |
| 672 | compatible = "fixed-factor-clock"; | |
| 673 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 674 | #clock-cells = <0>; | |
| 675 | clock-div = <48>; | |
| 676 | clock-mult = <1>; | |
| 677 | clock-output-names = "cl"; | |
| 678 | }; | |
| 679 | m2_clk: m2_clk { | |
| 680 | compatible = "fixed-factor-clock"; | |
| 681 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 682 | #clock-cells = <0>; | |
| 683 | clock-div = <8>; | |
| 684 | clock-mult = <1>; | |
| 685 | clock-output-names = "m2"; | |
| 686 | }; | |
| 687 | imp_clk: imp_clk { | |
| 688 | compatible = "fixed-factor-clock"; | |
| 689 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 690 | #clock-cells = <0>; | |
| 691 | clock-div = <4>; | |
| 692 | clock-mult = <1>; | |
| 693 | clock-output-names = "imp"; | |
| 694 | }; | |
| 695 | rclk_clk: rclk_clk { | |
| 696 | compatible = "fixed-factor-clock"; | |
| 697 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 698 | #clock-cells = <0>; | |
| 699 | clock-div = <(48 * 1024)>; | |
| 700 | clock-mult = <1>; | |
| 701 | clock-output-names = "rclk"; | |
| 702 | }; | |
| 703 | oscclk_clk: oscclk_clk { | |
| 704 | compatible = "fixed-factor-clock"; | |
| 705 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 706 | #clock-cells = <0>; | |
| 707 | clock-div = <(12 * 1024)>; | |
| 708 | clock-mult = <1>; | |
| 709 | clock-output-names = "oscclk"; | |
| 710 | }; | |
| 711 | zb3_clk: zb3_clk { | |
| 712 | compatible = "fixed-factor-clock"; | |
| 713 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
| 714 | #clock-cells = <0>; | |
| 715 | clock-div = <4>; | |
| 716 | clock-mult = <1>; | |
| 717 | clock-output-names = "zb3"; | |
| 718 | }; | |
| 719 | zb3d2_clk: zb3d2_clk { | |
| 720 | compatible = "fixed-factor-clock"; | |
| 721 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
| 722 | #clock-cells = <0>; | |
| 723 | clock-div = <8>; | |
| 724 | clock-mult = <1>; | |
| 725 | clock-output-names = "zb3d2"; | |
| 726 | }; | |
| 727 | ddr_clk: ddr_clk { | |
| 728 | compatible = "fixed-factor-clock"; | |
| 729 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
| 730 | #clock-cells = <0>; | |
| 731 | clock-div = <8>; | |
| 732 | clock-mult = <1>; | |
| 733 | clock-output-names = "ddr"; | |
| 734 | }; | |
| 735 | mp_clk: mp_clk { | |
| 736 | compatible = "fixed-factor-clock"; | |
| 737 | clocks = <&pll1_div2_clk>; | |
| 738 | #clock-cells = <0>; | |
| 739 | clock-div = <15>; | |
| 740 | clock-mult = <1>; | |
| 741 | clock-output-names = "mp"; | |
| 742 | }; | |
| 743 | cp_clk: cp_clk { | |
| 744 | compatible = "fixed-factor-clock"; | |
| 745 | clocks = <&extal_clk>; | |
| 746 | #clock-cells = <0>; | |
| 747 | clock-div = <2>; | |
| 748 | clock-mult = <1>; | |
| 749 | clock-output-names = "cp"; | |
| 750 | }; | |
| 751 | ||
| 752 | /* Gate clocks */ | |
| cded80f8 LP |
753 | mstp0_clks: mstp0_clks@e6150130 { |
| 754 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 755 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; | |
| 756 | clocks = <&mp_clk>; | |
| 757 | #clock-cells = <1>; | |
| 758 | renesas,clock-indices = <R8A7791_CLK_MSIOF0>; | |
| 759 | clock-output-names = "msiof0"; | |
| 760 | }; | |
| 59e79895 LP |
761 | mstp1_clks: mstp1_clks@e6150134 { |
| 762 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 763 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
| 764 | clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, | |
| 765 | <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; | |
| 766 | #clock-cells = <1>; | |
| 767 | renesas,clock-indices = < | |
| 768 | R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 | |
| 769 | R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 | |
| 58ea1d53 | 770 | R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S |
| 59e79895 LP |
771 | >; |
| 772 | clock-output-names = | |
| 773 | "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", | |
| 774 | "vsp1-du0", "vsp1-sy"; | |
| 775 | }; | |
| 776 | mstp2_clks: mstp2_clks@e6150138 { | |
| 777 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 778 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
| 779 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
| 4e074bc8 GU |
780 | <&mp_clk>, <&mp_clk>, <&mp_clk>, |
| 781 | <&zs_clk>, <&zs_clk>; | |
| 59e79895 LP |
782 | #clock-cells = <1>; |
| 783 | renesas,clock-indices = < | |
| 784 | R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 | |
| cded80f8 LP |
785 | R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 |
| 786 | R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 | |
| 4e074bc8 | 787 | R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 |
| 59e79895 LP |
788 | >; |
| 789 | clock-output-names = | |
| 0c002ef8 | 790 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
| 4e074bc8 GU |
791 | "scifb1", "msiof1", "scifb2", |
| 792 | "sys-dmac1", "sys-dmac0"; | |
| 59e79895 LP |
793 | }; |
| 794 | mstp3_clks: mstp3_clks@e615013c { | |
| 795 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 796 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
| c08691b5 | 797 | clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, |
| 308f3062 | 798 | <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; |
| 59e79895 LP |
799 | #clock-cells = <1>; |
| 800 | renesas,clock-indices = < | |
| c08691b5 | 801 | R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 |
| 308f3062 | 802 | R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 |
| 59e79895 LP |
803 | >; |
| 804 | clock-output-names = | |
| c08691b5 | 805 | "tpu0", "sdhi2", "sdhi1", "sdhi0", |
| 308f3062 | 806 | "mmcif0", "i2c7", "i2c8", "ssusb", "cmt1"; |
| 59e79895 LP |
807 | }; |
| 808 | mstp5_clks: mstp5_clks@e6150144 { | |
| 809 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 810 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; | |
| 811 | clocks = <&extal_clk>, <&p_clk>; | |
| 812 | #clock-cells = <1>; | |
| 813 | renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; | |
| 814 | clock-output-names = "thermal", "pwm"; | |
| 815 | }; | |
| 816 | mstp7_clks: mstp7_clks@e615014c { | |
| 817 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 818 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
| 6225b99a | 819 | clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, |
| 59e79895 LP |
820 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
| 821 | <&zx_clk>, <&zx_clk>, <&zx_clk>; | |
| 822 | #clock-cells = <1>; | |
| 823 | renesas,clock-indices = < | |
| 6225b99a | 824 | R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 |
| 59e79895 LP |
825 | R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 |
| 826 | R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 | |
| 827 | R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 | |
| 828 | R8A7791_CLK_LVDS0 | |
| 829 | >; | |
| 830 | clock-output-names = | |
| 6225b99a | 831 | "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", |
| 59e79895 LP |
832 | "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; |
| 833 | }; | |
| 834 | mstp8_clks: mstp8_clks@e6150990 { | |
| 835 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 836 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
| 65f05c38 LP |
837 | clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, |
| 838 | <&zs_clk>; | |
| 59e79895 | 839 | #clock-cells = <1>; |
| 09c98346 LP |
840 | renesas,clock-indices = < |
| 841 | R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 | |
| 65f05c38 | 842 | R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 |
| 09c98346 | 843 | >; |
| 65f05c38 LP |
844 | clock-output-names = |
| 845 | "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; | |
| 59e79895 LP |
846 | }; |
| 847 | mstp9_clks: mstp9_clks@e6150994 { | |
| 848 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 849 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
| 4faf9c5e GU |
850 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
| 851 | <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, | |
| 852 | <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, | |
| 11b48db9 LP |
853 | <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, |
| 854 | <&hp_clk>, <&hp_clk>; | |
| 59e79895 LP |
855 | #clock-cells = <1>; |
| 856 | renesas,clock-indices = < | |
| 4faf9c5e GU |
857 | R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 |
| 858 | R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 | |
| c08691b5 WS |
859 | R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 |
| 860 | R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 | |
| 861 | R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 | |
| 59e79895 LP |
862 | >; |
| 863 | clock-output-names = | |
| 4faf9c5e GU |
864 | "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", |
| 865 | "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", | |
| 866 | "i2c1", "i2c0"; | |
| 59e79895 | 867 | }; |
| ee914152 KM |
868 | mstp10_clks: mstp10_clks@e6150998 { |
| 869 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 870 | reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; | |
| 871 | clocks = <&p_clk>, | |
| 872 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
| 873 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
| 874 | <&p_clk>, | |
| 875 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
| 876 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
| 877 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
| 878 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
| 879 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
| 880 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; | |
| 881 | ||
| 882 | #clock-cells = <1>; | |
| 883 | clock-indices = < | |
| 884 | R8A7791_CLK_SSI_ALL | |
| 885 | R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 | |
| 886 | R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 | |
| 887 | R8A7791_CLK_SCU_ALL | |
| 888 | R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 | |
| 889 | R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 | |
| 890 | R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 | |
| 891 | >; | |
| 892 | clock-output-names = | |
| 893 | "ssi-all", | |
| 894 | "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", | |
| 895 | "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", | |
| 896 | "scu-all", | |
| 897 | "scu-dvc1", "scu-dvc0", | |
| 898 | "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", | |
| 899 | "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; | |
| 900 | }; | |
| 59e79895 LP |
901 | mstp11_clks: mstp11_clks@e615099c { |
| 902 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 903 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; | |
| 904 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; | |
| 905 | #clock-cells = <1>; | |
| 906 | renesas,clock-indices = < | |
| 907 | R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 | |
| 908 | >; | |
| 909 | clock-output-names = "scifa3", "scifa4", "scifa5"; | |
| 910 | }; | |
| 911 | }; | |
| 4d5b59cd | 912 | |
| 6f3e4ee3 | 913 | qspi: spi@e6b10000 { |
| 4d5b59cd GU |
914 | compatible = "renesas,qspi-r8a7791", "renesas,qspi"; |
| 915 | reg = <0 0xe6b10000 0 0x2c>; | |
| 4d5b59cd GU |
916 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
| 917 | clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; | |
| 918 | num-cs = <1>; | |
| 919 | #address-cells = <1>; | |
| 920 | #size-cells = <0>; | |
| 921 | status = "disabled"; | |
| 922 | }; | |
| 7713d3ab GU |
923 | |
| 924 | msiof0: spi@e6e20000 { | |
| 925 | compatible = "renesas,msiof-r8a7791"; | |
| 926 | reg = <0 0xe6e20000 0 0x0064>; | |
| 927 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; | |
| 928 | clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; | |
| 929 | #address-cells = <1>; | |
| 930 | #size-cells = <0>; | |
| 931 | status = "disabled"; | |
| 932 | }; | |
| 933 | ||
| 934 | msiof1: spi@e6e10000 { | |
| 935 | compatible = "renesas,msiof-r8a7791"; | |
| 936 | reg = <0 0xe6e10000 0 0x0064>; | |
| 937 | interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; | |
| 938 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; | |
| 939 | #address-cells = <1>; | |
| 940 | #size-cells = <0>; | |
| 941 | status = "disabled"; | |
| 942 | }; | |
| 943 | ||
| 944 | msiof2: spi@e6e00000 { | |
| 945 | compatible = "renesas,msiof-r8a7791"; | |
| 946 | reg = <0 0xe6e00000 0 0x0064>; | |
| 947 | interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; | |
| 948 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; | |
| 949 | #address-cells = <1>; | |
| 950 | #size-cells = <0>; | |
| 951 | status = "disabled"; | |
| 952 | }; | |
| 0d0771ab | 953 | }; |