projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 0d0771ab HN |
1 | /* |
| 2 | * Device Tree Source for the r8a7791 SoC | |
| 3 | * | |
| 118e4e6a | 4 | * Copyright (C) 2013-2015 Renesas Electronics Corporation |
| 2e5d55ce SS |
5 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
| 6 | * Copyright (C) 2014 Cogent Embedded Inc. | |
| 0d0771ab HN |
7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public License | |
| 9 | * version 2. This program is licensed "as is" without any warranty of any | |
| 10 | * kind, whether express or implied. | |
| 11 | */ | |
| 12 | ||
| 59e79895 | 13 | #include <dt-bindings/clock/r8a7791-clock.h> |
| 5f75e73c LP |
14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 16 | ||
| 0d0771ab HN |
17 | / { |
| 18 | compatible = "renesas,r8a7791"; | |
| 19 | interrupt-parent = <&gic>; | |
| 20 | #address-cells = <2>; | |
| 21 | #size-cells = <2>; | |
| 22 | ||
| 5bd3de7b WS |
23 | aliases { |
| 24 | i2c0 = &i2c0; | |
| 25 | i2c1 = &i2c1; | |
| 26 | i2c2 = &i2c2; | |
| 27 | i2c3 = &i2c3; | |
| 28 | i2c4 = &i2c4; | |
| 29 | i2c5 = &i2c5; | |
| 36408d9d WS |
30 | i2c6 = &i2c6; |
| 31 | i2c7 = &i2c7; | |
| 32 | i2c8 = &i2c8; | |
| 6f3e4ee3 | 33 | spi0 = &qspi; |
| 7713d3ab GU |
34 | spi1 = &msiof0; |
| 35 | spi2 = &msiof1; | |
| 36 | spi3 = &msiof2; | |
| 0b8d1d57 SS |
37 | vin0 = &vin0; |
| 38 | vin1 = &vin1; | |
| 39 | vin2 = &vin2; | |
| 5bd3de7b WS |
40 | }; |
| 41 | ||
| 0d0771ab HN |
42 | cpus { |
| 43 | #address-cells = <1>; | |
| 44 | #size-cells = <0>; | |
| 45 | ||
| 46 | cpu0: cpu@0 { | |
| 47 | device_type = "cpu"; | |
| 48 | compatible = "arm,cortex-a15"; | |
| 49 | reg = <0>; | |
| 896b79df | 50 | clock-frequency = <1500000000>; |
| a57004ec GI |
51 | voltage-tolerance = <1>; /* 1% */ |
| 52 | clocks = <&cpg_clocks R8A7791_CLK_Z>; | |
| 53 | clock-latency = <300000>; /* 300 us */ | |
| 54 | ||
| 55 | /* kHz - uV - OPPs unknown yet */ | |
| 56 | operating-points = <1500000 1000000>, | |
| 57 | <1312500 1000000>, | |
| 58 | <1125000 1000000>, | |
| 59 | < 937500 1000000>, | |
| 60 | < 750000 1000000>, | |
| 61 | < 375000 1000000>; | |
| 0d0771ab | 62 | }; |
| 15ab426c MD |
63 | |
| 64 | cpu1: cpu@1 { | |
| 65 | device_type = "cpu"; | |
| 66 | compatible = "arm,cortex-a15"; | |
| 67 | reg = <1>; | |
| 896b79df | 68 | clock-frequency = <1500000000>; |
| 15ab426c | 69 | }; |
| 0d0771ab HN |
70 | }; |
| 71 | ||
| 72 | gic: interrupt-controller@f1001000 { | |
| d238b5e6 | 73 | compatible = "arm,gic-400"; |
| 0d0771ab HN |
74 | #interrupt-cells = <3>; |
| 75 | #address-cells = <0>; | |
| 76 | interrupt-controller; | |
| 77 | reg = <0 0xf1001000 0 0x1000>, | |
| 78 | <0 0xf1002000 0 0x1000>, | |
| 79 | <0 0xf1004000 0 0x2000>, | |
| 80 | <0 0xf1006000 0 0x2000>; | |
| aa5404fc | 81 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| 0d0771ab | 82 | }; |
| d77db73e | 83 | |
| 89fbba12 | 84 | gpio0: gpio@e6050000 { |
| ab87e3fc | 85 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 86 | reg = <0 0xe6050000 0 0x50>; |
| 5f75e73c | 87 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
88 | #gpio-cells = <2>; |
| 89 | gpio-controller; | |
| 90 | gpio-ranges = <&pfc 0 0 32>; | |
| 91 | #interrupt-cells = <2>; | |
| 92 | interrupt-controller; | |
| 4faf9c5e | 93 | clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; |
| ab87e3fc MD |
94 | }; |
| 95 | ||
| 89fbba12 | 96 | gpio1: gpio@e6051000 { |
| ab87e3fc | 97 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 98 | reg = <0 0xe6051000 0 0x50>; |
| 5f75e73c | 99 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
100 | #gpio-cells = <2>; |
| 101 | gpio-controller; | |
| 102 | gpio-ranges = <&pfc 0 32 32>; | |
| 103 | #interrupt-cells = <2>; | |
| 104 | interrupt-controller; | |
| 4faf9c5e | 105 | clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; |
| ab87e3fc MD |
106 | }; |
| 107 | ||
| 89fbba12 | 108 | gpio2: gpio@e6052000 { |
| ab87e3fc | 109 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 110 | reg = <0 0xe6052000 0 0x50>; |
| 5f75e73c | 111 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
112 | #gpio-cells = <2>; |
| 113 | gpio-controller; | |
| 114 | gpio-ranges = <&pfc 0 64 32>; | |
| 115 | #interrupt-cells = <2>; | |
| 116 | interrupt-controller; | |
| 4faf9c5e | 117 | clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; |
| ab87e3fc MD |
118 | }; |
| 119 | ||
| 89fbba12 | 120 | gpio3: gpio@e6053000 { |
| ab87e3fc | 121 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 122 | reg = <0 0xe6053000 0 0x50>; |
| 5f75e73c | 123 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
124 | #gpio-cells = <2>; |
| 125 | gpio-controller; | |
| 126 | gpio-ranges = <&pfc 0 96 32>; | |
| 127 | #interrupt-cells = <2>; | |
| 128 | interrupt-controller; | |
| 4faf9c5e | 129 | clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; |
| ab87e3fc MD |
130 | }; |
| 131 | ||
| 89fbba12 | 132 | gpio4: gpio@e6054000 { |
| ab87e3fc | 133 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 134 | reg = <0 0xe6054000 0 0x50>; |
| 5f75e73c | 135 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
136 | #gpio-cells = <2>; |
| 137 | gpio-controller; | |
| 138 | gpio-ranges = <&pfc 0 128 32>; | |
| 139 | #interrupt-cells = <2>; | |
| 140 | interrupt-controller; | |
| 4faf9c5e | 141 | clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; |
| ab87e3fc MD |
142 | }; |
| 143 | ||
| 89fbba12 | 144 | gpio5: gpio@e6055000 { |
| ab87e3fc | 145 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 146 | reg = <0 0xe6055000 0 0x50>; |
| 5f75e73c | 147 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
148 | #gpio-cells = <2>; |
| 149 | gpio-controller; | |
| 150 | gpio-ranges = <&pfc 0 160 32>; | |
| 151 | #interrupt-cells = <2>; | |
| 152 | interrupt-controller; | |
| 4faf9c5e | 153 | clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; |
| ab87e3fc MD |
154 | }; |
| 155 | ||
| 89fbba12 | 156 | gpio6: gpio@e6055400 { |
| ab87e3fc | 157 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 158 | reg = <0 0xe6055400 0 0x50>; |
| 5f75e73c | 159 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
160 | #gpio-cells = <2>; |
| 161 | gpio-controller; | |
| 162 | gpio-ranges = <&pfc 0 192 32>; | |
| 163 | #interrupt-cells = <2>; | |
| 164 | interrupt-controller; | |
| 4faf9c5e | 165 | clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; |
| ab87e3fc MD |
166 | }; |
| 167 | ||
| 89fbba12 | 168 | gpio7: gpio@e6055800 { |
| ab87e3fc | 169 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
| 89fbba12 | 170 | reg = <0 0xe6055800 0 0x50>; |
| 5f75e73c | 171 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
| ab87e3fc MD |
172 | #gpio-cells = <2>; |
| 173 | gpio-controller; | |
| 174 | gpio-ranges = <&pfc 0 224 26>; | |
| 175 | #interrupt-cells = <2>; | |
| 176 | interrupt-controller; | |
| 4faf9c5e | 177 | clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; |
| ab87e3fc MD |
178 | }; |
| 179 | ||
| d103f4d3 MD |
180 | thermal@e61f0000 { |
| 181 | compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal"; | |
| 182 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; | |
| d103f4d3 | 183 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
| 563bc8eb | 184 | clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; |
| d103f4d3 MD |
185 | }; |
| 186 | ||
| 03586acf MD |
187 | timer { |
| 188 | compatible = "arm,armv7-timer"; | |
| aa5404fc GU |
189 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 190 | <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
| 191 | <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
| 192 | <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
| 03586acf MD |
193 | }; |
| 194 | ||
| ceaa1894 | 195 | cmt0: timer@ffca0000 { |
| 4217f323 | 196 | compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; |
| ceaa1894 LP |
197 | reg = <0 0xffca0000 0 0x1004>; |
| 198 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, | |
| 199 | <0 143 IRQ_TYPE_LEVEL_HIGH>; | |
| 200 | clocks = <&mstp1_clks R8A7791_CLK_CMT0>; | |
| 201 | clock-names = "fck"; | |
| 202 | ||
| 203 | renesas,channels-mask = <0x60>; | |
| 204 | ||
| 205 | status = "disabled"; | |
| 206 | }; | |
| 207 | ||
| 208 | cmt1: timer@e6130000 { | |
| 4217f323 | 209 | compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; |
| ceaa1894 LP |
210 | reg = <0 0xe6130000 0 0x1004>; |
| 211 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, | |
| 212 | <0 121 IRQ_TYPE_LEVEL_HIGH>, | |
| 213 | <0 122 IRQ_TYPE_LEVEL_HIGH>, | |
| 214 | <0 123 IRQ_TYPE_LEVEL_HIGH>, | |
| 215 | <0 124 IRQ_TYPE_LEVEL_HIGH>, | |
| 216 | <0 125 IRQ_TYPE_LEVEL_HIGH>, | |
| 217 | <0 126 IRQ_TYPE_LEVEL_HIGH>, | |
| 218 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
| 219 | clocks = <&mstp3_clks R8A7791_CLK_CMT1>; | |
| 220 | clock-names = "fck"; | |
| 221 | ||
| 222 | renesas,channels-mask = <0xff>; | |
| 223 | ||
| 224 | status = "disabled"; | |
| 225 | }; | |
| 226 | ||
| d77db73e | 227 | irqc0: interrupt-controller@e61c0000 { |
| 26041b06 | 228 | compatible = "renesas,irqc-r8a7791", "renesas,irqc"; |
| d77db73e MD |
229 | #interrupt-cells = <2>; |
| 230 | interrupt-controller; | |
| 231 | reg = <0 0xe61c0000 0 0x200>; | |
| 5f75e73c LP |
232 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
| 233 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | |
| 234 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | |
| 235 | <0 3 IRQ_TYPE_LEVEL_HIGH>, | |
| 236 | <0 12 IRQ_TYPE_LEVEL_HIGH>, | |
| 237 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
| 238 | <0 14 IRQ_TYPE_LEVEL_HIGH>, | |
| 239 | <0 15 IRQ_TYPE_LEVEL_HIGH>, | |
| 240 | <0 16 IRQ_TYPE_LEVEL_HIGH>, | |
| 241 | <0 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 62d386c0 | 242 | clocks = <&mstp4_clks R8A7791_CLK_IRQC>; |
| d77db73e | 243 | }; |
| 55146927 | 244 | |
| fde8feef LP |
245 | dmac0: dma-controller@e6700000 { |
| 246 | compatible = "renesas,rcar-dmac"; | |
| 247 | reg = <0 0xe6700000 0 0x20000>; | |
| 248 | interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH | |
| 249 | 0 200 IRQ_TYPE_LEVEL_HIGH | |
| 250 | 0 201 IRQ_TYPE_LEVEL_HIGH | |
| 251 | 0 202 IRQ_TYPE_LEVEL_HIGH | |
| 252 | 0 203 IRQ_TYPE_LEVEL_HIGH | |
| 253 | 0 204 IRQ_TYPE_LEVEL_HIGH | |
| 254 | 0 205 IRQ_TYPE_LEVEL_HIGH | |
| 255 | 0 206 IRQ_TYPE_LEVEL_HIGH | |
| 256 | 0 207 IRQ_TYPE_LEVEL_HIGH | |
| 257 | 0 208 IRQ_TYPE_LEVEL_HIGH | |
| 258 | 0 209 IRQ_TYPE_LEVEL_HIGH | |
| 259 | 0 210 IRQ_TYPE_LEVEL_HIGH | |
| 260 | 0 211 IRQ_TYPE_LEVEL_HIGH | |
| 261 | 0 212 IRQ_TYPE_LEVEL_HIGH | |
| 262 | 0 213 IRQ_TYPE_LEVEL_HIGH | |
| 263 | 0 214 IRQ_TYPE_LEVEL_HIGH>; | |
| 264 | interrupt-names = "error", | |
| 265 | "ch0", "ch1", "ch2", "ch3", | |
| 266 | "ch4", "ch5", "ch6", "ch7", | |
| 267 | "ch8", "ch9", "ch10", "ch11", | |
| 268 | "ch12", "ch13", "ch14"; | |
| 269 | clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; | |
| 270 | clock-names = "fck"; | |
| 271 | #dma-cells = <1>; | |
| 272 | dma-channels = <15>; | |
| 273 | }; | |
| 274 | ||
| 275 | dmac1: dma-controller@e6720000 { | |
| 276 | compatible = "renesas,rcar-dmac"; | |
| 277 | reg = <0 0xe6720000 0 0x20000>; | |
| 278 | interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH | |
| 279 | 0 216 IRQ_TYPE_LEVEL_HIGH | |
| 280 | 0 217 IRQ_TYPE_LEVEL_HIGH | |
| 281 | 0 218 IRQ_TYPE_LEVEL_HIGH | |
| 282 | 0 219 IRQ_TYPE_LEVEL_HIGH | |
| 283 | 0 308 IRQ_TYPE_LEVEL_HIGH | |
| 284 | 0 309 IRQ_TYPE_LEVEL_HIGH | |
| 285 | 0 310 IRQ_TYPE_LEVEL_HIGH | |
| 286 | 0 311 IRQ_TYPE_LEVEL_HIGH | |
| 287 | 0 312 IRQ_TYPE_LEVEL_HIGH | |
| 288 | 0 313 IRQ_TYPE_LEVEL_HIGH | |
| 289 | 0 314 IRQ_TYPE_LEVEL_HIGH | |
| 290 | 0 315 IRQ_TYPE_LEVEL_HIGH | |
| 291 | 0 316 IRQ_TYPE_LEVEL_HIGH | |
| 292 | 0 317 IRQ_TYPE_LEVEL_HIGH | |
| 293 | 0 318 IRQ_TYPE_LEVEL_HIGH>; | |
| 294 | interrupt-names = "error", | |
| 295 | "ch0", "ch1", "ch2", "ch3", | |
| 296 | "ch4", "ch5", "ch6", "ch7", | |
| 297 | "ch8", "ch9", "ch10", "ch11", | |
| 298 | "ch12", "ch13", "ch14"; | |
| 299 | clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; | |
| 300 | clock-names = "fck"; | |
| 301 | #dma-cells = <1>; | |
| 302 | dma-channels = <15>; | |
| 303 | }; | |
| 304 | ||
| 8994fff6 KM |
305 | audma0: dma-controller@ec700000 { |
| 306 | compatible = "renesas,rcar-dmac"; | |
| 307 | reg = <0 0xec700000 0 0x10000>; | |
| 308 | interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH | |
| 309 | 0 320 IRQ_TYPE_LEVEL_HIGH | |
| 310 | 0 321 IRQ_TYPE_LEVEL_HIGH | |
| 311 | 0 322 IRQ_TYPE_LEVEL_HIGH | |
| 312 | 0 323 IRQ_TYPE_LEVEL_HIGH | |
| 313 | 0 324 IRQ_TYPE_LEVEL_HIGH | |
| 314 | 0 325 IRQ_TYPE_LEVEL_HIGH | |
| 315 | 0 326 IRQ_TYPE_LEVEL_HIGH | |
| 316 | 0 327 IRQ_TYPE_LEVEL_HIGH | |
| 317 | 0 328 IRQ_TYPE_LEVEL_HIGH | |
| 318 | 0 329 IRQ_TYPE_LEVEL_HIGH | |
| 319 | 0 330 IRQ_TYPE_LEVEL_HIGH | |
| 320 | 0 331 IRQ_TYPE_LEVEL_HIGH | |
| 321 | 0 332 IRQ_TYPE_LEVEL_HIGH>; | |
| 322 | interrupt-names = "error", | |
| 323 | "ch0", "ch1", "ch2", "ch3", | |
| 324 | "ch4", "ch5", "ch6", "ch7", | |
| 325 | "ch8", "ch9", "ch10", "ch11", | |
| 326 | "ch12"; | |
| 327 | clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>; | |
| 328 | clock-names = "fck"; | |
| 329 | #dma-cells = <1>; | |
| 330 | dma-channels = <13>; | |
| 331 | }; | |
| 332 | ||
| 333 | audma1: dma-controller@ec720000 { | |
| 334 | compatible = "renesas,rcar-dmac"; | |
| 335 | reg = <0 0xec720000 0 0x10000>; | |
| 336 | interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH | |
| 337 | 0 333 IRQ_TYPE_LEVEL_HIGH | |
| 338 | 0 334 IRQ_TYPE_LEVEL_HIGH | |
| 339 | 0 335 IRQ_TYPE_LEVEL_HIGH | |
| 340 | 0 336 IRQ_TYPE_LEVEL_HIGH | |
| 341 | 0 337 IRQ_TYPE_LEVEL_HIGH | |
| 342 | 0 338 IRQ_TYPE_LEVEL_HIGH | |
| 343 | 0 339 IRQ_TYPE_LEVEL_HIGH | |
| 344 | 0 340 IRQ_TYPE_LEVEL_HIGH | |
| 345 | 0 341 IRQ_TYPE_LEVEL_HIGH | |
| 346 | 0 342 IRQ_TYPE_LEVEL_HIGH | |
| 347 | 0 343 IRQ_TYPE_LEVEL_HIGH | |
| 348 | 0 344 IRQ_TYPE_LEVEL_HIGH | |
| 349 | 0 345 IRQ_TYPE_LEVEL_HIGH>; | |
| 350 | interrupt-names = "error", | |
| 351 | "ch0", "ch1", "ch2", "ch3", | |
| 352 | "ch4", "ch5", "ch6", "ch7", | |
| 353 | "ch8", "ch9", "ch10", "ch11", | |
| 354 | "ch12"; | |
| 355 | clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>; | |
| 356 | clock-names = "fck"; | |
| 357 | #dma-cells = <1>; | |
| 358 | dma-channels = <13>; | |
| 359 | }; | |
| 360 | ||
| e3e25edc YS |
361 | usb_dmac0: dma-controller@e65a0000 { |
| 362 | compatible = "renesas,usb-dmac"; | |
| 363 | reg = <0 0xe65a0000 0 0x100>; | |
| 364 | interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH | |
| 365 | 0 109 IRQ_TYPE_LEVEL_HIGH>; | |
| 366 | interrupt-names = "ch0", "ch1"; | |
| 367 | clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>; | |
| 368 | #dma-cells = <1>; | |
| 369 | dma-channels = <2>; | |
| 370 | }; | |
| 371 | ||
| 372 | usb_dmac1: dma-controller@e65b0000 { | |
| 373 | compatible = "renesas,usb-dmac"; | |
| 374 | reg = <0 0xe65b0000 0 0x100>; | |
| 375 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH | |
| 376 | 0 110 IRQ_TYPE_LEVEL_HIGH>; | |
| 377 | interrupt-names = "ch0", "ch1"; | |
| 378 | clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>; | |
| 379 | #dma-cells = <1>; | |
| 380 | dma-channels = <2>; | |
| 381 | }; | |
| 382 | ||
| 36408d9d | 383 | /* The memory map in the User's Manual maps the cores to bus numbers */ |
| 5bd3de7b WS |
384 | i2c0: i2c@e6508000 { |
| 385 | #address-cells = <1>; | |
| 386 | #size-cells = <0>; | |
| 387 | compatible = "renesas,i2c-r8a7791"; | |
| 388 | reg = <0 0xe6508000 0 0x40>; | |
| 389 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; | |
| 390 | clocks = <&mstp9_clks R8A7791_CLK_I2C0>; | |
| 391 | status = "disabled"; | |
| 392 | }; | |
| 393 | ||
| 394 | i2c1: i2c@e6518000 { | |
| 395 | #address-cells = <1>; | |
| 396 | #size-cells = <0>; | |
| 397 | compatible = "renesas,i2c-r8a7791"; | |
| 398 | reg = <0 0xe6518000 0 0x40>; | |
| 399 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; | |
| 400 | clocks = <&mstp9_clks R8A7791_CLK_I2C1>; | |
| 401 | status = "disabled"; | |
| 402 | }; | |
| 403 | ||
| 404 | i2c2: i2c@e6530000 { | |
| 405 | #address-cells = <1>; | |
| 406 | #size-cells = <0>; | |
| 407 | compatible = "renesas,i2c-r8a7791"; | |
| 408 | reg = <0 0xe6530000 0 0x40>; | |
| 409 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; | |
| 410 | clocks = <&mstp9_clks R8A7791_CLK_I2C2>; | |
| 411 | status = "disabled"; | |
| 412 | }; | |
| 413 | ||
| 414 | i2c3: i2c@e6540000 { | |
| 415 | #address-cells = <1>; | |
| 416 | #size-cells = <0>; | |
| 417 | compatible = "renesas,i2c-r8a7791"; | |
| 418 | reg = <0 0xe6540000 0 0x40>; | |
| 419 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; | |
| 420 | clocks = <&mstp9_clks R8A7791_CLK_I2C3>; | |
| 421 | status = "disabled"; | |
| 422 | }; | |
| 423 | ||
| 424 | i2c4: i2c@e6520000 { | |
| 425 | #address-cells = <1>; | |
| 426 | #size-cells = <0>; | |
| 427 | compatible = "renesas,i2c-r8a7791"; | |
| 428 | reg = <0 0xe6520000 0 0x40>; | |
| 429 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; | |
| 430 | clocks = <&mstp9_clks R8A7791_CLK_I2C4>; | |
| 431 | status = "disabled"; | |
| 432 | }; | |
| 433 | ||
| 434 | i2c5: i2c@e6528000 { | |
| 36408d9d | 435 | /* doesn't need pinmux */ |
| 5bd3de7b WS |
436 | #address-cells = <1>; |
| 437 | #size-cells = <0>; | |
| 438 | compatible = "renesas,i2c-r8a7791"; | |
| 439 | reg = <0 0xe6528000 0 0x40>; | |
| 440 | interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
| 441 | clocks = <&mstp9_clks R8A7791_CLK_I2C5>; | |
| 442 | status = "disabled"; | |
| 443 | }; | |
| 444 | ||
| 36408d9d WS |
445 | i2c6: i2c@e60b0000 { |
| 446 | /* doesn't need pinmux */ | |
| 447 | #address-cells = <1>; | |
| 448 | #size-cells = <0>; | |
| 449 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
| 450 | reg = <0 0xe60b0000 0 0x425>; | |
| 451 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; | |
| 452 | clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; | |
| 3f58c54b WS |
453 | dmas = <&dmac0 0x77>, <&dmac0 0x78>; |
| 454 | dma-names = "tx", "rx"; | |
| 36408d9d WS |
455 | status = "disabled"; |
| 456 | }; | |
| 457 | ||
| 458 | i2c7: i2c@e6500000 { | |
| 459 | #address-cells = <1>; | |
| 460 | #size-cells = <0>; | |
| 461 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
| 462 | reg = <0 0xe6500000 0 0x425>; | |
| 463 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; | |
| 464 | clocks = <&mstp3_clks R8A7791_CLK_IIC0>; | |
| 3f58c54b WS |
465 | dmas = <&dmac0 0x61>, <&dmac0 0x62>; |
| 466 | dma-names = "tx", "rx"; | |
| 36408d9d WS |
467 | status = "disabled"; |
| 468 | }; | |
| 469 | ||
| 470 | i2c8: i2c@e6510000 { | |
| 471 | #address-cells = <1>; | |
| 472 | #size-cells = <0>; | |
| 473 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
| 474 | reg = <0 0xe6510000 0 0x425>; | |
| 475 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; | |
| 476 | clocks = <&mstp3_clks R8A7791_CLK_IIC1>; | |
| 3f58c54b WS |
477 | dmas = <&dmac0 0x65>, <&dmac0 0x66>; |
| 478 | dma-names = "tx", "rx"; | |
| 36408d9d WS |
479 | status = "disabled"; |
| 480 | }; | |
| 481 | ||
| 55146927 MD |
482 | pfc: pfc@e6060000 { |
| 483 | compatible = "renesas,pfc-r8a7791"; | |
| 484 | reg = <0 0xe6060000 0 0x250>; | |
| 485 | #gpio-range-cells = <3>; | |
| 486 | }; | |
| 59e79895 | 487 | |
| 8edae499 LP |
488 | mmcif0: mmc@ee200000 { |
| 489 | compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif"; | |
| 490 | reg = <0 0xee200000 0 0x80>; | |
| 491 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; | |
| 492 | clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; | |
| 16b355b4 LP |
493 | dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; |
| 494 | dma-names = "tx", "rx"; | |
| 8edae499 LP |
495 | reg-io-width = <4>; |
| 496 | status = "disabled"; | |
| d957ab8d | 497 | max-frequency = <97500000>; |
| 8edae499 LP |
498 | }; |
| 499 | ||
| b7ed8a0d MD |
500 | sdhi0: sd@ee100000 { |
| 501 | compatible = "renesas,sdhi-r8a7791"; | |
| e849b065 | 502 | reg = <0 0xee100000 0 0x328>; |
| b7ed8a0d MD |
503 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
| 504 | clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; | |
| ae67fa2f LP |
505 | dmas = <&dmac1 0xcd>, <&dmac1 0xce>; |
| 506 | dma-names = "tx", "rx"; | |
| b7ed8a0d MD |
507 | status = "disabled"; |
| 508 | }; | |
| 509 | ||
| 510 | sdhi1: sd@ee140000 { | |
| 511 | compatible = "renesas,sdhi-r8a7791"; | |
| 512 | reg = <0 0xee140000 0 0x100>; | |
| b7ed8a0d MD |
513 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
| 514 | clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; | |
| ae67fa2f LP |
515 | dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; |
| 516 | dma-names = "tx", "rx"; | |
| b7ed8a0d MD |
517 | status = "disabled"; |
| 518 | }; | |
| 519 | ||
| 520 | sdhi2: sd@ee160000 { | |
| 521 | compatible = "renesas,sdhi-r8a7791"; | |
| 522 | reg = <0 0xee160000 0 0x100>; | |
| b7ed8a0d MD |
523 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; |
| 524 | clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; | |
| ae67fa2f LP |
525 | dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; |
| 526 | dma-names = "tx", "rx"; | |
| b7ed8a0d MD |
527 | status = "disabled"; |
| 528 | }; | |
| 529 | ||
| 9640cf25 LP |
530 | scifa0: serial@e6c40000 { |
| 531 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
| 532 | reg = <0 0xe6c40000 0 64>; | |
| 9640cf25 LP |
533 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; |
| 534 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; | |
| 535 | clock-names = "sci_ick"; | |
| 558d6565 GU |
536 | dmas = <&dmac0 0x21>, <&dmac0 0x22>; |
| 537 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
538 | status = "disabled"; |
| 539 | }; | |
| 540 | ||
| 541 | scifa1: serial@e6c50000 { | |
| 542 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
| 9640cf25 LP |
543 | reg = <0 0xe6c50000 0 64>; |
| 544 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; | |
| 545 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; | |
| 546 | clock-names = "sci_ick"; | |
| 558d6565 GU |
547 | dmas = <&dmac0 0x25>, <&dmac0 0x26>; |
| 548 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
549 | status = "disabled"; |
| 550 | }; | |
| 551 | ||
| 552 | scifa2: serial@e6c60000 { | |
| 553 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
| 9640cf25 LP |
554 | reg = <0 0xe6c60000 0 64>; |
| 555 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; | |
| 556 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; | |
| 557 | clock-names = "sci_ick"; | |
| 558d6565 GU |
558 | dmas = <&dmac0 0x27>, <&dmac0 0x28>; |
| 559 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
560 | status = "disabled"; |
| 561 | }; | |
| 562 | ||
| 563 | scifa3: serial@e6c70000 { | |
| 564 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
| 9640cf25 LP |
565 | reg = <0 0xe6c70000 0 64>; |
| 566 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; | |
| 567 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; | |
| 568 | clock-names = "sci_ick"; | |
| 558d6565 GU |
569 | dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; |
| 570 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
571 | status = "disabled"; |
| 572 | }; | |
| 573 | ||
| 574 | scifa4: serial@e6c78000 { | |
| 575 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
| 9640cf25 LP |
576 | reg = <0 0xe6c78000 0 64>; |
| 577 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; | |
| 578 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; | |
| 579 | clock-names = "sci_ick"; | |
| 558d6565 GU |
580 | dmas = <&dmac0 0x1f>, <&dmac0 0x20>; |
| 581 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
582 | status = "disabled"; |
| 583 | }; | |
| 584 | ||
| 585 | scifa5: serial@e6c80000 { | |
| 586 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
| 9640cf25 LP |
587 | reg = <0 0xe6c80000 0 64>; |
| 588 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; | |
| 589 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; | |
| 590 | clock-names = "sci_ick"; | |
| 558d6565 GU |
591 | dmas = <&dmac0 0x23>, <&dmac0 0x24>; |
| 592 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
593 | status = "disabled"; |
| 594 | }; | |
| 595 | ||
| 596 | scifb0: serial@e6c20000 { | |
| 597 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
| 9640cf25 LP |
598 | reg = <0 0xe6c20000 0 64>; |
| 599 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; | |
| 600 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; | |
| 601 | clock-names = "sci_ick"; | |
| 558d6565 GU |
602 | dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; |
| 603 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
604 | status = "disabled"; |
| 605 | }; | |
| 606 | ||
| 607 | scifb1: serial@e6c30000 { | |
| 608 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
| 9640cf25 LP |
609 | reg = <0 0xe6c30000 0 64>; |
| 610 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; | |
| 611 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; | |
| 612 | clock-names = "sci_ick"; | |
| 558d6565 GU |
613 | dmas = <&dmac0 0x19>, <&dmac0 0x1a>; |
| 614 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
615 | status = "disabled"; |
| 616 | }; | |
| 617 | ||
| 618 | scifb2: serial@e6ce0000 { | |
| 619 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
| 9640cf25 LP |
620 | reg = <0 0xe6ce0000 0 64>; |
| 621 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; | |
| 622 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; | |
| 623 | clock-names = "sci_ick"; | |
| 558d6565 GU |
624 | dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; |
| 625 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
626 | status = "disabled"; |
| 627 | }; | |
| 628 | ||
| 629 | scif0: serial@e6e60000 { | |
| 630 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
| 9640cf25 LP |
631 | reg = <0 0xe6e60000 0 64>; |
| 632 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; | |
| 633 | clocks = <&mstp7_clks R8A7791_CLK_SCIF0>; | |
| 634 | clock-names = "sci_ick"; | |
| 558d6565 GU |
635 | dmas = <&dmac0 0x29>, <&dmac0 0x2a>; |
| 636 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
637 | status = "disabled"; |
| 638 | }; | |
| 639 | ||
| 640 | scif1: serial@e6e68000 { | |
| 641 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
| 9640cf25 LP |
642 | reg = <0 0xe6e68000 0 64>; |
| 643 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; | |
| 644 | clocks = <&mstp7_clks R8A7791_CLK_SCIF1>; | |
| 645 | clock-names = "sci_ick"; | |
| 558d6565 GU |
646 | dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; |
| 647 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
648 | status = "disabled"; |
| 649 | }; | |
| 650 | ||
| 651 | scif2: serial@e6e58000 { | |
| 652 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
| 9640cf25 LP |
653 | reg = <0 0xe6e58000 0 64>; |
| 654 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; | |
| 655 | clocks = <&mstp7_clks R8A7791_CLK_SCIF2>; | |
| 656 | clock-names = "sci_ick"; | |
| 558d6565 GU |
657 | dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; |
| 658 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
659 | status = "disabled"; |
| 660 | }; | |
| 661 | ||
| 662 | scif3: serial@e6ea8000 { | |
| 663 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
| 9640cf25 LP |
664 | reg = <0 0xe6ea8000 0 64>; |
| 665 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; | |
| 666 | clocks = <&mstp7_clks R8A7791_CLK_SCIF3>; | |
| 667 | clock-names = "sci_ick"; | |
| 558d6565 GU |
668 | dmas = <&dmac0 0x2f>, <&dmac0 0x30>; |
| 669 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
670 | status = "disabled"; |
| 671 | }; | |
| 672 | ||
| 673 | scif4: serial@e6ee0000 { | |
| 674 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
| 9640cf25 LP |
675 | reg = <0 0xe6ee0000 0 64>; |
| 676 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; | |
| 677 | clocks = <&mstp7_clks R8A7791_CLK_SCIF4>; | |
| 678 | clock-names = "sci_ick"; | |
| 558d6565 GU |
679 | dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; |
| 680 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
681 | status = "disabled"; |
| 682 | }; | |
| 683 | ||
| 684 | scif5: serial@e6ee8000 { | |
| 685 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
| 9640cf25 LP |
686 | reg = <0 0xe6ee8000 0 64>; |
| 687 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; | |
| 688 | clocks = <&mstp7_clks R8A7791_CLK_SCIF5>; | |
| 689 | clock-names = "sci_ick"; | |
| 558d6565 GU |
690 | dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; |
| 691 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
692 | status = "disabled"; |
| 693 | }; | |
| 694 | ||
| 695 | hscif0: serial@e62c0000 { | |
| 696 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
| 9640cf25 LP |
697 | reg = <0 0xe62c0000 0 96>; |
| 698 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; | |
| 699 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>; | |
| 700 | clock-names = "sci_ick"; | |
| 558d6565 GU |
701 | dmas = <&dmac0 0x39>, <&dmac0 0x3a>; |
| 702 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
703 | status = "disabled"; |
| 704 | }; | |
| 705 | ||
| 706 | hscif1: serial@e62c8000 { | |
| 707 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
| 9640cf25 LP |
708 | reg = <0 0xe62c8000 0 96>; |
| 709 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; | |
| 710 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>; | |
| 711 | clock-names = "sci_ick"; | |
| 558d6565 GU |
712 | dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; |
| 713 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
714 | status = "disabled"; |
| 715 | }; | |
| 716 | ||
| 717 | hscif2: serial@e62d0000 { | |
| 718 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
| 9640cf25 LP |
719 | reg = <0 0xe62d0000 0 96>; |
| 720 | interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; | |
| 721 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>; | |
| 722 | clock-names = "sci_ick"; | |
| 558d6565 GU |
723 | dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; |
| 724 | dma-names = "tx", "rx"; | |
| 9640cf25 LP |
725 | status = "disabled"; |
| 726 | }; | |
| 727 | ||
| 2e5d55ce SS |
728 | ether: ethernet@ee700000 { |
| 729 | compatible = "renesas,ether-r8a7791"; | |
| 730 | reg = <0 0xee700000 0 0x400>; | |
| 731 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; | |
| 732 | clocks = <&mstp8_clks R8A7791_CLK_ETHER>; | |
| 733 | phy-mode = "rmii"; | |
| 734 | #address-cells = <1>; | |
| 735 | #size-cells = <0>; | |
| 736 | status = "disabled"; | |
| 737 | }; | |
| 738 | ||
| b8532c69 VB |
739 | sata0: sata@ee300000 { |
| 740 | compatible = "renesas,sata-r8a7791"; | |
| 741 | reg = <0 0xee300000 0 0x2000>; | |
| b8532c69 VB |
742 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; |
| 743 | clocks = <&mstp8_clks R8A7791_CLK_SATA0>; | |
| 744 | status = "disabled"; | |
| 745 | }; | |
| 746 | ||
| 747 | sata1: sata@ee500000 { | |
| 748 | compatible = "renesas,sata-r8a7791"; | |
| 749 | reg = <0 0xee500000 0 0x2000>; | |
| b8532c69 VB |
750 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
| 751 | clocks = <&mstp8_clks R8A7791_CLK_SATA1>; | |
| 752 | status = "disabled"; | |
| 753 | }; | |
| 754 | ||
| 1c1fee7c YS |
755 | hsusb: usb@e6590000 { |
| 756 | compatible = "renesas,usbhs-r8a7791"; | |
| 757 | reg = <0 0xe6590000 0 0x100>; | |
| 758 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; | |
| 759 | clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; | |
| 760 | renesas,buswait = <4>; | |
| 761 | phys = <&usb0 1>; | |
| 762 | phy-names = "usb"; | |
| 7706993e YS |
763 | dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, |
| 764 | <&usb_dmac1 0>, <&usb_dmac1 1>; | |
| 765 | dma-names = "ch0", "ch1", "ch2", "ch3"; | |
| 1c1fee7c YS |
766 | status = "disabled"; |
| 767 | }; | |
| 768 | ||
| 3b7e530d SS |
769 | usbphy: usb-phy@e6590100 { |
| 770 | compatible = "renesas,usb-phy-r8a7791"; | |
| 771 | reg = <0 0xe6590100 0 0x100>; | |
| 772 | #address-cells = <1>; | |
| 773 | #size-cells = <0>; | |
| 774 | clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; | |
| 775 | clock-names = "usbhs"; | |
| 776 | status = "disabled"; | |
| 777 | ||
| 778 | usb0: usb-channel@0 { | |
| 779 | reg = <0>; | |
| 780 | #phy-cells = <1>; | |
| 781 | }; | |
| 782 | usb2: usb-channel@2 { | |
| 783 | reg = <2>; | |
| 784 | #phy-cells = <1>; | |
| 785 | }; | |
| 786 | }; | |
| 787 | ||
| 0b8d1d57 SS |
788 | vin0: video@e6ef0000 { |
| 789 | compatible = "renesas,vin-r8a7791"; | |
| 790 | clocks = <&mstp8_clks R8A7791_CLK_VIN0>; | |
| 791 | reg = <0 0xe6ef0000 0 0x1000>; | |
| 792 | interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; | |
| 793 | status = "disabled"; | |
| 794 | }; | |
| 795 | ||
| 796 | vin1: video@e6ef1000 { | |
| 797 | compatible = "renesas,vin-r8a7791"; | |
| 798 | clocks = <&mstp8_clks R8A7791_CLK_VIN1>; | |
| 799 | reg = <0 0xe6ef1000 0 0x1000>; | |
| 800 | interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; | |
| 801 | status = "disabled"; | |
| 802 | }; | |
| 803 | ||
| 804 | vin2: video@e6ef2000 { | |
| 805 | compatible = "renesas,vin-r8a7791"; | |
| 806 | clocks = <&mstp8_clks R8A7791_CLK_VIN2>; | |
| 807 | reg = <0 0xe6ef2000 0 0x1000>; | |
| 808 | interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; | |
| 809 | status = "disabled"; | |
| 810 | }; | |
| 811 | ||
| 8eefac2d LP |
812 | vsp1@fe928000 { |
| 813 | compatible = "renesas,vsp1"; | |
| 814 | reg = <0 0xfe928000 0 0x8000>; | |
| 815 | interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; | |
| 816 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; | |
| 817 | ||
| 818 | renesas,has-lut; | |
| 819 | renesas,has-sru; | |
| 820 | renesas,#rpf = <5>; | |
| 821 | renesas,#uds = <3>; | |
| 822 | renesas,#wpf = <4>; | |
| 823 | }; | |
| 824 | ||
| 825 | vsp1@fe930000 { | |
| 826 | compatible = "renesas,vsp1"; | |
| 827 | reg = <0 0xfe930000 0 0x8000>; | |
| 828 | interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; | |
| 829 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; | |
| 830 | ||
| 831 | renesas,has-lif; | |
| 832 | renesas,has-lut; | |
| 833 | renesas,#rpf = <4>; | |
| 834 | renesas,#uds = <1>; | |
| 835 | renesas,#wpf = <4>; | |
| 836 | }; | |
| 837 | ||
| 838 | vsp1@fe938000 { | |
| 839 | compatible = "renesas,vsp1"; | |
| 840 | reg = <0 0xfe938000 0 0x8000>; | |
| 841 | interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; | |
| 842 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; | |
| 843 | ||
| 844 | renesas,has-lif; | |
| 845 | renesas,has-lut; | |
| 846 | renesas,#rpf = <4>; | |
| 847 | renesas,#uds = <1>; | |
| 848 | renesas,#wpf = <4>; | |
| 849 | }; | |
| 850 | ||
| 851 | du: display@feb00000 { | |
| 852 | compatible = "renesas,du-r8a7791"; | |
| 853 | reg = <0 0xfeb00000 0 0x40000>, | |
| 854 | <0 0xfeb90000 0 0x1c>; | |
| 855 | reg-names = "du", "lvds.0"; | |
| 856 | interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, | |
| 857 | <0 268 IRQ_TYPE_LEVEL_HIGH>; | |
| 858 | clocks = <&mstp7_clks R8A7791_CLK_DU0>, | |
| 859 | <&mstp7_clks R8A7791_CLK_DU1>, | |
| 860 | <&mstp7_clks R8A7791_CLK_LVDS0>; | |
| 861 | clock-names = "du.0", "du.1", "lvds.0"; | |
| 862 | status = "disabled"; | |
| 863 | ||
| 864 | ports { | |
| 865 | #address-cells = <1>; | |
| 866 | #size-cells = <0>; | |
| 867 | ||
| 868 | port@0 { | |
| 869 | reg = <0>; | |
| 870 | du_out_rgb: endpoint { | |
| 871 | }; | |
| 872 | }; | |
| 873 | port@1 { | |
| 874 | reg = <1>; | |
| 875 | du_out_lvds0: endpoint { | |
| 876 | }; | |
| 877 | }; | |
| 878 | }; | |
| 879 | }; | |
| 880 | ||
| 3cf01884 SS |
881 | can0: can@e6e80000 { |
| 882 | compatible = "renesas,can-r8a7791"; | |
| 883 | reg = <0 0xe6e80000 0 0x1000>; | |
| 884 | interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; | |
| 885 | clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, | |
| 886 | <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; | |
| 887 | clock-names = "clkp1", "clkp2", "can_clk"; | |
| 888 | status = "disabled"; | |
| 889 | }; | |
| 890 | ||
| 891 | can1: can@e6e88000 { | |
| 892 | compatible = "renesas,can-r8a7791"; | |
| 893 | reg = <0 0xe6e88000 0 0x1000>; | |
| 894 | interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>; | |
| 895 | clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, | |
| 896 | <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; | |
| 897 | clock-names = "clkp1", "clkp2", "can_clk"; | |
| 898 | status = "disabled"; | |
| 899 | }; | |
| 900 | ||
| 59e79895 LP |
901 | clocks { |
| 902 | #address-cells = <2>; | |
| 903 | #size-cells = <2>; | |
| 904 | ranges; | |
| 905 | ||
| 906 | /* External root clock */ | |
| 907 | extal_clk: extal_clk { | |
| 908 | compatible = "fixed-clock"; | |
| 909 | #clock-cells = <0>; | |
| 910 | /* This value must be overriden by the board. */ | |
| 911 | clock-frequency = <0>; | |
| 912 | clock-output-names = "extal"; | |
| 913 | }; | |
| 914 | ||
| 0d3dbde8 KM |
915 | /* |
| 916 | * The external audio clocks are configured as 0 Hz fixed frequency clocks by | |
| 917 | * default. Boards that provide audio clocks should override them. | |
| 918 | */ | |
| 919 | audio_clk_a: audio_clk_a { | |
| 920 | compatible = "fixed-clock"; | |
| 921 | #clock-cells = <0>; | |
| 922 | clock-frequency = <0>; | |
| 923 | clock-output-names = "audio_clk_a"; | |
| 924 | }; | |
| 925 | audio_clk_b: audio_clk_b { | |
| 926 | compatible = "fixed-clock"; | |
| 927 | #clock-cells = <0>; | |
| 928 | clock-frequency = <0>; | |
| 929 | clock-output-names = "audio_clk_b"; | |
| 930 | }; | |
| 931 | audio_clk_c: audio_clk_c { | |
| 932 | compatible = "fixed-clock"; | |
| 933 | #clock-cells = <0>; | |
| 934 | clock-frequency = <0>; | |
| 935 | clock-output-names = "audio_clk_c"; | |
| 936 | }; | |
| 937 | ||
| 66c405e7 PE |
938 | /* External PCIe clock - can be overridden by the board */ |
| 939 | pcie_bus_clk: pcie_bus_clk { | |
| 940 | compatible = "fixed-clock"; | |
| 941 | #clock-cells = <0>; | |
| 942 | clock-frequency = <100000000>; | |
| 943 | clock-output-names = "pcie_bus"; | |
| 944 | status = "disabled"; | |
| 945 | }; | |
| 946 | ||
| b324252c SS |
947 | /* External USB clock - can be overridden by the board */ |
| 948 | usb_extal_clk: usb_extal_clk { | |
| 949 | compatible = "fixed-clock"; | |
| 950 | #clock-cells = <0>; | |
| 951 | clock-frequency = <48000000>; | |
| 952 | clock-output-names = "usb_extal"; | |
| 953 | }; | |
| 954 | ||
| 955 | /* External CAN clock */ | |
| 956 | can_clk: can_clk { | |
| 957 | compatible = "fixed-clock"; | |
| 958 | #clock-cells = <0>; | |
| 959 | /* This value must be overridden by the board. */ | |
| 960 | clock-frequency = <0>; | |
| 961 | clock-output-names = "can_clk"; | |
| 962 | status = "disabled"; | |
| 963 | }; | |
| 964 | ||
| 59e79895 LP |
965 | /* Special CPG clocks */ |
| 966 | cpg_clocks: cpg_clocks@e6150000 { | |
| 967 | compatible = "renesas,r8a7791-cpg-clocks", | |
| 968 | "renesas,rcar-gen2-cpg-clocks"; | |
| 969 | reg = <0 0xe6150000 0 0x1000>; | |
| b324252c | 970 | clocks = <&extal_clk &usb_extal_clk>; |
| 59e79895 LP |
971 | #clock-cells = <1>; |
| 972 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
| b324252c | 973 | "lb", "qspi", "sdh", "sd0", "z", |
| ae65a8ae | 974 | "rcan", "adsp"; |
| 59e79895 LP |
975 | }; |
| 976 | ||
| 977 | /* Variable factor clocks */ | |
| 2ea0d4ec | 978 | sd2_clk: sd2_clk@e6150078 { |
| 59e79895 LP |
979 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; |
| 980 | reg = <0 0xe6150078 0 4>; | |
| 981 | clocks = <&pll1_div2_clk>; | |
| 982 | #clock-cells = <0>; | |
| 2ea0d4ec | 983 | clock-output-names = "sd2"; |
| 59e79895 | 984 | }; |
| 2ea0d4ec | 985 | sd3_clk: sd3_clk@e615026c { |
| 59e79895 | 986 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; |
| c9b22772 | 987 | reg = <0 0xe615026c 0 4>; |
| 59e79895 LP |
988 | clocks = <&pll1_div2_clk>; |
| 989 | #clock-cells = <0>; | |
| 2ea0d4ec | 990 | clock-output-names = "sd3"; |
| 59e79895 LP |
991 | }; |
| 992 | mmc0_clk: mmc0_clk@e6150240 { | |
| 993 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
| 994 | reg = <0 0xe6150240 0 4>; | |
| 995 | clocks = <&pll1_div2_clk>; | |
| 996 | #clock-cells = <0>; | |
| 997 | clock-output-names = "mmc0"; | |
| 998 | }; | |
| 999 | ssp_clk: ssp_clk@e6150248 { | |
| 1000 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
| 1001 | reg = <0 0xe6150248 0 4>; | |
| 1002 | clocks = <&pll1_div2_clk>; | |
| 1003 | #clock-cells = <0>; | |
| 1004 | clock-output-names = "ssp"; | |
| 1005 | }; | |
| 1006 | ssprs_clk: ssprs_clk@e615024c { | |
| 1007 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
| 1008 | reg = <0 0xe615024c 0 4>; | |
| 1009 | clocks = <&pll1_div2_clk>; | |
| 1010 | #clock-cells = <0>; | |
| 1011 | clock-output-names = "ssprs"; | |
| 1012 | }; | |
| 1013 | ||
| 1014 | /* Fixed factor clocks */ | |
| 1015 | pll1_div2_clk: pll1_div2_clk { | |
| 1016 | compatible = "fixed-factor-clock"; | |
| 1017 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 1018 | #clock-cells = <0>; | |
| 1019 | clock-div = <2>; | |
| 1020 | clock-mult = <1>; | |
| 1021 | clock-output-names = "pll1_div2"; | |
| 1022 | }; | |
| 1023 | zg_clk: zg_clk { | |
| 1024 | compatible = "fixed-factor-clock"; | |
| 1025 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 1026 | #clock-cells = <0>; | |
| 1027 | clock-div = <3>; | |
| 1028 | clock-mult = <1>; | |
| 1029 | clock-output-names = "zg"; | |
| 1030 | }; | |
| 1031 | zx_clk: zx_clk { | |
| 1032 | compatible = "fixed-factor-clock"; | |
| 1033 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 1034 | #clock-cells = <0>; | |
| 1035 | clock-div = <3>; | |
| 1036 | clock-mult = <1>; | |
| 1037 | clock-output-names = "zx"; | |
| 1038 | }; | |
| 1039 | zs_clk: zs_clk { | |
| 1040 | compatible = "fixed-factor-clock"; | |
| 1041 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 1042 | #clock-cells = <0>; | |
| 1043 | clock-div = <6>; | |
| 1044 | clock-mult = <1>; | |
| 1045 | clock-output-names = "zs"; | |
| 1046 | }; | |
| 1047 | hp_clk: hp_clk { | |
| 1048 | compatible = "fixed-factor-clock"; | |
| 1049 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 1050 | #clock-cells = <0>; | |
| 1051 | clock-div = <12>; | |
| 1052 | clock-mult = <1>; | |
| 1053 | clock-output-names = "hp"; | |
| 1054 | }; | |
| 1055 | i_clk: i_clk { | |
| 1056 | compatible = "fixed-factor-clock"; | |
| 1057 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 1058 | #clock-cells = <0>; | |
| 1059 | clock-div = <2>; | |
| 1060 | clock-mult = <1>; | |
| 1061 | clock-output-names = "i"; | |
| 1062 | }; | |
| 1063 | b_clk: b_clk { | |
| 1064 | compatible = "fixed-factor-clock"; | |
| 1065 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 1066 | #clock-cells = <0>; | |
| 1067 | clock-div = <12>; | |
| 1068 | clock-mult = <1>; | |
| 1069 | clock-output-names = "b"; | |
| 1070 | }; | |
| 1071 | p_clk: p_clk { | |
| 1072 | compatible = "fixed-factor-clock"; | |
| 1073 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 1074 | #clock-cells = <0>; | |
| 1075 | clock-div = <24>; | |
| 1076 | clock-mult = <1>; | |
| 1077 | clock-output-names = "p"; | |
| 1078 | }; | |
| 1079 | cl_clk: cl_clk { | |
| 1080 | compatible = "fixed-factor-clock"; | |
| 1081 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 1082 | #clock-cells = <0>; | |
| 1083 | clock-div = <48>; | |
| 1084 | clock-mult = <1>; | |
| 1085 | clock-output-names = "cl"; | |
| 1086 | }; | |
| 1087 | m2_clk: m2_clk { | |
| 1088 | compatible = "fixed-factor-clock"; | |
| 1089 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 1090 | #clock-cells = <0>; | |
| 1091 | clock-div = <8>; | |
| 1092 | clock-mult = <1>; | |
| 1093 | clock-output-names = "m2"; | |
| 1094 | }; | |
| 1095 | imp_clk: imp_clk { | |
| 1096 | compatible = "fixed-factor-clock"; | |
| 1097 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 1098 | #clock-cells = <0>; | |
| 1099 | clock-div = <4>; | |
| 1100 | clock-mult = <1>; | |
| 1101 | clock-output-names = "imp"; | |
| 1102 | }; | |
| 1103 | rclk_clk: rclk_clk { | |
| 1104 | compatible = "fixed-factor-clock"; | |
| 1105 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 1106 | #clock-cells = <0>; | |
| 1107 | clock-div = <(48 * 1024)>; | |
| 1108 | clock-mult = <1>; | |
| 1109 | clock-output-names = "rclk"; | |
| 1110 | }; | |
| 1111 | oscclk_clk: oscclk_clk { | |
| 1112 | compatible = "fixed-factor-clock"; | |
| 1113 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
| 1114 | #clock-cells = <0>; | |
| 1115 | clock-div = <(12 * 1024)>; | |
| 1116 | clock-mult = <1>; | |
| 1117 | clock-output-names = "oscclk"; | |
| 1118 | }; | |
| 1119 | zb3_clk: zb3_clk { | |
| 1120 | compatible = "fixed-factor-clock"; | |
| 1121 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
| 1122 | #clock-cells = <0>; | |
| 1123 | clock-div = <4>; | |
| 1124 | clock-mult = <1>; | |
| 1125 | clock-output-names = "zb3"; | |
| 1126 | }; | |
| 1127 | zb3d2_clk: zb3d2_clk { | |
| 1128 | compatible = "fixed-factor-clock"; | |
| 1129 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
| 1130 | #clock-cells = <0>; | |
| 1131 | clock-div = <8>; | |
| 1132 | clock-mult = <1>; | |
| 1133 | clock-output-names = "zb3d2"; | |
| 1134 | }; | |
| 1135 | ddr_clk: ddr_clk { | |
| 1136 | compatible = "fixed-factor-clock"; | |
| 1137 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
| 1138 | #clock-cells = <0>; | |
| 1139 | clock-div = <8>; | |
| 1140 | clock-mult = <1>; | |
| 1141 | clock-output-names = "ddr"; | |
| 1142 | }; | |
| 1143 | mp_clk: mp_clk { | |
| 1144 | compatible = "fixed-factor-clock"; | |
| 1145 | clocks = <&pll1_div2_clk>; | |
| 1146 | #clock-cells = <0>; | |
| 1147 | clock-div = <15>; | |
| 1148 | clock-mult = <1>; | |
| 1149 | clock-output-names = "mp"; | |
| 1150 | }; | |
| 1151 | cp_clk: cp_clk { | |
| 1152 | compatible = "fixed-factor-clock"; | |
| 1153 | clocks = <&extal_clk>; | |
| 1154 | #clock-cells = <0>; | |
| 1155 | clock-div = <2>; | |
| 1156 | clock-mult = <1>; | |
| 1157 | clock-output-names = "cp"; | |
| 1158 | }; | |
| 1159 | ||
| 1160 | /* Gate clocks */ | |
| cded80f8 LP |
1161 | mstp0_clks: mstp0_clks@e6150130 { |
| 1162 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1163 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; | |
| 1164 | clocks = <&mp_clk>; | |
| 1165 | #clock-cells = <1>; | |
| cb0bf851 | 1166 | clock-indices = <R8A7791_CLK_MSIOF0>; |
| cded80f8 LP |
1167 | clock-output-names = "msiof0"; |
| 1168 | }; | |
| 59e79895 LP |
1169 | mstp1_clks: mstp1_clks@e6150134 { |
| 1170 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1171 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
| 74d89d25 YH |
1172 | clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>, |
| 1173 | <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, | |
| 1174 | <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, | |
| 1175 | <&zs_clk>; | |
| 59e79895 | 1176 | #clock-cells = <1>; |
| cb0bf851 | 1177 | clock-indices = < |
| 74d89d25 YH |
1178 | R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU |
| 1179 | R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG | |
| 1180 | R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 | |
| 1181 | R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 | |
| 1182 | R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0 | |
| 1183 | R8A7791_CLK_VSP1_S | |
| 59e79895 LP |
1184 | >; |
| 1185 | clock-output-names = | |
| 74d89d25 YH |
1186 | "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg", |
| 1187 | "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0", | |
| 1188 | "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy"; | |
| 59e79895 LP |
1189 | }; |
| 1190 | mstp2_clks: mstp2_clks@e6150138 { | |
| 1191 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1192 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
| 1193 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
| 4e074bc8 GU |
1194 | <&mp_clk>, <&mp_clk>, <&mp_clk>, |
| 1195 | <&zs_clk>, <&zs_clk>; | |
| 59e79895 | 1196 | #clock-cells = <1>; |
| cb0bf851 | 1197 | clock-indices = < |
| 59e79895 | 1198 | R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 |
| cded80f8 LP |
1199 | R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 |
| 1200 | R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 | |
| 4e074bc8 | 1201 | R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 |
| 59e79895 LP |
1202 | >; |
| 1203 | clock-output-names = | |
| 0c002ef8 | 1204 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
| 4e074bc8 GU |
1205 | "scifb1", "msiof1", "scifb2", |
| 1206 | "sys-dmac1", "sys-dmac0"; | |
| 59e79895 LP |
1207 | }; |
| 1208 | mstp3_clks: mstp3_clks@e615013c { | |
| 1209 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1210 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
| 2ea0d4ec | 1211 | clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>, |
| b9473d9f YS |
1212 | <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, |
| 1213 | <&hp_clk>, <&hp_clk>; | |
| 59e79895 | 1214 | #clock-cells = <1>; |
| cb0bf851 | 1215 | clock-indices = < |
| c08691b5 | 1216 | R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 |
| 4bfb3767 PE |
1217 | R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 |
| 1218 | R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 | |
| b9473d9f | 1219 | R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1 |
| 59e79895 LP |
1220 | >; |
| 1221 | clock-output-names = | |
| c08691b5 | 1222 | "tpu0", "sdhi2", "sdhi1", "sdhi0", |
| b9473d9f YS |
1223 | "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1", |
| 1224 | "usbdmac0", "usbdmac1"; | |
| 59e79895 | 1225 | }; |
| 62d386c0 GU |
1226 | mstp4_clks: mstp4_clks@e6150140 { |
| 1227 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1228 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; | |
| 1229 | clocks = <&cp_clk>; | |
| 1230 | #clock-cells = <1>; | |
| 1231 | clock-indices = <R8A7791_CLK_IRQC>; | |
| 1232 | clock-output-names = "irqc"; | |
| 1233 | }; | |
| 59e79895 LP |
1234 | mstp5_clks: mstp5_clks@e6150144 { |
| 1235 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1236 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; | |
| ae65a8ae SS |
1237 | clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>, |
| 1238 | <&extal_clk>, <&p_clk>; | |
| 59e79895 | 1239 | #clock-cells = <1>; |
| cb0bf851 BD |
1240 | clock-indices = < |
| 1241 | R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 | |
| ae65a8ae SS |
1242 | R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL |
| 1243 | R8A7791_CLK_PWM | |
| cb0bf851 | 1244 | >; |
| ae65a8ae SS |
1245 | clock-output-names = "audmac0", "audmac1", "adsp_mod", |
| 1246 | "thermal", "pwm"; | |
| 59e79895 LP |
1247 | }; |
| 1248 | mstp7_clks: mstp7_clks@e615014c { | |
| 1249 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1250 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
| 118e4e6a | 1251 | clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, |
| 59e79895 LP |
1252 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
| 1253 | <&zx_clk>, <&zx_clk>, <&zx_clk>; | |
| 1254 | #clock-cells = <1>; | |
| cb0bf851 | 1255 | clock-indices = < |
| 6225b99a | 1256 | R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 |
| 59e79895 LP |
1257 | R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 |
| 1258 | R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 | |
| 1259 | R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 | |
| 1260 | R8A7791_CLK_LVDS0 | |
| 1261 | >; | |
| 1262 | clock-output-names = | |
| 6225b99a | 1263 | "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", |
| 59e79895 LP |
1264 | "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; |
| 1265 | }; | |
| 1266 | mstp8_clks: mstp8_clks@e6150990 { | |
| 1267 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1268 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
| 75a499a6 | 1269 | clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>, |
| 7408d306 | 1270 | <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>; |
| 59e79895 | 1271 | #clock-cells = <1>; |
| cb0bf851 | 1272 | clock-indices = < |
| 7408d306 | 1273 | R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB |
| 09c98346 | 1274 | R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 |
| 65f05c38 | 1275 | R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 |
| 09c98346 | 1276 | >; |
| 65f05c38 | 1277 | clock-output-names = |
| 7408d306 AG |
1278 | "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether", |
| 1279 | "sata1", "sata0"; | |
| 59e79895 LP |
1280 | }; |
| 1281 | mstp9_clks: mstp9_clks@e6150994 { | |
| 1282 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1283 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
| 4faf9c5e GU |
1284 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
| 1285 | <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, | |
| 1286 | <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, | |
| 11b48db9 LP |
1287 | <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, |
| 1288 | <&hp_clk>, <&hp_clk>; | |
| 59e79895 | 1289 | #clock-cells = <1>; |
| cb0bf851 | 1290 | clock-indices = < |
| 4faf9c5e GU |
1291 | R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 |
| 1292 | R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 | |
| c08691b5 WS |
1293 | R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 |
| 1294 | R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 | |
| 1295 | R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 | |
| 59e79895 LP |
1296 | >; |
| 1297 | clock-output-names = | |
| 4faf9c5e GU |
1298 | "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", |
| 1299 | "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", | |
| 1300 | "i2c1", "i2c0"; | |
| 59e79895 | 1301 | }; |
| ee914152 KM |
1302 | mstp10_clks: mstp10_clks@e6150998 { |
| 1303 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1304 | reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; | |
| 1305 | clocks = <&p_clk>, | |
| 1306 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
| 1307 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
| 1308 | <&p_clk>, | |
| 1309 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
| 1310 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
| 1311 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
| 1312 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
| 1313 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
| 88401702 | 1314 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, |
| ee914152 KM |
1315 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; |
| 1316 | ||
| 1317 | #clock-cells = <1>; | |
| 1318 | clock-indices = < | |
| 1319 | R8A7791_CLK_SSI_ALL | |
| 1320 | R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 | |
| 1321 | R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 | |
| 1322 | R8A7791_CLK_SCU_ALL | |
| 1323 | R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 | |
| 88401702 | 1324 | R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0 |
| ee914152 KM |
1325 | R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 |
| 1326 | R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 | |
| 1327 | >; | |
| 1328 | clock-output-names = | |
| 1329 | "ssi-all", | |
| 1330 | "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", | |
| 1331 | "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", | |
| 1332 | "scu-all", | |
| 1333 | "scu-dvc1", "scu-dvc0", | |
| 88401702 | 1334 | "scu-ctu1-mix1", "scu-ctu0-mix0", |
| ee914152 KM |
1335 | "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", |
| 1336 | "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; | |
| 1337 | }; | |
| 59e79895 LP |
1338 | mstp11_clks: mstp11_clks@e615099c { |
| 1339 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1340 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; | |
| 1341 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; | |
| 1342 | #clock-cells = <1>; | |
| cb0bf851 | 1343 | clock-indices = < |
| 59e79895 LP |
1344 | R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 |
| 1345 | >; | |
| 1346 | clock-output-names = "scifa3", "scifa4", "scifa5"; | |
| 1347 | }; | |
| 1348 | }; | |
| 4d5b59cd | 1349 | |
| 6f3e4ee3 | 1350 | qspi: spi@e6b10000 { |
| 4d5b59cd GU |
1351 | compatible = "renesas,qspi-r8a7791", "renesas,qspi"; |
| 1352 | reg = <0 0xe6b10000 0 0x2c>; | |
| 4d5b59cd GU |
1353 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
| 1354 | clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; | |
| 591f2fa4 GU |
1355 | dmas = <&dmac0 0x17>, <&dmac0 0x18>; |
| 1356 | dma-names = "tx", "rx"; | |
| 4d5b59cd GU |
1357 | num-cs = <1>; |
| 1358 | #address-cells = <1>; | |
| 1359 | #size-cells = <0>; | |
| 1360 | status = "disabled"; | |
| 1361 | }; | |
| 7713d3ab GU |
1362 | |
| 1363 | msiof0: spi@e6e20000 { | |
| 1364 | compatible = "renesas,msiof-r8a7791"; | |
| cb6d08a2 | 1365 | reg = <0 0xe6e20000 0 0x0064>; |
| 7713d3ab GU |
1366 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; |
| 1367 | clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; | |
| a5ce27f5 GU |
1368 | dmas = <&dmac0 0x51>, <&dmac0 0x52>; |
| 1369 | dma-names = "tx", "rx"; | |
| 7713d3ab GU |
1370 | #address-cells = <1>; |
| 1371 | #size-cells = <0>; | |
| 1372 | status = "disabled"; | |
| 1373 | }; | |
| 1374 | ||
| 1375 | msiof1: spi@e6e10000 { | |
| 1376 | compatible = "renesas,msiof-r8a7791"; | |
| cb6d08a2 | 1377 | reg = <0 0xe6e10000 0 0x0064>; |
| 7713d3ab GU |
1378 | interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; |
| 1379 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; | |
| a5ce27f5 GU |
1380 | dmas = <&dmac0 0x55>, <&dmac0 0x56>; |
| 1381 | dma-names = "tx", "rx"; | |
| 7713d3ab GU |
1382 | #address-cells = <1>; |
| 1383 | #size-cells = <0>; | |
| 1384 | status = "disabled"; | |
| 1385 | }; | |
| 1386 | ||
| 1387 | msiof2: spi@e6e00000 { | |
| 1388 | compatible = "renesas,msiof-r8a7791"; | |
| cb6d08a2 | 1389 | reg = <0 0xe6e00000 0 0x0064>; |
| 7713d3ab GU |
1390 | interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; |
| 1391 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; | |
| a5ce27f5 GU |
1392 | dmas = <&dmac0 0x41>, <&dmac0 0x42>; |
| 1393 | dma-names = "tx", "rx"; | |
| 7713d3ab GU |
1394 | #address-cells = <1>; |
| 1395 | #size-cells = <0>; | |
| 1396 | status = "disabled"; | |
| 1397 | }; | |
| 811cdfae | 1398 | |
| c196931e YS |
1399 | xhci: usb@ee000000 { |
| 1400 | compatible = "renesas,xhci-r8a7791"; | |
| 1401 | reg = <0 0xee000000 0 0xc00>; | |
| 1402 | interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; | |
| 1403 | clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; | |
| 1404 | phys = <&usb2 1>; | |
| 1405 | phy-names = "usb"; | |
| 1406 | status = "disabled"; | |
| 1407 | }; | |
| 1408 | ||
| aace0809 SS |
1409 | pci0: pci@ee090000 { |
| 1410 | compatible = "renesas,pci-r8a7791"; | |
| 1411 | device_type = "pci"; | |
| 1412 | clocks = <&mstp7_clks R8A7791_CLK_EHCI>; | |
| 1413 | reg = <0 0xee090000 0 0xc00>, | |
| 1414 | <0 0xee080000 0 0x1100>; | |
| 1415 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 1416 | status = "disabled"; | |
| 1417 | ||
| 1418 | bus-range = <0 0>; | |
| 1419 | #address-cells = <3>; | |
| 1420 | #size-cells = <2>; | |
| 1421 | #interrupt-cells = <1>; | |
| 1422 | ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; | |
| 1423 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
| 1424 | interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH | |
| 1425 | 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH | |
| 1426 | 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; | |
| e1bce124 SS |
1427 | |
| 1428 | usb@0,1 { | |
| 1429 | reg = <0x800 0 0 0 0>; | |
| 1430 | device_type = "pci"; | |
| 1431 | phys = <&usb0 0>; | |
| 1432 | phy-names = "usb"; | |
| 1433 | }; | |
| 1434 | ||
| 1435 | usb@0,2 { | |
| 1436 | reg = <0x1000 0 0 0 0>; | |
| 1437 | device_type = "pci"; | |
| 1438 | phys = <&usb0 0>; | |
| 1439 | phy-names = "usb"; | |
| 1440 | }; | |
| aace0809 SS |
1441 | }; |
| 1442 | ||
| 1443 | pci1: pci@ee0d0000 { | |
| 1444 | compatible = "renesas,pci-r8a7791"; | |
| 1445 | device_type = "pci"; | |
| 1446 | clocks = <&mstp7_clks R8A7791_CLK_EHCI>; | |
| 1447 | reg = <0 0xee0d0000 0 0xc00>, | |
| 1448 | <0 0xee0c0000 0 0x1100>; | |
| 1449 | interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; | |
| 1450 | status = "disabled"; | |
| 1451 | ||
| 1452 | bus-range = <1 1>; | |
| 1453 | #address-cells = <3>; | |
| 1454 | #size-cells = <2>; | |
| 1455 | #interrupt-cells = <1>; | |
| 1456 | ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; | |
| 1457 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
| 1458 | interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH | |
| 1459 | 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH | |
| 1460 | 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; | |
| e1bce124 SS |
1461 | |
| 1462 | usb@0,1 { | |
| 1463 | reg = <0x800 0 0 0 0>; | |
| 1464 | device_type = "pci"; | |
| 1465 | phys = <&usb2 0>; | |
| 1466 | phy-names = "usb"; | |
| 1467 | }; | |
| 1468 | ||
| 1469 | usb@0,2 { | |
| 1470 | reg = <0x1000 0 0 0 0>; | |
| 1471 | device_type = "pci"; | |
| 1472 | phys = <&usb2 0>; | |
| 1473 | phy-names = "usb"; | |
| 1474 | }; | |
| aace0809 SS |
1475 | }; |
| 1476 | ||
| 811cdfae PE |
1477 | pciec: pcie@fe000000 { |
| 1478 | compatible = "renesas,pcie-r8a7791"; | |
| 1479 | reg = <0 0xfe000000 0 0x80000>; | |
| 1480 | #address-cells = <3>; | |
| 1481 | #size-cells = <2>; | |
| 1482 | bus-range = <0x00 0xff>; | |
| 1483 | device_type = "pci"; | |
| 1484 | ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 | |
| 1485 | 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 | |
| 1486 | 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 | |
| 1487 | 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; | |
| 1488 | /* Map all possible DDR as inbound ranges */ | |
| 1489 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 | |
| 1490 | 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; | |
| 1491 | interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, | |
| 1492 | <0 117 IRQ_TYPE_LEVEL_HIGH>, | |
| 1493 | <0 118 IRQ_TYPE_LEVEL_HIGH>; | |
| 1494 | #interrupt-cells = <1>; | |
| 1495 | interrupt-map-mask = <0 0 0 0>; | |
| 1496 | interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; | |
| 1497 | clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; | |
| 1498 | clock-names = "pcie", "pcie_bus"; | |
| 1499 | status = "disabled"; | |
| 1500 | }; | |
| 09abd1fd | 1501 | |
| f1951852 LP |
1502 | ipmmu_sy0: mmu@e6280000 { |
| 1503 | compatible = "renesas,ipmmu-vmsa"; | |
| 1504 | reg = <0 0xe6280000 0 0x1000>; | |
| 1505 | interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, | |
| 1506 | <0 224 IRQ_TYPE_LEVEL_HIGH>; | |
| 1507 | #iommu-cells = <1>; | |
| 1508 | status = "disabled"; | |
| 1509 | }; | |
| 1510 | ||
| 1511 | ipmmu_sy1: mmu@e6290000 { | |
| 1512 | compatible = "renesas,ipmmu-vmsa"; | |
| 1513 | reg = <0 0xe6290000 0 0x1000>; | |
| 1514 | interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; | |
| 1515 | #iommu-cells = <1>; | |
| 1516 | status = "disabled"; | |
| 1517 | }; | |
| 1518 | ||
| 1519 | ipmmu_ds: mmu@e6740000 { | |
| 1520 | compatible = "renesas,ipmmu-vmsa"; | |
| 1521 | reg = <0 0xe6740000 0 0x1000>; | |
| 1522 | interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, | |
| 1523 | <0 199 IRQ_TYPE_LEVEL_HIGH>; | |
| 1524 | #iommu-cells = <1>; | |
| 1525 | status = "disabled"; | |
| 1526 | }; | |
| 1527 | ||
| 1528 | ipmmu_mp: mmu@ec680000 { | |
| 1529 | compatible = "renesas,ipmmu-vmsa"; | |
| 1530 | reg = <0 0xec680000 0 0x1000>; | |
| 1531 | interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; | |
| 1532 | #iommu-cells = <1>; | |
| 1533 | status = "disabled"; | |
| 1534 | }; | |
| 1535 | ||
| 1536 | ipmmu_mx: mmu@fe951000 { | |
| 1537 | compatible = "renesas,ipmmu-vmsa"; | |
| 1538 | reg = <0 0xfe951000 0 0x1000>; | |
| 1539 | interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, | |
| 1540 | <0 221 IRQ_TYPE_LEVEL_HIGH>; | |
| 1541 | #iommu-cells = <1>; | |
| 1542 | status = "disabled"; | |
| 1543 | }; | |
| 1544 | ||
| 1545 | ipmmu_rt: mmu@ffc80000 { | |
| 1546 | compatible = "renesas,ipmmu-vmsa"; | |
| 1547 | reg = <0 0xffc80000 0 0x1000>; | |
| 1548 | interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>; | |
| 1549 | #iommu-cells = <1>; | |
| 1550 | status = "disabled"; | |
| 1551 | }; | |
| 1552 | ||
| 1553 | ipmmu_gp: mmu@e62a0000 { | |
| 1554 | compatible = "renesas,ipmmu-vmsa"; | |
| 1555 | reg = <0 0xe62a0000 0 0x1000>; | |
| 1556 | interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>, | |
| 1557 | <0 261 IRQ_TYPE_LEVEL_HIGH>; | |
| 1558 | #iommu-cells = <1>; | |
| 1559 | status = "disabled"; | |
| 1560 | }; | |
| 1561 | ||
| 6c63e07d | 1562 | rcar_sound: sound@ec500000 { |
| d2b541c9 KM |
1563 | /* |
| 1564 | * #sound-dai-cells is required | |
| 1565 | * | |
| 1566 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; | |
| 1567 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; | |
| 1568 | */ | |
| f49cd2b3 | 1569 | compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2"; |
| 09abd1fd KM |
1570 | reg = <0 0xec500000 0 0x1000>, /* SCU */ |
| 1571 | <0 0xec5a0000 0 0x100>, /* ADG */ | |
| 1572 | <0 0xec540000 0 0x1000>, /* SSIU */ | |
| d73a5013 KM |
1573 | <0 0xec541000 0 0x1280>, /* SSI */ |
| 1574 | <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ | |
| 1575 | reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; | |
| d88a6a2a | 1576 | |
| 09abd1fd KM |
1577 | clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, |
| 1578 | <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, | |
| 1579 | <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>, | |
| 1580 | <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>, | |
| 1581 | <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>, | |
| 1582 | <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>, | |
| 1583 | <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>, | |
| 1584 | <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>, | |
| 1585 | <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, | |
| 1586 | <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, | |
| 1587 | <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, | |
| 88401702 | 1588 | <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, |
| 150c8ad4 | 1589 | <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, |
| 09abd1fd KM |
1590 | <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; |
| 1591 | clock-names = "ssi-all", | |
| 1592 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", | |
| 1593 | "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", | |
| 1594 | "src.9", "src.8", "src.7", "src.6", "src.5", | |
| 1595 | "src.4", "src.3", "src.2", "src.1", "src.0", | |
| 88401702 | 1596 | "ctu.0", "ctu.1", |
| 150c8ad4 | 1597 | "dvc.0", "dvc.1", |
| 09abd1fd KM |
1598 | "clk_a", "clk_b", "clk_c", "clk_i"; |
| 1599 | ||
| 1600 | status = "disabled"; | |
| 1601 | ||
| 150c8ad4 | 1602 | rcar_sound,dvc { |
| 63573339 KM |
1603 | dvc0: dvc@0 { |
| 1604 | dmas = <&audma0 0xbc>; | |
| 1605 | dma-names = "tx"; | |
| 1606 | }; | |
| 1607 | dvc1: dvc@1 { | |
| 1608 | dmas = <&audma0 0xbe>; | |
| 1609 | dma-names = "tx"; | |
| 1610 | }; | |
| 150c8ad4 KM |
1611 | }; |
| 1612 | ||
| 88401702 KM |
1613 | rcar_sound,ctu { |
| 1614 | ctu00: ctu@0 { }; | |
| 1615 | ctu01: ctu@1 { }; | |
| 1616 | ctu02: ctu@2 { }; | |
| 1617 | ctu03: ctu@3 { }; | |
| 1618 | ctu10: ctu@4 { }; | |
| 1619 | ctu11: ctu@5 { }; | |
| 1620 | ctu12: ctu@6 { }; | |
| 1621 | ctu13: ctu@7 { }; | |
| 1622 | }; | |
| 1623 | ||
| 09abd1fd | 1624 | rcar_sound,src { |
| 63573339 KM |
1625 | src0: src@0 { |
| 1626 | interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; | |
| 1627 | dmas = <&audma0 0x85>, <&audma1 0x9a>; | |
| 1628 | dma-names = "rx", "tx"; | |
| 1629 | }; | |
| 1630 | src1: src@1 { | |
| 1631 | interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; | |
| 1632 | dmas = <&audma0 0x87>, <&audma1 0x9c>; | |
| 1633 | dma-names = "rx", "tx"; | |
| 1634 | }; | |
| 1635 | src2: src@2 { | |
| 1636 | interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; | |
| 1637 | dmas = <&audma0 0x89>, <&audma1 0x9e>; | |
| 1638 | dma-names = "rx", "tx"; | |
| 1639 | }; | |
| 1640 | src3: src@3 { | |
| 1641 | interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; | |
| 1642 | dmas = <&audma0 0x8b>, <&audma1 0xa0>; | |
| 1643 | dma-names = "rx", "tx"; | |
| 1644 | }; | |
| 1645 | src4: src@4 { | |
| 1646 | interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; | |
| 1647 | dmas = <&audma0 0x8d>, <&audma1 0xb0>; | |
| 1648 | dma-names = "rx", "tx"; | |
| 1649 | }; | |
| 1650 | src5: src@5 { | |
| 1651 | interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; | |
| 1652 | dmas = <&audma0 0x8f>, <&audma1 0xb2>; | |
| 1653 | dma-names = "rx", "tx"; | |
| 1654 | }; | |
| 1655 | src6: src@6 { | |
| 1656 | interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; | |
| 1657 | dmas = <&audma0 0x91>, <&audma1 0xb4>; | |
| 1658 | dma-names = "rx", "tx"; | |
| 1659 | }; | |
| 1660 | src7: src@7 { | |
| 1661 | interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; | |
| 1662 | dmas = <&audma0 0x93>, <&audma1 0xb6>; | |
| 1663 | dma-names = "rx", "tx"; | |
| 1664 | }; | |
| 1665 | src8: src@8 { | |
| 1666 | interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; | |
| 1667 | dmas = <&audma0 0x95>, <&audma1 0xb8>; | |
| 1668 | dma-names = "rx", "tx"; | |
| 1669 | }; | |
| 1670 | src9: src@9 { | |
| 1671 | interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; | |
| 1672 | dmas = <&audma0 0x97>, <&audma1 0xba>; | |
| 1673 | dma-names = "rx", "tx"; | |
| 1674 | }; | |
| 09abd1fd KM |
1675 | }; |
| 1676 | ||
| 1677 | rcar_sound,ssi { | |
| 63573339 KM |
1678 | ssi0: ssi@0 { |
| 1679 | interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; | |
| 1680 | dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; | |
| 1681 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 1682 | }; | |
| 1683 | ssi1: ssi@1 { | |
| 1684 | interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; | |
| 1685 | dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; | |
| 1686 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 1687 | }; | |
| 1688 | ssi2: ssi@2 { | |
| 1689 | interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; | |
| 1690 | dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; | |
| 1691 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 1692 | }; | |
| 1693 | ssi3: ssi@3 { | |
| 1694 | interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; | |
| 1695 | dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; | |
| 1696 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 1697 | }; | |
| 1698 | ssi4: ssi@4 { | |
| 1699 | interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; | |
| 1700 | dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; | |
| 1701 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 1702 | }; | |
| 1703 | ssi5: ssi@5 { | |
| 1704 | interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; | |
| 1705 | dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; | |
| 1706 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 1707 | }; | |
| 1708 | ssi6: ssi@6 { | |
| 1709 | interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; | |
| 1710 | dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; | |
| 1711 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 1712 | }; | |
| 1713 | ssi7: ssi@7 { | |
| 1714 | interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; | |
| 1715 | dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; | |
| 1716 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 1717 | }; | |
| 1718 | ssi8: ssi@8 { | |
| 1719 | interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; | |
| 1720 | dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; | |
| 1721 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 1722 | }; | |
| 1723 | ssi9: ssi@9 { | |
| 1724 | interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; | |
| 1725 | dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; | |
| 1726 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 1727 | }; | |
| 09abd1fd KM |
1728 | }; |
| 1729 | }; | |
| 0d0771ab | 1730 | }; |