Commit | Line | Data |
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0d0771ab HN |
1 | /* |
2 | * Device Tree Source for the r8a7791 SoC | |
3 | * | |
118e4e6a | 4 | * Copyright (C) 2013-2015 Renesas Electronics Corporation |
2e5d55ce SS |
5 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
6 | * Copyright (C) 2014 Cogent Embedded Inc. | |
0d0771ab HN |
7 | * |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
11 | */ | |
12 | ||
59e79895 | 13 | #include <dt-bindings/clock/r8a7791-clock.h> |
5f75e73c LP |
14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
15 | #include <dt-bindings/interrupt-controller/irq.h> | |
16 | ||
0d0771ab HN |
17 | / { |
18 | compatible = "renesas,r8a7791"; | |
19 | interrupt-parent = <&gic>; | |
20 | #address-cells = <2>; | |
21 | #size-cells = <2>; | |
22 | ||
5bd3de7b WS |
23 | aliases { |
24 | i2c0 = &i2c0; | |
25 | i2c1 = &i2c1; | |
26 | i2c2 = &i2c2; | |
27 | i2c3 = &i2c3; | |
28 | i2c4 = &i2c4; | |
29 | i2c5 = &i2c5; | |
36408d9d WS |
30 | i2c6 = &i2c6; |
31 | i2c7 = &i2c7; | |
32 | i2c8 = &i2c8; | |
6f3e4ee3 | 33 | spi0 = &qspi; |
7713d3ab GU |
34 | spi1 = &msiof0; |
35 | spi2 = &msiof1; | |
36 | spi3 = &msiof2; | |
0b8d1d57 SS |
37 | vin0 = &vin0; |
38 | vin1 = &vin1; | |
39 | vin2 = &vin2; | |
5bd3de7b WS |
40 | }; |
41 | ||
0d0771ab HN |
42 | cpus { |
43 | #address-cells = <1>; | |
44 | #size-cells = <0>; | |
45 | ||
46 | cpu0: cpu@0 { | |
47 | device_type = "cpu"; | |
48 | compatible = "arm,cortex-a15"; | |
49 | reg = <0>; | |
896b79df | 50 | clock-frequency = <1500000000>; |
a57004ec GI |
51 | voltage-tolerance = <1>; /* 1% */ |
52 | clocks = <&cpg_clocks R8A7791_CLK_Z>; | |
53 | clock-latency = <300000>; /* 300 us */ | |
54 | ||
55 | /* kHz - uV - OPPs unknown yet */ | |
56 | operating-points = <1500000 1000000>, | |
57 | <1312500 1000000>, | |
58 | <1125000 1000000>, | |
59 | < 937500 1000000>, | |
60 | < 750000 1000000>, | |
61 | < 375000 1000000>; | |
0d0771ab | 62 | }; |
15ab426c MD |
63 | |
64 | cpu1: cpu@1 { | |
65 | device_type = "cpu"; | |
66 | compatible = "arm,cortex-a15"; | |
67 | reg = <1>; | |
896b79df | 68 | clock-frequency = <1500000000>; |
15ab426c | 69 | }; |
0d0771ab HN |
70 | }; |
71 | ||
72 | gic: interrupt-controller@f1001000 { | |
d238b5e6 | 73 | compatible = "arm,gic-400"; |
0d0771ab HN |
74 | #interrupt-cells = <3>; |
75 | #address-cells = <0>; | |
76 | interrupt-controller; | |
77 | reg = <0 0xf1001000 0 0x1000>, | |
78 | <0 0xf1002000 0 0x1000>, | |
79 | <0 0xf1004000 0 0x2000>, | |
80 | <0 0xf1006000 0 0x2000>; | |
386a9291 | 81 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
0d0771ab | 82 | }; |
d77db73e | 83 | |
89fbba12 | 84 | gpio0: gpio@e6050000 { |
ab87e3fc | 85 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 86 | reg = <0 0xe6050000 0 0x50>; |
386a9291 | 87 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
88 | #gpio-cells = <2>; |
89 | gpio-controller; | |
90 | gpio-ranges = <&pfc 0 0 32>; | |
91 | #interrupt-cells = <2>; | |
92 | interrupt-controller; | |
4faf9c5e | 93 | clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; |
797a0626 | 94 | power-domains = <&cpg_clocks>; |
ab87e3fc MD |
95 | }; |
96 | ||
89fbba12 | 97 | gpio1: gpio@e6051000 { |
ab87e3fc | 98 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 99 | reg = <0 0xe6051000 0 0x50>; |
386a9291 | 100 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
101 | #gpio-cells = <2>; |
102 | gpio-controller; | |
1329f6d0 | 103 | gpio-ranges = <&pfc 0 32 26>; |
ab87e3fc MD |
104 | #interrupt-cells = <2>; |
105 | interrupt-controller; | |
4faf9c5e | 106 | clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; |
797a0626 | 107 | power-domains = <&cpg_clocks>; |
ab87e3fc MD |
108 | }; |
109 | ||
89fbba12 | 110 | gpio2: gpio@e6052000 { |
ab87e3fc | 111 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 112 | reg = <0 0xe6052000 0 0x50>; |
386a9291 | 113 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
114 | #gpio-cells = <2>; |
115 | gpio-controller; | |
116 | gpio-ranges = <&pfc 0 64 32>; | |
117 | #interrupt-cells = <2>; | |
118 | interrupt-controller; | |
4faf9c5e | 119 | clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; |
797a0626 | 120 | power-domains = <&cpg_clocks>; |
ab87e3fc MD |
121 | }; |
122 | ||
89fbba12 | 123 | gpio3: gpio@e6053000 { |
ab87e3fc | 124 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 125 | reg = <0 0xe6053000 0 0x50>; |
386a9291 | 126 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
127 | #gpio-cells = <2>; |
128 | gpio-controller; | |
129 | gpio-ranges = <&pfc 0 96 32>; | |
130 | #interrupt-cells = <2>; | |
131 | interrupt-controller; | |
4faf9c5e | 132 | clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; |
797a0626 | 133 | power-domains = <&cpg_clocks>; |
ab87e3fc MD |
134 | }; |
135 | ||
89fbba12 | 136 | gpio4: gpio@e6054000 { |
ab87e3fc | 137 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 138 | reg = <0 0xe6054000 0 0x50>; |
386a9291 | 139 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
140 | #gpio-cells = <2>; |
141 | gpio-controller; | |
142 | gpio-ranges = <&pfc 0 128 32>; | |
143 | #interrupt-cells = <2>; | |
144 | interrupt-controller; | |
4faf9c5e | 145 | clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; |
797a0626 | 146 | power-domains = <&cpg_clocks>; |
ab87e3fc MD |
147 | }; |
148 | ||
89fbba12 | 149 | gpio5: gpio@e6055000 { |
ab87e3fc | 150 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 151 | reg = <0 0xe6055000 0 0x50>; |
386a9291 | 152 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
153 | #gpio-cells = <2>; |
154 | gpio-controller; | |
155 | gpio-ranges = <&pfc 0 160 32>; | |
156 | #interrupt-cells = <2>; | |
157 | interrupt-controller; | |
4faf9c5e | 158 | clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; |
797a0626 | 159 | power-domains = <&cpg_clocks>; |
ab87e3fc MD |
160 | }; |
161 | ||
89fbba12 | 162 | gpio6: gpio@e6055400 { |
ab87e3fc | 163 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 164 | reg = <0 0xe6055400 0 0x50>; |
386a9291 | 165 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
166 | #gpio-cells = <2>; |
167 | gpio-controller; | |
168 | gpio-ranges = <&pfc 0 192 32>; | |
169 | #interrupt-cells = <2>; | |
170 | interrupt-controller; | |
4faf9c5e | 171 | clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; |
797a0626 | 172 | power-domains = <&cpg_clocks>; |
ab87e3fc MD |
173 | }; |
174 | ||
89fbba12 | 175 | gpio7: gpio@e6055800 { |
ab87e3fc | 176 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 177 | reg = <0 0xe6055800 0 0x50>; |
386a9291 | 178 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
179 | #gpio-cells = <2>; |
180 | gpio-controller; | |
181 | gpio-ranges = <&pfc 0 224 26>; | |
182 | #interrupt-cells = <2>; | |
183 | interrupt-controller; | |
4faf9c5e | 184 | clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; |
797a0626 | 185 | power-domains = <&cpg_clocks>; |
ab87e3fc MD |
186 | }; |
187 | ||
d103f4d3 MD |
188 | thermal@e61f0000 { |
189 | compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal"; | |
190 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; | |
386a9291 | 191 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
563bc8eb | 192 | clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; |
797a0626 | 193 | power-domains = <&cpg_clocks>; |
d103f4d3 MD |
194 | }; |
195 | ||
03586acf MD |
196 | timer { |
197 | compatible = "arm,armv7-timer"; | |
386a9291 SH |
198 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
199 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
200 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
201 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
03586acf MD |
202 | }; |
203 | ||
ceaa1894 | 204 | cmt0: timer@ffca0000 { |
4217f323 | 205 | compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; |
ceaa1894 | 206 | reg = <0 0xffca0000 0 0x1004>; |
386a9291 SH |
207 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
208 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
ceaa1894 LP |
209 | clocks = <&mstp1_clks R8A7791_CLK_CMT0>; |
210 | clock-names = "fck"; | |
797a0626 | 211 | power-domains = <&cpg_clocks>; |
ceaa1894 LP |
212 | |
213 | renesas,channels-mask = <0x60>; | |
214 | ||
215 | status = "disabled"; | |
216 | }; | |
217 | ||
218 | cmt1: timer@e6130000 { | |
4217f323 | 219 | compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; |
ceaa1894 | 220 | reg = <0 0xe6130000 0 0x1004>; |
386a9291 SH |
221 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
222 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
223 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
224 | <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
225 | <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, | |
226 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, | |
227 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, | |
228 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; | |
ceaa1894 LP |
229 | clocks = <&mstp3_clks R8A7791_CLK_CMT1>; |
230 | clock-names = "fck"; | |
797a0626 | 231 | power-domains = <&cpg_clocks>; |
ceaa1894 LP |
232 | |
233 | renesas,channels-mask = <0xff>; | |
234 | ||
235 | status = "disabled"; | |
236 | }; | |
237 | ||
d77db73e | 238 | irqc0: interrupt-controller@e61c0000 { |
26041b06 | 239 | compatible = "renesas,irqc-r8a7791", "renesas,irqc"; |
d77db73e MD |
240 | #interrupt-cells = <2>; |
241 | interrupt-controller; | |
242 | reg = <0 0xe61c0000 0 0x200>; | |
386a9291 SH |
243 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
244 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
245 | <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
246 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
247 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | |
248 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
249 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
250 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, | |
251 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, | |
252 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
62d386c0 | 253 | clocks = <&mstp4_clks R8A7791_CLK_IRQC>; |
797a0626 | 254 | power-domains = <&cpg_clocks>; |
d77db73e | 255 | }; |
55146927 | 256 | |
fde8feef | 257 | dmac0: dma-controller@e6700000 { |
e6d12b49 | 258 | compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; |
fde8feef | 259 | reg = <0 0xe6700000 0 0x20000>; |
386a9291 SH |
260 | interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH |
261 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH | |
262 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH | |
263 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH | |
264 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH | |
265 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH | |
266 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH | |
267 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH | |
268 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH | |
269 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH | |
270 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH | |
271 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH | |
272 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH | |
273 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH | |
274 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH | |
275 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; | |
fde8feef LP |
276 | interrupt-names = "error", |
277 | "ch0", "ch1", "ch2", "ch3", | |
278 | "ch4", "ch5", "ch6", "ch7", | |
279 | "ch8", "ch9", "ch10", "ch11", | |
280 | "ch12", "ch13", "ch14"; | |
281 | clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; | |
282 | clock-names = "fck"; | |
797a0626 | 283 | power-domains = <&cpg_clocks>; |
fde8feef LP |
284 | #dma-cells = <1>; |
285 | dma-channels = <15>; | |
286 | }; | |
287 | ||
288 | dmac1: dma-controller@e6720000 { | |
e6d12b49 | 289 | compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; |
fde8feef | 290 | reg = <0 0xe6720000 0 0x20000>; |
386a9291 SH |
291 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
292 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH | |
293 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH | |
294 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH | |
295 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH | |
296 | GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH | |
297 | GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH | |
298 | GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH | |
299 | GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH | |
300 | GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH | |
301 | GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH | |
302 | GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH | |
303 | GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH | |
304 | GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH | |
305 | GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH | |
306 | GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; | |
fde8feef LP |
307 | interrupt-names = "error", |
308 | "ch0", "ch1", "ch2", "ch3", | |
309 | "ch4", "ch5", "ch6", "ch7", | |
310 | "ch8", "ch9", "ch10", "ch11", | |
311 | "ch12", "ch13", "ch14"; | |
312 | clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; | |
313 | clock-names = "fck"; | |
797a0626 | 314 | power-domains = <&cpg_clocks>; |
fde8feef LP |
315 | #dma-cells = <1>; |
316 | dma-channels = <15>; | |
317 | }; | |
318 | ||
8994fff6 | 319 | audma0: dma-controller@ec700000 { |
e6d12b49 | 320 | compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; |
8994fff6 | 321 | reg = <0 0xec700000 0 0x10000>; |
386a9291 SH |
322 | interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH |
323 | GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH | |
324 | GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH | |
325 | GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH | |
326 | GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH | |
327 | GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH | |
328 | GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH | |
329 | GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH | |
330 | GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH | |
331 | GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH | |
332 | GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH | |
333 | GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH | |
334 | GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH | |
335 | GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; | |
8994fff6 KM |
336 | interrupt-names = "error", |
337 | "ch0", "ch1", "ch2", "ch3", | |
338 | "ch4", "ch5", "ch6", "ch7", | |
339 | "ch8", "ch9", "ch10", "ch11", | |
340 | "ch12"; | |
341 | clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>; | |
342 | clock-names = "fck"; | |
797a0626 | 343 | power-domains = <&cpg_clocks>; |
8994fff6 KM |
344 | #dma-cells = <1>; |
345 | dma-channels = <13>; | |
346 | }; | |
347 | ||
348 | audma1: dma-controller@ec720000 { | |
e6d12b49 | 349 | compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; |
8994fff6 | 350 | reg = <0 0xec720000 0 0x10000>; |
386a9291 SH |
351 | interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH |
352 | GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH | |
353 | GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH | |
354 | GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH | |
355 | GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH | |
356 | GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH | |
357 | GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH | |
358 | GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH | |
359 | GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH | |
360 | GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH | |
361 | GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH | |
362 | GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH | |
363 | GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH | |
364 | GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; | |
8994fff6 KM |
365 | interrupt-names = "error", |
366 | "ch0", "ch1", "ch2", "ch3", | |
367 | "ch4", "ch5", "ch6", "ch7", | |
368 | "ch8", "ch9", "ch10", "ch11", | |
369 | "ch12"; | |
370 | clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>; | |
371 | clock-names = "fck"; | |
797a0626 | 372 | power-domains = <&cpg_clocks>; |
8994fff6 KM |
373 | #dma-cells = <1>; |
374 | dma-channels = <13>; | |
375 | }; | |
376 | ||
e3e25edc | 377 | usb_dmac0: dma-controller@e65a0000 { |
d01c8bec | 378 | compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac"; |
e3e25edc | 379 | reg = <0 0xe65a0000 0 0x100>; |
386a9291 SH |
380 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH |
381 | GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
e3e25edc YS |
382 | interrupt-names = "ch0", "ch1"; |
383 | clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>; | |
797a0626 | 384 | power-domains = <&cpg_clocks>; |
e3e25edc YS |
385 | #dma-cells = <1>; |
386 | dma-channels = <2>; | |
387 | }; | |
388 | ||
389 | usb_dmac1: dma-controller@e65b0000 { | |
d01c8bec | 390 | compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac"; |
e3e25edc | 391 | reg = <0 0xe65b0000 0 0x100>; |
386a9291 SH |
392 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH |
393 | GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
e3e25edc YS |
394 | interrupt-names = "ch0", "ch1"; |
395 | clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>; | |
797a0626 | 396 | power-domains = <&cpg_clocks>; |
e3e25edc YS |
397 | #dma-cells = <1>; |
398 | dma-channels = <2>; | |
399 | }; | |
400 | ||
36408d9d | 401 | /* The memory map in the User's Manual maps the cores to bus numbers */ |
5bd3de7b WS |
402 | i2c0: i2c@e6508000 { |
403 | #address-cells = <1>; | |
404 | #size-cells = <0>; | |
405 | compatible = "renesas,i2c-r8a7791"; | |
406 | reg = <0 0xe6508000 0 0x40>; | |
386a9291 | 407 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; |
5bd3de7b | 408 | clocks = <&mstp9_clks R8A7791_CLK_I2C0>; |
797a0626 | 409 | power-domains = <&cpg_clocks>; |
49160dc1 | 410 | i2c-scl-internal-delay-ns = <6>; |
5bd3de7b WS |
411 | status = "disabled"; |
412 | }; | |
413 | ||
414 | i2c1: i2c@e6518000 { | |
415 | #address-cells = <1>; | |
416 | #size-cells = <0>; | |
417 | compatible = "renesas,i2c-r8a7791"; | |
418 | reg = <0 0xe6518000 0 0x40>; | |
386a9291 | 419 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; |
5bd3de7b | 420 | clocks = <&mstp9_clks R8A7791_CLK_I2C1>; |
797a0626 | 421 | power-domains = <&cpg_clocks>; |
49160dc1 | 422 | i2c-scl-internal-delay-ns = <6>; |
5bd3de7b WS |
423 | status = "disabled"; |
424 | }; | |
425 | ||
426 | i2c2: i2c@e6530000 { | |
427 | #address-cells = <1>; | |
428 | #size-cells = <0>; | |
429 | compatible = "renesas,i2c-r8a7791"; | |
430 | reg = <0 0xe6530000 0 0x40>; | |
386a9291 | 431 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; |
5bd3de7b | 432 | clocks = <&mstp9_clks R8A7791_CLK_I2C2>; |
797a0626 | 433 | power-domains = <&cpg_clocks>; |
49160dc1 | 434 | i2c-scl-internal-delay-ns = <6>; |
5bd3de7b WS |
435 | status = "disabled"; |
436 | }; | |
437 | ||
438 | i2c3: i2c@e6540000 { | |
439 | #address-cells = <1>; | |
440 | #size-cells = <0>; | |
441 | compatible = "renesas,i2c-r8a7791"; | |
442 | reg = <0 0xe6540000 0 0x40>; | |
386a9291 | 443 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; |
5bd3de7b | 444 | clocks = <&mstp9_clks R8A7791_CLK_I2C3>; |
797a0626 | 445 | power-domains = <&cpg_clocks>; |
49160dc1 | 446 | i2c-scl-internal-delay-ns = <6>; |
5bd3de7b WS |
447 | status = "disabled"; |
448 | }; | |
449 | ||
450 | i2c4: i2c@e6520000 { | |
451 | #address-cells = <1>; | |
452 | #size-cells = <0>; | |
453 | compatible = "renesas,i2c-r8a7791"; | |
454 | reg = <0 0xe6520000 0 0x40>; | |
386a9291 | 455 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
5bd3de7b | 456 | clocks = <&mstp9_clks R8A7791_CLK_I2C4>; |
797a0626 | 457 | power-domains = <&cpg_clocks>; |
49160dc1 | 458 | i2c-scl-internal-delay-ns = <6>; |
5bd3de7b WS |
459 | status = "disabled"; |
460 | }; | |
461 | ||
462 | i2c5: i2c@e6528000 { | |
36408d9d | 463 | /* doesn't need pinmux */ |
5bd3de7b WS |
464 | #address-cells = <1>; |
465 | #size-cells = <0>; | |
466 | compatible = "renesas,i2c-r8a7791"; | |
467 | reg = <0 0xe6528000 0 0x40>; | |
386a9291 | 468 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
5bd3de7b | 469 | clocks = <&mstp9_clks R8A7791_CLK_I2C5>; |
797a0626 | 470 | power-domains = <&cpg_clocks>; |
49160dc1 | 471 | i2c-scl-internal-delay-ns = <110>; |
5bd3de7b WS |
472 | status = "disabled"; |
473 | }; | |
474 | ||
36408d9d WS |
475 | i2c6: i2c@e60b0000 { |
476 | /* doesn't need pinmux */ | |
477 | #address-cells = <1>; | |
478 | #size-cells = <0>; | |
479 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
480 | reg = <0 0xe60b0000 0 0x425>; | |
386a9291 | 481 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
36408d9d | 482 | clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; |
3f58c54b WS |
483 | dmas = <&dmac0 0x77>, <&dmac0 0x78>; |
484 | dma-names = "tx", "rx"; | |
797a0626 | 485 | power-domains = <&cpg_clocks>; |
36408d9d WS |
486 | status = "disabled"; |
487 | }; | |
488 | ||
489 | i2c7: i2c@e6500000 { | |
490 | #address-cells = <1>; | |
491 | #size-cells = <0>; | |
492 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
493 | reg = <0 0xe6500000 0 0x425>; | |
386a9291 | 494 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
36408d9d | 495 | clocks = <&mstp3_clks R8A7791_CLK_IIC0>; |
3f58c54b WS |
496 | dmas = <&dmac0 0x61>, <&dmac0 0x62>; |
497 | dma-names = "tx", "rx"; | |
797a0626 | 498 | power-domains = <&cpg_clocks>; |
36408d9d WS |
499 | status = "disabled"; |
500 | }; | |
501 | ||
502 | i2c8: i2c@e6510000 { | |
503 | #address-cells = <1>; | |
504 | #size-cells = <0>; | |
505 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
506 | reg = <0 0xe6510000 0 0x425>; | |
386a9291 | 507 | interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; |
36408d9d | 508 | clocks = <&mstp3_clks R8A7791_CLK_IIC1>; |
3f58c54b WS |
509 | dmas = <&dmac0 0x65>, <&dmac0 0x66>; |
510 | dma-names = "tx", "rx"; | |
797a0626 | 511 | power-domains = <&cpg_clocks>; |
36408d9d WS |
512 | status = "disabled"; |
513 | }; | |
514 | ||
55146927 MD |
515 | pfc: pfc@e6060000 { |
516 | compatible = "renesas,pfc-r8a7791"; | |
517 | reg = <0 0xe6060000 0 0x250>; | |
55146927 | 518 | }; |
59e79895 | 519 | |
8edae499 LP |
520 | mmcif0: mmc@ee200000 { |
521 | compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif"; | |
522 | reg = <0 0xee200000 0 0x80>; | |
386a9291 | 523 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
8edae499 | 524 | clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; |
16b355b4 LP |
525 | dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; |
526 | dma-names = "tx", "rx"; | |
797a0626 | 527 | power-domains = <&cpg_clocks>; |
8edae499 LP |
528 | reg-io-width = <4>; |
529 | status = "disabled"; | |
d957ab8d | 530 | max-frequency = <97500000>; |
8edae499 LP |
531 | }; |
532 | ||
b7ed8a0d MD |
533 | sdhi0: sd@ee100000 { |
534 | compatible = "renesas,sdhi-r8a7791"; | |
e849b065 | 535 | reg = <0 0xee100000 0 0x328>; |
386a9291 | 536 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
b7ed8a0d | 537 | clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; |
ae67fa2f LP |
538 | dmas = <&dmac1 0xcd>, <&dmac1 0xce>; |
539 | dma-names = "tx", "rx"; | |
797a0626 | 540 | power-domains = <&cpg_clocks>; |
b7ed8a0d MD |
541 | status = "disabled"; |
542 | }; | |
543 | ||
544 | sdhi1: sd@ee140000 { | |
545 | compatible = "renesas,sdhi-r8a7791"; | |
546 | reg = <0 0xee140000 0 0x100>; | |
386a9291 | 547 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
b7ed8a0d | 548 | clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; |
ae67fa2f LP |
549 | dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; |
550 | dma-names = "tx", "rx"; | |
797a0626 | 551 | power-domains = <&cpg_clocks>; |
b7ed8a0d MD |
552 | status = "disabled"; |
553 | }; | |
554 | ||
555 | sdhi2: sd@ee160000 { | |
556 | compatible = "renesas,sdhi-r8a7791"; | |
557 | reg = <0 0xee160000 0 0x100>; | |
386a9291 | 558 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
b7ed8a0d | 559 | clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; |
ae67fa2f LP |
560 | dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; |
561 | dma-names = "tx", "rx"; | |
797a0626 | 562 | power-domains = <&cpg_clocks>; |
b7ed8a0d MD |
563 | status = "disabled"; |
564 | }; | |
565 | ||
9640cf25 | 566 | scifa0: serial@e6c40000 { |
b5b52dd7 GU |
567 | compatible = "renesas,scifa-r8a7791", |
568 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
9640cf25 | 569 | reg = <0 0xe6c40000 0 64>; |
386a9291 | 570 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
9640cf25 | 571 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; |
bb7ca195 | 572 | clock-names = "fck"; |
558d6565 GU |
573 | dmas = <&dmac0 0x21>, <&dmac0 0x22>; |
574 | dma-names = "tx", "rx"; | |
797a0626 | 575 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
576 | status = "disabled"; |
577 | }; | |
578 | ||
579 | scifa1: serial@e6c50000 { | |
b5b52dd7 GU |
580 | compatible = "renesas,scifa-r8a7791", |
581 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
9640cf25 | 582 | reg = <0 0xe6c50000 0 64>; |
386a9291 | 583 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
9640cf25 | 584 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; |
bb7ca195 | 585 | clock-names = "fck"; |
558d6565 GU |
586 | dmas = <&dmac0 0x25>, <&dmac0 0x26>; |
587 | dma-names = "tx", "rx"; | |
797a0626 | 588 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
589 | status = "disabled"; |
590 | }; | |
591 | ||
592 | scifa2: serial@e6c60000 { | |
b5b52dd7 GU |
593 | compatible = "renesas,scifa-r8a7791", |
594 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
9640cf25 | 595 | reg = <0 0xe6c60000 0 64>; |
386a9291 | 596 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; |
9640cf25 | 597 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; |
bb7ca195 | 598 | clock-names = "fck"; |
558d6565 GU |
599 | dmas = <&dmac0 0x27>, <&dmac0 0x28>; |
600 | dma-names = "tx", "rx"; | |
797a0626 | 601 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
602 | status = "disabled"; |
603 | }; | |
604 | ||
605 | scifa3: serial@e6c70000 { | |
b5b52dd7 GU |
606 | compatible = "renesas,scifa-r8a7791", |
607 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
9640cf25 | 608 | reg = <0 0xe6c70000 0 64>; |
386a9291 | 609 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
9640cf25 | 610 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; |
bb7ca195 | 611 | clock-names = "fck"; |
558d6565 GU |
612 | dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; |
613 | dma-names = "tx", "rx"; | |
797a0626 | 614 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
615 | status = "disabled"; |
616 | }; | |
617 | ||
618 | scifa4: serial@e6c78000 { | |
b5b52dd7 GU |
619 | compatible = "renesas,scifa-r8a7791", |
620 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
9640cf25 | 621 | reg = <0 0xe6c78000 0 64>; |
386a9291 | 622 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
9640cf25 | 623 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; |
bb7ca195 | 624 | clock-names = "fck"; |
558d6565 GU |
625 | dmas = <&dmac0 0x1f>, <&dmac0 0x20>; |
626 | dma-names = "tx", "rx"; | |
797a0626 | 627 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
628 | status = "disabled"; |
629 | }; | |
630 | ||
631 | scifa5: serial@e6c80000 { | |
b5b52dd7 GU |
632 | compatible = "renesas,scifa-r8a7791", |
633 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
9640cf25 | 634 | reg = <0 0xe6c80000 0 64>; |
386a9291 | 635 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
9640cf25 | 636 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; |
bb7ca195 | 637 | clock-names = "fck"; |
558d6565 GU |
638 | dmas = <&dmac0 0x23>, <&dmac0 0x24>; |
639 | dma-names = "tx", "rx"; | |
797a0626 | 640 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
641 | status = "disabled"; |
642 | }; | |
643 | ||
644 | scifb0: serial@e6c20000 { | |
b5b52dd7 GU |
645 | compatible = "renesas,scifb-r8a7791", |
646 | "renesas,rcar-gen2-scifb", "renesas,scifb"; | |
9640cf25 | 647 | reg = <0 0xe6c20000 0 64>; |
386a9291 | 648 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
9640cf25 | 649 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; |
bb7ca195 | 650 | clock-names = "fck"; |
558d6565 GU |
651 | dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; |
652 | dma-names = "tx", "rx"; | |
797a0626 | 653 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
654 | status = "disabled"; |
655 | }; | |
656 | ||
657 | scifb1: serial@e6c30000 { | |
b5b52dd7 GU |
658 | compatible = "renesas,scifb-r8a7791", |
659 | "renesas,rcar-gen2-scifb", "renesas,scifb"; | |
9640cf25 | 660 | reg = <0 0xe6c30000 0 64>; |
386a9291 | 661 | interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; |
9640cf25 | 662 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; |
bb7ca195 | 663 | clock-names = "fck"; |
558d6565 GU |
664 | dmas = <&dmac0 0x19>, <&dmac0 0x1a>; |
665 | dma-names = "tx", "rx"; | |
797a0626 | 666 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
667 | status = "disabled"; |
668 | }; | |
669 | ||
670 | scifb2: serial@e6ce0000 { | |
b5b52dd7 GU |
671 | compatible = "renesas,scifb-r8a7791", |
672 | "renesas,rcar-gen2-scifb", "renesas,scifb"; | |
9640cf25 | 673 | reg = <0 0xe6ce0000 0 64>; |
386a9291 | 674 | interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; |
9640cf25 | 675 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; |
bb7ca195 | 676 | clock-names = "fck"; |
558d6565 GU |
677 | dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; |
678 | dma-names = "tx", "rx"; | |
797a0626 | 679 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
680 | status = "disabled"; |
681 | }; | |
682 | ||
683 | scif0: serial@e6e60000 { | |
b5b52dd7 GU |
684 | compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", |
685 | "renesas,scif"; | |
9640cf25 | 686 | reg = <0 0xe6e60000 0 64>; |
386a9291 | 687 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
394730a1 GU |
688 | clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>, |
689 | <&scif_clk>; | |
690 | clock-names = "fck", "brg_int", "scif_clk"; | |
558d6565 GU |
691 | dmas = <&dmac0 0x29>, <&dmac0 0x2a>; |
692 | dma-names = "tx", "rx"; | |
797a0626 | 693 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
694 | status = "disabled"; |
695 | }; | |
696 | ||
697 | scif1: serial@e6e68000 { | |
b5b52dd7 GU |
698 | compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", |
699 | "renesas,scif"; | |
9640cf25 | 700 | reg = <0 0xe6e68000 0 64>; |
386a9291 | 701 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
394730a1 GU |
702 | clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>, |
703 | <&scif_clk>; | |
704 | clock-names = "fck", "brg_int", "scif_clk"; | |
558d6565 GU |
705 | dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; |
706 | dma-names = "tx", "rx"; | |
797a0626 | 707 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
708 | status = "disabled"; |
709 | }; | |
710 | ||
711 | scif2: serial@e6e58000 { | |
b5b52dd7 GU |
712 | compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", |
713 | "renesas,scif"; | |
9640cf25 | 714 | reg = <0 0xe6e58000 0 64>; |
386a9291 | 715 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
394730a1 GU |
716 | clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>, |
717 | <&scif_clk>; | |
718 | clock-names = "fck", "brg_int", "scif_clk"; | |
558d6565 GU |
719 | dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; |
720 | dma-names = "tx", "rx"; | |
797a0626 | 721 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
722 | status = "disabled"; |
723 | }; | |
724 | ||
725 | scif3: serial@e6ea8000 { | |
b5b52dd7 GU |
726 | compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", |
727 | "renesas,scif"; | |
9640cf25 | 728 | reg = <0 0xe6ea8000 0 64>; |
386a9291 | 729 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
394730a1 GU |
730 | clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>, |
731 | <&scif_clk>; | |
732 | clock-names = "fck", "brg_int", "scif_clk"; | |
558d6565 GU |
733 | dmas = <&dmac0 0x2f>, <&dmac0 0x30>; |
734 | dma-names = "tx", "rx"; | |
797a0626 | 735 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
736 | status = "disabled"; |
737 | }; | |
738 | ||
739 | scif4: serial@e6ee0000 { | |
b5b52dd7 GU |
740 | compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", |
741 | "renesas,scif"; | |
9640cf25 | 742 | reg = <0 0xe6ee0000 0 64>; |
386a9291 | 743 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
394730a1 GU |
744 | clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>, |
745 | <&scif_clk>; | |
746 | clock-names = "fck", "brg_int", "scif_clk"; | |
558d6565 GU |
747 | dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; |
748 | dma-names = "tx", "rx"; | |
797a0626 | 749 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
750 | status = "disabled"; |
751 | }; | |
752 | ||
753 | scif5: serial@e6ee8000 { | |
b5b52dd7 GU |
754 | compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", |
755 | "renesas,scif"; | |
9640cf25 | 756 | reg = <0 0xe6ee8000 0 64>; |
386a9291 | 757 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
394730a1 GU |
758 | clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>, |
759 | <&scif_clk>; | |
760 | clock-names = "fck", "brg_int", "scif_clk"; | |
558d6565 GU |
761 | dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; |
762 | dma-names = "tx", "rx"; | |
797a0626 | 763 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
764 | status = "disabled"; |
765 | }; | |
766 | ||
767 | hscif0: serial@e62c0000 { | |
b5b52dd7 GU |
768 | compatible = "renesas,hscif-r8a7791", |
769 | "renesas,rcar-gen2-hscif", "renesas,hscif"; | |
9640cf25 | 770 | reg = <0 0xe62c0000 0 96>; |
386a9291 | 771 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
394730a1 GU |
772 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>, |
773 | <&scif_clk>; | |
774 | clock-names = "fck", "brg_int", "scif_clk"; | |
558d6565 GU |
775 | dmas = <&dmac0 0x39>, <&dmac0 0x3a>; |
776 | dma-names = "tx", "rx"; | |
797a0626 | 777 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
778 | status = "disabled"; |
779 | }; | |
780 | ||
781 | hscif1: serial@e62c8000 { | |
b5b52dd7 GU |
782 | compatible = "renesas,hscif-r8a7791", |
783 | "renesas,rcar-gen2-hscif", "renesas,hscif"; | |
9640cf25 | 784 | reg = <0 0xe62c8000 0 96>; |
386a9291 | 785 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
394730a1 GU |
786 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>, |
787 | <&scif_clk>; | |
788 | clock-names = "fck", "brg_int", "scif_clk"; | |
558d6565 GU |
789 | dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; |
790 | dma-names = "tx", "rx"; | |
797a0626 | 791 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
792 | status = "disabled"; |
793 | }; | |
794 | ||
795 | hscif2: serial@e62d0000 { | |
b5b52dd7 GU |
796 | compatible = "renesas,hscif-r8a7791", |
797 | "renesas,rcar-gen2-hscif", "renesas,hscif"; | |
9640cf25 | 798 | reg = <0 0xe62d0000 0 96>; |
386a9291 | 799 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
394730a1 GU |
800 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>, |
801 | <&scif_clk>; | |
802 | clock-names = "fck", "brg_int", "scif_clk"; | |
558d6565 GU |
803 | dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; |
804 | dma-names = "tx", "rx"; | |
797a0626 | 805 | power-domains = <&cpg_clocks>; |
9640cf25 LP |
806 | status = "disabled"; |
807 | }; | |
808 | ||
2e5d55ce SS |
809 | ether: ethernet@ee700000 { |
810 | compatible = "renesas,ether-r8a7791"; | |
811 | reg = <0 0xee700000 0 0x400>; | |
386a9291 | 812 | interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; |
2e5d55ce | 813 | clocks = <&mstp8_clks R8A7791_CLK_ETHER>; |
797a0626 | 814 | power-domains = <&cpg_clocks>; |
2e5d55ce SS |
815 | phy-mode = "rmii"; |
816 | #address-cells = <1>; | |
817 | #size-cells = <0>; | |
818 | status = "disabled"; | |
819 | }; | |
820 | ||
46ece349 SS |
821 | avb: ethernet@e6800000 { |
822 | compatible = "renesas,etheravb-r8a7791", | |
823 | "renesas,etheravb-rcar-gen2"; | |
824 | reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; | |
386a9291 | 825 | interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; |
46ece349 SS |
826 | clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>; |
827 | power-domains = <&cpg_clocks>; | |
828 | #address-cells = <1>; | |
829 | #size-cells = <0>; | |
830 | status = "disabled"; | |
831 | }; | |
832 | ||
b8532c69 VB |
833 | sata0: sata@ee300000 { |
834 | compatible = "renesas,sata-r8a7791"; | |
835 | reg = <0 0xee300000 0 0x2000>; | |
386a9291 | 836 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
b8532c69 | 837 | clocks = <&mstp8_clks R8A7791_CLK_SATA0>; |
797a0626 | 838 | power-domains = <&cpg_clocks>; |
b8532c69 VB |
839 | status = "disabled"; |
840 | }; | |
841 | ||
842 | sata1: sata@ee500000 { | |
843 | compatible = "renesas,sata-r8a7791"; | |
844 | reg = <0 0xee500000 0 0x2000>; | |
386a9291 | 845 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
b8532c69 | 846 | clocks = <&mstp8_clks R8A7791_CLK_SATA1>; |
797a0626 | 847 | power-domains = <&cpg_clocks>; |
b8532c69 VB |
848 | status = "disabled"; |
849 | }; | |
850 | ||
1c1fee7c | 851 | hsusb: usb@e6590000 { |
8cf1d454 | 852 | compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs"; |
1c1fee7c | 853 | reg = <0 0xe6590000 0 0x100>; |
386a9291 | 854 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
1c1fee7c | 855 | clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; |
7706993e YS |
856 | dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, |
857 | <&usb_dmac1 0>, <&usb_dmac1 1>; | |
858 | dma-names = "ch0", "ch1", "ch2", "ch3"; | |
797a0626 GU |
859 | power-domains = <&cpg_clocks>; |
860 | renesas,buswait = <4>; | |
861 | phys = <&usb0 1>; | |
862 | phy-names = "usb"; | |
1c1fee7c YS |
863 | status = "disabled"; |
864 | }; | |
865 | ||
3b7e530d SS |
866 | usbphy: usb-phy@e6590100 { |
867 | compatible = "renesas,usb-phy-r8a7791"; | |
868 | reg = <0 0xe6590100 0 0x100>; | |
869 | #address-cells = <1>; | |
870 | #size-cells = <0>; | |
871 | clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; | |
872 | clock-names = "usbhs"; | |
797a0626 | 873 | power-domains = <&cpg_clocks>; |
3b7e530d SS |
874 | status = "disabled"; |
875 | ||
876 | usb0: usb-channel@0 { | |
877 | reg = <0>; | |
878 | #phy-cells = <1>; | |
879 | }; | |
880 | usb2: usb-channel@2 { | |
881 | reg = <2>; | |
882 | #phy-cells = <1>; | |
883 | }; | |
884 | }; | |
885 | ||
0b8d1d57 SS |
886 | vin0: video@e6ef0000 { |
887 | compatible = "renesas,vin-r8a7791"; | |
0b8d1d57 | 888 | reg = <0 0xe6ef0000 0 0x1000>; |
386a9291 | 889 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; |
797a0626 GU |
890 | clocks = <&mstp8_clks R8A7791_CLK_VIN0>; |
891 | power-domains = <&cpg_clocks>; | |
0b8d1d57 SS |
892 | status = "disabled"; |
893 | }; | |
894 | ||
895 | vin1: video@e6ef1000 { | |
896 | compatible = "renesas,vin-r8a7791"; | |
0b8d1d57 | 897 | reg = <0 0xe6ef1000 0 0x1000>; |
386a9291 | 898 | interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; |
797a0626 GU |
899 | clocks = <&mstp8_clks R8A7791_CLK_VIN1>; |
900 | power-domains = <&cpg_clocks>; | |
0b8d1d57 SS |
901 | status = "disabled"; |
902 | }; | |
903 | ||
904 | vin2: video@e6ef2000 { | |
905 | compatible = "renesas,vin-r8a7791"; | |
0b8d1d57 | 906 | reg = <0 0xe6ef2000 0 0x1000>; |
386a9291 | 907 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; |
797a0626 GU |
908 | clocks = <&mstp8_clks R8A7791_CLK_VIN2>; |
909 | power-domains = <&cpg_clocks>; | |
0b8d1d57 SS |
910 | status = "disabled"; |
911 | }; | |
912 | ||
8eefac2d LP |
913 | vsp1@fe928000 { |
914 | compatible = "renesas,vsp1"; | |
915 | reg = <0 0xfe928000 0 0x8000>; | |
386a9291 | 916 | interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; |
8eefac2d | 917 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; |
797a0626 | 918 | power-domains = <&cpg_clocks>; |
8eefac2d LP |
919 | |
920 | renesas,has-lut; | |
921 | renesas,has-sru; | |
922 | renesas,#rpf = <5>; | |
923 | renesas,#uds = <3>; | |
924 | renesas,#wpf = <4>; | |
925 | }; | |
926 | ||
927 | vsp1@fe930000 { | |
928 | compatible = "renesas,vsp1"; | |
929 | reg = <0 0xfe930000 0 0x8000>; | |
386a9291 | 930 | interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; |
8eefac2d | 931 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; |
797a0626 | 932 | power-domains = <&cpg_clocks>; |
8eefac2d LP |
933 | |
934 | renesas,has-lif; | |
935 | renesas,has-lut; | |
936 | renesas,#rpf = <4>; | |
937 | renesas,#uds = <1>; | |
938 | renesas,#wpf = <4>; | |
939 | }; | |
940 | ||
941 | vsp1@fe938000 { | |
942 | compatible = "renesas,vsp1"; | |
943 | reg = <0 0xfe938000 0 0x8000>; | |
386a9291 | 944 | interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; |
8eefac2d | 945 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; |
797a0626 | 946 | power-domains = <&cpg_clocks>; |
8eefac2d LP |
947 | |
948 | renesas,has-lif; | |
949 | renesas,has-lut; | |
950 | renesas,#rpf = <4>; | |
951 | renesas,#uds = <1>; | |
952 | renesas,#wpf = <4>; | |
953 | }; | |
954 | ||
955 | du: display@feb00000 { | |
956 | compatible = "renesas,du-r8a7791"; | |
957 | reg = <0 0xfeb00000 0 0x40000>, | |
958 | <0 0xfeb90000 0 0x1c>; | |
959 | reg-names = "du", "lvds.0"; | |
386a9291 SH |
960 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
961 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; | |
8eefac2d LP |
962 | clocks = <&mstp7_clks R8A7791_CLK_DU0>, |
963 | <&mstp7_clks R8A7791_CLK_DU1>, | |
964 | <&mstp7_clks R8A7791_CLK_LVDS0>; | |
965 | clock-names = "du.0", "du.1", "lvds.0"; | |
966 | status = "disabled"; | |
967 | ||
968 | ports { | |
969 | #address-cells = <1>; | |
970 | #size-cells = <0>; | |
971 | ||
972 | port@0 { | |
973 | reg = <0>; | |
974 | du_out_rgb: endpoint { | |
975 | }; | |
976 | }; | |
977 | port@1 { | |
978 | reg = <1>; | |
979 | du_out_lvds0: endpoint { | |
980 | }; | |
981 | }; | |
982 | }; | |
983 | }; | |
984 | ||
3cf01884 SS |
985 | can0: can@e6e80000 { |
986 | compatible = "renesas,can-r8a7791"; | |
987 | reg = <0 0xe6e80000 0 0x1000>; | |
386a9291 | 988 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; |
3cf01884 SS |
989 | clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, |
990 | <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; | |
991 | clock-names = "clkp1", "clkp2", "can_clk"; | |
797a0626 | 992 | power-domains = <&cpg_clocks>; |
3cf01884 SS |
993 | status = "disabled"; |
994 | }; | |
995 | ||
996 | can1: can@e6e88000 { | |
997 | compatible = "renesas,can-r8a7791"; | |
998 | reg = <0 0xe6e88000 0 0x1000>; | |
386a9291 | 999 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; |
3cf01884 SS |
1000 | clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, |
1001 | <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; | |
1002 | clock-names = "clkp1", "clkp2", "can_clk"; | |
797a0626 | 1003 | power-domains = <&cpg_clocks>; |
3cf01884 SS |
1004 | status = "disabled"; |
1005 | }; | |
1006 | ||
0caa3660 MU |
1007 | jpu: jpeg-codec@fe980000 { |
1008 | compatible = "renesas,jpu-r8a7791"; | |
1009 | reg = <0 0xfe980000 0 0x10300>; | |
386a9291 | 1010 | interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
0caa3660 | 1011 | clocks = <&mstp1_clks R8A7791_CLK_JPU>; |
797a0626 | 1012 | power-domains = <&cpg_clocks>; |
0caa3660 MU |
1013 | }; |
1014 | ||
59e79895 LP |
1015 | clocks { |
1016 | #address-cells = <2>; | |
1017 | #size-cells = <2>; | |
1018 | ranges; | |
1019 | ||
1020 | /* External root clock */ | |
1021 | extal_clk: extal_clk { | |
1022 | compatible = "fixed-clock"; | |
1023 | #clock-cells = <0>; | |
1024 | /* This value must be overriden by the board. */ | |
1025 | clock-frequency = <0>; | |
1026 | clock-output-names = "extal"; | |
1027 | }; | |
1028 | ||
0d3dbde8 KM |
1029 | /* |
1030 | * The external audio clocks are configured as 0 Hz fixed frequency clocks by | |
1031 | * default. Boards that provide audio clocks should override them. | |
1032 | */ | |
1033 | audio_clk_a: audio_clk_a { | |
1034 | compatible = "fixed-clock"; | |
1035 | #clock-cells = <0>; | |
1036 | clock-frequency = <0>; | |
1037 | clock-output-names = "audio_clk_a"; | |
1038 | }; | |
1039 | audio_clk_b: audio_clk_b { | |
1040 | compatible = "fixed-clock"; | |
1041 | #clock-cells = <0>; | |
1042 | clock-frequency = <0>; | |
1043 | clock-output-names = "audio_clk_b"; | |
1044 | }; | |
1045 | audio_clk_c: audio_clk_c { | |
1046 | compatible = "fixed-clock"; | |
1047 | #clock-cells = <0>; | |
1048 | clock-frequency = <0>; | |
1049 | clock-output-names = "audio_clk_c"; | |
1050 | }; | |
1051 | ||
66c405e7 PE |
1052 | /* External PCIe clock - can be overridden by the board */ |
1053 | pcie_bus_clk: pcie_bus_clk { | |
1054 | compatible = "fixed-clock"; | |
1055 | #clock-cells = <0>; | |
1056 | clock-frequency = <100000000>; | |
1057 | clock-output-names = "pcie_bus"; | |
1058 | status = "disabled"; | |
1059 | }; | |
1060 | ||
394730a1 GU |
1061 | /* External SCIF clock */ |
1062 | scif_clk: scif { | |
1063 | compatible = "fixed-clock"; | |
1064 | #clock-cells = <0>; | |
1065 | /* This value must be overridden by the board. */ | |
1066 | clock-frequency = <0>; | |
1067 | status = "disabled"; | |
1068 | }; | |
1069 | ||
b324252c SS |
1070 | /* External USB clock - can be overridden by the board */ |
1071 | usb_extal_clk: usb_extal_clk { | |
1072 | compatible = "fixed-clock"; | |
1073 | #clock-cells = <0>; | |
1074 | clock-frequency = <48000000>; | |
1075 | clock-output-names = "usb_extal"; | |
1076 | }; | |
1077 | ||
1078 | /* External CAN clock */ | |
1079 | can_clk: can_clk { | |
1080 | compatible = "fixed-clock"; | |
1081 | #clock-cells = <0>; | |
1082 | /* This value must be overridden by the board. */ | |
1083 | clock-frequency = <0>; | |
1084 | clock-output-names = "can_clk"; | |
1085 | status = "disabled"; | |
1086 | }; | |
1087 | ||
59e79895 LP |
1088 | /* Special CPG clocks */ |
1089 | cpg_clocks: cpg_clocks@e6150000 { | |
1090 | compatible = "renesas,r8a7791-cpg-clocks", | |
1091 | "renesas,rcar-gen2-cpg-clocks"; | |
1092 | reg = <0 0xe6150000 0 0x1000>; | |
b324252c | 1093 | clocks = <&extal_clk &usb_extal_clk>; |
59e79895 LP |
1094 | #clock-cells = <1>; |
1095 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
b324252c | 1096 | "lb", "qspi", "sdh", "sd0", "z", |
ae65a8ae | 1097 | "rcan", "adsp"; |
797a0626 | 1098 | #power-domain-cells = <0>; |
59e79895 LP |
1099 | }; |
1100 | ||
1101 | /* Variable factor clocks */ | |
2ea0d4ec | 1102 | sd2_clk: sd2_clk@e6150078 { |
59e79895 LP |
1103 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; |
1104 | reg = <0 0xe6150078 0 4>; | |
1105 | clocks = <&pll1_div2_clk>; | |
1106 | #clock-cells = <0>; | |
2ea0d4ec | 1107 | clock-output-names = "sd2"; |
59e79895 | 1108 | }; |
2ea0d4ec | 1109 | sd3_clk: sd3_clk@e615026c { |
59e79895 | 1110 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; |
c9b22772 | 1111 | reg = <0 0xe615026c 0 4>; |
59e79895 LP |
1112 | clocks = <&pll1_div2_clk>; |
1113 | #clock-cells = <0>; | |
2ea0d4ec | 1114 | clock-output-names = "sd3"; |
59e79895 LP |
1115 | }; |
1116 | mmc0_clk: mmc0_clk@e6150240 { | |
1117 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
1118 | reg = <0 0xe6150240 0 4>; | |
1119 | clocks = <&pll1_div2_clk>; | |
1120 | #clock-cells = <0>; | |
1121 | clock-output-names = "mmc0"; | |
1122 | }; | |
1123 | ssp_clk: ssp_clk@e6150248 { | |
1124 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
1125 | reg = <0 0xe6150248 0 4>; | |
1126 | clocks = <&pll1_div2_clk>; | |
1127 | #clock-cells = <0>; | |
1128 | clock-output-names = "ssp"; | |
1129 | }; | |
1130 | ssprs_clk: ssprs_clk@e615024c { | |
1131 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
1132 | reg = <0 0xe615024c 0 4>; | |
1133 | clocks = <&pll1_div2_clk>; | |
1134 | #clock-cells = <0>; | |
1135 | clock-output-names = "ssprs"; | |
1136 | }; | |
1137 | ||
1138 | /* Fixed factor clocks */ | |
1139 | pll1_div2_clk: pll1_div2_clk { | |
1140 | compatible = "fixed-factor-clock"; | |
1141 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
1142 | #clock-cells = <0>; | |
1143 | clock-div = <2>; | |
1144 | clock-mult = <1>; | |
1145 | clock-output-names = "pll1_div2"; | |
1146 | }; | |
1147 | zg_clk: zg_clk { | |
1148 | compatible = "fixed-factor-clock"; | |
1149 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
1150 | #clock-cells = <0>; | |
1151 | clock-div = <3>; | |
1152 | clock-mult = <1>; | |
1153 | clock-output-names = "zg"; | |
1154 | }; | |
1155 | zx_clk: zx_clk { | |
1156 | compatible = "fixed-factor-clock"; | |
1157 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
1158 | #clock-cells = <0>; | |
1159 | clock-div = <3>; | |
1160 | clock-mult = <1>; | |
1161 | clock-output-names = "zx"; | |
1162 | }; | |
1163 | zs_clk: zs_clk { | |
1164 | compatible = "fixed-factor-clock"; | |
1165 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
1166 | #clock-cells = <0>; | |
1167 | clock-div = <6>; | |
1168 | clock-mult = <1>; | |
1169 | clock-output-names = "zs"; | |
1170 | }; | |
1171 | hp_clk: hp_clk { | |
1172 | compatible = "fixed-factor-clock"; | |
1173 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
1174 | #clock-cells = <0>; | |
1175 | clock-div = <12>; | |
1176 | clock-mult = <1>; | |
1177 | clock-output-names = "hp"; | |
1178 | }; | |
1179 | i_clk: i_clk { | |
1180 | compatible = "fixed-factor-clock"; | |
1181 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
1182 | #clock-cells = <0>; | |
1183 | clock-div = <2>; | |
1184 | clock-mult = <1>; | |
1185 | clock-output-names = "i"; | |
1186 | }; | |
1187 | b_clk: b_clk { | |
1188 | compatible = "fixed-factor-clock"; | |
1189 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
1190 | #clock-cells = <0>; | |
1191 | clock-div = <12>; | |
1192 | clock-mult = <1>; | |
1193 | clock-output-names = "b"; | |
1194 | }; | |
1195 | p_clk: p_clk { | |
1196 | compatible = "fixed-factor-clock"; | |
1197 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
1198 | #clock-cells = <0>; | |
1199 | clock-div = <24>; | |
1200 | clock-mult = <1>; | |
1201 | clock-output-names = "p"; | |
1202 | }; | |
1203 | cl_clk: cl_clk { | |
1204 | compatible = "fixed-factor-clock"; | |
1205 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
1206 | #clock-cells = <0>; | |
1207 | clock-div = <48>; | |
1208 | clock-mult = <1>; | |
1209 | clock-output-names = "cl"; | |
1210 | }; | |
1211 | m2_clk: m2_clk { | |
1212 | compatible = "fixed-factor-clock"; | |
1213 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
1214 | #clock-cells = <0>; | |
1215 | clock-div = <8>; | |
1216 | clock-mult = <1>; | |
1217 | clock-output-names = "m2"; | |
1218 | }; | |
59e79895 LP |
1219 | rclk_clk: rclk_clk { |
1220 | compatible = "fixed-factor-clock"; | |
1221 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
1222 | #clock-cells = <0>; | |
1223 | clock-div = <(48 * 1024)>; | |
1224 | clock-mult = <1>; | |
1225 | clock-output-names = "rclk"; | |
1226 | }; | |
1227 | oscclk_clk: oscclk_clk { | |
1228 | compatible = "fixed-factor-clock"; | |
1229 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
1230 | #clock-cells = <0>; | |
1231 | clock-div = <(12 * 1024)>; | |
1232 | clock-mult = <1>; | |
1233 | clock-output-names = "oscclk"; | |
1234 | }; | |
1235 | zb3_clk: zb3_clk { | |
1236 | compatible = "fixed-factor-clock"; | |
1237 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
1238 | #clock-cells = <0>; | |
1239 | clock-div = <4>; | |
1240 | clock-mult = <1>; | |
1241 | clock-output-names = "zb3"; | |
1242 | }; | |
1243 | zb3d2_clk: zb3d2_clk { | |
1244 | compatible = "fixed-factor-clock"; | |
1245 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
1246 | #clock-cells = <0>; | |
1247 | clock-div = <8>; | |
1248 | clock-mult = <1>; | |
1249 | clock-output-names = "zb3d2"; | |
1250 | }; | |
1251 | ddr_clk: ddr_clk { | |
1252 | compatible = "fixed-factor-clock"; | |
1253 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
1254 | #clock-cells = <0>; | |
1255 | clock-div = <8>; | |
1256 | clock-mult = <1>; | |
1257 | clock-output-names = "ddr"; | |
1258 | }; | |
1259 | mp_clk: mp_clk { | |
1260 | compatible = "fixed-factor-clock"; | |
1261 | clocks = <&pll1_div2_clk>; | |
1262 | #clock-cells = <0>; | |
1263 | clock-div = <15>; | |
1264 | clock-mult = <1>; | |
1265 | clock-output-names = "mp"; | |
1266 | }; | |
1267 | cp_clk: cp_clk { | |
1268 | compatible = "fixed-factor-clock"; | |
1269 | clocks = <&extal_clk>; | |
1270 | #clock-cells = <0>; | |
1271 | clock-div = <2>; | |
1272 | clock-mult = <1>; | |
1273 | clock-output-names = "cp"; | |
1274 | }; | |
1275 | ||
1276 | /* Gate clocks */ | |
cded80f8 LP |
1277 | mstp0_clks: mstp0_clks@e6150130 { |
1278 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1279 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; | |
1280 | clocks = <&mp_clk>; | |
1281 | #clock-cells = <1>; | |
cb0bf851 | 1282 | clock-indices = <R8A7791_CLK_MSIOF0>; |
cded80f8 LP |
1283 | clock-output-names = "msiof0"; |
1284 | }; | |
59e79895 LP |
1285 | mstp1_clks: mstp1_clks@e6150134 { |
1286 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1287 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
74d89d25 YH |
1288 | clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>, |
1289 | <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, | |
1290 | <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, | |
1291 | <&zs_clk>; | |
59e79895 | 1292 | #clock-cells = <1>; |
cb0bf851 | 1293 | clock-indices = < |
74d89d25 YH |
1294 | R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU |
1295 | R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG | |
1296 | R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 | |
1297 | R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 | |
1298 | R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0 | |
1299 | R8A7791_CLK_VSP1_S | |
59e79895 LP |
1300 | >; |
1301 | clock-output-names = | |
74d89d25 YH |
1302 | "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg", |
1303 | "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0", | |
1304 | "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy"; | |
59e79895 LP |
1305 | }; |
1306 | mstp2_clks: mstp2_clks@e6150138 { | |
1307 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1308 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
1309 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
4e074bc8 GU |
1310 | <&mp_clk>, <&mp_clk>, <&mp_clk>, |
1311 | <&zs_clk>, <&zs_clk>; | |
59e79895 | 1312 | #clock-cells = <1>; |
cb0bf851 | 1313 | clock-indices = < |
59e79895 | 1314 | R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 |
cded80f8 LP |
1315 | R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 |
1316 | R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 | |
4e074bc8 | 1317 | R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 |
59e79895 LP |
1318 | >; |
1319 | clock-output-names = | |
0c002ef8 | 1320 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
4e074bc8 GU |
1321 | "scifb1", "msiof1", "scifb2", |
1322 | "sys-dmac1", "sys-dmac0"; | |
59e79895 LP |
1323 | }; |
1324 | mstp3_clks: mstp3_clks@e615013c { | |
1325 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1326 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
2ea0d4ec | 1327 | clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>, |
b9473d9f YS |
1328 | <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, |
1329 | <&hp_clk>, <&hp_clk>; | |
59e79895 | 1330 | #clock-cells = <1>; |
cb0bf851 | 1331 | clock-indices = < |
c08691b5 | 1332 | R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 |
4bfb3767 PE |
1333 | R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 |
1334 | R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 | |
b9473d9f | 1335 | R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1 |
59e79895 LP |
1336 | >; |
1337 | clock-output-names = | |
c08691b5 | 1338 | "tpu0", "sdhi2", "sdhi1", "sdhi0", |
b9473d9f YS |
1339 | "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1", |
1340 | "usbdmac0", "usbdmac1"; | |
59e79895 | 1341 | }; |
62d386c0 GU |
1342 | mstp4_clks: mstp4_clks@e6150140 { |
1343 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1344 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; | |
1345 | clocks = <&cp_clk>; | |
1346 | #clock-cells = <1>; | |
1347 | clock-indices = <R8A7791_CLK_IRQC>; | |
1348 | clock-output-names = "irqc"; | |
1349 | }; | |
59e79895 LP |
1350 | mstp5_clks: mstp5_clks@e6150144 { |
1351 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1352 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; | |
ae65a8ae SS |
1353 | clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>, |
1354 | <&extal_clk>, <&p_clk>; | |
59e79895 | 1355 | #clock-cells = <1>; |
cb0bf851 BD |
1356 | clock-indices = < |
1357 | R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 | |
ae65a8ae SS |
1358 | R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL |
1359 | R8A7791_CLK_PWM | |
cb0bf851 | 1360 | >; |
ae65a8ae SS |
1361 | clock-output-names = "audmac0", "audmac1", "adsp_mod", |
1362 | "thermal", "pwm"; | |
59e79895 LP |
1363 | }; |
1364 | mstp7_clks: mstp7_clks@e615014c { | |
1365 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1366 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
118e4e6a | 1367 | clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, |
59e79895 LP |
1368 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
1369 | <&zx_clk>, <&zx_clk>, <&zx_clk>; | |
1370 | #clock-cells = <1>; | |
cb0bf851 | 1371 | clock-indices = < |
6225b99a | 1372 | R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 |
59e79895 LP |
1373 | R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 |
1374 | R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 | |
1375 | R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 | |
1376 | R8A7791_CLK_LVDS0 | |
1377 | >; | |
1378 | clock-output-names = | |
6225b99a | 1379 | "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", |
59e79895 LP |
1380 | "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; |
1381 | }; | |
1382 | mstp8_clks: mstp8_clks@e6150990 { | |
1383 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1384 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
75a499a6 | 1385 | clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>, |
eaa870b3 SS |
1386 | <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, |
1387 | <&zs_clk>; | |
59e79895 | 1388 | #clock-cells = <1>; |
cb0bf851 | 1389 | clock-indices = < |
7408d306 | 1390 | R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB |
09c98346 | 1391 | R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 |
eaa870b3 SS |
1392 | R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER |
1393 | R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 | |
09c98346 | 1394 | >; |
65f05c38 | 1395 | clock-output-names = |
eaa870b3 SS |
1396 | "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", |
1397 | "etheravb", "ether", "sata1", "sata0"; | |
59e79895 LP |
1398 | }; |
1399 | mstp9_clks: mstp9_clks@e6150994 { | |
1400 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1401 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
4faf9c5e GU |
1402 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
1403 | <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, | |
1404 | <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, | |
11b48db9 LP |
1405 | <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, |
1406 | <&hp_clk>, <&hp_clk>; | |
59e79895 | 1407 | #clock-cells = <1>; |
cb0bf851 | 1408 | clock-indices = < |
4faf9c5e GU |
1409 | R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 |
1410 | R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 | |
c08691b5 WS |
1411 | R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 |
1412 | R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 | |
1413 | R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 | |
59e79895 LP |
1414 | >; |
1415 | clock-output-names = | |
4faf9c5e GU |
1416 | "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", |
1417 | "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", | |
1418 | "i2c1", "i2c0"; | |
59e79895 | 1419 | }; |
ee914152 KM |
1420 | mstp10_clks: mstp10_clks@e6150998 { |
1421 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1422 | reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; | |
1423 | clocks = <&p_clk>, | |
1424 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
1425 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
1426 | <&p_clk>, | |
1427 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
1428 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
1429 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
1430 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
1431 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
88401702 | 1432 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, |
ee914152 KM |
1433 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; |
1434 | ||
1435 | #clock-cells = <1>; | |
1436 | clock-indices = < | |
1437 | R8A7791_CLK_SSI_ALL | |
1438 | R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 | |
1439 | R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 | |
1440 | R8A7791_CLK_SCU_ALL | |
1441 | R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 | |
88401702 | 1442 | R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0 |
ee914152 KM |
1443 | R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 |
1444 | R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 | |
1445 | >; | |
1446 | clock-output-names = | |
1447 | "ssi-all", | |
1448 | "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", | |
1449 | "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", | |
1450 | "scu-all", | |
1451 | "scu-dvc1", "scu-dvc0", | |
88401702 | 1452 | "scu-ctu1-mix1", "scu-ctu0-mix0", |
ee914152 KM |
1453 | "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", |
1454 | "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; | |
1455 | }; | |
59e79895 LP |
1456 | mstp11_clks: mstp11_clks@e615099c { |
1457 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1458 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; | |
1459 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; | |
1460 | #clock-cells = <1>; | |
cb0bf851 | 1461 | clock-indices = < |
59e79895 LP |
1462 | R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 |
1463 | >; | |
1464 | clock-output-names = "scifa3", "scifa4", "scifa5"; | |
1465 | }; | |
1466 | }; | |
4d5b59cd | 1467 | |
6f3e4ee3 | 1468 | qspi: spi@e6b10000 { |
4d5b59cd GU |
1469 | compatible = "renesas,qspi-r8a7791", "renesas,qspi"; |
1470 | reg = <0 0xe6b10000 0 0x2c>; | |
386a9291 | 1471 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
4d5b59cd | 1472 | clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; |
591f2fa4 GU |
1473 | dmas = <&dmac0 0x17>, <&dmac0 0x18>; |
1474 | dma-names = "tx", "rx"; | |
797a0626 | 1475 | power-domains = <&cpg_clocks>; |
4d5b59cd GU |
1476 | num-cs = <1>; |
1477 | #address-cells = <1>; | |
1478 | #size-cells = <0>; | |
1479 | status = "disabled"; | |
1480 | }; | |
7713d3ab GU |
1481 | |
1482 | msiof0: spi@e6e20000 { | |
1483 | compatible = "renesas,msiof-r8a7791"; | |
cb6d08a2 | 1484 | reg = <0 0xe6e20000 0 0x0064>; |
386a9291 | 1485 | interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; |
7713d3ab | 1486 | clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; |
a5ce27f5 GU |
1487 | dmas = <&dmac0 0x51>, <&dmac0 0x52>; |
1488 | dma-names = "tx", "rx"; | |
797a0626 | 1489 | power-domains = <&cpg_clocks>; |
7713d3ab GU |
1490 | #address-cells = <1>; |
1491 | #size-cells = <0>; | |
1492 | status = "disabled"; | |
1493 | }; | |
1494 | ||
1495 | msiof1: spi@e6e10000 { | |
1496 | compatible = "renesas,msiof-r8a7791"; | |
cb6d08a2 | 1497 | reg = <0 0xe6e10000 0 0x0064>; |
386a9291 | 1498 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; |
7713d3ab | 1499 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; |
a5ce27f5 GU |
1500 | dmas = <&dmac0 0x55>, <&dmac0 0x56>; |
1501 | dma-names = "tx", "rx"; | |
797a0626 | 1502 | power-domains = <&cpg_clocks>; |
7713d3ab GU |
1503 | #address-cells = <1>; |
1504 | #size-cells = <0>; | |
1505 | status = "disabled"; | |
1506 | }; | |
1507 | ||
1508 | msiof2: spi@e6e00000 { | |
1509 | compatible = "renesas,msiof-r8a7791"; | |
cb6d08a2 | 1510 | reg = <0 0xe6e00000 0 0x0064>; |
386a9291 | 1511 | interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; |
7713d3ab | 1512 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; |
a5ce27f5 GU |
1513 | dmas = <&dmac0 0x41>, <&dmac0 0x42>; |
1514 | dma-names = "tx", "rx"; | |
797a0626 | 1515 | power-domains = <&cpg_clocks>; |
7713d3ab GU |
1516 | #address-cells = <1>; |
1517 | #size-cells = <0>; | |
1518 | status = "disabled"; | |
1519 | }; | |
811cdfae | 1520 | |
c196931e YS |
1521 | xhci: usb@ee000000 { |
1522 | compatible = "renesas,xhci-r8a7791"; | |
1523 | reg = <0 0xee000000 0 0xc00>; | |
386a9291 | 1524 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
c196931e | 1525 | clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; |
797a0626 | 1526 | power-domains = <&cpg_clocks>; |
c196931e YS |
1527 | phys = <&usb2 1>; |
1528 | phy-names = "usb"; | |
1529 | status = "disabled"; | |
1530 | }; | |
1531 | ||
aace0809 | 1532 | pci0: pci@ee090000 { |
d4809689 | 1533 | compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2"; |
aace0809 | 1534 | device_type = "pci"; |
aace0809 SS |
1535 | reg = <0 0xee090000 0 0xc00>, |
1536 | <0 0xee080000 0 0x1100>; | |
386a9291 | 1537 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
797a0626 GU |
1538 | clocks = <&mstp7_clks R8A7791_CLK_EHCI>; |
1539 | power-domains = <&cpg_clocks>; | |
aace0809 SS |
1540 | status = "disabled"; |
1541 | ||
1542 | bus-range = <0 0>; | |
1543 | #address-cells = <3>; | |
1544 | #size-cells = <2>; | |
1545 | #interrupt-cells = <1>; | |
1546 | ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; | |
1547 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
386a9291 SH |
1548 | interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH |
1549 | 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH | |
1550 | 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
e1bce124 SS |
1551 | |
1552 | usb@0,1 { | |
1553 | reg = <0x800 0 0 0 0>; | |
1554 | device_type = "pci"; | |
1555 | phys = <&usb0 0>; | |
1556 | phy-names = "usb"; | |
1557 | }; | |
1558 | ||
1559 | usb@0,2 { | |
1560 | reg = <0x1000 0 0 0 0>; | |
1561 | device_type = "pci"; | |
1562 | phys = <&usb0 0>; | |
1563 | phy-names = "usb"; | |
1564 | }; | |
aace0809 SS |
1565 | }; |
1566 | ||
1567 | pci1: pci@ee0d0000 { | |
d4809689 | 1568 | compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2"; |
aace0809 | 1569 | device_type = "pci"; |
aace0809 SS |
1570 | reg = <0 0xee0d0000 0 0xc00>, |
1571 | <0 0xee0c0000 0 0x1100>; | |
386a9291 | 1572 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
797a0626 GU |
1573 | clocks = <&mstp7_clks R8A7791_CLK_EHCI>; |
1574 | power-domains = <&cpg_clocks>; | |
aace0809 SS |
1575 | status = "disabled"; |
1576 | ||
1577 | bus-range = <1 1>; | |
1578 | #address-cells = <3>; | |
1579 | #size-cells = <2>; | |
1580 | #interrupt-cells = <1>; | |
1581 | ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; | |
1582 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
386a9291 SH |
1583 | interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH |
1584 | 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH | |
1585 | 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
e1bce124 SS |
1586 | |
1587 | usb@0,1 { | |
1588 | reg = <0x800 0 0 0 0>; | |
1589 | device_type = "pci"; | |
1590 | phys = <&usb2 0>; | |
1591 | phy-names = "usb"; | |
1592 | }; | |
1593 | ||
1594 | usb@0,2 { | |
1595 | reg = <0x1000 0 0 0 0>; | |
1596 | device_type = "pci"; | |
1597 | phys = <&usb2 0>; | |
1598 | phy-names = "usb"; | |
1599 | }; | |
aace0809 SS |
1600 | }; |
1601 | ||
811cdfae | 1602 | pciec: pcie@fe000000 { |
bbb45f69 | 1603 | compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; |
811cdfae PE |
1604 | reg = <0 0xfe000000 0 0x80000>; |
1605 | #address-cells = <3>; | |
1606 | #size-cells = <2>; | |
1607 | bus-range = <0x00 0xff>; | |
1608 | device_type = "pci"; | |
1609 | ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 | |
1610 | 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 | |
1611 | 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 | |
1612 | 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; | |
1613 | /* Map all possible DDR as inbound ranges */ | |
1614 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 | |
1615 | 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; | |
386a9291 SH |
1616 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
1617 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
1618 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; | |
811cdfae PE |
1619 | #interrupt-cells = <1>; |
1620 | interrupt-map-mask = <0 0 0 0>; | |
386a9291 | 1621 | interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
811cdfae PE |
1622 | clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; |
1623 | clock-names = "pcie", "pcie_bus"; | |
797a0626 | 1624 | power-domains = <&cpg_clocks>; |
811cdfae PE |
1625 | status = "disabled"; |
1626 | }; | |
09abd1fd | 1627 | |
f1951852 | 1628 | ipmmu_sy0: mmu@e6280000 { |
3c8ab0c8 | 1629 | compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; |
f1951852 | 1630 | reg = <0 0xe6280000 0 0x1000>; |
386a9291 SH |
1631 | interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, |
1632 | <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; | |
f1951852 LP |
1633 | #iommu-cells = <1>; |
1634 | status = "disabled"; | |
1635 | }; | |
1636 | ||
1637 | ipmmu_sy1: mmu@e6290000 { | |
3c8ab0c8 | 1638 | compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; |
f1951852 | 1639 | reg = <0 0xe6290000 0 0x1000>; |
386a9291 | 1640 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
f1951852 LP |
1641 | #iommu-cells = <1>; |
1642 | status = "disabled"; | |
1643 | }; | |
1644 | ||
1645 | ipmmu_ds: mmu@e6740000 { | |
3c8ab0c8 | 1646 | compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; |
f1951852 | 1647 | reg = <0 0xe6740000 0 0x1000>; |
386a9291 SH |
1648 | interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
1649 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; | |
f1951852 LP |
1650 | #iommu-cells = <1>; |
1651 | status = "disabled"; | |
1652 | }; | |
1653 | ||
1654 | ipmmu_mp: mmu@ec680000 { | |
3c8ab0c8 | 1655 | compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; |
f1951852 | 1656 | reg = <0 0xec680000 0 0x1000>; |
386a9291 | 1657 | interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; |
f1951852 LP |
1658 | #iommu-cells = <1>; |
1659 | status = "disabled"; | |
1660 | }; | |
1661 | ||
1662 | ipmmu_mx: mmu@fe951000 { | |
3c8ab0c8 | 1663 | compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; |
f1951852 | 1664 | reg = <0 0xfe951000 0 0x1000>; |
386a9291 SH |
1665 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, |
1666 | <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; | |
f1951852 LP |
1667 | #iommu-cells = <1>; |
1668 | status = "disabled"; | |
1669 | }; | |
1670 | ||
1671 | ipmmu_rt: mmu@ffc80000 { | |
3c8ab0c8 | 1672 | compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; |
f1951852 | 1673 | reg = <0 0xffc80000 0 0x1000>; |
386a9291 | 1674 | interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; |
f1951852 LP |
1675 | #iommu-cells = <1>; |
1676 | status = "disabled"; | |
1677 | }; | |
1678 | ||
1679 | ipmmu_gp: mmu@e62a0000 { | |
3c8ab0c8 | 1680 | compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; |
f1951852 | 1681 | reg = <0 0xe62a0000 0 0x1000>; |
386a9291 SH |
1682 | interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, |
1683 | <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; | |
f1951852 LP |
1684 | #iommu-cells = <1>; |
1685 | status = "disabled"; | |
1686 | }; | |
1687 | ||
6c63e07d | 1688 | rcar_sound: sound@ec500000 { |
d2b541c9 KM |
1689 | /* |
1690 | * #sound-dai-cells is required | |
1691 | * | |
1692 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; | |
1693 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; | |
1694 | */ | |
f49cd2b3 | 1695 | compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2"; |
09abd1fd KM |
1696 | reg = <0 0xec500000 0 0x1000>, /* SCU */ |
1697 | <0 0xec5a0000 0 0x100>, /* ADG */ | |
1698 | <0 0xec540000 0 0x1000>, /* SSIU */ | |
8c3f903b | 1699 | <0 0xec541000 0 0x280>, /* SSI */ |
d73a5013 KM |
1700 | <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ |
1701 | reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; | |
d88a6a2a | 1702 | |
09abd1fd KM |
1703 | clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, |
1704 | <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, | |
1705 | <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>, | |
1706 | <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>, | |
1707 | <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>, | |
1708 | <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>, | |
1709 | <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>, | |
1710 | <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>, | |
1711 | <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, | |
1712 | <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, | |
1713 | <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, | |
88401702 | 1714 | <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, |
7fd6e11d | 1715 | <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, |
150c8ad4 | 1716 | <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, |
09abd1fd KM |
1717 | <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; |
1718 | clock-names = "ssi-all", | |
1719 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", | |
1720 | "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", | |
1721 | "src.9", "src.8", "src.7", "src.6", "src.5", | |
1722 | "src.4", "src.3", "src.2", "src.1", "src.0", | |
88401702 | 1723 | "ctu.0", "ctu.1", |
7fd6e11d | 1724 | "mix.0", "mix.1", |
150c8ad4 | 1725 | "dvc.0", "dvc.1", |
09abd1fd | 1726 | "clk_a", "clk_b", "clk_c", "clk_i"; |
56e86dd4 | 1727 | power-domains = <&cpg_clocks>; |
09abd1fd KM |
1728 | |
1729 | status = "disabled"; | |
1730 | ||
150c8ad4 | 1731 | rcar_sound,dvc { |
63573339 KM |
1732 | dvc0: dvc@0 { |
1733 | dmas = <&audma0 0xbc>; | |
1734 | dma-names = "tx"; | |
1735 | }; | |
1736 | dvc1: dvc@1 { | |
1737 | dmas = <&audma0 0xbe>; | |
1738 | dma-names = "tx"; | |
1739 | }; | |
150c8ad4 KM |
1740 | }; |
1741 | ||
7fd6e11d KM |
1742 | rcar_sound,mix { |
1743 | mix0: mix@0 { }; | |
1744 | mix1: mix@1 { }; | |
1745 | }; | |
1746 | ||
88401702 KM |
1747 | rcar_sound,ctu { |
1748 | ctu00: ctu@0 { }; | |
1749 | ctu01: ctu@1 { }; | |
1750 | ctu02: ctu@2 { }; | |
1751 | ctu03: ctu@3 { }; | |
1752 | ctu10: ctu@4 { }; | |
1753 | ctu11: ctu@5 { }; | |
1754 | ctu12: ctu@6 { }; | |
1755 | ctu13: ctu@7 { }; | |
1756 | }; | |
1757 | ||
09abd1fd | 1758 | rcar_sound,src { |
63573339 | 1759 | src0: src@0 { |
386a9291 | 1760 | interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1761 | dmas = <&audma0 0x85>, <&audma1 0x9a>; |
1762 | dma-names = "rx", "tx"; | |
1763 | }; | |
1764 | src1: src@1 { | |
386a9291 | 1765 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1766 | dmas = <&audma0 0x87>, <&audma1 0x9c>; |
1767 | dma-names = "rx", "tx"; | |
1768 | }; | |
1769 | src2: src@2 { | |
386a9291 | 1770 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1771 | dmas = <&audma0 0x89>, <&audma1 0x9e>; |
1772 | dma-names = "rx", "tx"; | |
1773 | }; | |
1774 | src3: src@3 { | |
386a9291 | 1775 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1776 | dmas = <&audma0 0x8b>, <&audma1 0xa0>; |
1777 | dma-names = "rx", "tx"; | |
1778 | }; | |
1779 | src4: src@4 { | |
386a9291 | 1780 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1781 | dmas = <&audma0 0x8d>, <&audma1 0xb0>; |
1782 | dma-names = "rx", "tx"; | |
1783 | }; | |
1784 | src5: src@5 { | |
386a9291 | 1785 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1786 | dmas = <&audma0 0x8f>, <&audma1 0xb2>; |
1787 | dma-names = "rx", "tx"; | |
1788 | }; | |
1789 | src6: src@6 { | |
386a9291 | 1790 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1791 | dmas = <&audma0 0x91>, <&audma1 0xb4>; |
1792 | dma-names = "rx", "tx"; | |
1793 | }; | |
1794 | src7: src@7 { | |
386a9291 | 1795 | interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1796 | dmas = <&audma0 0x93>, <&audma1 0xb6>; |
1797 | dma-names = "rx", "tx"; | |
1798 | }; | |
1799 | src8: src@8 { | |
386a9291 | 1800 | interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1801 | dmas = <&audma0 0x95>, <&audma1 0xb8>; |
1802 | dma-names = "rx", "tx"; | |
1803 | }; | |
1804 | src9: src@9 { | |
386a9291 | 1805 | interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1806 | dmas = <&audma0 0x97>, <&audma1 0xba>; |
1807 | dma-names = "rx", "tx"; | |
1808 | }; | |
09abd1fd KM |
1809 | }; |
1810 | ||
1811 | rcar_sound,ssi { | |
63573339 | 1812 | ssi0: ssi@0 { |
386a9291 | 1813 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1814 | dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; |
1815 | dma-names = "rx", "tx", "rxu", "txu"; | |
1816 | }; | |
1817 | ssi1: ssi@1 { | |
386a9291 | 1818 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1819 | dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; |
1820 | dma-names = "rx", "tx", "rxu", "txu"; | |
1821 | }; | |
1822 | ssi2: ssi@2 { | |
386a9291 | 1823 | interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1824 | dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; |
1825 | dma-names = "rx", "tx", "rxu", "txu"; | |
1826 | }; | |
1827 | ssi3: ssi@3 { | |
386a9291 | 1828 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1829 | dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; |
1830 | dma-names = "rx", "tx", "rxu", "txu"; | |
1831 | }; | |
1832 | ssi4: ssi@4 { | |
386a9291 | 1833 | interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1834 | dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; |
1835 | dma-names = "rx", "tx", "rxu", "txu"; | |
1836 | }; | |
1837 | ssi5: ssi@5 { | |
386a9291 | 1838 | interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1839 | dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; |
1840 | dma-names = "rx", "tx", "rxu", "txu"; | |
1841 | }; | |
1842 | ssi6: ssi@6 { | |
386a9291 | 1843 | interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1844 | dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; |
1845 | dma-names = "rx", "tx", "rxu", "txu"; | |
1846 | }; | |
1847 | ssi7: ssi@7 { | |
386a9291 | 1848 | interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1849 | dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; |
1850 | dma-names = "rx", "tx", "rxu", "txu"; | |
1851 | }; | |
1852 | ssi8: ssi@8 { | |
386a9291 | 1853 | interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1854 | dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; |
1855 | dma-names = "rx", "tx", "rxu", "txu"; | |
1856 | }; | |
1857 | ssi9: ssi@9 { | |
386a9291 | 1858 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; |
63573339 KM |
1859 | dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; |
1860 | dma-names = "rx", "tx", "rxu", "txu"; | |
1861 | }; | |
09abd1fd KM |
1862 | }; |
1863 | }; | |
0d0771ab | 1864 | }; |