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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm...
[deliverable/linux.git] / arch / arm / boot / dts / r8a7791.dtsi
CommitLineData
0d0771ab
HN		 1/*
2 * Device Tree Source for the r8a7791 SoC
3 *
118e4e6a 4 * Copyright (C) 2013-2015 Renesas Electronics Corporation
2e5d55ce
SS		 5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
0d0771ab
HN		 7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
59e79895 13#include <dt-bindings/clock/r8a7791-clock.h>
5f75e73c
LP		 14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
0d0771ab
HN		 17/ {
18 compatible = "renesas,r8a7791";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
5bd3de7b
WS		 23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &i2c4;
29 i2c5 = &i2c5;
36408d9d
WS		 30 i2c6 = &i2c6;
31 i2c7 = &i2c7;
32 i2c8 = &i2c8;
6f3e4ee3 33 spi0 = &qspi;
7713d3ab
GU		 34 spi1 = &msiof0;
35 spi2 = &msiof1;
36 spi3 = &msiof2;
0b8d1d57
SS		 37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
5bd3de7b
WS		 40 };
41
0d0771ab
HN		 42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 cpu0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a15";
49 reg = <0>;
896b79df 50 clock-frequency = <1500000000>;
a57004ec
GI		 51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7791_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
8ffe93a5 54 next-level-cache = <&L2_CA15>;
a57004ec
GI		 55
56 /* kHz - uV - OPPs unknown yet */
57 operating-points = <1500000 1000000>,
58 <1312500 1000000>,
59 <1125000 1000000>,
60 < 937500 1000000>,
61 < 750000 1000000>,
62 < 375000 1000000>;
0d0771ab 63 };
15ab426c
MD		 64
65 cpu1: cpu@1 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a15";
68 reg = <1>;
896b79df 69 clock-frequency = <1500000000>;
8ffe93a5 70 next-level-cache = <&L2_CA15>;
15ab426c 71 };
0d0771ab
HN		 72 };
73
cac68a56
KM		 74 thermal-zones {
75 cpu_thermal: cpu-thermal {
76 polling-delay-passive = <0>;
77 polling-delay = <0>;
78
79 thermal-sensors = <&thermal>;
80
81 trips {
82 cpu-crit {
83 temperature = <115000>;
84 hysteresis = <0>;
85 type = "critical";
86 };
87 };
88 cooling-maps {
89 };
90 };
91 };
92
8ffe93a5
GU		 93 L2_CA15: cache-controller@0 {
94 compatible = "cache";
95 cache-unified;
96 cache-level = <2>;
97 };
98
0d0771ab 99 gic: interrupt-controller@f1001000 {
d238b5e6 100 compatible = "arm,gic-400";
0d0771ab
HN		 101 #interrupt-cells = <3>;
102 #address-cells = <0>;
103 interrupt-controller;
104 reg = <0 0xf1001000 0 0x1000>,
105 <0 0xf1002000 0 0x1000>,
106 <0 0xf1004000 0 0x2000>,
107 <0 0xf1006000 0 0x2000>;
386a9291 108 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0d0771ab 109 };
d77db73e 110
89fbba12 111 gpio0: gpio@e6050000 {
ab87e3fc 112 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 113 reg = <0 0xe6050000 0 0x50>;
386a9291 114 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 115 #gpio-cells = <2>;
116 gpio-controller;
117 gpio-ranges = <&pfc 0 0 32>;
118 #interrupt-cells = <2>;
119 interrupt-controller;
4faf9c5e 120 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
797a0626 121 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 122 };
123
89fbba12 124 gpio1: gpio@e6051000 {
ab87e3fc 125 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 126 reg = <0 0xe6051000 0 0x50>;
386a9291 127 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 128 #gpio-cells = <2>;
129 gpio-controller;
1329f6d0 130 gpio-ranges = <&pfc 0 32 26>;
ab87e3fc
MD		 131 #interrupt-cells = <2>;
132 interrupt-controller;
4faf9c5e 133 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
797a0626 134 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 135 };
136
89fbba12 137 gpio2: gpio@e6052000 {
ab87e3fc 138 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 139 reg = <0 0xe6052000 0 0x50>;
386a9291 140 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 141 #gpio-cells = <2>;
142 gpio-controller;
143 gpio-ranges = <&pfc 0 64 32>;
144 #interrupt-cells = <2>;
145 interrupt-controller;
4faf9c5e 146 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
797a0626 147 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 148 };
149
89fbba12 150 gpio3: gpio@e6053000 {
ab87e3fc 151 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 152 reg = <0 0xe6053000 0 0x50>;
386a9291 153 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 154 #gpio-cells = <2>;
155 gpio-controller;
156 gpio-ranges = <&pfc 0 96 32>;
157 #interrupt-cells = <2>;
158 interrupt-controller;
4faf9c5e 159 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
797a0626 160 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 161 };
162
89fbba12 163 gpio4: gpio@e6054000 {
ab87e3fc 164 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 165 reg = <0 0xe6054000 0 0x50>;
386a9291 166 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 167 #gpio-cells = <2>;
168 gpio-controller;
169 gpio-ranges = <&pfc 0 128 32>;
170 #interrupt-cells = <2>;
171 interrupt-controller;
4faf9c5e 172 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
797a0626 173 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 174 };
175
89fbba12 176 gpio5: gpio@e6055000 {
ab87e3fc 177 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 178 reg = <0 0xe6055000 0 0x50>;
386a9291 179 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 180 #gpio-cells = <2>;
181 gpio-controller;
182 gpio-ranges = <&pfc 0 160 32>;
183 #interrupt-cells = <2>;
184 interrupt-controller;
4faf9c5e 185 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
797a0626 186 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 187 };
188
89fbba12 189 gpio6: gpio@e6055400 {
ab87e3fc 190 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 191 reg = <0 0xe6055400 0 0x50>;
386a9291 192 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 193 #gpio-cells = <2>;
194 gpio-controller;
195 gpio-ranges = <&pfc 0 192 32>;
196 #interrupt-cells = <2>;
197 interrupt-controller;
4faf9c5e 198 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
797a0626 199 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 200 };
201
89fbba12 202 gpio7: gpio@e6055800 {
ab87e3fc 203 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 204 reg = <0 0xe6055800 0 0x50>;
386a9291 205 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 206 #gpio-cells = <2>;
207 gpio-controller;
208 gpio-ranges = <&pfc 0 224 26>;
209 #interrupt-cells = <2>;
210 interrupt-controller;
4faf9c5e 211 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
797a0626 212 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 213 };
214
cac68a56
KM		 215 thermal: thermal@e61f0000 {
216 compatible = "renesas,thermal-r8a7791",
217 "renesas,rcar-gen2-thermal",
218 "renesas,rcar-thermal";
d103f4d3 219 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
386a9291 220 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
563bc8eb 221 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
797a0626 222 power-domains = <&cpg_clocks>;
cac68a56 223 #thermal-sensor-cells = <0>;
d103f4d3
MD		 224 };
225
03586acf
MD		 226 timer {
227 compatible = "arm,armv7-timer";
386a9291
SH		 228 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
229 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
230 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
231 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
03586acf
MD		 232 };
233
ceaa1894 234 cmt0: timer@ffca0000 {
4217f323 235 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
ceaa1894 236 reg = <0 0xffca0000 0 0x1004>;
386a9291
SH		 237 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
ceaa1894
LP		 239 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
240 clock-names = "fck";
797a0626 241 power-domains = <&cpg_clocks>;
ceaa1894
LP		 242
243 renesas,channels-mask = <0x60>;
244
245 status = "disabled";
246 };
247
248 cmt1: timer@e6130000 {
4217f323 249 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
ceaa1894 250 reg = <0 0xe6130000 0 0x1004>;
386a9291
SH		 251 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
ceaa1894
LP		 259 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
260 clock-names = "fck";
797a0626 261 power-domains = <&cpg_clocks>;
ceaa1894
LP		 262
263 renesas,channels-mask = <0xff>;
264
265 status = "disabled";
266 };
267
d77db73e 268 irqc0: interrupt-controller@e61c0000 {
26041b06 269 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
d77db73e
MD		 270 #interrupt-cells = <2>;
271 interrupt-controller;
272 reg = <0 0xe61c0000 0 0x200>;
386a9291
SH		 273 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
62d386c0 283 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
797a0626 284 power-domains = <&cpg_clocks>;
d77db73e 285 };
55146927 286
fde8feef 287 dmac0: dma-controller@e6700000 {
e6d12b49 288 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
fde8feef 289 reg = <0 0xe6700000 0 0x20000>;
386a9291
SH		 290 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
291 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
292 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
293 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
294 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
295 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
296 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
297 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
298 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
299 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
300 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
301 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
302 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
303 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
304 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
305 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
fde8feef
LP		 306 interrupt-names = "error",
307 "ch0", "ch1", "ch2", "ch3",
308 "ch4", "ch5", "ch6", "ch7",
309 "ch8", "ch9", "ch10", "ch11",
310 "ch12", "ch13", "ch14";
311 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
312 clock-names = "fck";
797a0626 313 power-domains = <&cpg_clocks>;
fde8feef
LP		 314 #dma-cells = <1>;
315 dma-channels = <15>;
316 };
317
318 dmac1: dma-controller@e6720000 {
e6d12b49 319 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
fde8feef 320 reg = <0 0xe6720000 0 0x20000>;
386a9291
SH		 321 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
335 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
336 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
fde8feef
LP		 337 interrupt-names = "error",
338 "ch0", "ch1", "ch2", "ch3",
339 "ch4", "ch5", "ch6", "ch7",
340 "ch8", "ch9", "ch10", "ch11",
341 "ch12", "ch13", "ch14";
342 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
343 clock-names = "fck";
797a0626 344 power-domains = <&cpg_clocks>;
fde8feef
LP		 345 #dma-cells = <1>;
346 dma-channels = <15>;
347 };
348
8994fff6 349 audma0: dma-controller@ec700000 {
e6d12b49 350 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
8994fff6 351 reg = <0 0xec700000 0 0x10000>;
386a9291
SH		 352 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
355 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
360 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
361 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
362 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
363 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
364 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
365 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
8994fff6
KM		 366 interrupt-names = "error",
367 "ch0", "ch1", "ch2", "ch3",
368 "ch4", "ch5", "ch6", "ch7",
369 "ch8", "ch9", "ch10", "ch11",
370 "ch12";
371 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
372 clock-names = "fck";
797a0626 373 power-domains = <&cpg_clocks>;
8994fff6
KM		 374 #dma-cells = <1>;
375 dma-channels = <13>;
376 };
377
378 audma1: dma-controller@ec720000 {
e6d12b49 379 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
8994fff6 380 reg = <0 0xec720000 0 0x10000>;
386a9291
SH		 381 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
389 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
390 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
391 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
392 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
393 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
394 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
8994fff6
KM		 395 interrupt-names = "error",
396 "ch0", "ch1", "ch2", "ch3",
397 "ch4", "ch5", "ch6", "ch7",
398 "ch8", "ch9", "ch10", "ch11",
399 "ch12";
400 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
401 clock-names = "fck";
797a0626 402 power-domains = <&cpg_clocks>;
8994fff6
KM		 403 #dma-cells = <1>;
404 dma-channels = <13>;
405 };
406
e3e25edc 407 usb_dmac0: dma-controller@e65a0000 {
d01c8bec 408 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
e3e25edc 409 reg = <0 0xe65a0000 0 0x100>;
386a9291
SH		 410 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
411 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
e3e25edc
YS		 412 interrupt-names = "ch0", "ch1";
413 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
797a0626 414 power-domains = <&cpg_clocks>;
e3e25edc
YS		 415 #dma-cells = <1>;
416 dma-channels = <2>;
417 };
418
419 usb_dmac1: dma-controller@e65b0000 {
d01c8bec 420 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
e3e25edc 421 reg = <0 0xe65b0000 0 0x100>;
386a9291
SH		 422 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
423 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e3e25edc
YS		 424 interrupt-names = "ch0", "ch1";
425 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
797a0626 426 power-domains = <&cpg_clocks>;
e3e25edc
YS		 427 #dma-cells = <1>;
428 dma-channels = <2>;
429 };
430
36408d9d 431 /* The memory map in the User's Manual maps the cores to bus numbers */
5bd3de7b
WS		 432 i2c0: i2c@e6508000 {
433 #address-cells = <1>;
434 #size-cells = <0>;
435 compatible = "renesas,i2c-r8a7791";
436 reg = <0 0xe6508000 0 0x40>;
386a9291 437 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
5bd3de7b 438 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
797a0626 439 power-domains = <&cpg_clocks>;
49160dc1 440 i2c-scl-internal-delay-ns = <6>;
5bd3de7b
WS		 441 status = "disabled";
442 };
443
444 i2c1: i2c@e6518000 {
445 #address-cells = <1>;
446 #size-cells = <0>;
447 compatible = "renesas,i2c-r8a7791";
448 reg = <0 0xe6518000 0 0x40>;
386a9291 449 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
5bd3de7b 450 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
797a0626 451 power-domains = <&cpg_clocks>;
49160dc1 452 i2c-scl-internal-delay-ns = <6>;
5bd3de7b
WS		 453 status = "disabled";
454 };
455
456 i2c2: i2c@e6530000 {
457 #address-cells = <1>;
458 #size-cells = <0>;
459 compatible = "renesas,i2c-r8a7791";
460 reg = <0 0xe6530000 0 0x40>;
386a9291 461 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
5bd3de7b 462 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
797a0626 463 power-domains = <&cpg_clocks>;
49160dc1 464 i2c-scl-internal-delay-ns = <6>;
5bd3de7b
WS		 465 status = "disabled";
466 };
467
468 i2c3: i2c@e6540000 {
469 #address-cells = <1>;
470 #size-cells = <0>;
471 compatible = "renesas,i2c-r8a7791";
472 reg = <0 0xe6540000 0 0x40>;
386a9291 473 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
5bd3de7b 474 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
797a0626 475 power-domains = <&cpg_clocks>;
49160dc1 476 i2c-scl-internal-delay-ns = <6>;
5bd3de7b
WS		 477 status = "disabled";
478 };
479
480 i2c4: i2c@e6520000 {
481 #address-cells = <1>;
482 #size-cells = <0>;
483 compatible = "renesas,i2c-r8a7791";
484 reg = <0 0xe6520000 0 0x40>;
386a9291 485 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5bd3de7b 486 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
797a0626 487 power-domains = <&cpg_clocks>;
49160dc1 488 i2c-scl-internal-delay-ns = <6>;
5bd3de7b
WS		 489 status = "disabled";
490 };
491
492 i2c5: i2c@e6528000 {
36408d9d 493 /* doesn't need pinmux */
5bd3de7b
WS		 494 #address-cells = <1>;
495 #size-cells = <0>;
496 compatible = "renesas,i2c-r8a7791";
497 reg = <0 0xe6528000 0 0x40>;
386a9291 498 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
5bd3de7b 499 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
797a0626 500 power-domains = <&cpg_clocks>;
49160dc1 501 i2c-scl-internal-delay-ns = <110>;
5bd3de7b
WS		 502 status = "disabled";
503 };
504
36408d9d
WS		 505 i2c6: i2c@e60b0000 {
506 /* doesn't need pinmux */
507 #address-cells = <1>;
508 #size-cells = <0>;
509 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
510 reg = <0 0xe60b0000 0 0x425>;
386a9291 511 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
36408d9d 512 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
3f58c54b
WS		 513 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
514 dma-names = "tx", "rx";
797a0626 515 power-domains = <&cpg_clocks>;
36408d9d
WS		 516 status = "disabled";
517 };
518
519 i2c7: i2c@e6500000 {
520 #address-cells = <1>;
521 #size-cells = <0>;
522 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
523 reg = <0 0xe6500000 0 0x425>;
386a9291 524 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
36408d9d 525 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
3f58c54b
WS		 526 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
527 dma-names = "tx", "rx";
797a0626 528 power-domains = <&cpg_clocks>;
36408d9d
WS		 529 status = "disabled";
530 };
531
532 i2c8: i2c@e6510000 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
536 reg = <0 0xe6510000 0 0x425>;
386a9291 537 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
36408d9d 538 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
3f58c54b
WS		 539 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
540 dma-names = "tx", "rx";
797a0626 541 power-domains = <&cpg_clocks>;
36408d9d
WS		 542 status = "disabled";
543 };
544
55146927
MD		 545 pfc: pfc@e6060000 {
546 compatible = "renesas,pfc-r8a7791";
547 reg = <0 0xe6060000 0 0x250>;
55146927 548 };
59e79895 549
8edae499
LP		 550 mmcif0: mmc@ee200000 {
551 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
552 reg = <0 0xee200000 0 0x80>;
386a9291 553 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
8edae499 554 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
16b355b4
LP		 555 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
556 dma-names = "tx", "rx";
797a0626 557 power-domains = <&cpg_clocks>;
8edae499
LP		 558 reg-io-width = <4>;
559 status = "disabled";
d957ab8d 560 max-frequency = <97500000>;
8edae499
LP		 561 };
562
b7ed8a0d
MD		 563 sdhi0: sd@ee100000 {
564 compatible = "renesas,sdhi-r8a7791";
e849b065 565 reg = <0 0xee100000 0 0x328>;
386a9291 566 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
b7ed8a0d 567 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
ae67fa2f
LP		 568 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
569 dma-names = "tx", "rx";
797a0626 570 power-domains = <&cpg_clocks>;
b7ed8a0d
MD		 571 status = "disabled";
572 };
573
574 sdhi1: sd@ee140000 {
575 compatible = "renesas,sdhi-r8a7791";
576 reg = <0 0xee140000 0 0x100>;
386a9291 577 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
b7ed8a0d 578 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
ae67fa2f
LP		 579 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
580 dma-names = "tx", "rx";
797a0626 581 power-domains = <&cpg_clocks>;
b7ed8a0d
MD		 582 status = "disabled";
583 };
584
585 sdhi2: sd@ee160000 {
586 compatible = "renesas,sdhi-r8a7791";
587 reg = <0 0xee160000 0 0x100>;
386a9291 588 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
b7ed8a0d 589 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
ae67fa2f
LP		 590 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
591 dma-names = "tx", "rx";
797a0626 592 power-domains = <&cpg_clocks>;
b7ed8a0d
MD		 593 status = "disabled";
594 };
595
9640cf25 596 scifa0: serial@e6c40000 {
b5b52dd7
GU		 597 compatible = "renesas,scifa-r8a7791",
598 "renesas,rcar-gen2-scifa", "renesas,scifa";
9640cf25 599 reg = <0 0xe6c40000 0 64>;
386a9291 600 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
9640cf25 601 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
bb7ca195 602 clock-names = "fck";
558d6565
GU		 603 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
604 dma-names = "tx", "rx";
797a0626 605 power-domains = <&cpg_clocks>;
9640cf25
LP		 606 status = "disabled";
607 };
608
609 scifa1: serial@e6c50000 {
b5b52dd7
GU		 610 compatible = "renesas,scifa-r8a7791",
611 "renesas,rcar-gen2-scifa", "renesas,scifa";
9640cf25 612 reg = <0 0xe6c50000 0 64>;
386a9291 613 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
9640cf25 614 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
bb7ca195 615 clock-names = "fck";
558d6565
GU		 616 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
617 dma-names = "tx", "rx";
797a0626 618 power-domains = <&cpg_clocks>;
9640cf25
LP		 619 status = "disabled";
620 };
621
622 scifa2: serial@e6c60000 {
b5b52dd7
GU		 623 compatible = "renesas,scifa-r8a7791",
624 "renesas,rcar-gen2-scifa", "renesas,scifa";
9640cf25 625 reg = <0 0xe6c60000 0 64>;
386a9291 626 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
9640cf25 627 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
bb7ca195 628 clock-names = "fck";
558d6565
GU		 629 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
630 dma-names = "tx", "rx";
797a0626 631 power-domains = <&cpg_clocks>;
9640cf25
LP		 632 status = "disabled";
633 };
634
635 scifa3: serial@e6c70000 {
b5b52dd7
GU		 636 compatible = "renesas,scifa-r8a7791",
637 "renesas,rcar-gen2-scifa", "renesas,scifa";
9640cf25 638 reg = <0 0xe6c70000 0 64>;
386a9291 639 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
9640cf25 640 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
bb7ca195 641 clock-names = "fck";
558d6565
GU		 642 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
643 dma-names = "tx", "rx";
797a0626 644 power-domains = <&cpg_clocks>;
9640cf25
LP		 645 status = "disabled";
646 };
647
648 scifa4: serial@e6c78000 {
b5b52dd7
GU		 649 compatible = "renesas,scifa-r8a7791",
650 "renesas,rcar-gen2-scifa", "renesas,scifa";
9640cf25 651 reg = <0 0xe6c78000 0 64>;
386a9291 652 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
9640cf25 653 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
bb7ca195 654 clock-names = "fck";
558d6565
GU		 655 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
656 dma-names = "tx", "rx";
797a0626 657 power-domains = <&cpg_clocks>;
9640cf25
LP		 658 status = "disabled";
659 };
660
661 scifa5: serial@e6c80000 {
b5b52dd7
GU		 662 compatible = "renesas,scifa-r8a7791",
663 "renesas,rcar-gen2-scifa", "renesas,scifa";
9640cf25 664 reg = <0 0xe6c80000 0 64>;
386a9291 665 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
9640cf25 666 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
bb7ca195 667 clock-names = "fck";
558d6565
GU		 668 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
669 dma-names = "tx", "rx";
797a0626 670 power-domains = <&cpg_clocks>;
9640cf25
LP		 671 status = "disabled";
672 };
673
674 scifb0: serial@e6c20000 {
b5b52dd7
GU		 675 compatible = "renesas,scifb-r8a7791",
676 "renesas,rcar-gen2-scifb", "renesas,scifb";
9640cf25 677 reg = <0 0xe6c20000 0 64>;
386a9291 678 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
9640cf25 679 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
bb7ca195 680 clock-names = "fck";
558d6565
GU		 681 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
682 dma-names = "tx", "rx";
797a0626 683 power-domains = <&cpg_clocks>;
9640cf25
LP		 684 status = "disabled";
685 };
686
687 scifb1: serial@e6c30000 {
b5b52dd7
GU		 688 compatible = "renesas,scifb-r8a7791",
689 "renesas,rcar-gen2-scifb", "renesas,scifb";
9640cf25 690 reg = <0 0xe6c30000 0 64>;
386a9291 691 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
9640cf25 692 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
bb7ca195 693 clock-names = "fck";
558d6565
GU		 694 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
695 dma-names = "tx", "rx";
797a0626 696 power-domains = <&cpg_clocks>;
9640cf25
LP		 697 status = "disabled";
698 };
699
700 scifb2: serial@e6ce0000 {
b5b52dd7
GU		 701 compatible = "renesas,scifb-r8a7791",
702 "renesas,rcar-gen2-scifb", "renesas,scifb";
9640cf25 703 reg = <0 0xe6ce0000 0 64>;
386a9291 704 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
9640cf25 705 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
bb7ca195 706 clock-names = "fck";
558d6565
GU		 707 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
708 dma-names = "tx", "rx";
797a0626 709 power-domains = <&cpg_clocks>;
9640cf25
LP		 710 status = "disabled";
711 };
712
713 scif0: serial@e6e60000 {
b5b52dd7
GU		 714 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
715 "renesas,scif";
9640cf25 716 reg = <0 0xe6e60000 0 64>;
386a9291 717 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
394730a1
GU		 718 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>,
719 <&scif_clk>;
720 clock-names = "fck", "brg_int", "scif_clk";
558d6565
GU		 721 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
722 dma-names = "tx", "rx";
797a0626 723 power-domains = <&cpg_clocks>;
9640cf25
LP		 724 status = "disabled";
725 };
726
727 scif1: serial@e6e68000 {
b5b52dd7
GU		 728 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
729 "renesas,scif";
9640cf25 730 reg = <0 0xe6e68000 0 64>;
386a9291 731 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
394730a1
GU		 732 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>,
733 <&scif_clk>;
734 clock-names = "fck", "brg_int", "scif_clk";
558d6565
GU		 735 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
736 dma-names = "tx", "rx";
797a0626 737 power-domains = <&cpg_clocks>;
9640cf25
LP		 738 status = "disabled";
739 };
740
741 scif2: serial@e6e58000 {
b5b52dd7
GU		 742 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
743 "renesas,scif";
9640cf25 744 reg = <0 0xe6e58000 0 64>;
386a9291 745 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
394730a1
GU		 746 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>,
747 <&scif_clk>;
748 clock-names = "fck", "brg_int", "scif_clk";
558d6565
GU		 749 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
750 dma-names = "tx", "rx";
797a0626 751 power-domains = <&cpg_clocks>;
9640cf25
LP		 752 status = "disabled";
753 };
754
755 scif3: serial@e6ea8000 {
b5b52dd7
GU		 756 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
757 "renesas,scif";
9640cf25 758 reg = <0 0xe6ea8000 0 64>;
386a9291 759 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
394730a1
GU		 760 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>,
761 <&scif_clk>;
762 clock-names = "fck", "brg_int", "scif_clk";
558d6565
GU		 763 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
764 dma-names = "tx", "rx";
797a0626 765 power-domains = <&cpg_clocks>;
9640cf25
LP		 766 status = "disabled";
767 };
768
769 scif4: serial@e6ee0000 {
b5b52dd7
GU		 770 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
771 "renesas,scif";
9640cf25 772 reg = <0 0xe6ee0000 0 64>;
386a9291 773 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
394730a1
GU		 774 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>,
775 <&scif_clk>;
776 clock-names = "fck", "brg_int", "scif_clk";
558d6565
GU		 777 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
778 dma-names = "tx", "rx";
797a0626 779 power-domains = <&cpg_clocks>;
9640cf25
LP		 780 status = "disabled";
781 };
782
783 scif5: serial@e6ee8000 {
b5b52dd7
GU		 784 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
785 "renesas,scif";
9640cf25 786 reg = <0 0xe6ee8000 0 64>;
386a9291 787 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
394730a1
GU		 788 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>,
789 <&scif_clk>;
790 clock-names = "fck", "brg_int", "scif_clk";
558d6565
GU		 791 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
792 dma-names = "tx", "rx";
797a0626 793 power-domains = <&cpg_clocks>;
9640cf25
LP		 794 status = "disabled";
795 };
796
797 hscif0: serial@e62c0000 {
b5b52dd7
GU		 798 compatible = "renesas,hscif-r8a7791",
799 "renesas,rcar-gen2-hscif", "renesas,hscif";
9640cf25 800 reg = <0 0xe62c0000 0 96>;
386a9291 801 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
394730a1
GU		 802 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>,
803 <&scif_clk>;
804 clock-names = "fck", "brg_int", "scif_clk";
558d6565
GU		 805 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
806 dma-names = "tx", "rx";
797a0626 807 power-domains = <&cpg_clocks>;
9640cf25
LP		 808 status = "disabled";
809 };
810
811 hscif1: serial@e62c8000 {
b5b52dd7
GU		 812 compatible = "renesas,hscif-r8a7791",
813 "renesas,rcar-gen2-hscif", "renesas,hscif";
9640cf25 814 reg = <0 0xe62c8000 0 96>;
386a9291 815 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
394730a1
GU		 816 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>,
817 <&scif_clk>;
818 clock-names = "fck", "brg_int", "scif_clk";
558d6565
GU		 819 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
820 dma-names = "tx", "rx";
797a0626 821 power-domains = <&cpg_clocks>;
9640cf25
LP		 822 status = "disabled";
823 };
824
825 hscif2: serial@e62d0000 {
b5b52dd7
GU		 826 compatible = "renesas,hscif-r8a7791",
827 "renesas,rcar-gen2-hscif", "renesas,hscif";
9640cf25 828 reg = <0 0xe62d0000 0 96>;
386a9291 829 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
394730a1
GU		 830 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>,
831 <&scif_clk>;
832 clock-names = "fck", "brg_int", "scif_clk";
558d6565
GU		 833 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
834 dma-names = "tx", "rx";
797a0626 835 power-domains = <&cpg_clocks>;
9640cf25
LP		 836 status = "disabled";
837 };
838
2e5d55ce
SS		 839 ether: ethernet@ee700000 {
840 compatible = "renesas,ether-r8a7791";
841 reg = <0 0xee700000 0 0x400>;
386a9291 842 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
2e5d55ce 843 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
797a0626 844 power-domains = <&cpg_clocks>;
2e5d55ce
SS		 845 phy-mode = "rmii";
846 #address-cells = <1>;
847 #size-cells = <0>;
848 status = "disabled";
849 };
850
46ece349
SS		 851 avb: ethernet@e6800000 {
852 compatible = "renesas,etheravb-r8a7791",
853 "renesas,etheravb-rcar-gen2";
854 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
386a9291 855 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
46ece349
SS		 856 clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>;
857 power-domains = <&cpg_clocks>;
858 #address-cells = <1>;
859 #size-cells = <0>;
860 status = "disabled";
861 };
862
b8532c69
VB		 863 sata0: sata@ee300000 {
864 compatible = "renesas,sata-r8a7791";
865 reg = <0 0xee300000 0 0x2000>;
386a9291 866 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
b8532c69 867 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
797a0626 868 power-domains = <&cpg_clocks>;
b8532c69
VB		 869 status = "disabled";
870 };
871
872 sata1: sata@ee500000 {
873 compatible = "renesas,sata-r8a7791";
874 reg = <0 0xee500000 0 0x2000>;
386a9291 875 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
b8532c69 876 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
797a0626 877 power-domains = <&cpg_clocks>;
b8532c69
VB		 878 status = "disabled";
879 };
880
1c1fee7c 881 hsusb: usb@e6590000 {
8cf1d454 882 compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs";
1c1fee7c 883 reg = <0 0xe6590000 0 0x100>;
386a9291 884 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1c1fee7c 885 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
7706993e
YS		 886 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
887 <&usb_dmac1 0>, <&usb_dmac1 1>;
888 dma-names = "ch0", "ch1", "ch2", "ch3";
797a0626
GU		 889 power-domains = <&cpg_clocks>;
890 renesas,buswait = <4>;
891 phys = <&usb0 1>;
892 phy-names = "usb";
1c1fee7c
YS		 893 status = "disabled";
894 };
895
3b7e530d
SS		 896 usbphy: usb-phy@e6590100 {
897 compatible = "renesas,usb-phy-r8a7791";
898 reg = <0 0xe6590100 0 0x100>;
899 #address-cells = <1>;
900 #size-cells = <0>;
901 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
902 clock-names = "usbhs";
797a0626 903 power-domains = <&cpg_clocks>;
3b7e530d
SS		 904 status = "disabled";
905
906 usb0: usb-channel@0 {
907 reg = <0>;
908 #phy-cells = <1>;
909 };
910 usb2: usb-channel@2 {
911 reg = <2>;
912 #phy-cells = <1>;
913 };
914 };
915
0b8d1d57
SS		 916 vin0: video@e6ef0000 {
917 compatible = "renesas,vin-r8a7791";
0b8d1d57 918 reg = <0 0xe6ef0000 0 0x1000>;
386a9291 919 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
797a0626
GU		 920 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
921 power-domains = <&cpg_clocks>;
0b8d1d57
SS		 922 status = "disabled";
923 };
924
925 vin1: video@e6ef1000 {
926 compatible = "renesas,vin-r8a7791";
0b8d1d57 927 reg = <0 0xe6ef1000 0 0x1000>;
386a9291 928 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
797a0626
GU		 929 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
930 power-domains = <&cpg_clocks>;
0b8d1d57
SS		 931 status = "disabled";
932 };
933
934 vin2: video@e6ef2000 {
935 compatible = "renesas,vin-r8a7791";
0b8d1d57 936 reg = <0 0xe6ef2000 0 0x1000>;
386a9291 937 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
797a0626
GU		 938 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
939 power-domains = <&cpg_clocks>;
0b8d1d57
SS		 940 status = "disabled";
941 };
942
8eefac2d
LP		 943 vsp1@fe928000 {
944 compatible = "renesas,vsp1";
945 reg = <0 0xfe928000 0 0x8000>;
386a9291 946 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
8eefac2d 947 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
797a0626 948 power-domains = <&cpg_clocks>;
8eefac2d
LP		 949
950 renesas,has-lut;
951 renesas,has-sru;
952 renesas,#rpf = <5>;
953 renesas,#uds = <3>;
954 renesas,#wpf = <4>;
955 };
956
957 vsp1@fe930000 {
958 compatible = "renesas,vsp1";
959 reg = <0 0xfe930000 0 0x8000>;
386a9291 960 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
8eefac2d 961 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
797a0626 962 power-domains = <&cpg_clocks>;
8eefac2d
LP		 963
964 renesas,has-lif;
965 renesas,has-lut;
966 renesas,#rpf = <4>;
967 renesas,#uds = <1>;
968 renesas,#wpf = <4>;
969 };
970
971 vsp1@fe938000 {
972 compatible = "renesas,vsp1";
973 reg = <0 0xfe938000 0 0x8000>;
386a9291 974 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
8eefac2d 975 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
797a0626 976 power-domains = <&cpg_clocks>;
8eefac2d
LP		 977
978 renesas,has-lif;
979 renesas,has-lut;
980 renesas,#rpf = <4>;
981 renesas,#uds = <1>;
982 renesas,#wpf = <4>;
983 };
984
985 du: display@feb00000 {
986 compatible = "renesas,du-r8a7791";
987 reg = <0 0xfeb00000 0 0x40000>,
988 <0 0xfeb90000 0 0x1c>;
989 reg-names = "du", "lvds.0";
386a9291
SH		 990 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
8eefac2d
LP		 992 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
993 <&mstp7_clks R8A7791_CLK_DU1>,
994 <&mstp7_clks R8A7791_CLK_LVDS0>;
995 clock-names = "du.0", "du.1", "lvds.0";
996 status = "disabled";
997
998 ports {
999 #address-cells = <1>;
1000 #size-cells = <0>;
1001
1002 port@0 {
1003 reg = <0>;
1004 du_out_rgb: endpoint {
1005 };
1006 };
1007 port@1 {
1008 reg = <1>;
1009 du_out_lvds0: endpoint {
1010 };
1011 };
1012 };
1013 };
1014
3cf01884
SS		 1015 can0: can@e6e80000 {
1016 compatible = "renesas,can-r8a7791";
1017 reg = <0 0xe6e80000 0 0x1000>;
386a9291 1018 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
3cf01884
SS		 1019 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
1020 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1021 clock-names = "clkp1", "clkp2", "can_clk";
797a0626 1022 power-domains = <&cpg_clocks>;
3cf01884
SS		 1023 status = "disabled";
1024 };
1025
1026 can1: can@e6e88000 {
1027 compatible = "renesas,can-r8a7791";
1028 reg = <0 0xe6e88000 0 0x1000>;
386a9291 1029 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
3cf01884
SS		 1030 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
1031 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1032 clock-names = "clkp1", "clkp2", "can_clk";
797a0626 1033 power-domains = <&cpg_clocks>;
3cf01884
SS		 1034 status = "disabled";
1035 };
1036
0caa3660
MU		 1037 jpu: jpeg-codec@fe980000 {
1038 compatible = "renesas,jpu-r8a7791";
1039 reg = <0 0xfe980000 0 0x10300>;
386a9291 1040 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
0caa3660 1041 clocks = <&mstp1_clks R8A7791_CLK_JPU>;
797a0626 1042 power-domains = <&cpg_clocks>;
0caa3660
MU		 1043 };
1044
59e79895
LP		 1045 clocks {
1046 #address-cells = <2>;
1047 #size-cells = <2>;
1048 ranges;
1049
1050 /* External root clock */
1051 extal_clk: extal_clk {
1052 compatible = "fixed-clock";
1053 #clock-cells = <0>;
1054 /* This value must be overriden by the board. */
1055 clock-frequency = <0>;
1056 clock-output-names = "extal";
1057 };
1058
0d3dbde8
KM		 1059 /*
1060 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1061 * default. Boards that provide audio clocks should override them.
1062 */
1063 audio_clk_a: audio_clk_a {
1064 compatible = "fixed-clock";
1065 #clock-cells = <0>;
1066 clock-frequency = <0>;
1067 clock-output-names = "audio_clk_a";
1068 };
1069 audio_clk_b: audio_clk_b {
1070 compatible = "fixed-clock";
1071 #clock-cells = <0>;
1072 clock-frequency = <0>;
1073 clock-output-names = "audio_clk_b";
1074 };
1075 audio_clk_c: audio_clk_c {
1076 compatible = "fixed-clock";
1077 #clock-cells = <0>;
1078 clock-frequency = <0>;
1079 clock-output-names = "audio_clk_c";
1080 };
1081
66c405e7
PE		 1082 /* External PCIe clock - can be overridden by the board */
1083 pcie_bus_clk: pcie_bus_clk {
1084 compatible = "fixed-clock";
1085 #clock-cells = <0>;
ac6908b3 1086 clock-frequency = <0>;
66c405e7 1087 clock-output-names = "pcie_bus";
66c405e7
PE		 1088 };
1089
394730a1
GU		 1090 /* External SCIF clock */
1091 scif_clk: scif {
1092 compatible = "fixed-clock";
1093 #clock-cells = <0>;
1094 /* This value must be overridden by the board. */
1095 clock-frequency = <0>;
394730a1
GU		 1096 };
1097
b324252c
SS		 1098 /* External USB clock - can be overridden by the board */
1099 usb_extal_clk: usb_extal_clk {
1100 compatible = "fixed-clock";
1101 #clock-cells = <0>;
1102 clock-frequency = <48000000>;
1103 clock-output-names = "usb_extal";
1104 };
1105
1106 /* External CAN clock */
1107 can_clk: can_clk {
1108 compatible = "fixed-clock";
1109 #clock-cells = <0>;
1110 /* This value must be overridden by the board. */
1111 clock-frequency = <0>;
1112 clock-output-names = "can_clk";
b324252c
SS		 1113 };
1114
59e79895
LP		 1115 /* Special CPG clocks */
1116 cpg_clocks: cpg_clocks@e6150000 {
1117 compatible = "renesas,r8a7791-cpg-clocks",
1118 "renesas,rcar-gen2-cpg-clocks";
1119 reg = <0 0xe6150000 0 0x1000>;
b324252c 1120 clocks = <&extal_clk &usb_extal_clk>;
59e79895
LP		 1121 #clock-cells = <1>;
1122 clock-output-names = "main", "pll0", "pll1", "pll3",
b324252c 1123 "lb", "qspi", "sdh", "sd0", "z",
ae65a8ae 1124 "rcan", "adsp";
797a0626 1125 #power-domain-cells = <0>;
59e79895
LP		 1126 };
1127
1128 /* Variable factor clocks */
2ea0d4ec 1129 sd2_clk: sd2_clk@e6150078 {
59e79895
LP		 1130 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1131 reg = <0 0xe6150078 0 4>;
1132 clocks = <&pll1_div2_clk>;
1133 #clock-cells = <0>;
2ea0d4ec 1134 clock-output-names = "sd2";
59e79895 1135 };
2ea0d4ec 1136 sd3_clk: sd3_clk@e615026c {
59e79895 1137 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
c9b22772 1138 reg = <0 0xe615026c 0 4>;
59e79895
LP		 1139 clocks = <&pll1_div2_clk>;
1140 #clock-cells = <0>;
2ea0d4ec 1141 clock-output-names = "sd3";
59e79895
LP		 1142 };
1143 mmc0_clk: mmc0_clk@e6150240 {
1144 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1145 reg = <0 0xe6150240 0 4>;
1146 clocks = <&pll1_div2_clk>;
1147 #clock-cells = <0>;
1148 clock-output-names = "mmc0";
1149 };
1150 ssp_clk: ssp_clk@e6150248 {
1151 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1152 reg = <0 0xe6150248 0 4>;
1153 clocks = <&pll1_div2_clk>;
1154 #clock-cells = <0>;
1155 clock-output-names = "ssp";
1156 };
1157 ssprs_clk: ssprs_clk@e615024c {
1158 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1159 reg = <0 0xe615024c 0 4>;
1160 clocks = <&pll1_div2_clk>;
1161 #clock-cells = <0>;
1162 clock-output-names = "ssprs";
1163 };
1164
1165 /* Fixed factor clocks */
1166 pll1_div2_clk: pll1_div2_clk {
1167 compatible = "fixed-factor-clock";
1168 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1169 #clock-cells = <0>;
1170 clock-div = <2>;
1171 clock-mult = <1>;
1172 clock-output-names = "pll1_div2";
1173 };
1174 zg_clk: zg_clk {
1175 compatible = "fixed-factor-clock";
1176 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1177 #clock-cells = <0>;
1178 clock-div = <3>;
1179 clock-mult = <1>;
1180 clock-output-names = "zg";
1181 };
1182 zx_clk: zx_clk {
1183 compatible = "fixed-factor-clock";
1184 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1185 #clock-cells = <0>;
1186 clock-div = <3>;
1187 clock-mult = <1>;
1188 clock-output-names = "zx";
1189 };
1190 zs_clk: zs_clk {
1191 compatible = "fixed-factor-clock";
1192 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1193 #clock-cells = <0>;
1194 clock-div = <6>;
1195 clock-mult = <1>;
1196 clock-output-names = "zs";
1197 };
1198 hp_clk: hp_clk {
1199 compatible = "fixed-factor-clock";
1200 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1201 #clock-cells = <0>;
1202 clock-div = <12>;
1203 clock-mult = <1>;
1204 clock-output-names = "hp";
1205 };
1206 i_clk: i_clk {
1207 compatible = "fixed-factor-clock";
1208 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1209 #clock-cells = <0>;
1210 clock-div = <2>;
1211 clock-mult = <1>;
1212 clock-output-names = "i";
1213 };
1214 b_clk: b_clk {
1215 compatible = "fixed-factor-clock";
1216 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1217 #clock-cells = <0>;
1218 clock-div = <12>;
1219 clock-mult = <1>;
1220 clock-output-names = "b";
1221 };
1222 p_clk: p_clk {
1223 compatible = "fixed-factor-clock";
1224 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1225 #clock-cells = <0>;
1226 clock-div = <24>;
1227 clock-mult = <1>;
1228 clock-output-names = "p";
1229 };
1230 cl_clk: cl_clk {
1231 compatible = "fixed-factor-clock";
1232 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1233 #clock-cells = <0>;
1234 clock-div = <48>;
1235 clock-mult = <1>;
1236 clock-output-names = "cl";
1237 };
1238 m2_clk: m2_clk {
1239 compatible = "fixed-factor-clock";
1240 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1241 #clock-cells = <0>;
1242 clock-div = <8>;
1243 clock-mult = <1>;
1244 clock-output-names = "m2";
1245 };
59e79895
LP		 1246 rclk_clk: rclk_clk {
1247 compatible = "fixed-factor-clock";
1248 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1249 #clock-cells = <0>;
1250 clock-div = <(48 * 1024)>;
1251 clock-mult = <1>;
1252 clock-output-names = "rclk";
1253 };
1254 oscclk_clk: oscclk_clk {
1255 compatible = "fixed-factor-clock";
1256 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1257 #clock-cells = <0>;
1258 clock-div = <(12 * 1024)>;
1259 clock-mult = <1>;
1260 clock-output-names = "oscclk";
1261 };
1262 zb3_clk: zb3_clk {
1263 compatible = "fixed-factor-clock";
1264 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1265 #clock-cells = <0>;
1266 clock-div = <4>;
1267 clock-mult = <1>;
1268 clock-output-names = "zb3";
1269 };
1270 zb3d2_clk: zb3d2_clk {
1271 compatible = "fixed-factor-clock";
1272 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1273 #clock-cells = <0>;
1274 clock-div = <8>;
1275 clock-mult = <1>;
1276 clock-output-names = "zb3d2";
1277 };
1278 ddr_clk: ddr_clk {
1279 compatible = "fixed-factor-clock";
1280 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1281 #clock-cells = <0>;
1282 clock-div = <8>;
1283 clock-mult = <1>;
1284 clock-output-names = "ddr";
1285 };
1286 mp_clk: mp_clk {
1287 compatible = "fixed-factor-clock";
1288 clocks = <&pll1_div2_clk>;
1289 #clock-cells = <0>;
1290 clock-div = <15>;
1291 clock-mult = <1>;
1292 clock-output-names = "mp";
1293 };
1294 cp_clk: cp_clk {
1295 compatible = "fixed-factor-clock";
1296 clocks = <&extal_clk>;
1297 #clock-cells = <0>;
1298 clock-div = <2>;
1299 clock-mult = <1>;
1300 clock-output-names = "cp";
1301 };
1302
1303 /* Gate clocks */
cded80f8
LP		 1304 mstp0_clks: mstp0_clks@e6150130 {
1305 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1306 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1307 clocks = <&mp_clk>;
1308 #clock-cells = <1>;
cb0bf851 1309 clock-indices = <R8A7791_CLK_MSIOF0>;
cded80f8
LP		 1310 clock-output-names = "msiof0";
1311 };
59e79895
LP		 1312 mstp1_clks: mstp1_clks@e6150134 {
1313 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1314 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
74d89d25
YH		 1315 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1316 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1317 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1318 <&zs_clk>;
59e79895 1319 #clock-cells = <1>;
cb0bf851 1320 clock-indices = <
74d89d25
YH		 1321 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1322 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1323 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1324 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1325 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1326 R8A7791_CLK_VSP1_S
59e79895
LP		 1327 >;
1328 clock-output-names =
74d89d25
YH		 1329 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1330 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1331 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
59e79895
LP		 1332 };
1333 mstp2_clks: mstp2_clks@e6150138 {
1334 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1335 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1336 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
4e074bc8
GU		 1337 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1338 <&zs_clk>, <&zs_clk>;
59e79895 1339 #clock-cells = <1>;
cb0bf851 1340 clock-indices = <
59e79895 1341 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
cded80f8
LP		 1342 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1343 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
4e074bc8 1344 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
59e79895
LP		 1345 >;
1346 clock-output-names =
0c002ef8 1347 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
4e074bc8
GU		 1348 "scifb1", "msiof1", "scifb2",
1349 "sys-dmac1", "sys-dmac0";
59e79895
LP		 1350 };
1351 mstp3_clks: mstp3_clks@e615013c {
1352 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1353 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
2ea0d4ec 1354 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
b9473d9f
YS		 1355 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1356 <&hp_clk>, <&hp_clk>;
59e79895 1357 #clock-cells = <1>;
cb0bf851 1358 clock-indices = <
c08691b5 1359 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
4bfb3767
PE		 1360 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1361 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
b9473d9f 1362 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
59e79895
LP		 1363 >;
1364 clock-output-names =
c08691b5 1365 "tpu0", "sdhi2", "sdhi1", "sdhi0",
b9473d9f
YS		 1366 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1367 "usbdmac0", "usbdmac1";
59e79895 1368 };
62d386c0
GU		 1369 mstp4_clks: mstp4_clks@e6150140 {
1370 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1371 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1372 clocks = <&cp_clk>;
1373 #clock-cells = <1>;
1374 clock-indices = <R8A7791_CLK_IRQC>;
1375 clock-output-names = "irqc";
1376 };
59e79895
LP		 1377 mstp5_clks: mstp5_clks@e6150144 {
1378 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1379 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
ae65a8ae
SS		 1380 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1381 <&extal_clk>, <&p_clk>;
59e79895 1382 #clock-cells = <1>;
cb0bf851
BD		 1383 clock-indices = <
1384 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
ae65a8ae
SS		 1385 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1386 R8A7791_CLK_PWM
cb0bf851 1387 >;
ae65a8ae
SS		 1388 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1389 "thermal", "pwm";
59e79895
LP		 1390 };
1391 mstp7_clks: mstp7_clks@e615014c {
1392 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1393 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
118e4e6a 1394 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
59e79895
LP		 1395 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1396 <&zx_clk>, <&zx_clk>, <&zx_clk>;
1397 #clock-cells = <1>;
cb0bf851 1398 clock-indices = <
6225b99a 1399 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
59e79895
LP		 1400 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1401 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1402 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1403 R8A7791_CLK_LVDS0
1404 >;
1405 clock-output-names =
6225b99a 1406 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
59e79895
LP		 1407 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1408 };
1409 mstp8_clks: mstp8_clks@e6150990 {
1410 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1411 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
75a499a6 1412 clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
eaa870b3
SS		 1413 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1414 <&zs_clk>;
59e79895 1415 #clock-cells = <1>;
cb0bf851 1416 clock-indices = <
7408d306 1417 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
09c98346 1418 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
eaa870b3
SS		 1419 R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER
1420 R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
09c98346 1421 >;
65f05c38 1422 clock-output-names =
eaa870b3
SS		 1423 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0",
1424 "etheravb", "ether", "sata1", "sata0";
59e79895
LP		 1425 };
1426 mstp9_clks: mstp9_clks@e6150994 {
1427 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1428 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
4faf9c5e
GU		 1429 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1430 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1431 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
11b48db9
LP		 1432 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1433 <&hp_clk>, <&hp_clk>;
59e79895 1434 #clock-cells = <1>;
cb0bf851 1435 clock-indices = <
4faf9c5e
GU		 1436 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1437 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
c08691b5
WS		 1438 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1439 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1440 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
59e79895
LP		 1441 >;
1442 clock-output-names =
4faf9c5e
GU		 1443 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1444 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1445 "i2c1", "i2c0";
59e79895 1446 };
ee914152
KM		 1447 mstp10_clks: mstp10_clks@e6150998 {
1448 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1449 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1450 clocks = <&p_clk>,
1451 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1452 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1453 <&p_clk>,
1454 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1455 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1456 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1457 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1458 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
88401702 1459 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
ee914152
KM		 1460 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1461
1462 #clock-cells = <1>;
1463 clock-indices = <
1464 R8A7791_CLK_SSI_ALL
1465 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1466 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1467 R8A7791_CLK_SCU_ALL
1468 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
88401702 1469 R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
ee914152
KM		 1470 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1471 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1472 >;
1473 clock-output-names =
1474 "ssi-all",
1475 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1476 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1477 "scu-all",
1478 "scu-dvc1", "scu-dvc0",
88401702 1479 "scu-ctu1-mix1", "scu-ctu0-mix0",
ee914152
KM		 1480 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1481 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1482 };
59e79895
LP		 1483 mstp11_clks: mstp11_clks@e615099c {
1484 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1485 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1486 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1487 #clock-cells = <1>;
cb0bf851 1488 clock-indices = <
59e79895
LP		 1489 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1490 >;
1491 clock-output-names = "scifa3", "scifa4", "scifa5";
1492 };
1493 };
4d5b59cd 1494
6f3e4ee3 1495 qspi: spi@e6b10000 {
4d5b59cd
GU		 1496 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1497 reg = <0 0xe6b10000 0 0x2c>;
386a9291 1498 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
4d5b59cd 1499 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
591f2fa4
GU		 1500 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1501 dma-names = "tx", "rx";
797a0626 1502 power-domains = <&cpg_clocks>;
4d5b59cd
GU		 1503 num-cs = <1>;
1504 #address-cells = <1>;
1505 #size-cells = <0>;
1506 status = "disabled";
1507 };
7713d3ab
GU		 1508
1509 msiof0: spi@e6e20000 {
1510 compatible = "renesas,msiof-r8a7791";
cb6d08a2 1511 reg = <0 0xe6e20000 0 0x0064>;
386a9291 1512 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
7713d3ab 1513 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
a5ce27f5
GU		 1514 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1515 dma-names = "tx", "rx";
797a0626 1516 power-domains = <&cpg_clocks>;
7713d3ab
GU		 1517 #address-cells = <1>;
1518 #size-cells = <0>;
1519 status = "disabled";
1520 };
1521
1522 msiof1: spi@e6e10000 {
1523 compatible = "renesas,msiof-r8a7791";
cb6d08a2 1524 reg = <0 0xe6e10000 0 0x0064>;
386a9291 1525 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
7713d3ab 1526 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
a5ce27f5
GU		 1527 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1528 dma-names = "tx", "rx";
797a0626 1529 power-domains = <&cpg_clocks>;
7713d3ab
GU		 1530 #address-cells = <1>;
1531 #size-cells = <0>;
1532 status = "disabled";
1533 };
1534
1535 msiof2: spi@e6e00000 {
1536 compatible = "renesas,msiof-r8a7791";
cb6d08a2 1537 reg = <0 0xe6e00000 0 0x0064>;
386a9291 1538 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
7713d3ab 1539 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
a5ce27f5
GU		 1540 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1541 dma-names = "tx", "rx";
797a0626 1542 power-domains = <&cpg_clocks>;
7713d3ab
GU		 1543 #address-cells = <1>;
1544 #size-cells = <0>;
1545 status = "disabled";
1546 };
811cdfae 1547
c196931e
YS		 1548 xhci: usb@ee000000 {
1549 compatible = "renesas,xhci-r8a7791";
1550 reg = <0 0xee000000 0 0xc00>;
386a9291 1551 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
c196931e 1552 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
797a0626 1553 power-domains = <&cpg_clocks>;
c196931e
YS		 1554 phys = <&usb2 1>;
1555 phy-names = "usb";
1556 status = "disabled";
1557 };
1558
aace0809 1559 pci0: pci@ee090000 {
d4809689 1560 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
aace0809 1561 device_type = "pci";
aace0809
SS		 1562 reg = <0 0xee090000 0 0xc00>,
1563 <0 0xee080000 0 0x1100>;
386a9291 1564 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
797a0626
GU		 1565 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1566 power-domains = <&cpg_clocks>;
aace0809
SS		 1567 status = "disabled";
1568
1569 bus-range = <0 0>;
1570 #address-cells = <3>;
1571 #size-cells = <2>;
1572 #interrupt-cells = <1>;
1573 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1574 interrupt-map-mask = <0xff00 0 0 0x7>;
386a9291
SH		 1575 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1576 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1577 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
e1bce124
SS		 1578
1579 usb@0,1 {
1580 reg = <0x800 0 0 0 0>;
1581 device_type = "pci";
1582 phys = <&usb0 0>;
1583 phy-names = "usb";
1584 };
1585
1586 usb@0,2 {
1587 reg = <0x1000 0 0 0 0>;
1588 device_type = "pci";
1589 phys = <&usb0 0>;
1590 phy-names = "usb";
1591 };
aace0809
SS		 1592 };
1593
1594 pci1: pci@ee0d0000 {
d4809689 1595 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
aace0809 1596 device_type = "pci";
aace0809
SS		 1597 reg = <0 0xee0d0000 0 0xc00>,
1598 <0 0xee0c0000 0 0x1100>;
386a9291 1599 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
797a0626
GU		 1600 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1601 power-domains = <&cpg_clocks>;
aace0809
SS		 1602 status = "disabled";
1603
1604 bus-range = <1 1>;
1605 #address-cells = <3>;
1606 #size-cells = <2>;
1607 #interrupt-cells = <1>;
1608 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1609 interrupt-map-mask = <0xff00 0 0 0x7>;
386a9291
SH		 1610 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1611 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1612 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
e1bce124
SS		 1613
1614 usb@0,1 {
1615 reg = <0x800 0 0 0 0>;
1616 device_type = "pci";
1617 phys = <&usb2 0>;
1618 phy-names = "usb";
1619 };
1620
1621 usb@0,2 {
1622 reg = <0x1000 0 0 0 0>;
1623 device_type = "pci";
1624 phys = <&usb2 0>;
1625 phy-names = "usb";
1626 };
aace0809
SS		 1627 };
1628
811cdfae 1629 pciec: pcie@fe000000 {
bbb45f69 1630 compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
811cdfae
PE		 1631 reg = <0 0xfe000000 0 0x80000>;
1632 #address-cells = <3>;
1633 #size-cells = <2>;
1634 bus-range = <0x00 0xff>;
1635 device_type = "pci";
1636 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1637 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1638 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1639 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1640 /* Map all possible DDR as inbound ranges */
1641 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1642 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
386a9291
SH		 1643 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1644 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1645 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
811cdfae
PE		 1646 #interrupt-cells = <1>;
1647 interrupt-map-mask = <0 0 0 0>;
386a9291 1648 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
811cdfae
PE		 1649 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1650 clock-names = "pcie", "pcie_bus";
797a0626 1651 power-domains = <&cpg_clocks>;
811cdfae
PE		 1652 status = "disabled";
1653 };
09abd1fd 1654
f1951852 1655 ipmmu_sy0: mmu@e6280000 {
3c8ab0c8 1656 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
f1951852 1657 reg = <0 0xe6280000 0 0x1000>;
386a9291
SH		 1658 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1659 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
f1951852
LP		 1660 #iommu-cells = <1>;
1661 status = "disabled";
1662 };
1663
1664 ipmmu_sy1: mmu@e6290000 {
3c8ab0c8 1665 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
f1951852 1666 reg = <0 0xe6290000 0 0x1000>;
386a9291 1667 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
f1951852
LP		 1668 #iommu-cells = <1>;
1669 status = "disabled";
1670 };
1671
1672 ipmmu_ds: mmu@e6740000 {
3c8ab0c8 1673 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
f1951852 1674 reg = <0 0xe6740000 0 0x1000>;
386a9291
SH		 1675 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1676 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
f1951852
LP		 1677 #iommu-cells = <1>;
1678 status = "disabled";
1679 };
1680
1681 ipmmu_mp: mmu@ec680000 {
3c8ab0c8 1682 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
f1951852 1683 reg = <0 0xec680000 0 0x1000>;
386a9291 1684 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
f1951852
LP		 1685 #iommu-cells = <1>;
1686 status = "disabled";
1687 };
1688
1689 ipmmu_mx: mmu@fe951000 {
3c8ab0c8 1690 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
f1951852 1691 reg = <0 0xfe951000 0 0x1000>;
386a9291
SH		 1692 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1693 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
f1951852
LP		 1694 #iommu-cells = <1>;
1695 status = "disabled";
1696 };
1697
1698 ipmmu_rt: mmu@ffc80000 {
3c8ab0c8 1699 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
f1951852 1700 reg = <0 0xffc80000 0 0x1000>;
386a9291 1701 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
f1951852
LP		 1702 #iommu-cells = <1>;
1703 status = "disabled";
1704 };
1705
1706 ipmmu_gp: mmu@e62a0000 {
3c8ab0c8 1707 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
f1951852 1708 reg = <0 0xe62a0000 0 0x1000>;
386a9291
SH		 1709 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1710 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
f1951852
LP		 1711 #iommu-cells = <1>;
1712 status = "disabled";
1713 };
1714
6c63e07d 1715 rcar_sound: sound@ec500000 {
d2b541c9
KM		 1716 /*
1717 * #sound-dai-cells is required
1718 *
1719 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1720 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1721 */
f49cd2b3 1722 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
09abd1fd
KM		 1723 reg = <0 0xec500000 0 0x1000>, /* SCU */
1724 <0 0xec5a0000 0 0x100>, /* ADG */
1725 <0 0xec540000 0 0x1000>, /* SSIU */
8c3f903b 1726 <0 0xec541000 0 0x280>, /* SSI */
d73a5013
KM		 1727 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1728 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
d88a6a2a 1729
09abd1fd
KM		 1730 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1731 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1732 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1733 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1734 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1735 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1736 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1737 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1738 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1739 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1740 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
88401702 1741 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
7fd6e11d 1742 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
150c8ad4 1743 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
09abd1fd
KM		 1744 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1745 clock-names = "ssi-all",
1746 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1747 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1748 "src.9", "src.8", "src.7", "src.6", "src.5",
1749 "src.4", "src.3", "src.2", "src.1", "src.0",
88401702 1750 "ctu.0", "ctu.1",
7fd6e11d 1751 "mix.0", "mix.1",
150c8ad4 1752 "dvc.0", "dvc.1",
09abd1fd 1753 "clk_a", "clk_b", "clk_c", "clk_i";
56e86dd4 1754 power-domains = <&cpg_clocks>;
09abd1fd
KM		 1755
1756 status = "disabled";
1757
150c8ad4 1758 rcar_sound,dvc {
63573339
KM		 1759 dvc0: dvc@0 {
1760 dmas = <&audma0 0xbc>;
1761 dma-names = "tx";
1762 };
1763 dvc1: dvc@1 {
1764 dmas = <&audma0 0xbe>;
1765 dma-names = "tx";
1766 };
150c8ad4
KM		 1767 };
1768
7fd6e11d
KM		 1769 rcar_sound,mix {
1770 mix0: mix@0 { };
1771 mix1: mix@1 { };
1772 };
1773
88401702
KM		 1774 rcar_sound,ctu {
1775 ctu00: ctu@0 { };
1776 ctu01: ctu@1 { };
1777 ctu02: ctu@2 { };
1778 ctu03: ctu@3 { };
1779 ctu10: ctu@4 { };
1780 ctu11: ctu@5 { };
1781 ctu12: ctu@6 { };
1782 ctu13: ctu@7 { };
1783 };
1784
09abd1fd 1785 rcar_sound,src {
63573339 1786 src0: src@0 {
386a9291 1787 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1788 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1789 dma-names = "rx", "tx";
1790 };
1791 src1: src@1 {
386a9291 1792 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1793 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1794 dma-names = "rx", "tx";
1795 };
1796 src2: src@2 {
386a9291 1797 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1798 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1799 dma-names = "rx", "tx";
1800 };
1801 src3: src@3 {
386a9291 1802 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1803 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1804 dma-names = "rx", "tx";
1805 };
1806 src4: src@4 {
386a9291 1807 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1808 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1809 dma-names = "rx", "tx";
1810 };
1811 src5: src@5 {
386a9291 1812 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1813 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1814 dma-names = "rx", "tx";
1815 };
1816 src6: src@6 {
386a9291 1817 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1818 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1819 dma-names = "rx", "tx";
1820 };
1821 src7: src@7 {
386a9291 1822 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1823 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1824 dma-names = "rx", "tx";
1825 };
1826 src8: src@8 {
386a9291 1827 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1828 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1829 dma-names = "rx", "tx";
1830 };
1831 src9: src@9 {
386a9291 1832 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1833 dmas = <&audma0 0x97>, <&audma1 0xba>;
1834 dma-names = "rx", "tx";
1835 };
09abd1fd
KM		 1836 };
1837
1838 rcar_sound,ssi {
63573339 1839 ssi0: ssi@0 {
386a9291 1840 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1841 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1842 dma-names = "rx", "tx", "rxu", "txu";
1843 };
1844 ssi1: ssi@1 {
386a9291 1845 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1846 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1847 dma-names = "rx", "tx", "rxu", "txu";
1848 };
1849 ssi2: ssi@2 {
386a9291 1850 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1851 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1852 dma-names = "rx", "tx", "rxu", "txu";
1853 };
1854 ssi3: ssi@3 {
386a9291 1855 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1856 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1857 dma-names = "rx", "tx", "rxu", "txu";
1858 };
1859 ssi4: ssi@4 {
386a9291 1860 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1861 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1862 dma-names = "rx", "tx", "rxu", "txu";
1863 };
1864 ssi5: ssi@5 {
386a9291 1865 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1866 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1867 dma-names = "rx", "tx", "rxu", "txu";
1868 };
1869 ssi6: ssi@6 {
386a9291 1870 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1871 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1872 dma-names = "rx", "tx", "rxu", "txu";
1873 };
1874 ssi7: ssi@7 {
386a9291 1875 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1876 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1877 dma-names = "rx", "tx", "rxu", "txu";
1878 };
1879 ssi8: ssi@8 {
386a9291 1880 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1881 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1882 dma-names = "rx", "tx", "rxu", "txu";
1883 };
1884 ssi9: ssi@9 {
386a9291 1885 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
63573339
KM		 1886 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1887 dma-names = "rx", "tx", "rxu", "txu";
1888 };
09abd1fd
KM		 1889 };
1890 };
0d0771ab 1891};
Linux kernel - Deliverables
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