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ARM: shmobile: sh73a0: Add MSIOF device nodes
[deliverable/linux.git] / arch / arm / boot / dts / r8a7791.dtsi
CommitLineData
0d0771ab
HN		 1/*
2 * Device Tree Source for the r8a7791 SoC
3 *
118e4e6a 4 * Copyright (C) 2013-2015 Renesas Electronics Corporation
2e5d55ce
SS		 5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
0d0771ab
HN		 7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
59e79895 13#include <dt-bindings/clock/r8a7791-clock.h>
5f75e73c
LP		 14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
0d0771ab
HN		 17/ {
18 compatible = "renesas,r8a7791";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
5bd3de7b
WS		 23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &i2c4;
29 i2c5 = &i2c5;
36408d9d
WS		 30 i2c6 = &i2c6;
31 i2c7 = &i2c7;
32 i2c8 = &i2c8;
6f3e4ee3 33 spi0 = &qspi;
7713d3ab
GU		 34 spi1 = &msiof0;
35 spi2 = &msiof1;
36 spi3 = &msiof2;
0b8d1d57
SS		 37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
5bd3de7b
WS		 40 };
41
0d0771ab
HN		 42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 cpu0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a15";
49 reg = <0>;
896b79df 50 clock-frequency = <1500000000>;
a57004ec
GI		 51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7791_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
54
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1500000 1000000>,
57 <1312500 1000000>,
58 <1125000 1000000>,
59 < 937500 1000000>,
60 < 750000 1000000>,
61 < 375000 1000000>;
0d0771ab 62 };
15ab426c
MD		 63
64 cpu1: cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <1>;
896b79df 68 clock-frequency = <1500000000>;
15ab426c 69 };
0d0771ab
HN		 70 };
71
72 gic: interrupt-controller@f1001000 {
d238b5e6 73 compatible = "arm,gic-400";
0d0771ab
HN		 74 #interrupt-cells = <3>;
75 #address-cells = <0>;
76 interrupt-controller;
77 reg = <0 0xf1001000 0 0x1000>,
78 <0 0xf1002000 0 0x1000>,
79 <0 0xf1004000 0 0x2000>,
80 <0 0xf1006000 0 0x2000>;
aa5404fc 81 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0d0771ab 82 };
d77db73e 83
89fbba12 84 gpio0: gpio@e6050000 {
ab87e3fc 85 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 86 reg = <0 0xe6050000 0 0x50>;
5f75e73c 87 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 88 #gpio-cells = <2>;
89 gpio-controller;
90 gpio-ranges = <&pfc 0 0 32>;
91 #interrupt-cells = <2>;
92 interrupt-controller;
4faf9c5e 93 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
797a0626 94 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 95 };
96
89fbba12 97 gpio1: gpio@e6051000 {
ab87e3fc 98 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 99 reg = <0 0xe6051000 0 0x50>;
5f75e73c 100 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 101 #gpio-cells = <2>;
102 gpio-controller;
1329f6d0 103 gpio-ranges = <&pfc 0 32 26>;
ab87e3fc
MD		 104 #interrupt-cells = <2>;
105 interrupt-controller;
4faf9c5e 106 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
797a0626 107 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 108 };
109
89fbba12 110 gpio2: gpio@e6052000 {
ab87e3fc 111 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 112 reg = <0 0xe6052000 0 0x50>;
5f75e73c 113 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 114 #gpio-cells = <2>;
115 gpio-controller;
116 gpio-ranges = <&pfc 0 64 32>;
117 #interrupt-cells = <2>;
118 interrupt-controller;
4faf9c5e 119 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
797a0626 120 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 121 };
122
89fbba12 123 gpio3: gpio@e6053000 {
ab87e3fc 124 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 125 reg = <0 0xe6053000 0 0x50>;
5f75e73c 126 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 127 #gpio-cells = <2>;
128 gpio-controller;
129 gpio-ranges = <&pfc 0 96 32>;
130 #interrupt-cells = <2>;
131 interrupt-controller;
4faf9c5e 132 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
797a0626 133 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 134 };
135
89fbba12 136 gpio4: gpio@e6054000 {
ab87e3fc 137 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 138 reg = <0 0xe6054000 0 0x50>;
5f75e73c 139 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 140 #gpio-cells = <2>;
141 gpio-controller;
142 gpio-ranges = <&pfc 0 128 32>;
143 #interrupt-cells = <2>;
144 interrupt-controller;
4faf9c5e 145 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
797a0626 146 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 147 };
148
89fbba12 149 gpio5: gpio@e6055000 {
ab87e3fc 150 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 151 reg = <0 0xe6055000 0 0x50>;
5f75e73c 152 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 153 #gpio-cells = <2>;
154 gpio-controller;
155 gpio-ranges = <&pfc 0 160 32>;
156 #interrupt-cells = <2>;
157 interrupt-controller;
4faf9c5e 158 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
797a0626 159 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 160 };
161
89fbba12 162 gpio6: gpio@e6055400 {
ab87e3fc 163 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 164 reg = <0 0xe6055400 0 0x50>;
5f75e73c 165 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 166 #gpio-cells = <2>;
167 gpio-controller;
168 gpio-ranges = <&pfc 0 192 32>;
169 #interrupt-cells = <2>;
170 interrupt-controller;
4faf9c5e 171 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
797a0626 172 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 173 };
174
89fbba12 175 gpio7: gpio@e6055800 {
ab87e3fc 176 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 177 reg = <0 0xe6055800 0 0x50>;
5f75e73c 178 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 179 #gpio-cells = <2>;
180 gpio-controller;
181 gpio-ranges = <&pfc 0 224 26>;
182 #interrupt-cells = <2>;
183 interrupt-controller;
4faf9c5e 184 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
797a0626 185 power-domains = <&cpg_clocks>;
ab87e3fc
MD		 186 };
187
d103f4d3
MD		 188 thermal@e61f0000 {
189 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
190 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
d103f4d3 191 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
563bc8eb 192 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
797a0626 193 power-domains = <&cpg_clocks>;
d103f4d3
MD		 194 };
195
03586acf
MD		 196 timer {
197 compatible = "arm,armv7-timer";
aa5404fc
GU		 198 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
199 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
200 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
201 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
03586acf
MD		 202 };
203
ceaa1894 204 cmt0: timer@ffca0000 {
4217f323 205 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
ceaa1894
LP		 206 reg = <0 0xffca0000 0 0x1004>;
207 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
208 <0 143 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
210 clock-names = "fck";
797a0626 211 power-domains = <&cpg_clocks>;
ceaa1894
LP		 212
213 renesas,channels-mask = <0x60>;
214
215 status = "disabled";
216 };
217
218 cmt1: timer@e6130000 {
4217f323 219 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
ceaa1894
LP		 220 reg = <0 0xe6130000 0 0x1004>;
221 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
222 <0 121 IRQ_TYPE_LEVEL_HIGH>,
223 <0 122 IRQ_TYPE_LEVEL_HIGH>,
224 <0 123 IRQ_TYPE_LEVEL_HIGH>,
225 <0 124 IRQ_TYPE_LEVEL_HIGH>,
226 <0 125 IRQ_TYPE_LEVEL_HIGH>,
227 <0 126 IRQ_TYPE_LEVEL_HIGH>,
228 <0 127 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
230 clock-names = "fck";
797a0626 231 power-domains = <&cpg_clocks>;
ceaa1894
LP		 232
233 renesas,channels-mask = <0xff>;
234
235 status = "disabled";
236 };
237
d77db73e 238 irqc0: interrupt-controller@e61c0000 {
26041b06 239 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
d77db73e
MD		 240 #interrupt-cells = <2>;
241 interrupt-controller;
242 reg = <0 0xe61c0000 0 0x200>;
5f75e73c
LP		 243 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
244 <0 1 IRQ_TYPE_LEVEL_HIGH>,
245 <0 2 IRQ_TYPE_LEVEL_HIGH>,
246 <0 3 IRQ_TYPE_LEVEL_HIGH>,
247 <0 12 IRQ_TYPE_LEVEL_HIGH>,
248 <0 13 IRQ_TYPE_LEVEL_HIGH>,
249 <0 14 IRQ_TYPE_LEVEL_HIGH>,
250 <0 15 IRQ_TYPE_LEVEL_HIGH>,
251 <0 16 IRQ_TYPE_LEVEL_HIGH>,
252 <0 17 IRQ_TYPE_LEVEL_HIGH>;
62d386c0 253 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
797a0626 254 power-domains = <&cpg_clocks>;
d77db73e 255 };
55146927 256
fde8feef 257 dmac0: dma-controller@e6700000 {
e6d12b49 258 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
fde8feef
LP		 259 reg = <0 0xe6700000 0 0x20000>;
260 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
261 0 200 IRQ_TYPE_LEVEL_HIGH
262 0 201 IRQ_TYPE_LEVEL_HIGH
263 0 202 IRQ_TYPE_LEVEL_HIGH
264 0 203 IRQ_TYPE_LEVEL_HIGH
265 0 204 IRQ_TYPE_LEVEL_HIGH
266 0 205 IRQ_TYPE_LEVEL_HIGH
267 0 206 IRQ_TYPE_LEVEL_HIGH
268 0 207 IRQ_TYPE_LEVEL_HIGH
269 0 208 IRQ_TYPE_LEVEL_HIGH
270 0 209 IRQ_TYPE_LEVEL_HIGH
271 0 210 IRQ_TYPE_LEVEL_HIGH
272 0 211 IRQ_TYPE_LEVEL_HIGH
273 0 212 IRQ_TYPE_LEVEL_HIGH
274 0 213 IRQ_TYPE_LEVEL_HIGH
275 0 214 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-names = "error",
277 "ch0", "ch1", "ch2", "ch3",
278 "ch4", "ch5", "ch6", "ch7",
279 "ch8", "ch9", "ch10", "ch11",
280 "ch12", "ch13", "ch14";
281 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
282 clock-names = "fck";
797a0626 283 power-domains = <&cpg_clocks>;
fde8feef
LP		 284 #dma-cells = <1>;
285 dma-channels = <15>;
286 };
287
288 dmac1: dma-controller@e6720000 {
e6d12b49 289 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
fde8feef
LP		 290 reg = <0 0xe6720000 0 0x20000>;
291 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
292 0 216 IRQ_TYPE_LEVEL_HIGH
293 0 217 IRQ_TYPE_LEVEL_HIGH
294 0 218 IRQ_TYPE_LEVEL_HIGH
295 0 219 IRQ_TYPE_LEVEL_HIGH
296 0 308 IRQ_TYPE_LEVEL_HIGH
297 0 309 IRQ_TYPE_LEVEL_HIGH
298 0 310 IRQ_TYPE_LEVEL_HIGH
299 0 311 IRQ_TYPE_LEVEL_HIGH
300 0 312 IRQ_TYPE_LEVEL_HIGH
301 0 313 IRQ_TYPE_LEVEL_HIGH
302 0 314 IRQ_TYPE_LEVEL_HIGH
303 0 315 IRQ_TYPE_LEVEL_HIGH
304 0 316 IRQ_TYPE_LEVEL_HIGH
305 0 317 IRQ_TYPE_LEVEL_HIGH
306 0 318 IRQ_TYPE_LEVEL_HIGH>;
307 interrupt-names = "error",
308 "ch0", "ch1", "ch2", "ch3",
309 "ch4", "ch5", "ch6", "ch7",
310 "ch8", "ch9", "ch10", "ch11",
311 "ch12", "ch13", "ch14";
312 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
313 clock-names = "fck";
797a0626 314 power-domains = <&cpg_clocks>;
fde8feef
LP		 315 #dma-cells = <1>;
316 dma-channels = <15>;
317 };
318
8994fff6 319 audma0: dma-controller@ec700000 {
e6d12b49 320 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
8994fff6
KM		 321 reg = <0 0xec700000 0 0x10000>;
322 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
323 0 320 IRQ_TYPE_LEVEL_HIGH
324 0 321 IRQ_TYPE_LEVEL_HIGH
325 0 322 IRQ_TYPE_LEVEL_HIGH
326 0 323 IRQ_TYPE_LEVEL_HIGH
327 0 324 IRQ_TYPE_LEVEL_HIGH
328 0 325 IRQ_TYPE_LEVEL_HIGH
329 0 326 IRQ_TYPE_LEVEL_HIGH
330 0 327 IRQ_TYPE_LEVEL_HIGH
331 0 328 IRQ_TYPE_LEVEL_HIGH
332 0 329 IRQ_TYPE_LEVEL_HIGH
333 0 330 IRQ_TYPE_LEVEL_HIGH
334 0 331 IRQ_TYPE_LEVEL_HIGH
335 0 332 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-names = "error",
337 "ch0", "ch1", "ch2", "ch3",
338 "ch4", "ch5", "ch6", "ch7",
339 "ch8", "ch9", "ch10", "ch11",
340 "ch12";
341 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
342 clock-names = "fck";
797a0626 343 power-domains = <&cpg_clocks>;
8994fff6
KM		 344 #dma-cells = <1>;
345 dma-channels = <13>;
346 };
347
348 audma1: dma-controller@ec720000 {
e6d12b49 349 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
8994fff6
KM		 350 reg = <0 0xec720000 0 0x10000>;
351 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
352 0 333 IRQ_TYPE_LEVEL_HIGH
353 0 334 IRQ_TYPE_LEVEL_HIGH
354 0 335 IRQ_TYPE_LEVEL_HIGH
355 0 336 IRQ_TYPE_LEVEL_HIGH
356 0 337 IRQ_TYPE_LEVEL_HIGH
357 0 338 IRQ_TYPE_LEVEL_HIGH
358 0 339 IRQ_TYPE_LEVEL_HIGH
359 0 340 IRQ_TYPE_LEVEL_HIGH
360 0 341 IRQ_TYPE_LEVEL_HIGH
361 0 342 IRQ_TYPE_LEVEL_HIGH
362 0 343 IRQ_TYPE_LEVEL_HIGH
363 0 344 IRQ_TYPE_LEVEL_HIGH
364 0 345 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-names = "error",
366 "ch0", "ch1", "ch2", "ch3",
367 "ch4", "ch5", "ch6", "ch7",
368 "ch8", "ch9", "ch10", "ch11",
369 "ch12";
370 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
371 clock-names = "fck";
797a0626 372 power-domains = <&cpg_clocks>;
8994fff6
KM		 373 #dma-cells = <1>;
374 dma-channels = <13>;
375 };
376
e3e25edc
YS		 377 usb_dmac0: dma-controller@e65a0000 {
378 compatible = "renesas,usb-dmac";
379 reg = <0 0xe65a0000 0 0x100>;
380 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
381 0 109 IRQ_TYPE_LEVEL_HIGH>;
382 interrupt-names = "ch0", "ch1";
383 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
797a0626 384 power-domains = <&cpg_clocks>;
e3e25edc
YS		 385 #dma-cells = <1>;
386 dma-channels = <2>;
387 };
388
389 usb_dmac1: dma-controller@e65b0000 {
390 compatible = "renesas,usb-dmac";
391 reg = <0 0xe65b0000 0 0x100>;
392 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
393 0 110 IRQ_TYPE_LEVEL_HIGH>;
394 interrupt-names = "ch0", "ch1";
395 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
797a0626 396 power-domains = <&cpg_clocks>;
e3e25edc
YS		 397 #dma-cells = <1>;
398 dma-channels = <2>;
399 };
400
36408d9d 401 /* The memory map in the User's Manual maps the cores to bus numbers */
5bd3de7b
WS		 402 i2c0: i2c@e6508000 {
403 #address-cells = <1>;
404 #size-cells = <0>;
405 compatible = "renesas,i2c-r8a7791";
406 reg = <0 0xe6508000 0 0x40>;
407 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
797a0626 409 power-domains = <&cpg_clocks>;
5bd3de7b
WS		 410 status = "disabled";
411 };
412
413 i2c1: i2c@e6518000 {
414 #address-cells = <1>;
415 #size-cells = <0>;
416 compatible = "renesas,i2c-r8a7791";
417 reg = <0 0xe6518000 0 0x40>;
418 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
797a0626 420 power-domains = <&cpg_clocks>;
5bd3de7b
WS		 421 status = "disabled";
422 };
423
424 i2c2: i2c@e6530000 {
425 #address-cells = <1>;
426 #size-cells = <0>;
427 compatible = "renesas,i2c-r8a7791";
428 reg = <0 0xe6530000 0 0x40>;
429 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
797a0626 431 power-domains = <&cpg_clocks>;
5bd3de7b
WS		 432 status = "disabled";
433 };
434
435 i2c3: i2c@e6540000 {
436 #address-cells = <1>;
437 #size-cells = <0>;
438 compatible = "renesas,i2c-r8a7791";
439 reg = <0 0xe6540000 0 0x40>;
440 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
797a0626 442 power-domains = <&cpg_clocks>;
5bd3de7b
WS		 443 status = "disabled";
444 };
445
446 i2c4: i2c@e6520000 {
447 #address-cells = <1>;
448 #size-cells = <0>;
449 compatible = "renesas,i2c-r8a7791";
450 reg = <0 0xe6520000 0 0x40>;
451 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
797a0626 453 power-domains = <&cpg_clocks>;
5bd3de7b
WS		 454 status = "disabled";
455 };
456
457 i2c5: i2c@e6528000 {
36408d9d 458 /* doesn't need pinmux */
5bd3de7b
WS		 459 #address-cells = <1>;
460 #size-cells = <0>;
461 compatible = "renesas,i2c-r8a7791";
462 reg = <0 0xe6528000 0 0x40>;
463 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
797a0626 465 power-domains = <&cpg_clocks>;
5bd3de7b
WS		 466 status = "disabled";
467 };
468
36408d9d
WS		 469 i2c6: i2c@e60b0000 {
470 /* doesn't need pinmux */
471 #address-cells = <1>;
472 #size-cells = <0>;
473 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
474 reg = <0 0xe60b0000 0 0x425>;
475 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
3f58c54b
WS		 477 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
478 dma-names = "tx", "rx";
797a0626 479 power-domains = <&cpg_clocks>;
36408d9d
WS		 480 status = "disabled";
481 };
482
483 i2c7: i2c@e6500000 {
484 #address-cells = <1>;
485 #size-cells = <0>;
486 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
487 reg = <0 0xe6500000 0 0x425>;
488 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
3f58c54b
WS		 490 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
491 dma-names = "tx", "rx";
797a0626 492 power-domains = <&cpg_clocks>;
36408d9d
WS		 493 status = "disabled";
494 };
495
496 i2c8: i2c@e6510000 {
497 #address-cells = <1>;
498 #size-cells = <0>;
499 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
500 reg = <0 0xe6510000 0 0x425>;
501 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
3f58c54b
WS		 503 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
504 dma-names = "tx", "rx";
797a0626 505 power-domains = <&cpg_clocks>;
36408d9d
WS		 506 status = "disabled";
507 };
508
55146927
MD		 509 pfc: pfc@e6060000 {
510 compatible = "renesas,pfc-r8a7791";
511 reg = <0 0xe6060000 0 0x250>;
55146927 512 };
59e79895 513
8edae499
LP		 514 mmcif0: mmc@ee200000 {
515 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
516 reg = <0 0xee200000 0 0x80>;
517 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
16b355b4
LP		 519 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
520 dma-names = "tx", "rx";
797a0626 521 power-domains = <&cpg_clocks>;
8edae499
LP		 522 reg-io-width = <4>;
523 status = "disabled";
d957ab8d 524 max-frequency = <97500000>;
8edae499
LP		 525 };
526
b7ed8a0d
MD		 527 sdhi0: sd@ee100000 {
528 compatible = "renesas,sdhi-r8a7791";
e849b065 529 reg = <0 0xee100000 0 0x328>;
b7ed8a0d
MD		 530 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
ae67fa2f
LP		 532 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
533 dma-names = "tx", "rx";
797a0626 534 power-domains = <&cpg_clocks>;
b7ed8a0d
MD		 535 status = "disabled";
536 };
537
538 sdhi1: sd@ee140000 {
539 compatible = "renesas,sdhi-r8a7791";
540 reg = <0 0xee140000 0 0x100>;
b7ed8a0d
MD		 541 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
ae67fa2f
LP		 543 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
544 dma-names = "tx", "rx";
797a0626 545 power-domains = <&cpg_clocks>;
b7ed8a0d
MD		 546 status = "disabled";
547 };
548
549 sdhi2: sd@ee160000 {
550 compatible = "renesas,sdhi-r8a7791";
551 reg = <0 0xee160000 0 0x100>;
b7ed8a0d
MD		 552 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
ae67fa2f
LP		 554 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
555 dma-names = "tx", "rx";
797a0626 556 power-domains = <&cpg_clocks>;
b7ed8a0d
MD		 557 status = "disabled";
558 };
559
9640cf25
LP		 560 scifa0: serial@e6c40000 {
561 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
562 reg = <0 0xe6c40000 0 64>;
9640cf25
LP		 563 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
565 clock-names = "sci_ick";
558d6565
GU		 566 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
567 dma-names = "tx", "rx";
797a0626 568 power-domains = <&cpg_clocks>;
9640cf25
LP		 569 status = "disabled";
570 };
571
572 scifa1: serial@e6c50000 {
573 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 574 reg = <0 0xe6c50000 0 64>;
575 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
577 clock-names = "sci_ick";
558d6565
GU		 578 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
579 dma-names = "tx", "rx";
797a0626 580 power-domains = <&cpg_clocks>;
9640cf25
LP		 581 status = "disabled";
582 };
583
584 scifa2: serial@e6c60000 {
585 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 586 reg = <0 0xe6c60000 0 64>;
587 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
589 clock-names = "sci_ick";
558d6565
GU		 590 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
591 dma-names = "tx", "rx";
797a0626 592 power-domains = <&cpg_clocks>;
9640cf25
LP		 593 status = "disabled";
594 };
595
596 scifa3: serial@e6c70000 {
597 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 598 reg = <0 0xe6c70000 0 64>;
599 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
601 clock-names = "sci_ick";
558d6565
GU		 602 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
603 dma-names = "tx", "rx";
797a0626 604 power-domains = <&cpg_clocks>;
9640cf25
LP		 605 status = "disabled";
606 };
607
608 scifa4: serial@e6c78000 {
609 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 610 reg = <0 0xe6c78000 0 64>;
611 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
613 clock-names = "sci_ick";
558d6565
GU		 614 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
615 dma-names = "tx", "rx";
797a0626 616 power-domains = <&cpg_clocks>;
9640cf25
LP		 617 status = "disabled";
618 };
619
620 scifa5: serial@e6c80000 {
621 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 622 reg = <0 0xe6c80000 0 64>;
623 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
625 clock-names = "sci_ick";
558d6565
GU		 626 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
627 dma-names = "tx", "rx";
797a0626 628 power-domains = <&cpg_clocks>;
9640cf25
LP		 629 status = "disabled";
630 };
631
632 scifb0: serial@e6c20000 {
633 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
9640cf25
LP		 634 reg = <0 0xe6c20000 0 64>;
635 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
637 clock-names = "sci_ick";
558d6565
GU		 638 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
639 dma-names = "tx", "rx";
797a0626 640 power-domains = <&cpg_clocks>;
9640cf25
LP		 641 status = "disabled";
642 };
643
644 scifb1: serial@e6c30000 {
645 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
9640cf25
LP		 646 reg = <0 0xe6c30000 0 64>;
647 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
649 clock-names = "sci_ick";
558d6565
GU		 650 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
651 dma-names = "tx", "rx";
797a0626 652 power-domains = <&cpg_clocks>;
9640cf25
LP		 653 status = "disabled";
654 };
655
656 scifb2: serial@e6ce0000 {
657 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
9640cf25
LP		 658 reg = <0 0xe6ce0000 0 64>;
659 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
661 clock-names = "sci_ick";
558d6565
GU		 662 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
663 dma-names = "tx", "rx";
797a0626 664 power-domains = <&cpg_clocks>;
9640cf25
LP		 665 status = "disabled";
666 };
667
668 scif0: serial@e6e60000 {
669 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 670 reg = <0 0xe6e60000 0 64>;
671 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
673 clock-names = "sci_ick";
558d6565
GU		 674 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
675 dma-names = "tx", "rx";
797a0626 676 power-domains = <&cpg_clocks>;
9640cf25
LP		 677 status = "disabled";
678 };
679
680 scif1: serial@e6e68000 {
681 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 682 reg = <0 0xe6e68000 0 64>;
683 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
685 clock-names = "sci_ick";
558d6565
GU		 686 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
687 dma-names = "tx", "rx";
797a0626 688 power-domains = <&cpg_clocks>;
9640cf25
LP		 689 status = "disabled";
690 };
691
692 scif2: serial@e6e58000 {
693 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 694 reg = <0 0xe6e58000 0 64>;
695 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
697 clock-names = "sci_ick";
558d6565
GU		 698 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
699 dma-names = "tx", "rx";
797a0626 700 power-domains = <&cpg_clocks>;
9640cf25
LP		 701 status = "disabled";
702 };
703
704 scif3: serial@e6ea8000 {
705 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 706 reg = <0 0xe6ea8000 0 64>;
707 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
709 clock-names = "sci_ick";
558d6565
GU		 710 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
711 dma-names = "tx", "rx";
797a0626 712 power-domains = <&cpg_clocks>;
9640cf25
LP		 713 status = "disabled";
714 };
715
716 scif4: serial@e6ee0000 {
717 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 718 reg = <0 0xe6ee0000 0 64>;
719 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
721 clock-names = "sci_ick";
558d6565
GU		 722 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
723 dma-names = "tx", "rx";
797a0626 724 power-domains = <&cpg_clocks>;
9640cf25
LP		 725 status = "disabled";
726 };
727
728 scif5: serial@e6ee8000 {
729 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 730 reg = <0 0xe6ee8000 0 64>;
731 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
733 clock-names = "sci_ick";
558d6565
GU		 734 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
735 dma-names = "tx", "rx";
797a0626 736 power-domains = <&cpg_clocks>;
9640cf25
LP		 737 status = "disabled";
738 };
739
740 hscif0: serial@e62c0000 {
741 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
9640cf25
LP		 742 reg = <0 0xe62c0000 0 96>;
743 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
745 clock-names = "sci_ick";
558d6565
GU		 746 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
747 dma-names = "tx", "rx";
797a0626 748 power-domains = <&cpg_clocks>;
9640cf25
LP		 749 status = "disabled";
750 };
751
752 hscif1: serial@e62c8000 {
753 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
9640cf25
LP		 754 reg = <0 0xe62c8000 0 96>;
755 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
757 clock-names = "sci_ick";
558d6565
GU		 758 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
759 dma-names = "tx", "rx";
797a0626 760 power-domains = <&cpg_clocks>;
9640cf25
LP		 761 status = "disabled";
762 };
763
764 hscif2: serial@e62d0000 {
765 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
9640cf25
LP		 766 reg = <0 0xe62d0000 0 96>;
767 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
769 clock-names = "sci_ick";
558d6565
GU		 770 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
771 dma-names = "tx", "rx";
797a0626 772 power-domains = <&cpg_clocks>;
9640cf25
LP		 773 status = "disabled";
774 };
775
2e5d55ce
SS		 776 ether: ethernet@ee700000 {
777 compatible = "renesas,ether-r8a7791";
778 reg = <0 0xee700000 0 0x400>;
779 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
797a0626 781 power-domains = <&cpg_clocks>;
2e5d55ce
SS		 782 phy-mode = "rmii";
783 #address-cells = <1>;
784 #size-cells = <0>;
785 status = "disabled";
786 };
787
b8532c69
VB		 788 sata0: sata@ee300000 {
789 compatible = "renesas,sata-r8a7791";
790 reg = <0 0xee300000 0 0x2000>;
b8532c69
VB		 791 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
797a0626 793 power-domains = <&cpg_clocks>;
b8532c69
VB		 794 status = "disabled";
795 };
796
797 sata1: sata@ee500000 {
798 compatible = "renesas,sata-r8a7791";
799 reg = <0 0xee500000 0 0x2000>;
b8532c69
VB		 800 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
797a0626 802 power-domains = <&cpg_clocks>;
b8532c69
VB		 803 status = "disabled";
804 };
805
1c1fee7c
YS		 806 hsusb: usb@e6590000 {
807 compatible = "renesas,usbhs-r8a7791";
808 reg = <0 0xe6590000 0 0x100>;
809 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
7706993e
YS		 811 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
812 <&usb_dmac1 0>, <&usb_dmac1 1>;
813 dma-names = "ch0", "ch1", "ch2", "ch3";
797a0626
GU		 814 power-domains = <&cpg_clocks>;
815 renesas,buswait = <4>;
816 phys = <&usb0 1>;
817 phy-names = "usb";
1c1fee7c
YS		 818 status = "disabled";
819 };
820
3b7e530d
SS		 821 usbphy: usb-phy@e6590100 {
822 compatible = "renesas,usb-phy-r8a7791";
823 reg = <0 0xe6590100 0 0x100>;
824 #address-cells = <1>;
825 #size-cells = <0>;
826 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
827 clock-names = "usbhs";
797a0626 828 power-domains = <&cpg_clocks>;
3b7e530d
SS		 829 status = "disabled";
830
831 usb0: usb-channel@0 {
832 reg = <0>;
833 #phy-cells = <1>;
834 };
835 usb2: usb-channel@2 {
836 reg = <2>;
837 #phy-cells = <1>;
838 };
839 };
840
0b8d1d57
SS		 841 vin0: video@e6ef0000 {
842 compatible = "renesas,vin-r8a7791";
0b8d1d57
SS		 843 reg = <0 0xe6ef0000 0 0x1000>;
844 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
797a0626
GU		 845 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
846 power-domains = <&cpg_clocks>;
0b8d1d57
SS		 847 status = "disabled";
848 };
849
850 vin1: video@e6ef1000 {
851 compatible = "renesas,vin-r8a7791";
0b8d1d57
SS		 852 reg = <0 0xe6ef1000 0 0x1000>;
853 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
797a0626
GU		 854 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
855 power-domains = <&cpg_clocks>;
0b8d1d57
SS		 856 status = "disabled";
857 };
858
859 vin2: video@e6ef2000 {
860 compatible = "renesas,vin-r8a7791";
0b8d1d57
SS		 861 reg = <0 0xe6ef2000 0 0x1000>;
862 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
797a0626
GU		 863 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
864 power-domains = <&cpg_clocks>;
0b8d1d57
SS		 865 status = "disabled";
866 };
867
8eefac2d
LP		 868 vsp1@fe928000 {
869 compatible = "renesas,vsp1";
870 reg = <0 0xfe928000 0 0x8000>;
871 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
797a0626 873 power-domains = <&cpg_clocks>;
8eefac2d
LP		 874
875 renesas,has-lut;
876 renesas,has-sru;
877 renesas,#rpf = <5>;
878 renesas,#uds = <3>;
879 renesas,#wpf = <4>;
880 };
881
882 vsp1@fe930000 {
883 compatible = "renesas,vsp1";
884 reg = <0 0xfe930000 0 0x8000>;
885 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
797a0626 887 power-domains = <&cpg_clocks>;
8eefac2d
LP		 888
889 renesas,has-lif;
890 renesas,has-lut;
891 renesas,#rpf = <4>;
892 renesas,#uds = <1>;
893 renesas,#wpf = <4>;
894 };
895
896 vsp1@fe938000 {
897 compatible = "renesas,vsp1";
898 reg = <0 0xfe938000 0 0x8000>;
899 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
900 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
797a0626 901 power-domains = <&cpg_clocks>;
8eefac2d
LP		 902
903 renesas,has-lif;
904 renesas,has-lut;
905 renesas,#rpf = <4>;
906 renesas,#uds = <1>;
907 renesas,#wpf = <4>;
908 };
909
910 du: display@feb00000 {
911 compatible = "renesas,du-r8a7791";
912 reg = <0 0xfeb00000 0 0x40000>,
913 <0 0xfeb90000 0 0x1c>;
914 reg-names = "du", "lvds.0";
915 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
916 <0 268 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
918 <&mstp7_clks R8A7791_CLK_DU1>,
919 <&mstp7_clks R8A7791_CLK_LVDS0>;
920 clock-names = "du.0", "du.1", "lvds.0";
921 status = "disabled";
922
923 ports {
924 #address-cells = <1>;
925 #size-cells = <0>;
926
927 port@0 {
928 reg = <0>;
929 du_out_rgb: endpoint {
930 };
931 };
932 port@1 {
933 reg = <1>;
934 du_out_lvds0: endpoint {
935 };
936 };
937 };
938 };
939
3cf01884
SS		 940 can0: can@e6e80000 {
941 compatible = "renesas,can-r8a7791";
942 reg = <0 0xe6e80000 0 0x1000>;
943 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
944 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
945 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
946 clock-names = "clkp1", "clkp2", "can_clk";
797a0626 947 power-domains = <&cpg_clocks>;
3cf01884
SS		 948 status = "disabled";
949 };
950
951 can1: can@e6e88000 {
952 compatible = "renesas,can-r8a7791";
953 reg = <0 0xe6e88000 0 0x1000>;
954 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
956 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
957 clock-names = "clkp1", "clkp2", "can_clk";
797a0626 958 power-domains = <&cpg_clocks>;
3cf01884
SS		 959 status = "disabled";
960 };
961
0caa3660
MU		 962 jpu: jpeg-codec@fe980000 {
963 compatible = "renesas,jpu-r8a7791";
964 reg = <0 0xfe980000 0 0x10300>;
965 interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&mstp1_clks R8A7791_CLK_JPU>;
797a0626 967 power-domains = <&cpg_clocks>;
0caa3660
MU		 968 };
969
59e79895
LP		 970 clocks {
971 #address-cells = <2>;
972 #size-cells = <2>;
973 ranges;
974
975 /* External root clock */
976 extal_clk: extal_clk {
977 compatible = "fixed-clock";
978 #clock-cells = <0>;
979 /* This value must be overriden by the board. */
980 clock-frequency = <0>;
981 clock-output-names = "extal";
982 };
983
0d3dbde8
KM		 984 /*
985 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
986 * default. Boards that provide audio clocks should override them.
987 */
988 audio_clk_a: audio_clk_a {
989 compatible = "fixed-clock";
990 #clock-cells = <0>;
991 clock-frequency = <0>;
992 clock-output-names = "audio_clk_a";
993 };
994 audio_clk_b: audio_clk_b {
995 compatible = "fixed-clock";
996 #clock-cells = <0>;
997 clock-frequency = <0>;
998 clock-output-names = "audio_clk_b";
999 };
1000 audio_clk_c: audio_clk_c {
1001 compatible = "fixed-clock";
1002 #clock-cells = <0>;
1003 clock-frequency = <0>;
1004 clock-output-names = "audio_clk_c";
1005 };
1006
66c405e7
PE		 1007 /* External PCIe clock - can be overridden by the board */
1008 pcie_bus_clk: pcie_bus_clk {
1009 compatible = "fixed-clock";
1010 #clock-cells = <0>;
1011 clock-frequency = <100000000>;
1012 clock-output-names = "pcie_bus";
1013 status = "disabled";
1014 };
1015
b324252c
SS		 1016 /* External USB clock - can be overridden by the board */
1017 usb_extal_clk: usb_extal_clk {
1018 compatible = "fixed-clock";
1019 #clock-cells = <0>;
1020 clock-frequency = <48000000>;
1021 clock-output-names = "usb_extal";
1022 };
1023
1024 /* External CAN clock */
1025 can_clk: can_clk {
1026 compatible = "fixed-clock";
1027 #clock-cells = <0>;
1028 /* This value must be overridden by the board. */
1029 clock-frequency = <0>;
1030 clock-output-names = "can_clk";
1031 status = "disabled";
1032 };
1033
59e79895
LP		 1034 /* Special CPG clocks */
1035 cpg_clocks: cpg_clocks@e6150000 {
1036 compatible = "renesas,r8a7791-cpg-clocks",
1037 "renesas,rcar-gen2-cpg-clocks";
1038 reg = <0 0xe6150000 0 0x1000>;
b324252c 1039 clocks = <&extal_clk &usb_extal_clk>;
59e79895
LP		 1040 #clock-cells = <1>;
1041 clock-output-names = "main", "pll0", "pll1", "pll3",
b324252c 1042 "lb", "qspi", "sdh", "sd0", "z",
ae65a8ae 1043 "rcan", "adsp";
797a0626 1044 #power-domain-cells = <0>;
59e79895
LP		 1045 };
1046
1047 /* Variable factor clocks */
2ea0d4ec 1048 sd2_clk: sd2_clk@e6150078 {
59e79895
LP		 1049 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1050 reg = <0 0xe6150078 0 4>;
1051 clocks = <&pll1_div2_clk>;
1052 #clock-cells = <0>;
2ea0d4ec 1053 clock-output-names = "sd2";
59e79895 1054 };
2ea0d4ec 1055 sd3_clk: sd3_clk@e615026c {
59e79895 1056 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
c9b22772 1057 reg = <0 0xe615026c 0 4>;
59e79895
LP		 1058 clocks = <&pll1_div2_clk>;
1059 #clock-cells = <0>;
2ea0d4ec 1060 clock-output-names = "sd3";
59e79895
LP		 1061 };
1062 mmc0_clk: mmc0_clk@e6150240 {
1063 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1064 reg = <0 0xe6150240 0 4>;
1065 clocks = <&pll1_div2_clk>;
1066 #clock-cells = <0>;
1067 clock-output-names = "mmc0";
1068 };
1069 ssp_clk: ssp_clk@e6150248 {
1070 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1071 reg = <0 0xe6150248 0 4>;
1072 clocks = <&pll1_div2_clk>;
1073 #clock-cells = <0>;
1074 clock-output-names = "ssp";
1075 };
1076 ssprs_clk: ssprs_clk@e615024c {
1077 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1078 reg = <0 0xe615024c 0 4>;
1079 clocks = <&pll1_div2_clk>;
1080 #clock-cells = <0>;
1081 clock-output-names = "ssprs";
1082 };
1083
1084 /* Fixed factor clocks */
1085 pll1_div2_clk: pll1_div2_clk {
1086 compatible = "fixed-factor-clock";
1087 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1088 #clock-cells = <0>;
1089 clock-div = <2>;
1090 clock-mult = <1>;
1091 clock-output-names = "pll1_div2";
1092 };
1093 zg_clk: zg_clk {
1094 compatible = "fixed-factor-clock";
1095 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1096 #clock-cells = <0>;
1097 clock-div = <3>;
1098 clock-mult = <1>;
1099 clock-output-names = "zg";
1100 };
1101 zx_clk: zx_clk {
1102 compatible = "fixed-factor-clock";
1103 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1104 #clock-cells = <0>;
1105 clock-div = <3>;
1106 clock-mult = <1>;
1107 clock-output-names = "zx";
1108 };
1109 zs_clk: zs_clk {
1110 compatible = "fixed-factor-clock";
1111 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1112 #clock-cells = <0>;
1113 clock-div = <6>;
1114 clock-mult = <1>;
1115 clock-output-names = "zs";
1116 };
1117 hp_clk: hp_clk {
1118 compatible = "fixed-factor-clock";
1119 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1120 #clock-cells = <0>;
1121 clock-div = <12>;
1122 clock-mult = <1>;
1123 clock-output-names = "hp";
1124 };
1125 i_clk: i_clk {
1126 compatible = "fixed-factor-clock";
1127 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1128 #clock-cells = <0>;
1129 clock-div = <2>;
1130 clock-mult = <1>;
1131 clock-output-names = "i";
1132 };
1133 b_clk: b_clk {
1134 compatible = "fixed-factor-clock";
1135 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1136 #clock-cells = <0>;
1137 clock-div = <12>;
1138 clock-mult = <1>;
1139 clock-output-names = "b";
1140 };
1141 p_clk: p_clk {
1142 compatible = "fixed-factor-clock";
1143 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1144 #clock-cells = <0>;
1145 clock-div = <24>;
1146 clock-mult = <1>;
1147 clock-output-names = "p";
1148 };
1149 cl_clk: cl_clk {
1150 compatible = "fixed-factor-clock";
1151 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1152 #clock-cells = <0>;
1153 clock-div = <48>;
1154 clock-mult = <1>;
1155 clock-output-names = "cl";
1156 };
1157 m2_clk: m2_clk {
1158 compatible = "fixed-factor-clock";
1159 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1160 #clock-cells = <0>;
1161 clock-div = <8>;
1162 clock-mult = <1>;
1163 clock-output-names = "m2";
1164 };
59e79895
LP		 1165 rclk_clk: rclk_clk {
1166 compatible = "fixed-factor-clock";
1167 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1168 #clock-cells = <0>;
1169 clock-div = <(48 * 1024)>;
1170 clock-mult = <1>;
1171 clock-output-names = "rclk";
1172 };
1173 oscclk_clk: oscclk_clk {
1174 compatible = "fixed-factor-clock";
1175 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1176 #clock-cells = <0>;
1177 clock-div = <(12 * 1024)>;
1178 clock-mult = <1>;
1179 clock-output-names = "oscclk";
1180 };
1181 zb3_clk: zb3_clk {
1182 compatible = "fixed-factor-clock";
1183 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1184 #clock-cells = <0>;
1185 clock-div = <4>;
1186 clock-mult = <1>;
1187 clock-output-names = "zb3";
1188 };
1189 zb3d2_clk: zb3d2_clk {
1190 compatible = "fixed-factor-clock";
1191 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1192 #clock-cells = <0>;
1193 clock-div = <8>;
1194 clock-mult = <1>;
1195 clock-output-names = "zb3d2";
1196 };
1197 ddr_clk: ddr_clk {
1198 compatible = "fixed-factor-clock";
1199 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1200 #clock-cells = <0>;
1201 clock-div = <8>;
1202 clock-mult = <1>;
1203 clock-output-names = "ddr";
1204 };
1205 mp_clk: mp_clk {
1206 compatible = "fixed-factor-clock";
1207 clocks = <&pll1_div2_clk>;
1208 #clock-cells = <0>;
1209 clock-div = <15>;
1210 clock-mult = <1>;
1211 clock-output-names = "mp";
1212 };
1213 cp_clk: cp_clk {
1214 compatible = "fixed-factor-clock";
1215 clocks = <&extal_clk>;
1216 #clock-cells = <0>;
1217 clock-div = <2>;
1218 clock-mult = <1>;
1219 clock-output-names = "cp";
1220 };
1221
1222 /* Gate clocks */
cded80f8
LP		 1223 mstp0_clks: mstp0_clks@e6150130 {
1224 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1225 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1226 clocks = <&mp_clk>;
1227 #clock-cells = <1>;
cb0bf851 1228 clock-indices = <R8A7791_CLK_MSIOF0>;
cded80f8
LP		 1229 clock-output-names = "msiof0";
1230 };
59e79895
LP		 1231 mstp1_clks: mstp1_clks@e6150134 {
1232 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1233 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
74d89d25
YH		 1234 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1235 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1236 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1237 <&zs_clk>;
59e79895 1238 #clock-cells = <1>;
cb0bf851 1239 clock-indices = <
74d89d25
YH		 1240 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1241 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1242 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1243 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1244 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1245 R8A7791_CLK_VSP1_S
59e79895
LP		 1246 >;
1247 clock-output-names =
74d89d25
YH		 1248 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1249 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1250 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
59e79895
LP		 1251 };
1252 mstp2_clks: mstp2_clks@e6150138 {
1253 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1254 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1255 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
4e074bc8
GU		 1256 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1257 <&zs_clk>, <&zs_clk>;
59e79895 1258 #clock-cells = <1>;
cb0bf851 1259 clock-indices = <
59e79895 1260 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
cded80f8
LP		 1261 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1262 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
4e074bc8 1263 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
59e79895
LP		 1264 >;
1265 clock-output-names =
0c002ef8 1266 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
4e074bc8
GU		 1267 "scifb1", "msiof1", "scifb2",
1268 "sys-dmac1", "sys-dmac0";
59e79895
LP		 1269 };
1270 mstp3_clks: mstp3_clks@e615013c {
1271 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1272 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
2ea0d4ec 1273 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
b9473d9f
YS		 1274 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1275 <&hp_clk>, <&hp_clk>;
59e79895 1276 #clock-cells = <1>;
cb0bf851 1277 clock-indices = <
c08691b5 1278 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
4bfb3767
PE		 1279 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1280 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
b9473d9f 1281 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
59e79895
LP		 1282 >;
1283 clock-output-names =
c08691b5 1284 "tpu0", "sdhi2", "sdhi1", "sdhi0",
b9473d9f
YS		 1285 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1286 "usbdmac0", "usbdmac1";
59e79895 1287 };
62d386c0
GU		 1288 mstp4_clks: mstp4_clks@e6150140 {
1289 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1290 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1291 clocks = <&cp_clk>;
1292 #clock-cells = <1>;
1293 clock-indices = <R8A7791_CLK_IRQC>;
1294 clock-output-names = "irqc";
1295 };
59e79895
LP		 1296 mstp5_clks: mstp5_clks@e6150144 {
1297 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1298 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
ae65a8ae
SS		 1299 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1300 <&extal_clk>, <&p_clk>;
59e79895 1301 #clock-cells = <1>;
cb0bf851
BD		 1302 clock-indices = <
1303 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
ae65a8ae
SS		 1304 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1305 R8A7791_CLK_PWM
cb0bf851 1306 >;
ae65a8ae
SS		 1307 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1308 "thermal", "pwm";
59e79895
LP		 1309 };
1310 mstp7_clks: mstp7_clks@e615014c {
1311 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1312 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
118e4e6a 1313 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
59e79895
LP		 1314 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1315 <&zx_clk>, <&zx_clk>, <&zx_clk>;
1316 #clock-cells = <1>;
cb0bf851 1317 clock-indices = <
6225b99a 1318 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
59e79895
LP		 1319 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1320 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1321 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1322 R8A7791_CLK_LVDS0
1323 >;
1324 clock-output-names =
6225b99a 1325 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
59e79895
LP		 1326 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1327 };
1328 mstp8_clks: mstp8_clks@e6150990 {
1329 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1330 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
75a499a6 1331 clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
7408d306 1332 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
59e79895 1333 #clock-cells = <1>;
cb0bf851 1334 clock-indices = <
7408d306 1335 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
09c98346 1336 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
65f05c38 1337 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
09c98346 1338 >;
65f05c38 1339 clock-output-names =
7408d306
AG		 1340 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether",
1341 "sata1", "sata0";
59e79895
LP		 1342 };
1343 mstp9_clks: mstp9_clks@e6150994 {
1344 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1345 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
4faf9c5e
GU		 1346 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1347 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1348 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
11b48db9
LP		 1349 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1350 <&hp_clk>, <&hp_clk>;
59e79895 1351 #clock-cells = <1>;
cb0bf851 1352 clock-indices = <
4faf9c5e
GU		 1353 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1354 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
c08691b5
WS		 1355 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1356 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1357 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
59e79895
LP		 1358 >;
1359 clock-output-names =
4faf9c5e
GU		 1360 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1361 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1362 "i2c1", "i2c0";
59e79895 1363 };
ee914152
KM		 1364 mstp10_clks: mstp10_clks@e6150998 {
1365 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1366 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1367 clocks = <&p_clk>,
1368 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1369 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1370 <&p_clk>,
1371 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1372 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1373 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1374 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1375 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
88401702 1376 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
ee914152
KM		 1377 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1378
1379 #clock-cells = <1>;
1380 clock-indices = <
1381 R8A7791_CLK_SSI_ALL
1382 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1383 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1384 R8A7791_CLK_SCU_ALL
1385 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
88401702 1386 R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
ee914152
KM		 1387 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1388 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1389 >;
1390 clock-output-names =
1391 "ssi-all",
1392 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1393 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1394 "scu-all",
1395 "scu-dvc1", "scu-dvc0",
88401702 1396 "scu-ctu1-mix1", "scu-ctu0-mix0",
ee914152
KM		 1397 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1398 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1399 };
59e79895
LP		 1400 mstp11_clks: mstp11_clks@e615099c {
1401 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1402 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1403 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1404 #clock-cells = <1>;
cb0bf851 1405 clock-indices = <
59e79895
LP		 1406 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1407 >;
1408 clock-output-names = "scifa3", "scifa4", "scifa5";
1409 };
1410 };
4d5b59cd 1411
6f3e4ee3 1412 qspi: spi@e6b10000 {
4d5b59cd
GU		 1413 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1414 reg = <0 0xe6b10000 0 0x2c>;
4d5b59cd
GU		 1415 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1416 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
591f2fa4
GU		 1417 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1418 dma-names = "tx", "rx";
797a0626 1419 power-domains = <&cpg_clocks>;
4d5b59cd
GU		 1420 num-cs = <1>;
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1423 status = "disabled";
1424 };
7713d3ab
GU		 1425
1426 msiof0: spi@e6e20000 {
1427 compatible = "renesas,msiof-r8a7791";
cb6d08a2 1428 reg = <0 0xe6e20000 0 0x0064>;
7713d3ab
GU		 1429 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1430 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
a5ce27f5
GU		 1431 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1432 dma-names = "tx", "rx";
797a0626 1433 power-domains = <&cpg_clocks>;
7713d3ab
GU		 1434 #address-cells = <1>;
1435 #size-cells = <0>;
1436 status = "disabled";
1437 };
1438
1439 msiof1: spi@e6e10000 {
1440 compatible = "renesas,msiof-r8a7791";
cb6d08a2 1441 reg = <0 0xe6e10000 0 0x0064>;
7713d3ab
GU		 1442 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1443 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
a5ce27f5
GU		 1444 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1445 dma-names = "tx", "rx";
797a0626 1446 power-domains = <&cpg_clocks>;
7713d3ab
GU		 1447 #address-cells = <1>;
1448 #size-cells = <0>;
1449 status = "disabled";
1450 };
1451
1452 msiof2: spi@e6e00000 {
1453 compatible = "renesas,msiof-r8a7791";
cb6d08a2 1454 reg = <0 0xe6e00000 0 0x0064>;
7713d3ab
GU		 1455 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1456 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
a5ce27f5
GU		 1457 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1458 dma-names = "tx", "rx";
797a0626 1459 power-domains = <&cpg_clocks>;
7713d3ab
GU		 1460 #address-cells = <1>;
1461 #size-cells = <0>;
1462 status = "disabled";
1463 };
811cdfae 1464
c196931e
YS		 1465 xhci: usb@ee000000 {
1466 compatible = "renesas,xhci-r8a7791";
1467 reg = <0 0xee000000 0 0xc00>;
1468 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1469 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
797a0626 1470 power-domains = <&cpg_clocks>;
c196931e
YS		 1471 phys = <&usb2 1>;
1472 phy-names = "usb";
1473 status = "disabled";
1474 };
1475
aace0809
SS		 1476 pci0: pci@ee090000 {
1477 compatible = "renesas,pci-r8a7791";
1478 device_type = "pci";
aace0809
SS		 1479 reg = <0 0xee090000 0 0xc00>,
1480 <0 0xee080000 0 0x1100>;
1481 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
797a0626
GU		 1482 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1483 power-domains = <&cpg_clocks>;
aace0809
SS		 1484 status = "disabled";
1485
1486 bus-range = <0 0>;
1487 #address-cells = <3>;
1488 #size-cells = <2>;
1489 #interrupt-cells = <1>;
1490 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1491 interrupt-map-mask = <0xff00 0 0 0x7>;
1492 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1493 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1494 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
e1bce124
SS		 1495
1496 usb@0,1 {
1497 reg = <0x800 0 0 0 0>;
1498 device_type = "pci";
1499 phys = <&usb0 0>;
1500 phy-names = "usb";
1501 };
1502
1503 usb@0,2 {
1504 reg = <0x1000 0 0 0 0>;
1505 device_type = "pci";
1506 phys = <&usb0 0>;
1507 phy-names = "usb";
1508 };
aace0809
SS		 1509 };
1510
1511 pci1: pci@ee0d0000 {
1512 compatible = "renesas,pci-r8a7791";
1513 device_type = "pci";
aace0809
SS		 1514 reg = <0 0xee0d0000 0 0xc00>,
1515 <0 0xee0c0000 0 0x1100>;
1516 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
797a0626
GU		 1517 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1518 power-domains = <&cpg_clocks>;
aace0809
SS		 1519 status = "disabled";
1520
1521 bus-range = <1 1>;
1522 #address-cells = <3>;
1523 #size-cells = <2>;
1524 #interrupt-cells = <1>;
1525 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1526 interrupt-map-mask = <0xff00 0 0 0x7>;
1527 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1528 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1529 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
e1bce124
SS		 1530
1531 usb@0,1 {
1532 reg = <0x800 0 0 0 0>;
1533 device_type = "pci";
1534 phys = <&usb2 0>;
1535 phy-names = "usb";
1536 };
1537
1538 usb@0,2 {
1539 reg = <0x1000 0 0 0 0>;
1540 device_type = "pci";
1541 phys = <&usb2 0>;
1542 phy-names = "usb";
1543 };
aace0809
SS		 1544 };
1545
811cdfae
PE		 1546 pciec: pcie@fe000000 {
1547 compatible = "renesas,pcie-r8a7791";
1548 reg = <0 0xfe000000 0 0x80000>;
1549 #address-cells = <3>;
1550 #size-cells = <2>;
1551 bus-range = <0x00 0xff>;
1552 device_type = "pci";
1553 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1554 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1555 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1556 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1557 /* Map all possible DDR as inbound ranges */
1558 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1559 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1560 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1561 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1562 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1563 #interrupt-cells = <1>;
1564 interrupt-map-mask = <0 0 0 0>;
1565 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1566 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1567 clock-names = "pcie", "pcie_bus";
797a0626 1568 power-domains = <&cpg_clocks>;
811cdfae
PE		 1569 status = "disabled";
1570 };
09abd1fd 1571
f1951852
LP		 1572 ipmmu_sy0: mmu@e6280000 {
1573 compatible = "renesas,ipmmu-vmsa";
1574 reg = <0 0xe6280000 0 0x1000>;
1575 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1576 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1577 #iommu-cells = <1>;
1578 status = "disabled";
1579 };
1580
1581 ipmmu_sy1: mmu@e6290000 {
1582 compatible = "renesas,ipmmu-vmsa";
1583 reg = <0 0xe6290000 0 0x1000>;
1584 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1585 #iommu-cells = <1>;
1586 status = "disabled";
1587 };
1588
1589 ipmmu_ds: mmu@e6740000 {
1590 compatible = "renesas,ipmmu-vmsa";
1591 reg = <0 0xe6740000 0 0x1000>;
1592 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1593 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1594 #iommu-cells = <1>;
1595 status = "disabled";
1596 };
1597
1598 ipmmu_mp: mmu@ec680000 {
1599 compatible = "renesas,ipmmu-vmsa";
1600 reg = <0 0xec680000 0 0x1000>;
1601 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1602 #iommu-cells = <1>;
1603 status = "disabled";
1604 };
1605
1606 ipmmu_mx: mmu@fe951000 {
1607 compatible = "renesas,ipmmu-vmsa";
1608 reg = <0 0xfe951000 0 0x1000>;
1609 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1610 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1611 #iommu-cells = <1>;
1612 status = "disabled";
1613 };
1614
1615 ipmmu_rt: mmu@ffc80000 {
1616 compatible = "renesas,ipmmu-vmsa";
1617 reg = <0 0xffc80000 0 0x1000>;
1618 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1619 #iommu-cells = <1>;
1620 status = "disabled";
1621 };
1622
1623 ipmmu_gp: mmu@e62a0000 {
1624 compatible = "renesas,ipmmu-vmsa";
1625 reg = <0 0xe62a0000 0 0x1000>;
1626 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
1627 <0 261 IRQ_TYPE_LEVEL_HIGH>;
1628 #iommu-cells = <1>;
1629 status = "disabled";
1630 };
1631
6c63e07d 1632 rcar_sound: sound@ec500000 {
d2b541c9
KM		 1633 /*
1634 * #sound-dai-cells is required
1635 *
1636 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1637 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1638 */
f49cd2b3 1639 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
09abd1fd
KM		 1640 reg = <0 0xec500000 0 0x1000>, /* SCU */
1641 <0 0xec5a0000 0 0x100>, /* ADG */
1642 <0 0xec540000 0 0x1000>, /* SSIU */
8c3f903b 1643 <0 0xec541000 0 0x280>, /* SSI */
d73a5013
KM		 1644 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1645 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
d88a6a2a 1646
09abd1fd
KM		 1647 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1648 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1649 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1650 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1651 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1652 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1653 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1654 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1655 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1656 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1657 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
88401702 1658 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
7fd6e11d 1659 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
150c8ad4 1660 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
09abd1fd
KM		 1661 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1662 clock-names = "ssi-all",
1663 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1664 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1665 "src.9", "src.8", "src.7", "src.6", "src.5",
1666 "src.4", "src.3", "src.2", "src.1", "src.0",
88401702 1667 "ctu.0", "ctu.1",
7fd6e11d 1668 "mix.0", "mix.1",
150c8ad4 1669 "dvc.0", "dvc.1",
09abd1fd 1670 "clk_a", "clk_b", "clk_c", "clk_i";
56e86dd4 1671 power-domains = <&cpg_clocks>;
09abd1fd
KM		 1672
1673 status = "disabled";
1674
150c8ad4 1675 rcar_sound,dvc {
63573339
KM		 1676 dvc0: dvc@0 {
1677 dmas = <&audma0 0xbc>;
1678 dma-names = "tx";
1679 };
1680 dvc1: dvc@1 {
1681 dmas = <&audma0 0xbe>;
1682 dma-names = "tx";
1683 };
150c8ad4
KM		 1684 };
1685
7fd6e11d
KM		 1686 rcar_sound,mix {
1687 mix0: mix@0 { };
1688 mix1: mix@1 { };
1689 };
1690
88401702
KM		 1691 rcar_sound,ctu {
1692 ctu00: ctu@0 { };
1693 ctu01: ctu@1 { };
1694 ctu02: ctu@2 { };
1695 ctu03: ctu@3 { };
1696 ctu10: ctu@4 { };
1697 ctu11: ctu@5 { };
1698 ctu12: ctu@6 { };
1699 ctu13: ctu@7 { };
1700 };
1701
09abd1fd 1702 rcar_sound,src {
63573339
KM		 1703 src0: src@0 {
1704 interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
1705 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1706 dma-names = "rx", "tx";
1707 };
1708 src1: src@1 {
1709 interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
1710 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1711 dma-names = "rx", "tx";
1712 };
1713 src2: src@2 {
1714 interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
1715 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1716 dma-names = "rx", "tx";
1717 };
1718 src3: src@3 {
1719 interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
1720 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1721 dma-names = "rx", "tx";
1722 };
1723 src4: src@4 {
1724 interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
1725 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1726 dma-names = "rx", "tx";
1727 };
1728 src5: src@5 {
1729 interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
1730 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1731 dma-names = "rx", "tx";
1732 };
1733 src6: src@6 {
1734 interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
1735 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1736 dma-names = "rx", "tx";
1737 };
1738 src7: src@7 {
1739 interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
1740 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1741 dma-names = "rx", "tx";
1742 };
1743 src8: src@8 {
1744 interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
1745 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1746 dma-names = "rx", "tx";
1747 };
1748 src9: src@9 {
1749 interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
1750 dmas = <&audma0 0x97>, <&audma1 0xba>;
1751 dma-names = "rx", "tx";
1752 };
09abd1fd
KM		 1753 };
1754
1755 rcar_sound,ssi {
63573339
KM		 1756 ssi0: ssi@0 {
1757 interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
1758 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1759 dma-names = "rx", "tx", "rxu", "txu";
1760 };
1761 ssi1: ssi@1 {
1762 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
1763 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1764 dma-names = "rx", "tx", "rxu", "txu";
1765 };
1766 ssi2: ssi@2 {
1767 interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
1768 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1769 dma-names = "rx", "tx", "rxu", "txu";
1770 };
1771 ssi3: ssi@3 {
1772 interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
1773 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1774 dma-names = "rx", "tx", "rxu", "txu";
1775 };
1776 ssi4: ssi@4 {
1777 interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
1778 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1779 dma-names = "rx", "tx", "rxu", "txu";
1780 };
1781 ssi5: ssi@5 {
1782 interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
1783 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1784 dma-names = "rx", "tx", "rxu", "txu";
1785 };
1786 ssi6: ssi@6 {
1787 interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
1788 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1789 dma-names = "rx", "tx", "rxu", "txu";
1790 };
1791 ssi7: ssi@7 {
1792 interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
1793 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1794 dma-names = "rx", "tx", "rxu", "txu";
1795 };
1796 ssi8: ssi@8 {
1797 interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
1798 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1799 dma-names = "rx", "tx", "rxu", "txu";
1800 };
1801 ssi9: ssi@9 {
1802 interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
1803 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1804 dma-names = "rx", "tx", "rxu", "txu";
1805 };
09abd1fd
KM		 1806 };
1807 };
0d0771ab 1808};
Linux kernel - Deliverables
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