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ARM: shmobile: r8a7790: Enable DMA for HSUSB
[deliverable/linux.git] / arch / arm / boot / dts / r8a7791.dtsi
CommitLineData
0d0771ab
HN		 1/*
2 * Device Tree Source for the r8a7791 SoC
3 *
118e4e6a 4 * Copyright (C) 2013-2015 Renesas Electronics Corporation
2e5d55ce
SS		 5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
0d0771ab
HN		 7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
59e79895 13#include <dt-bindings/clock/r8a7791-clock.h>
5f75e73c
LP		 14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
0d0771ab
HN		 17/ {
18 compatible = "renesas,r8a7791";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
5bd3de7b
WS		 23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &i2c4;
29 i2c5 = &i2c5;
36408d9d
WS		 30 i2c6 = &i2c6;
31 i2c7 = &i2c7;
32 i2c8 = &i2c8;
6f3e4ee3 33 spi0 = &qspi;
7713d3ab
GU		 34 spi1 = &msiof0;
35 spi2 = &msiof1;
36 spi3 = &msiof2;
0b8d1d57
SS		 37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
5bd3de7b
WS		 40 };
41
0d0771ab
HN		 42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 cpu0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a15";
49 reg = <0>;
896b79df 50 clock-frequency = <1500000000>;
a57004ec
GI		 51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7791_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
54
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1500000 1000000>,
57 <1312500 1000000>,
58 <1125000 1000000>,
59 < 937500 1000000>,
60 < 750000 1000000>,
61 < 375000 1000000>;
0d0771ab 62 };
15ab426c
MD		 63
64 cpu1: cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <1>;
896b79df 68 clock-frequency = <1500000000>;
15ab426c 69 };
0d0771ab
HN		 70 };
71
72 gic: interrupt-controller@f1001000 {
73 compatible = "arm,cortex-a15-gic";
74 #interrupt-cells = <3>;
75 #address-cells = <0>;
76 interrupt-controller;
77 reg = <0 0xf1001000 0 0x1000>,
78 <0 0xf1002000 0 0x1000>,
79 <0 0xf1004000 0 0x2000>,
80 <0 0xf1006000 0 0x2000>;
aa5404fc 81 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0d0771ab 82 };
d77db73e 83
89fbba12 84 gpio0: gpio@e6050000 {
ab87e3fc 85 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 86 reg = <0 0xe6050000 0 0x50>;
5f75e73c 87 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 88 #gpio-cells = <2>;
89 gpio-controller;
90 gpio-ranges = <&pfc 0 0 32>;
91 #interrupt-cells = <2>;
92 interrupt-controller;
4faf9c5e 93 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
ab87e3fc
MD		 94 };
95
89fbba12 96 gpio1: gpio@e6051000 {
ab87e3fc 97 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 98 reg = <0 0xe6051000 0 0x50>;
5f75e73c 99 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 100 #gpio-cells = <2>;
101 gpio-controller;
102 gpio-ranges = <&pfc 0 32 32>;
103 #interrupt-cells = <2>;
104 interrupt-controller;
4faf9c5e 105 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
ab87e3fc
MD		 106 };
107
89fbba12 108 gpio2: gpio@e6052000 {
ab87e3fc 109 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 110 reg = <0 0xe6052000 0 0x50>;
5f75e73c 111 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 112 #gpio-cells = <2>;
113 gpio-controller;
114 gpio-ranges = <&pfc 0 64 32>;
115 #interrupt-cells = <2>;
116 interrupt-controller;
4faf9c5e 117 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
ab87e3fc
MD		 118 };
119
89fbba12 120 gpio3: gpio@e6053000 {
ab87e3fc 121 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 122 reg = <0 0xe6053000 0 0x50>;
5f75e73c 123 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 124 #gpio-cells = <2>;
125 gpio-controller;
126 gpio-ranges = <&pfc 0 96 32>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
4faf9c5e 129 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
ab87e3fc
MD		 130 };
131
89fbba12 132 gpio4: gpio@e6054000 {
ab87e3fc 133 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 134 reg = <0 0xe6054000 0 0x50>;
5f75e73c 135 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 136 #gpio-cells = <2>;
137 gpio-controller;
138 gpio-ranges = <&pfc 0 128 32>;
139 #interrupt-cells = <2>;
140 interrupt-controller;
4faf9c5e 141 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
ab87e3fc
MD		 142 };
143
89fbba12 144 gpio5: gpio@e6055000 {
ab87e3fc 145 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 146 reg = <0 0xe6055000 0 0x50>;
5f75e73c 147 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 148 #gpio-cells = <2>;
149 gpio-controller;
150 gpio-ranges = <&pfc 0 160 32>;
151 #interrupt-cells = <2>;
152 interrupt-controller;
4faf9c5e 153 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
ab87e3fc
MD		 154 };
155
89fbba12 156 gpio6: gpio@e6055400 {
ab87e3fc 157 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 158 reg = <0 0xe6055400 0 0x50>;
5f75e73c 159 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 160 #gpio-cells = <2>;
161 gpio-controller;
162 gpio-ranges = <&pfc 0 192 32>;
163 #interrupt-cells = <2>;
164 interrupt-controller;
4faf9c5e 165 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
ab87e3fc
MD		 166 };
167
89fbba12 168 gpio7: gpio@e6055800 {
ab87e3fc 169 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 170 reg = <0 0xe6055800 0 0x50>;
5f75e73c 171 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 172 #gpio-cells = <2>;
173 gpio-controller;
174 gpio-ranges = <&pfc 0 224 26>;
175 #interrupt-cells = <2>;
176 interrupt-controller;
4faf9c5e 177 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
ab87e3fc
MD		 178 };
179
d103f4d3
MD		 180 thermal@e61f0000 {
181 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
182 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
d103f4d3 183 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
563bc8eb 184 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
d103f4d3
MD		 185 };
186
03586acf
MD		 187 timer {
188 compatible = "arm,armv7-timer";
aa5404fc
GU		 189 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
190 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
191 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
192 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
03586acf
MD		 193 };
194
ceaa1894 195 cmt0: timer@ffca0000 {
4217f323 196 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
ceaa1894
LP		 197 reg = <0 0xffca0000 0 0x1004>;
198 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
199 <0 143 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
201 clock-names = "fck";
202
203 renesas,channels-mask = <0x60>;
204
205 status = "disabled";
206 };
207
208 cmt1: timer@e6130000 {
4217f323 209 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
ceaa1894
LP		 210 reg = <0 0xe6130000 0 0x1004>;
211 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
212 <0 121 IRQ_TYPE_LEVEL_HIGH>,
213 <0 122 IRQ_TYPE_LEVEL_HIGH>,
214 <0 123 IRQ_TYPE_LEVEL_HIGH>,
215 <0 124 IRQ_TYPE_LEVEL_HIGH>,
216 <0 125 IRQ_TYPE_LEVEL_HIGH>,
217 <0 126 IRQ_TYPE_LEVEL_HIGH>,
218 <0 127 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
220 clock-names = "fck";
221
222 renesas,channels-mask = <0xff>;
223
224 status = "disabled";
225 };
226
d77db73e 227 irqc0: interrupt-controller@e61c0000 {
26041b06 228 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
d77db73e
MD		 229 #interrupt-cells = <2>;
230 interrupt-controller;
231 reg = <0 0xe61c0000 0 0x200>;
5f75e73c
LP		 232 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
233 <0 1 IRQ_TYPE_LEVEL_HIGH>,
234 <0 2 IRQ_TYPE_LEVEL_HIGH>,
235 <0 3 IRQ_TYPE_LEVEL_HIGH>,
236 <0 12 IRQ_TYPE_LEVEL_HIGH>,
237 <0 13 IRQ_TYPE_LEVEL_HIGH>,
238 <0 14 IRQ_TYPE_LEVEL_HIGH>,
239 <0 15 IRQ_TYPE_LEVEL_HIGH>,
240 <0 16 IRQ_TYPE_LEVEL_HIGH>,
241 <0 17 IRQ_TYPE_LEVEL_HIGH>;
62d386c0 242 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
d77db73e 243 };
55146927 244
fde8feef
LP		 245 dmac0: dma-controller@e6700000 {
246 compatible = "renesas,rcar-dmac";
247 reg = <0 0xe6700000 0 0x20000>;
248 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
249 0 200 IRQ_TYPE_LEVEL_HIGH
250 0 201 IRQ_TYPE_LEVEL_HIGH
251 0 202 IRQ_TYPE_LEVEL_HIGH
252 0 203 IRQ_TYPE_LEVEL_HIGH
253 0 204 IRQ_TYPE_LEVEL_HIGH
254 0 205 IRQ_TYPE_LEVEL_HIGH
255 0 206 IRQ_TYPE_LEVEL_HIGH
256 0 207 IRQ_TYPE_LEVEL_HIGH
257 0 208 IRQ_TYPE_LEVEL_HIGH
258 0 209 IRQ_TYPE_LEVEL_HIGH
259 0 210 IRQ_TYPE_LEVEL_HIGH
260 0 211 IRQ_TYPE_LEVEL_HIGH
261 0 212 IRQ_TYPE_LEVEL_HIGH
262 0 213 IRQ_TYPE_LEVEL_HIGH
263 0 214 IRQ_TYPE_LEVEL_HIGH>;
264 interrupt-names = "error",
265 "ch0", "ch1", "ch2", "ch3",
266 "ch4", "ch5", "ch6", "ch7",
267 "ch8", "ch9", "ch10", "ch11",
268 "ch12", "ch13", "ch14";
269 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
270 clock-names = "fck";
271 #dma-cells = <1>;
272 dma-channels = <15>;
273 };
274
275 dmac1: dma-controller@e6720000 {
276 compatible = "renesas,rcar-dmac";
277 reg = <0 0xe6720000 0 0x20000>;
278 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
279 0 216 IRQ_TYPE_LEVEL_HIGH
280 0 217 IRQ_TYPE_LEVEL_HIGH
281 0 218 IRQ_TYPE_LEVEL_HIGH
282 0 219 IRQ_TYPE_LEVEL_HIGH
283 0 308 IRQ_TYPE_LEVEL_HIGH
284 0 309 IRQ_TYPE_LEVEL_HIGH
285 0 310 IRQ_TYPE_LEVEL_HIGH
286 0 311 IRQ_TYPE_LEVEL_HIGH
287 0 312 IRQ_TYPE_LEVEL_HIGH
288 0 313 IRQ_TYPE_LEVEL_HIGH
289 0 314 IRQ_TYPE_LEVEL_HIGH
290 0 315 IRQ_TYPE_LEVEL_HIGH
291 0 316 IRQ_TYPE_LEVEL_HIGH
292 0 317 IRQ_TYPE_LEVEL_HIGH
293 0 318 IRQ_TYPE_LEVEL_HIGH>;
294 interrupt-names = "error",
295 "ch0", "ch1", "ch2", "ch3",
296 "ch4", "ch5", "ch6", "ch7",
297 "ch8", "ch9", "ch10", "ch11",
298 "ch12", "ch13", "ch14";
299 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
300 clock-names = "fck";
301 #dma-cells = <1>;
302 dma-channels = <15>;
303 };
304
8994fff6
KM		 305 audma0: dma-controller@ec700000 {
306 compatible = "renesas,rcar-dmac";
307 reg = <0 0xec700000 0 0x10000>;
308 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
309 0 320 IRQ_TYPE_LEVEL_HIGH
310 0 321 IRQ_TYPE_LEVEL_HIGH
311 0 322 IRQ_TYPE_LEVEL_HIGH
312 0 323 IRQ_TYPE_LEVEL_HIGH
313 0 324 IRQ_TYPE_LEVEL_HIGH
314 0 325 IRQ_TYPE_LEVEL_HIGH
315 0 326 IRQ_TYPE_LEVEL_HIGH
316 0 327 IRQ_TYPE_LEVEL_HIGH
317 0 328 IRQ_TYPE_LEVEL_HIGH
318 0 329 IRQ_TYPE_LEVEL_HIGH
319 0 330 IRQ_TYPE_LEVEL_HIGH
320 0 331 IRQ_TYPE_LEVEL_HIGH
321 0 332 IRQ_TYPE_LEVEL_HIGH>;
322 interrupt-names = "error",
323 "ch0", "ch1", "ch2", "ch3",
324 "ch4", "ch5", "ch6", "ch7",
325 "ch8", "ch9", "ch10", "ch11",
326 "ch12";
327 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
328 clock-names = "fck";
329 #dma-cells = <1>;
330 dma-channels = <13>;
331 };
332
333 audma1: dma-controller@ec720000 {
334 compatible = "renesas,rcar-dmac";
335 reg = <0 0xec720000 0 0x10000>;
336 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
337 0 333 IRQ_TYPE_LEVEL_HIGH
338 0 334 IRQ_TYPE_LEVEL_HIGH
339 0 335 IRQ_TYPE_LEVEL_HIGH
340 0 336 IRQ_TYPE_LEVEL_HIGH
341 0 337 IRQ_TYPE_LEVEL_HIGH
342 0 338 IRQ_TYPE_LEVEL_HIGH
343 0 339 IRQ_TYPE_LEVEL_HIGH
344 0 340 IRQ_TYPE_LEVEL_HIGH
345 0 341 IRQ_TYPE_LEVEL_HIGH
346 0 342 IRQ_TYPE_LEVEL_HIGH
347 0 343 IRQ_TYPE_LEVEL_HIGH
348 0 344 IRQ_TYPE_LEVEL_HIGH
349 0 345 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "error",
351 "ch0", "ch1", "ch2", "ch3",
352 "ch4", "ch5", "ch6", "ch7",
353 "ch8", "ch9", "ch10", "ch11",
354 "ch12";
355 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
356 clock-names = "fck";
357 #dma-cells = <1>;
358 dma-channels = <13>;
359 };
360
36408d9d 361 /* The memory map in the User's Manual maps the cores to bus numbers */
5bd3de7b
WS		 362 i2c0: i2c@e6508000 {
363 #address-cells = <1>;
364 #size-cells = <0>;
365 compatible = "renesas,i2c-r8a7791";
366 reg = <0 0xe6508000 0 0x40>;
367 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
369 status = "disabled";
370 };
371
372 i2c1: i2c@e6518000 {
373 #address-cells = <1>;
374 #size-cells = <0>;
375 compatible = "renesas,i2c-r8a7791";
376 reg = <0 0xe6518000 0 0x40>;
377 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
379 status = "disabled";
380 };
381
382 i2c2: i2c@e6530000 {
383 #address-cells = <1>;
384 #size-cells = <0>;
385 compatible = "renesas,i2c-r8a7791";
386 reg = <0 0xe6530000 0 0x40>;
387 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
389 status = "disabled";
390 };
391
392 i2c3: i2c@e6540000 {
393 #address-cells = <1>;
394 #size-cells = <0>;
395 compatible = "renesas,i2c-r8a7791";
396 reg = <0 0xe6540000 0 0x40>;
397 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
399 status = "disabled";
400 };
401
402 i2c4: i2c@e6520000 {
403 #address-cells = <1>;
404 #size-cells = <0>;
405 compatible = "renesas,i2c-r8a7791";
406 reg = <0 0xe6520000 0 0x40>;
407 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
409 status = "disabled";
410 };
411
412 i2c5: i2c@e6528000 {
36408d9d 413 /* doesn't need pinmux */
5bd3de7b
WS		 414 #address-cells = <1>;
415 #size-cells = <0>;
416 compatible = "renesas,i2c-r8a7791";
417 reg = <0 0xe6528000 0 0x40>;
418 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
420 status = "disabled";
421 };
422
36408d9d
WS		 423 i2c6: i2c@e60b0000 {
424 /* doesn't need pinmux */
425 #address-cells = <1>;
426 #size-cells = <0>;
427 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
428 reg = <0 0xe60b0000 0 0x425>;
429 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
3f58c54b
WS		 431 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
432 dma-names = "tx", "rx";
36408d9d
WS		 433 status = "disabled";
434 };
435
436 i2c7: i2c@e6500000 {
437 #address-cells = <1>;
438 #size-cells = <0>;
439 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
440 reg = <0 0xe6500000 0 0x425>;
441 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
3f58c54b
WS		 443 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
444 dma-names = "tx", "rx";
36408d9d
WS		 445 status = "disabled";
446 };
447
448 i2c8: i2c@e6510000 {
449 #address-cells = <1>;
450 #size-cells = <0>;
451 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
452 reg = <0 0xe6510000 0 0x425>;
453 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
3f58c54b
WS		 455 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
456 dma-names = "tx", "rx";
36408d9d
WS		 457 status = "disabled";
458 };
459
55146927
MD		 460 pfc: pfc@e6060000 {
461 compatible = "renesas,pfc-r8a7791";
462 reg = <0 0xe6060000 0 0x250>;
463 #gpio-range-cells = <3>;
464 };
59e79895 465
8edae499
LP		 466 mmcif0: mmc@ee200000 {
467 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
468 reg = <0 0xee200000 0 0x80>;
469 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
16b355b4
LP		 471 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
472 dma-names = "tx", "rx";
8edae499
LP		 473 reg-io-width = <4>;
474 status = "disabled";
475 };
476
b7ed8a0d
MD		 477 sdhi0: sd@ee100000 {
478 compatible = "renesas,sdhi-r8a7791";
e849b065 479 reg = <0 0xee100000 0 0x328>;
b7ed8a0d
MD		 480 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
ae67fa2f
LP		 482 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
483 dma-names = "tx", "rx";
b7ed8a0d
MD		 484 status = "disabled";
485 };
486
487 sdhi1: sd@ee140000 {
488 compatible = "renesas,sdhi-r8a7791";
489 reg = <0 0xee140000 0 0x100>;
b7ed8a0d
MD		 490 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
ae67fa2f
LP		 492 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
493 dma-names = "tx", "rx";
b7ed8a0d
MD		 494 status = "disabled";
495 };
496
497 sdhi2: sd@ee160000 {
498 compatible = "renesas,sdhi-r8a7791";
499 reg = <0 0xee160000 0 0x100>;
b7ed8a0d
MD		 500 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
ae67fa2f
LP		 502 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
503 dma-names = "tx", "rx";
b7ed8a0d
MD		 504 status = "disabled";
505 };
506
9640cf25
LP		 507 scifa0: serial@e6c40000 {
508 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
509 reg = <0 0xe6c40000 0 64>;
9640cf25
LP		 510 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
512 clock-names = "sci_ick";
513 status = "disabled";
514 };
515
516 scifa1: serial@e6c50000 {
517 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 518 reg = <0 0xe6c50000 0 64>;
519 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
521 clock-names = "sci_ick";
522 status = "disabled";
523 };
524
525 scifa2: serial@e6c60000 {
526 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 527 reg = <0 0xe6c60000 0 64>;
528 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
530 clock-names = "sci_ick";
531 status = "disabled";
532 };
533
534 scifa3: serial@e6c70000 {
535 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 536 reg = <0 0xe6c70000 0 64>;
537 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
539 clock-names = "sci_ick";
540 status = "disabled";
541 };
542
543 scifa4: serial@e6c78000 {
544 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 545 reg = <0 0xe6c78000 0 64>;
546 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
548 clock-names = "sci_ick";
549 status = "disabled";
550 };
551
552 scifa5: serial@e6c80000 {
553 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 554 reg = <0 0xe6c80000 0 64>;
555 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
557 clock-names = "sci_ick";
558 status = "disabled";
559 };
560
561 scifb0: serial@e6c20000 {
562 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
9640cf25
LP		 563 reg = <0 0xe6c20000 0 64>;
564 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
566 clock-names = "sci_ick";
567 status = "disabled";
568 };
569
570 scifb1: serial@e6c30000 {
571 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
9640cf25
LP		 572 reg = <0 0xe6c30000 0 64>;
573 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
575 clock-names = "sci_ick";
576 status = "disabled";
577 };
578
579 scifb2: serial@e6ce0000 {
580 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
9640cf25
LP		 581 reg = <0 0xe6ce0000 0 64>;
582 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
584 clock-names = "sci_ick";
585 status = "disabled";
586 };
587
588 scif0: serial@e6e60000 {
589 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 590 reg = <0 0xe6e60000 0 64>;
591 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
593 clock-names = "sci_ick";
594 status = "disabled";
595 };
596
597 scif1: serial@e6e68000 {
598 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 599 reg = <0 0xe6e68000 0 64>;
600 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
602 clock-names = "sci_ick";
603 status = "disabled";
604 };
605
606 scif2: serial@e6e58000 {
607 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 608 reg = <0 0xe6e58000 0 64>;
609 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
611 clock-names = "sci_ick";
612 status = "disabled";
613 };
614
615 scif3: serial@e6ea8000 {
616 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 617 reg = <0 0xe6ea8000 0 64>;
618 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
620 clock-names = "sci_ick";
621 status = "disabled";
622 };
623
624 scif4: serial@e6ee0000 {
625 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 626 reg = <0 0xe6ee0000 0 64>;
627 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
629 clock-names = "sci_ick";
630 status = "disabled";
631 };
632
633 scif5: serial@e6ee8000 {
634 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 635 reg = <0 0xe6ee8000 0 64>;
636 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
638 clock-names = "sci_ick";
639 status = "disabled";
640 };
641
642 hscif0: serial@e62c0000 {
643 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
9640cf25
LP		 644 reg = <0 0xe62c0000 0 96>;
645 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
647 clock-names = "sci_ick";
648 status = "disabled";
649 };
650
651 hscif1: serial@e62c8000 {
652 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
9640cf25
LP		 653 reg = <0 0xe62c8000 0 96>;
654 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
656 clock-names = "sci_ick";
657 status = "disabled";
658 };
659
660 hscif2: serial@e62d0000 {
661 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
9640cf25
LP		 662 reg = <0 0xe62d0000 0 96>;
663 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
665 clock-names = "sci_ick";
666 status = "disabled";
667 };
668
2e5d55ce
SS		 669 ether: ethernet@ee700000 {
670 compatible = "renesas,ether-r8a7791";
671 reg = <0 0xee700000 0 0x400>;
672 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
674 phy-mode = "rmii";
675 #address-cells = <1>;
676 #size-cells = <0>;
677 status = "disabled";
678 };
679
b8532c69
VB		 680 sata0: sata@ee300000 {
681 compatible = "renesas,sata-r8a7791";
682 reg = <0 0xee300000 0 0x2000>;
b8532c69
VB		 683 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
685 status = "disabled";
686 };
687
688 sata1: sata@ee500000 {
689 compatible = "renesas,sata-r8a7791";
690 reg = <0 0xee500000 0 0x2000>;
b8532c69
VB		 691 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
693 status = "disabled";
694 };
695
1c1fee7c
YS		 696 hsusb: usb@e6590000 {
697 compatible = "renesas,usbhs-r8a7791";
698 reg = <0 0xe6590000 0 0x100>;
699 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
701 renesas,buswait = <4>;
702 phys = <&usb0 1>;
703 phy-names = "usb";
704 status = "disabled";
705 };
706
3b7e530d
SS		 707 usbphy: usb-phy@e6590100 {
708 compatible = "renesas,usb-phy-r8a7791";
709 reg = <0 0xe6590100 0 0x100>;
710 #address-cells = <1>;
711 #size-cells = <0>;
712 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
713 clock-names = "usbhs";
714 status = "disabled";
715
716 usb0: usb-channel@0 {
717 reg = <0>;
718 #phy-cells = <1>;
719 };
720 usb2: usb-channel@2 {
721 reg = <2>;
722 #phy-cells = <1>;
723 };
724 };
725
0b8d1d57
SS		 726 vin0: video@e6ef0000 {
727 compatible = "renesas,vin-r8a7791";
728 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
729 reg = <0 0xe6ef0000 0 0x1000>;
730 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
731 status = "disabled";
732 };
733
734 vin1: video@e6ef1000 {
735 compatible = "renesas,vin-r8a7791";
736 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
737 reg = <0 0xe6ef1000 0 0x1000>;
738 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
739 status = "disabled";
740 };
741
742 vin2: video@e6ef2000 {
743 compatible = "renesas,vin-r8a7791";
744 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
745 reg = <0 0xe6ef2000 0 0x1000>;
746 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
747 status = "disabled";
748 };
749
8eefac2d
LP		 750 vsp1@fe928000 {
751 compatible = "renesas,vsp1";
752 reg = <0 0xfe928000 0 0x8000>;
753 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
755
756 renesas,has-lut;
757 renesas,has-sru;
758 renesas,#rpf = <5>;
759 renesas,#uds = <3>;
760 renesas,#wpf = <4>;
761 };
762
763 vsp1@fe930000 {
764 compatible = "renesas,vsp1";
765 reg = <0 0xfe930000 0 0x8000>;
766 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
768
769 renesas,has-lif;
770 renesas,has-lut;
771 renesas,#rpf = <4>;
772 renesas,#uds = <1>;
773 renesas,#wpf = <4>;
774 };
775
776 vsp1@fe938000 {
777 compatible = "renesas,vsp1";
778 reg = <0 0xfe938000 0 0x8000>;
779 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
781
782 renesas,has-lif;
783 renesas,has-lut;
784 renesas,#rpf = <4>;
785 renesas,#uds = <1>;
786 renesas,#wpf = <4>;
787 };
788
789 du: display@feb00000 {
790 compatible = "renesas,du-r8a7791";
791 reg = <0 0xfeb00000 0 0x40000>,
792 <0 0xfeb90000 0 0x1c>;
793 reg-names = "du", "lvds.0";
794 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
795 <0 268 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
797 <&mstp7_clks R8A7791_CLK_DU1>,
798 <&mstp7_clks R8A7791_CLK_LVDS0>;
799 clock-names = "du.0", "du.1", "lvds.0";
800 status = "disabled";
801
802 ports {
803 #address-cells = <1>;
804 #size-cells = <0>;
805
806 port@0 {
807 reg = <0>;
808 du_out_rgb: endpoint {
809 };
810 };
811 port@1 {
812 reg = <1>;
813 du_out_lvds0: endpoint {
814 };
815 };
816 };
817 };
818
3cf01884
SS		 819 can0: can@e6e80000 {
820 compatible = "renesas,can-r8a7791";
821 reg = <0 0xe6e80000 0 0x1000>;
822 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
824 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
825 clock-names = "clkp1", "clkp2", "can_clk";
826 status = "disabled";
827 };
828
829 can1: can@e6e88000 {
830 compatible = "renesas,can-r8a7791";
831 reg = <0 0xe6e88000 0 0x1000>;
832 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
834 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
835 clock-names = "clkp1", "clkp2", "can_clk";
836 status = "disabled";
837 };
838
59e79895
LP		 839 clocks {
840 #address-cells = <2>;
841 #size-cells = <2>;
842 ranges;
843
844 /* External root clock */
845 extal_clk: extal_clk {
846 compatible = "fixed-clock";
847 #clock-cells = <0>;
848 /* This value must be overriden by the board. */
849 clock-frequency = <0>;
850 clock-output-names = "extal";
851 };
852
0d3dbde8
KM		 853 /*
854 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
855 * default. Boards that provide audio clocks should override them.
856 */
857 audio_clk_a: audio_clk_a {
858 compatible = "fixed-clock";
859 #clock-cells = <0>;
860 clock-frequency = <0>;
861 clock-output-names = "audio_clk_a";
862 };
863 audio_clk_b: audio_clk_b {
864 compatible = "fixed-clock";
865 #clock-cells = <0>;
866 clock-frequency = <0>;
867 clock-output-names = "audio_clk_b";
868 };
869 audio_clk_c: audio_clk_c {
870 compatible = "fixed-clock";
871 #clock-cells = <0>;
872 clock-frequency = <0>;
873 clock-output-names = "audio_clk_c";
874 };
875
66c405e7
PE		 876 /* External PCIe clock - can be overridden by the board */
877 pcie_bus_clk: pcie_bus_clk {
878 compatible = "fixed-clock";
879 #clock-cells = <0>;
880 clock-frequency = <100000000>;
881 clock-output-names = "pcie_bus";
882 status = "disabled";
883 };
884
b324252c
SS		 885 /* External USB clock - can be overridden by the board */
886 usb_extal_clk: usb_extal_clk {
887 compatible = "fixed-clock";
888 #clock-cells = <0>;
889 clock-frequency = <48000000>;
890 clock-output-names = "usb_extal";
891 };
892
893 /* External CAN clock */
894 can_clk: can_clk {
895 compatible = "fixed-clock";
896 #clock-cells = <0>;
897 /* This value must be overridden by the board. */
898 clock-frequency = <0>;
899 clock-output-names = "can_clk";
900 status = "disabled";
901 };
902
59e79895
LP		 903 /* Special CPG clocks */
904 cpg_clocks: cpg_clocks@e6150000 {
905 compatible = "renesas,r8a7791-cpg-clocks",
906 "renesas,rcar-gen2-cpg-clocks";
907 reg = <0 0xe6150000 0 0x1000>;
b324252c 908 clocks = <&extal_clk &usb_extal_clk>;
59e79895
LP		 909 #clock-cells = <1>;
910 clock-output-names = "main", "pll0", "pll1", "pll3",
b324252c 911 "lb", "qspi", "sdh", "sd0", "z",
ae65a8ae 912 "rcan", "adsp";
59e79895
LP		 913 };
914
915 /* Variable factor clocks */
2ea0d4ec 916 sd2_clk: sd2_clk@e6150078 {
59e79895
LP		 917 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
918 reg = <0 0xe6150078 0 4>;
919 clocks = <&pll1_div2_clk>;
920 #clock-cells = <0>;
2ea0d4ec 921 clock-output-names = "sd2";
59e79895 922 };
2ea0d4ec 923 sd3_clk: sd3_clk@e615026c {
59e79895 924 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
c9b22772 925 reg = <0 0xe615026c 0 4>;
59e79895
LP		 926 clocks = <&pll1_div2_clk>;
927 #clock-cells = <0>;
2ea0d4ec 928 clock-output-names = "sd3";
59e79895
LP		 929 };
930 mmc0_clk: mmc0_clk@e6150240 {
931 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
932 reg = <0 0xe6150240 0 4>;
933 clocks = <&pll1_div2_clk>;
934 #clock-cells = <0>;
935 clock-output-names = "mmc0";
936 };
937 ssp_clk: ssp_clk@e6150248 {
938 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
939 reg = <0 0xe6150248 0 4>;
940 clocks = <&pll1_div2_clk>;
941 #clock-cells = <0>;
942 clock-output-names = "ssp";
943 };
944 ssprs_clk: ssprs_clk@e615024c {
945 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
946 reg = <0 0xe615024c 0 4>;
947 clocks = <&pll1_div2_clk>;
948 #clock-cells = <0>;
949 clock-output-names = "ssprs";
950 };
951
952 /* Fixed factor clocks */
953 pll1_div2_clk: pll1_div2_clk {
954 compatible = "fixed-factor-clock";
955 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
956 #clock-cells = <0>;
957 clock-div = <2>;
958 clock-mult = <1>;
959 clock-output-names = "pll1_div2";
960 };
961 zg_clk: zg_clk {
962 compatible = "fixed-factor-clock";
963 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
964 #clock-cells = <0>;
965 clock-div = <3>;
966 clock-mult = <1>;
967 clock-output-names = "zg";
968 };
969 zx_clk: zx_clk {
970 compatible = "fixed-factor-clock";
971 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
972 #clock-cells = <0>;
973 clock-div = <3>;
974 clock-mult = <1>;
975 clock-output-names = "zx";
976 };
977 zs_clk: zs_clk {
978 compatible = "fixed-factor-clock";
979 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
980 #clock-cells = <0>;
981 clock-div = <6>;
982 clock-mult = <1>;
983 clock-output-names = "zs";
984 };
985 hp_clk: hp_clk {
986 compatible = "fixed-factor-clock";
987 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
988 #clock-cells = <0>;
989 clock-div = <12>;
990 clock-mult = <1>;
991 clock-output-names = "hp";
992 };
993 i_clk: i_clk {
994 compatible = "fixed-factor-clock";
995 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
996 #clock-cells = <0>;
997 clock-div = <2>;
998 clock-mult = <1>;
999 clock-output-names = "i";
1000 };
1001 b_clk: b_clk {
1002 compatible = "fixed-factor-clock";
1003 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1004 #clock-cells = <0>;
1005 clock-div = <12>;
1006 clock-mult = <1>;
1007 clock-output-names = "b";
1008 };
1009 p_clk: p_clk {
1010 compatible = "fixed-factor-clock";
1011 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1012 #clock-cells = <0>;
1013 clock-div = <24>;
1014 clock-mult = <1>;
1015 clock-output-names = "p";
1016 };
1017 cl_clk: cl_clk {
1018 compatible = "fixed-factor-clock";
1019 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1020 #clock-cells = <0>;
1021 clock-div = <48>;
1022 clock-mult = <1>;
1023 clock-output-names = "cl";
1024 };
1025 m2_clk: m2_clk {
1026 compatible = "fixed-factor-clock";
1027 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1028 #clock-cells = <0>;
1029 clock-div = <8>;
1030 clock-mult = <1>;
1031 clock-output-names = "m2";
1032 };
1033 imp_clk: imp_clk {
1034 compatible = "fixed-factor-clock";
1035 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1036 #clock-cells = <0>;
1037 clock-div = <4>;
1038 clock-mult = <1>;
1039 clock-output-names = "imp";
1040 };
1041 rclk_clk: rclk_clk {
1042 compatible = "fixed-factor-clock";
1043 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1044 #clock-cells = <0>;
1045 clock-div = <(48 * 1024)>;
1046 clock-mult = <1>;
1047 clock-output-names = "rclk";
1048 };
1049 oscclk_clk: oscclk_clk {
1050 compatible = "fixed-factor-clock";
1051 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1052 #clock-cells = <0>;
1053 clock-div = <(12 * 1024)>;
1054 clock-mult = <1>;
1055 clock-output-names = "oscclk";
1056 };
1057 zb3_clk: zb3_clk {
1058 compatible = "fixed-factor-clock";
1059 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1060 #clock-cells = <0>;
1061 clock-div = <4>;
1062 clock-mult = <1>;
1063 clock-output-names = "zb3";
1064 };
1065 zb3d2_clk: zb3d2_clk {
1066 compatible = "fixed-factor-clock";
1067 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1068 #clock-cells = <0>;
1069 clock-div = <8>;
1070 clock-mult = <1>;
1071 clock-output-names = "zb3d2";
1072 };
1073 ddr_clk: ddr_clk {
1074 compatible = "fixed-factor-clock";
1075 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1076 #clock-cells = <0>;
1077 clock-div = <8>;
1078 clock-mult = <1>;
1079 clock-output-names = "ddr";
1080 };
1081 mp_clk: mp_clk {
1082 compatible = "fixed-factor-clock";
1083 clocks = <&pll1_div2_clk>;
1084 #clock-cells = <0>;
1085 clock-div = <15>;
1086 clock-mult = <1>;
1087 clock-output-names = "mp";
1088 };
1089 cp_clk: cp_clk {
1090 compatible = "fixed-factor-clock";
1091 clocks = <&extal_clk>;
1092 #clock-cells = <0>;
1093 clock-div = <2>;
1094 clock-mult = <1>;
1095 clock-output-names = "cp";
1096 };
1097
1098 /* Gate clocks */
cded80f8
LP		 1099 mstp0_clks: mstp0_clks@e6150130 {
1100 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1101 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1102 clocks = <&mp_clk>;
1103 #clock-cells = <1>;
cb0bf851 1104 clock-indices = <R8A7791_CLK_MSIOF0>;
cded80f8
LP		 1105 clock-output-names = "msiof0";
1106 };
59e79895
LP		 1107 mstp1_clks: mstp1_clks@e6150134 {
1108 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1109 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
74d89d25
YH		 1110 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1111 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1112 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1113 <&zs_clk>;
59e79895 1114 #clock-cells = <1>;
cb0bf851 1115 clock-indices = <
74d89d25
YH		 1116 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1117 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1118 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1119 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1120 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1121 R8A7791_CLK_VSP1_S
59e79895
LP		 1122 >;
1123 clock-output-names =
74d89d25
YH		 1124 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1125 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1126 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
59e79895
LP		 1127 };
1128 mstp2_clks: mstp2_clks@e6150138 {
1129 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1130 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1131 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
4e074bc8
GU		 1132 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1133 <&zs_clk>, <&zs_clk>;
59e79895 1134 #clock-cells = <1>;
cb0bf851 1135 clock-indices = <
59e79895 1136 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
cded80f8
LP		 1137 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1138 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
4e074bc8 1139 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
59e79895
LP		 1140 >;
1141 clock-output-names =
0c002ef8 1142 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
4e074bc8
GU		 1143 "scifb1", "msiof1", "scifb2",
1144 "sys-dmac1", "sys-dmac0";
59e79895
LP		 1145 };
1146 mstp3_clks: mstp3_clks@e615013c {
1147 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1148 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
2ea0d4ec 1149 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
b9473d9f
YS		 1150 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1151 <&hp_clk>, <&hp_clk>;
59e79895 1152 #clock-cells = <1>;
cb0bf851 1153 clock-indices = <
c08691b5 1154 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
4bfb3767
PE		 1155 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1156 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
b9473d9f 1157 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
59e79895
LP		 1158 >;
1159 clock-output-names =
c08691b5 1160 "tpu0", "sdhi2", "sdhi1", "sdhi0",
b9473d9f
YS		 1161 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1162 "usbdmac0", "usbdmac1";
59e79895 1163 };
62d386c0
GU		 1164 mstp4_clks: mstp4_clks@e6150140 {
1165 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1166 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1167 clocks = <&cp_clk>;
1168 #clock-cells = <1>;
1169 clock-indices = <R8A7791_CLK_IRQC>;
1170 clock-output-names = "irqc";
1171 };
59e79895
LP		 1172 mstp5_clks: mstp5_clks@e6150144 {
1173 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1174 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
ae65a8ae
SS		 1175 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1176 <&extal_clk>, <&p_clk>;
59e79895 1177 #clock-cells = <1>;
cb0bf851
BD		 1178 clock-indices = <
1179 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
ae65a8ae
SS		 1180 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1181 R8A7791_CLK_PWM
cb0bf851 1182 >;
ae65a8ae
SS		 1183 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1184 "thermal", "pwm";
59e79895
LP		 1185 };
1186 mstp7_clks: mstp7_clks@e615014c {
1187 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1188 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
118e4e6a 1189 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
59e79895
LP		 1190 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1191 <&zx_clk>, <&zx_clk>, <&zx_clk>;
1192 #clock-cells = <1>;
cb0bf851 1193 clock-indices = <
6225b99a 1194 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
59e79895
LP		 1195 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1196 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1197 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1198 R8A7791_CLK_LVDS0
1199 >;
1200 clock-output-names =
6225b99a 1201 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
59e79895
LP		 1202 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1203 };
1204 mstp8_clks: mstp8_clks@e6150990 {
1205 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1206 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
75a499a6 1207 clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
7408d306 1208 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
59e79895 1209 #clock-cells = <1>;
cb0bf851 1210 clock-indices = <
7408d306 1211 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
09c98346 1212 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
65f05c38 1213 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
09c98346 1214 >;
65f05c38 1215 clock-output-names =
7408d306
AG		 1216 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether",
1217 "sata1", "sata0";
59e79895
LP		 1218 };
1219 mstp9_clks: mstp9_clks@e6150994 {
1220 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1221 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
4faf9c5e
GU		 1222 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1223 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1224 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
11b48db9
LP		 1225 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1226 <&hp_clk>, <&hp_clk>;
59e79895 1227 #clock-cells = <1>;
cb0bf851 1228 clock-indices = <
4faf9c5e
GU		 1229 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1230 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
c08691b5
WS		 1231 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1232 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1233 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
59e79895
LP		 1234 >;
1235 clock-output-names =
4faf9c5e
GU		 1236 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1237 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1238 "i2c1", "i2c0";
59e79895 1239 };
ee914152
KM		 1240 mstp10_clks: mstp10_clks@e6150998 {
1241 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1242 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1243 clocks = <&p_clk>,
1244 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1245 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1246 <&p_clk>,
1247 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1248 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1249 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1250 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1251 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1252 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1253
1254 #clock-cells = <1>;
1255 clock-indices = <
1256 R8A7791_CLK_SSI_ALL
1257 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1258 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1259 R8A7791_CLK_SCU_ALL
1260 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1261 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1262 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1263 >;
1264 clock-output-names =
1265 "ssi-all",
1266 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1267 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1268 "scu-all",
1269 "scu-dvc1", "scu-dvc0",
1270 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1271 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1272 };
59e79895
LP		 1273 mstp11_clks: mstp11_clks@e615099c {
1274 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1275 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1276 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1277 #clock-cells = <1>;
cb0bf851 1278 clock-indices = <
59e79895
LP		 1279 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1280 >;
1281 clock-output-names = "scifa3", "scifa4", "scifa5";
1282 };
1283 };
4d5b59cd 1284
6f3e4ee3 1285 qspi: spi@e6b10000 {
4d5b59cd
GU		 1286 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1287 reg = <0 0xe6b10000 0 0x2c>;
4d5b59cd
GU		 1288 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1289 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
591f2fa4
GU		 1290 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1291 dma-names = "tx", "rx";
4d5b59cd
GU		 1292 num-cs = <1>;
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1295 status = "disabled";
1296 };
7713d3ab
GU		 1297
1298 msiof0: spi@e6e20000 {
1299 compatible = "renesas,msiof-r8a7791";
cb6d08a2 1300 reg = <0 0xe6e20000 0 0x0064>;
7713d3ab
GU		 1301 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1302 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
a5ce27f5
GU		 1303 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1304 dma-names = "tx", "rx";
7713d3ab
GU		 1305 #address-cells = <1>;
1306 #size-cells = <0>;
1307 status = "disabled";
1308 };
1309
1310 msiof1: spi@e6e10000 {
1311 compatible = "renesas,msiof-r8a7791";
cb6d08a2 1312 reg = <0 0xe6e10000 0 0x0064>;
7713d3ab
GU		 1313 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1314 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
a5ce27f5
GU		 1315 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1316 dma-names = "tx", "rx";
7713d3ab
GU		 1317 #address-cells = <1>;
1318 #size-cells = <0>;
1319 status = "disabled";
1320 };
1321
1322 msiof2: spi@e6e00000 {
1323 compatible = "renesas,msiof-r8a7791";
cb6d08a2 1324 reg = <0 0xe6e00000 0 0x0064>;
7713d3ab
GU		 1325 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1326 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
a5ce27f5
GU		 1327 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1328 dma-names = "tx", "rx";
7713d3ab
GU		 1329 #address-cells = <1>;
1330 #size-cells = <0>;
1331 status = "disabled";
1332 };
811cdfae 1333
c196931e
YS		 1334 xhci: usb@ee000000 {
1335 compatible = "renesas,xhci-r8a7791";
1336 reg = <0 0xee000000 0 0xc00>;
1337 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1338 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1339 phys = <&usb2 1>;
1340 phy-names = "usb";
1341 status = "disabled";
1342 };
1343
aace0809
SS		 1344 pci0: pci@ee090000 {
1345 compatible = "renesas,pci-r8a7791";
1346 device_type = "pci";
1347 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1348 reg = <0 0xee090000 0 0xc00>,
1349 <0 0xee080000 0 0x1100>;
1350 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1351 status = "disabled";
1352
1353 bus-range = <0 0>;
1354 #address-cells = <3>;
1355 #size-cells = <2>;
1356 #interrupt-cells = <1>;
1357 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1358 interrupt-map-mask = <0xff00 0 0 0x7>;
1359 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1360 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1361 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
e1bce124
SS		 1362
1363 usb@0,1 {
1364 reg = <0x800 0 0 0 0>;
1365 device_type = "pci";
1366 phys = <&usb0 0>;
1367 phy-names = "usb";
1368 };
1369
1370 usb@0,2 {
1371 reg = <0x1000 0 0 0 0>;
1372 device_type = "pci";
1373 phys = <&usb0 0>;
1374 phy-names = "usb";
1375 };
aace0809
SS		 1376 };
1377
1378 pci1: pci@ee0d0000 {
1379 compatible = "renesas,pci-r8a7791";
1380 device_type = "pci";
1381 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1382 reg = <0 0xee0d0000 0 0xc00>,
1383 <0 0xee0c0000 0 0x1100>;
1384 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1385 status = "disabled";
1386
1387 bus-range = <1 1>;
1388 #address-cells = <3>;
1389 #size-cells = <2>;
1390 #interrupt-cells = <1>;
1391 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1392 interrupt-map-mask = <0xff00 0 0 0x7>;
1393 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1394 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1395 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
e1bce124
SS		 1396
1397 usb@0,1 {
1398 reg = <0x800 0 0 0 0>;
1399 device_type = "pci";
1400 phys = <&usb2 0>;
1401 phy-names = "usb";
1402 };
1403
1404 usb@0,2 {
1405 reg = <0x1000 0 0 0 0>;
1406 device_type = "pci";
1407 phys = <&usb2 0>;
1408 phy-names = "usb";
1409 };
aace0809
SS		 1410 };
1411
811cdfae
PE		 1412 pciec: pcie@fe000000 {
1413 compatible = "renesas,pcie-r8a7791";
1414 reg = <0 0xfe000000 0 0x80000>;
1415 #address-cells = <3>;
1416 #size-cells = <2>;
1417 bus-range = <0x00 0xff>;
1418 device_type = "pci";
1419 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1420 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1421 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1422 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1423 /* Map all possible DDR as inbound ranges */
1424 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1425 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1426 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1427 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1428 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1429 #interrupt-cells = <1>;
1430 interrupt-map-mask = <0 0 0 0>;
1431 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1432 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1433 clock-names = "pcie", "pcie_bus";
1434 status = "disabled";
1435 };
09abd1fd 1436
f1951852
LP		 1437 ipmmu_sy0: mmu@e6280000 {
1438 compatible = "renesas,ipmmu-vmsa";
1439 reg = <0 0xe6280000 0 0x1000>;
1440 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1441 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1442 #iommu-cells = <1>;
1443 status = "disabled";
1444 };
1445
1446 ipmmu_sy1: mmu@e6290000 {
1447 compatible = "renesas,ipmmu-vmsa";
1448 reg = <0 0xe6290000 0 0x1000>;
1449 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1450 #iommu-cells = <1>;
1451 status = "disabled";
1452 };
1453
1454 ipmmu_ds: mmu@e6740000 {
1455 compatible = "renesas,ipmmu-vmsa";
1456 reg = <0 0xe6740000 0 0x1000>;
1457 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1458 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1459 #iommu-cells = <1>;
1460 status = "disabled";
1461 };
1462
1463 ipmmu_mp: mmu@ec680000 {
1464 compatible = "renesas,ipmmu-vmsa";
1465 reg = <0 0xec680000 0 0x1000>;
1466 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1467 #iommu-cells = <1>;
1468 status = "disabled";
1469 };
1470
1471 ipmmu_mx: mmu@fe951000 {
1472 compatible = "renesas,ipmmu-vmsa";
1473 reg = <0 0xfe951000 0 0x1000>;
1474 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1475 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1476 #iommu-cells = <1>;
1477 status = "disabled";
1478 };
1479
1480 ipmmu_rt: mmu@ffc80000 {
1481 compatible = "renesas,ipmmu-vmsa";
1482 reg = <0 0xffc80000 0 0x1000>;
1483 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1484 #iommu-cells = <1>;
1485 status = "disabled";
1486 };
1487
1488 ipmmu_gp: mmu@e62a0000 {
1489 compatible = "renesas,ipmmu-vmsa";
1490 reg = <0 0xe62a0000 0 0x1000>;
1491 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
1492 <0 261 IRQ_TYPE_LEVEL_HIGH>;
1493 #iommu-cells = <1>;
1494 status = "disabled";
1495 };
1496
6c63e07d 1497 rcar_sound: sound@ec500000 {
d2b541c9
KM		 1498 /*
1499 * #sound-dai-cells is required
1500 *
1501 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1502 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1503 */
f49cd2b3 1504 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
09abd1fd
KM		 1505 reg = <0 0xec500000 0 0x1000>, /* SCU */
1506 <0 0xec5a0000 0 0x100>, /* ADG */
1507 <0 0xec540000 0 0x1000>, /* SSIU */
d73a5013
KM		 1508 <0 0xec541000 0 0x1280>, /* SSI */
1509 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1510 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
d88a6a2a 1511
09abd1fd
KM		 1512 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1513 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1514 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1515 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1516 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1517 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1518 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1519 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1520 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1521 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1522 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
150c8ad4 1523 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
09abd1fd
KM		 1524 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1525 clock-names = "ssi-all",
1526 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1527 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1528 "src.9", "src.8", "src.7", "src.6", "src.5",
1529 "src.4", "src.3", "src.2", "src.1", "src.0",
150c8ad4 1530 "dvc.0", "dvc.1",
09abd1fd
KM		 1531 "clk_a", "clk_b", "clk_c", "clk_i";
1532
1533 status = "disabled";
1534
150c8ad4 1535 rcar_sound,dvc {
63573339
KM		 1536 dvc0: dvc@0 {
1537 dmas = <&audma0 0xbc>;
1538 dma-names = "tx";
1539 };
1540 dvc1: dvc@1 {
1541 dmas = <&audma0 0xbe>;
1542 dma-names = "tx";
1543 };
150c8ad4
KM		 1544 };
1545
09abd1fd 1546 rcar_sound,src {
63573339
KM		 1547 src0: src@0 {
1548 interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
1549 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1550 dma-names = "rx", "tx";
1551 };
1552 src1: src@1 {
1553 interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
1554 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1555 dma-names = "rx", "tx";
1556 };
1557 src2: src@2 {
1558 interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
1559 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1560 dma-names = "rx", "tx";
1561 };
1562 src3: src@3 {
1563 interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
1564 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1565 dma-names = "rx", "tx";
1566 };
1567 src4: src@4 {
1568 interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
1569 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1570 dma-names = "rx", "tx";
1571 };
1572 src5: src@5 {
1573 interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
1574 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1575 dma-names = "rx", "tx";
1576 };
1577 src6: src@6 {
1578 interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
1579 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1580 dma-names = "rx", "tx";
1581 };
1582 src7: src@7 {
1583 interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
1584 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1585 dma-names = "rx", "tx";
1586 };
1587 src8: src@8 {
1588 interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
1589 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1590 dma-names = "rx", "tx";
1591 };
1592 src9: src@9 {
1593 interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
1594 dmas = <&audma0 0x97>, <&audma1 0xba>;
1595 dma-names = "rx", "tx";
1596 };
09abd1fd
KM		 1597 };
1598
1599 rcar_sound,ssi {
63573339
KM		 1600 ssi0: ssi@0 {
1601 interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
1602 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1603 dma-names = "rx", "tx", "rxu", "txu";
1604 };
1605 ssi1: ssi@1 {
1606 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
1607 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1608 dma-names = "rx", "tx", "rxu", "txu";
1609 };
1610 ssi2: ssi@2 {
1611 interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
1612 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1613 dma-names = "rx", "tx", "rxu", "txu";
1614 };
1615 ssi3: ssi@3 {
1616 interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
1617 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1618 dma-names = "rx", "tx", "rxu", "txu";
1619 };
1620 ssi4: ssi@4 {
1621 interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
1622 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1623 dma-names = "rx", "tx", "rxu", "txu";
1624 };
1625 ssi5: ssi@5 {
1626 interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
1627 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1628 dma-names = "rx", "tx", "rxu", "txu";
1629 };
1630 ssi6: ssi@6 {
1631 interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1633 dma-names = "rx", "tx", "rxu", "txu";
1634 };
1635 ssi7: ssi@7 {
1636 interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
1637 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1638 dma-names = "rx", "tx", "rxu", "txu";
1639 };
1640 ssi8: ssi@8 {
1641 interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
1642 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1643 dma-names = "rx", "tx", "rxu", "txu";
1644 };
1645 ssi9: ssi@9 {
1646 interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
1647 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1648 dma-names = "rx", "tx", "rxu", "txu";
1649 };
09abd1fd
KM		 1650 };
1651 };
0d0771ab 1652};
Linux kernel - Deliverables
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