Commit | Line | Data |
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0d0771ab HN |
1 | /* |
2 | * Device Tree Source for the r8a7791 SoC | |
3 | * | |
e4d2fd9e | 4 | * Copyright (C) 2013-2014 Renesas Electronics Corporation |
2e5d55ce SS |
5 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
6 | * Copyright (C) 2014 Cogent Embedded Inc. | |
0d0771ab HN |
7 | * |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
11 | */ | |
12 | ||
59e79895 | 13 | #include <dt-bindings/clock/r8a7791-clock.h> |
5f75e73c LP |
14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
15 | #include <dt-bindings/interrupt-controller/irq.h> | |
16 | ||
0d0771ab HN |
17 | / { |
18 | compatible = "renesas,r8a7791"; | |
19 | interrupt-parent = <&gic>; | |
20 | #address-cells = <2>; | |
21 | #size-cells = <2>; | |
22 | ||
5bd3de7b WS |
23 | aliases { |
24 | i2c0 = &i2c0; | |
25 | i2c1 = &i2c1; | |
26 | i2c2 = &i2c2; | |
27 | i2c3 = &i2c3; | |
28 | i2c4 = &i2c4; | |
29 | i2c5 = &i2c5; | |
36408d9d WS |
30 | i2c6 = &i2c6; |
31 | i2c7 = &i2c7; | |
32 | i2c8 = &i2c8; | |
6f3e4ee3 | 33 | spi0 = &qspi; |
7713d3ab GU |
34 | spi1 = &msiof0; |
35 | spi2 = &msiof1; | |
36 | spi3 = &msiof2; | |
0b8d1d57 SS |
37 | vin0 = &vin0; |
38 | vin1 = &vin1; | |
39 | vin2 = &vin2; | |
5bd3de7b WS |
40 | }; |
41 | ||
0d0771ab HN |
42 | cpus { |
43 | #address-cells = <1>; | |
44 | #size-cells = <0>; | |
45 | ||
46 | cpu0: cpu@0 { | |
47 | device_type = "cpu"; | |
48 | compatible = "arm,cortex-a15"; | |
49 | reg = <0>; | |
896b79df | 50 | clock-frequency = <1500000000>; |
a57004ec GI |
51 | voltage-tolerance = <1>; /* 1% */ |
52 | clocks = <&cpg_clocks R8A7791_CLK_Z>; | |
53 | clock-latency = <300000>; /* 300 us */ | |
54 | ||
55 | /* kHz - uV - OPPs unknown yet */ | |
56 | operating-points = <1500000 1000000>, | |
57 | <1312500 1000000>, | |
58 | <1125000 1000000>, | |
59 | < 937500 1000000>, | |
60 | < 750000 1000000>, | |
61 | < 375000 1000000>; | |
0d0771ab | 62 | }; |
15ab426c MD |
63 | |
64 | cpu1: cpu@1 { | |
65 | device_type = "cpu"; | |
66 | compatible = "arm,cortex-a15"; | |
67 | reg = <1>; | |
896b79df | 68 | clock-frequency = <1500000000>; |
15ab426c | 69 | }; |
0d0771ab HN |
70 | }; |
71 | ||
72 | gic: interrupt-controller@f1001000 { | |
73 | compatible = "arm,cortex-a15-gic"; | |
74 | #interrupt-cells = <3>; | |
75 | #address-cells = <0>; | |
76 | interrupt-controller; | |
77 | reg = <0 0xf1001000 0 0x1000>, | |
78 | <0 0xf1002000 0 0x1000>, | |
79 | <0 0xf1004000 0 0x2000>, | |
80 | <0 0xf1006000 0 0x2000>; | |
aa5404fc | 81 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
0d0771ab | 82 | }; |
d77db73e | 83 | |
89fbba12 | 84 | gpio0: gpio@e6050000 { |
ab87e3fc | 85 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 86 | reg = <0 0xe6050000 0 0x50>; |
5f75e73c | 87 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
88 | #gpio-cells = <2>; |
89 | gpio-controller; | |
90 | gpio-ranges = <&pfc 0 0 32>; | |
91 | #interrupt-cells = <2>; | |
92 | interrupt-controller; | |
4faf9c5e | 93 | clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; |
ab87e3fc MD |
94 | }; |
95 | ||
89fbba12 | 96 | gpio1: gpio@e6051000 { |
ab87e3fc | 97 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 98 | reg = <0 0xe6051000 0 0x50>; |
5f75e73c | 99 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
100 | #gpio-cells = <2>; |
101 | gpio-controller; | |
102 | gpio-ranges = <&pfc 0 32 32>; | |
103 | #interrupt-cells = <2>; | |
104 | interrupt-controller; | |
4faf9c5e | 105 | clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; |
ab87e3fc MD |
106 | }; |
107 | ||
89fbba12 | 108 | gpio2: gpio@e6052000 { |
ab87e3fc | 109 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 110 | reg = <0 0xe6052000 0 0x50>; |
5f75e73c | 111 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
112 | #gpio-cells = <2>; |
113 | gpio-controller; | |
114 | gpio-ranges = <&pfc 0 64 32>; | |
115 | #interrupt-cells = <2>; | |
116 | interrupt-controller; | |
4faf9c5e | 117 | clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; |
ab87e3fc MD |
118 | }; |
119 | ||
89fbba12 | 120 | gpio3: gpio@e6053000 { |
ab87e3fc | 121 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 122 | reg = <0 0xe6053000 0 0x50>; |
5f75e73c | 123 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
124 | #gpio-cells = <2>; |
125 | gpio-controller; | |
126 | gpio-ranges = <&pfc 0 96 32>; | |
127 | #interrupt-cells = <2>; | |
128 | interrupt-controller; | |
4faf9c5e | 129 | clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; |
ab87e3fc MD |
130 | }; |
131 | ||
89fbba12 | 132 | gpio4: gpio@e6054000 { |
ab87e3fc | 133 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 134 | reg = <0 0xe6054000 0 0x50>; |
5f75e73c | 135 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
136 | #gpio-cells = <2>; |
137 | gpio-controller; | |
138 | gpio-ranges = <&pfc 0 128 32>; | |
139 | #interrupt-cells = <2>; | |
140 | interrupt-controller; | |
4faf9c5e | 141 | clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; |
ab87e3fc MD |
142 | }; |
143 | ||
89fbba12 | 144 | gpio5: gpio@e6055000 { |
ab87e3fc | 145 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 146 | reg = <0 0xe6055000 0 0x50>; |
5f75e73c | 147 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
148 | #gpio-cells = <2>; |
149 | gpio-controller; | |
150 | gpio-ranges = <&pfc 0 160 32>; | |
151 | #interrupt-cells = <2>; | |
152 | interrupt-controller; | |
4faf9c5e | 153 | clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; |
ab87e3fc MD |
154 | }; |
155 | ||
89fbba12 | 156 | gpio6: gpio@e6055400 { |
ab87e3fc | 157 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 158 | reg = <0 0xe6055400 0 0x50>; |
5f75e73c | 159 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
160 | #gpio-cells = <2>; |
161 | gpio-controller; | |
162 | gpio-ranges = <&pfc 0 192 32>; | |
163 | #interrupt-cells = <2>; | |
164 | interrupt-controller; | |
4faf9c5e | 165 | clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; |
ab87e3fc MD |
166 | }; |
167 | ||
89fbba12 | 168 | gpio7: gpio@e6055800 { |
ab87e3fc | 169 | compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; |
89fbba12 | 170 | reg = <0 0xe6055800 0 0x50>; |
5f75e73c | 171 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
ab87e3fc MD |
172 | #gpio-cells = <2>; |
173 | gpio-controller; | |
174 | gpio-ranges = <&pfc 0 224 26>; | |
175 | #interrupt-cells = <2>; | |
176 | interrupt-controller; | |
4faf9c5e | 177 | clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; |
ab87e3fc MD |
178 | }; |
179 | ||
d103f4d3 MD |
180 | thermal@e61f0000 { |
181 | compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal"; | |
182 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; | |
d103f4d3 | 183 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
563bc8eb | 184 | clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; |
d103f4d3 MD |
185 | }; |
186 | ||
03586acf MD |
187 | timer { |
188 | compatible = "arm,armv7-timer"; | |
aa5404fc GU |
189 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
190 | <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
191 | <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
192 | <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
03586acf MD |
193 | }; |
194 | ||
ceaa1894 | 195 | cmt0: timer@ffca0000 { |
4217f323 | 196 | compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; |
ceaa1894 LP |
197 | reg = <0 0xffca0000 0 0x1004>; |
198 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, | |
199 | <0 143 IRQ_TYPE_LEVEL_HIGH>; | |
200 | clocks = <&mstp1_clks R8A7791_CLK_CMT0>; | |
201 | clock-names = "fck"; | |
202 | ||
203 | renesas,channels-mask = <0x60>; | |
204 | ||
205 | status = "disabled"; | |
206 | }; | |
207 | ||
208 | cmt1: timer@e6130000 { | |
4217f323 | 209 | compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; |
ceaa1894 LP |
210 | reg = <0 0xe6130000 0 0x1004>; |
211 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, | |
212 | <0 121 IRQ_TYPE_LEVEL_HIGH>, | |
213 | <0 122 IRQ_TYPE_LEVEL_HIGH>, | |
214 | <0 123 IRQ_TYPE_LEVEL_HIGH>, | |
215 | <0 124 IRQ_TYPE_LEVEL_HIGH>, | |
216 | <0 125 IRQ_TYPE_LEVEL_HIGH>, | |
217 | <0 126 IRQ_TYPE_LEVEL_HIGH>, | |
218 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
219 | clocks = <&mstp3_clks R8A7791_CLK_CMT1>; | |
220 | clock-names = "fck"; | |
221 | ||
222 | renesas,channels-mask = <0xff>; | |
223 | ||
224 | status = "disabled"; | |
225 | }; | |
226 | ||
d77db73e | 227 | irqc0: interrupt-controller@e61c0000 { |
26041b06 | 228 | compatible = "renesas,irqc-r8a7791", "renesas,irqc"; |
d77db73e MD |
229 | #interrupt-cells = <2>; |
230 | interrupt-controller; | |
231 | reg = <0 0xe61c0000 0 0x200>; | |
5f75e73c LP |
232 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
233 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | |
234 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | |
235 | <0 3 IRQ_TYPE_LEVEL_HIGH>, | |
236 | <0 12 IRQ_TYPE_LEVEL_HIGH>, | |
237 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
238 | <0 14 IRQ_TYPE_LEVEL_HIGH>, | |
239 | <0 15 IRQ_TYPE_LEVEL_HIGH>, | |
240 | <0 16 IRQ_TYPE_LEVEL_HIGH>, | |
241 | <0 17 IRQ_TYPE_LEVEL_HIGH>; | |
d77db73e | 242 | }; |
55146927 | 243 | |
fde8feef LP |
244 | dmac0: dma-controller@e6700000 { |
245 | compatible = "renesas,rcar-dmac"; | |
246 | reg = <0 0xe6700000 0 0x20000>; | |
247 | interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH | |
248 | 0 200 IRQ_TYPE_LEVEL_HIGH | |
249 | 0 201 IRQ_TYPE_LEVEL_HIGH | |
250 | 0 202 IRQ_TYPE_LEVEL_HIGH | |
251 | 0 203 IRQ_TYPE_LEVEL_HIGH | |
252 | 0 204 IRQ_TYPE_LEVEL_HIGH | |
253 | 0 205 IRQ_TYPE_LEVEL_HIGH | |
254 | 0 206 IRQ_TYPE_LEVEL_HIGH | |
255 | 0 207 IRQ_TYPE_LEVEL_HIGH | |
256 | 0 208 IRQ_TYPE_LEVEL_HIGH | |
257 | 0 209 IRQ_TYPE_LEVEL_HIGH | |
258 | 0 210 IRQ_TYPE_LEVEL_HIGH | |
259 | 0 211 IRQ_TYPE_LEVEL_HIGH | |
260 | 0 212 IRQ_TYPE_LEVEL_HIGH | |
261 | 0 213 IRQ_TYPE_LEVEL_HIGH | |
262 | 0 214 IRQ_TYPE_LEVEL_HIGH>; | |
263 | interrupt-names = "error", | |
264 | "ch0", "ch1", "ch2", "ch3", | |
265 | "ch4", "ch5", "ch6", "ch7", | |
266 | "ch8", "ch9", "ch10", "ch11", | |
267 | "ch12", "ch13", "ch14"; | |
268 | clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; | |
269 | clock-names = "fck"; | |
270 | #dma-cells = <1>; | |
271 | dma-channels = <15>; | |
272 | }; | |
273 | ||
274 | dmac1: dma-controller@e6720000 { | |
275 | compatible = "renesas,rcar-dmac"; | |
276 | reg = <0 0xe6720000 0 0x20000>; | |
277 | interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH | |
278 | 0 216 IRQ_TYPE_LEVEL_HIGH | |
279 | 0 217 IRQ_TYPE_LEVEL_HIGH | |
280 | 0 218 IRQ_TYPE_LEVEL_HIGH | |
281 | 0 219 IRQ_TYPE_LEVEL_HIGH | |
282 | 0 308 IRQ_TYPE_LEVEL_HIGH | |
283 | 0 309 IRQ_TYPE_LEVEL_HIGH | |
284 | 0 310 IRQ_TYPE_LEVEL_HIGH | |
285 | 0 311 IRQ_TYPE_LEVEL_HIGH | |
286 | 0 312 IRQ_TYPE_LEVEL_HIGH | |
287 | 0 313 IRQ_TYPE_LEVEL_HIGH | |
288 | 0 314 IRQ_TYPE_LEVEL_HIGH | |
289 | 0 315 IRQ_TYPE_LEVEL_HIGH | |
290 | 0 316 IRQ_TYPE_LEVEL_HIGH | |
291 | 0 317 IRQ_TYPE_LEVEL_HIGH | |
292 | 0 318 IRQ_TYPE_LEVEL_HIGH>; | |
293 | interrupt-names = "error", | |
294 | "ch0", "ch1", "ch2", "ch3", | |
295 | "ch4", "ch5", "ch6", "ch7", | |
296 | "ch8", "ch9", "ch10", "ch11", | |
297 | "ch12", "ch13", "ch14"; | |
298 | clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; | |
299 | clock-names = "fck"; | |
300 | #dma-cells = <1>; | |
301 | dma-channels = <15>; | |
302 | }; | |
303 | ||
8994fff6 KM |
304 | audma0: dma-controller@ec700000 { |
305 | compatible = "renesas,rcar-dmac"; | |
306 | reg = <0 0xec700000 0 0x10000>; | |
307 | interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH | |
308 | 0 320 IRQ_TYPE_LEVEL_HIGH | |
309 | 0 321 IRQ_TYPE_LEVEL_HIGH | |
310 | 0 322 IRQ_TYPE_LEVEL_HIGH | |
311 | 0 323 IRQ_TYPE_LEVEL_HIGH | |
312 | 0 324 IRQ_TYPE_LEVEL_HIGH | |
313 | 0 325 IRQ_TYPE_LEVEL_HIGH | |
314 | 0 326 IRQ_TYPE_LEVEL_HIGH | |
315 | 0 327 IRQ_TYPE_LEVEL_HIGH | |
316 | 0 328 IRQ_TYPE_LEVEL_HIGH | |
317 | 0 329 IRQ_TYPE_LEVEL_HIGH | |
318 | 0 330 IRQ_TYPE_LEVEL_HIGH | |
319 | 0 331 IRQ_TYPE_LEVEL_HIGH | |
320 | 0 332 IRQ_TYPE_LEVEL_HIGH>; | |
321 | interrupt-names = "error", | |
322 | "ch0", "ch1", "ch2", "ch3", | |
323 | "ch4", "ch5", "ch6", "ch7", | |
324 | "ch8", "ch9", "ch10", "ch11", | |
325 | "ch12"; | |
326 | clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>; | |
327 | clock-names = "fck"; | |
328 | #dma-cells = <1>; | |
329 | dma-channels = <13>; | |
330 | }; | |
331 | ||
332 | audma1: dma-controller@ec720000 { | |
333 | compatible = "renesas,rcar-dmac"; | |
334 | reg = <0 0xec720000 0 0x10000>; | |
335 | interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH | |
336 | 0 333 IRQ_TYPE_LEVEL_HIGH | |
337 | 0 334 IRQ_TYPE_LEVEL_HIGH | |
338 | 0 335 IRQ_TYPE_LEVEL_HIGH | |
339 | 0 336 IRQ_TYPE_LEVEL_HIGH | |
340 | 0 337 IRQ_TYPE_LEVEL_HIGH | |
341 | 0 338 IRQ_TYPE_LEVEL_HIGH | |
342 | 0 339 IRQ_TYPE_LEVEL_HIGH | |
343 | 0 340 IRQ_TYPE_LEVEL_HIGH | |
344 | 0 341 IRQ_TYPE_LEVEL_HIGH | |
345 | 0 342 IRQ_TYPE_LEVEL_HIGH | |
346 | 0 343 IRQ_TYPE_LEVEL_HIGH | |
347 | 0 344 IRQ_TYPE_LEVEL_HIGH | |
348 | 0 345 IRQ_TYPE_LEVEL_HIGH>; | |
349 | interrupt-names = "error", | |
350 | "ch0", "ch1", "ch2", "ch3", | |
351 | "ch4", "ch5", "ch6", "ch7", | |
352 | "ch8", "ch9", "ch10", "ch11", | |
353 | "ch12"; | |
354 | clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>; | |
355 | clock-names = "fck"; | |
356 | #dma-cells = <1>; | |
357 | dma-channels = <13>; | |
358 | }; | |
359 | ||
40c6d9f0 KM |
360 | audmapp: dma-controller@ec740000 { |
361 | compatible = "renesas,rcar-audmapp"; | |
362 | #dma-cells = <1>; | |
363 | ||
364 | reg = <0 0xec740000 0 0x200>; | |
365 | }; | |
366 | ||
36408d9d | 367 | /* The memory map in the User's Manual maps the cores to bus numbers */ |
5bd3de7b WS |
368 | i2c0: i2c@e6508000 { |
369 | #address-cells = <1>; | |
370 | #size-cells = <0>; | |
371 | compatible = "renesas,i2c-r8a7791"; | |
372 | reg = <0 0xe6508000 0 0x40>; | |
373 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; | |
374 | clocks = <&mstp9_clks R8A7791_CLK_I2C0>; | |
375 | status = "disabled"; | |
376 | }; | |
377 | ||
378 | i2c1: i2c@e6518000 { | |
379 | #address-cells = <1>; | |
380 | #size-cells = <0>; | |
381 | compatible = "renesas,i2c-r8a7791"; | |
382 | reg = <0 0xe6518000 0 0x40>; | |
383 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; | |
384 | clocks = <&mstp9_clks R8A7791_CLK_I2C1>; | |
385 | status = "disabled"; | |
386 | }; | |
387 | ||
388 | i2c2: i2c@e6530000 { | |
389 | #address-cells = <1>; | |
390 | #size-cells = <0>; | |
391 | compatible = "renesas,i2c-r8a7791"; | |
392 | reg = <0 0xe6530000 0 0x40>; | |
393 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; | |
394 | clocks = <&mstp9_clks R8A7791_CLK_I2C2>; | |
395 | status = "disabled"; | |
396 | }; | |
397 | ||
398 | i2c3: i2c@e6540000 { | |
399 | #address-cells = <1>; | |
400 | #size-cells = <0>; | |
401 | compatible = "renesas,i2c-r8a7791"; | |
402 | reg = <0 0xe6540000 0 0x40>; | |
403 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; | |
404 | clocks = <&mstp9_clks R8A7791_CLK_I2C3>; | |
405 | status = "disabled"; | |
406 | }; | |
407 | ||
408 | i2c4: i2c@e6520000 { | |
409 | #address-cells = <1>; | |
410 | #size-cells = <0>; | |
411 | compatible = "renesas,i2c-r8a7791"; | |
412 | reg = <0 0xe6520000 0 0x40>; | |
413 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; | |
414 | clocks = <&mstp9_clks R8A7791_CLK_I2C4>; | |
415 | status = "disabled"; | |
416 | }; | |
417 | ||
418 | i2c5: i2c@e6528000 { | |
36408d9d | 419 | /* doesn't need pinmux */ |
5bd3de7b WS |
420 | #address-cells = <1>; |
421 | #size-cells = <0>; | |
422 | compatible = "renesas,i2c-r8a7791"; | |
423 | reg = <0 0xe6528000 0 0x40>; | |
424 | interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
425 | clocks = <&mstp9_clks R8A7791_CLK_I2C5>; | |
426 | status = "disabled"; | |
427 | }; | |
428 | ||
36408d9d WS |
429 | i2c6: i2c@e60b0000 { |
430 | /* doesn't need pinmux */ | |
431 | #address-cells = <1>; | |
432 | #size-cells = <0>; | |
433 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
434 | reg = <0 0xe60b0000 0 0x425>; | |
435 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; | |
436 | clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; | |
3f58c54b WS |
437 | dmas = <&dmac0 0x77>, <&dmac0 0x78>; |
438 | dma-names = "tx", "rx"; | |
36408d9d WS |
439 | status = "disabled"; |
440 | }; | |
441 | ||
442 | i2c7: i2c@e6500000 { | |
443 | #address-cells = <1>; | |
444 | #size-cells = <0>; | |
445 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
446 | reg = <0 0xe6500000 0 0x425>; | |
447 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; | |
448 | clocks = <&mstp3_clks R8A7791_CLK_IIC0>; | |
3f58c54b WS |
449 | dmas = <&dmac0 0x61>, <&dmac0 0x62>; |
450 | dma-names = "tx", "rx"; | |
36408d9d WS |
451 | status = "disabled"; |
452 | }; | |
453 | ||
454 | i2c8: i2c@e6510000 { | |
455 | #address-cells = <1>; | |
456 | #size-cells = <0>; | |
457 | compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; | |
458 | reg = <0 0xe6510000 0 0x425>; | |
459 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; | |
460 | clocks = <&mstp3_clks R8A7791_CLK_IIC1>; | |
3f58c54b WS |
461 | dmas = <&dmac0 0x65>, <&dmac0 0x66>; |
462 | dma-names = "tx", "rx"; | |
36408d9d WS |
463 | status = "disabled"; |
464 | }; | |
465 | ||
55146927 MD |
466 | pfc: pfc@e6060000 { |
467 | compatible = "renesas,pfc-r8a7791"; | |
468 | reg = <0 0xe6060000 0 0x250>; | |
469 | #gpio-range-cells = <3>; | |
470 | }; | |
59e79895 | 471 | |
8edae499 LP |
472 | mmcif0: mmc@ee200000 { |
473 | compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif"; | |
474 | reg = <0 0xee200000 0 0x80>; | |
475 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; | |
476 | clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; | |
16b355b4 LP |
477 | dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; |
478 | dma-names = "tx", "rx"; | |
8edae499 LP |
479 | reg-io-width = <4>; |
480 | status = "disabled"; | |
481 | }; | |
482 | ||
b7ed8a0d MD |
483 | sdhi0: sd@ee100000 { |
484 | compatible = "renesas,sdhi-r8a7791"; | |
485 | reg = <0 0xee100000 0 0x200>; | |
b7ed8a0d MD |
486 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
487 | clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; | |
488 | status = "disabled"; | |
489 | }; | |
490 | ||
491 | sdhi1: sd@ee140000 { | |
492 | compatible = "renesas,sdhi-r8a7791"; | |
493 | reg = <0 0xee140000 0 0x100>; | |
b7ed8a0d MD |
494 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
495 | clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; | |
496 | status = "disabled"; | |
497 | }; | |
498 | ||
499 | sdhi2: sd@ee160000 { | |
500 | compatible = "renesas,sdhi-r8a7791"; | |
501 | reg = <0 0xee160000 0 0x100>; | |
b7ed8a0d MD |
502 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; |
503 | clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; | |
504 | status = "disabled"; | |
505 | }; | |
506 | ||
9640cf25 LP |
507 | scifa0: serial@e6c40000 { |
508 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
509 | reg = <0 0xe6c40000 0 64>; | |
9640cf25 LP |
510 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; |
511 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; | |
512 | clock-names = "sci_ick"; | |
513 | status = "disabled"; | |
514 | }; | |
515 | ||
516 | scifa1: serial@e6c50000 { | |
517 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
518 | reg = <0 0xe6c50000 0 64>; |
519 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; | |
520 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; | |
521 | clock-names = "sci_ick"; | |
522 | status = "disabled"; | |
523 | }; | |
524 | ||
525 | scifa2: serial@e6c60000 { | |
526 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
527 | reg = <0 0xe6c60000 0 64>; |
528 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; | |
529 | clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; | |
530 | clock-names = "sci_ick"; | |
531 | status = "disabled"; | |
532 | }; | |
533 | ||
534 | scifa3: serial@e6c70000 { | |
535 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
536 | reg = <0 0xe6c70000 0 64>; |
537 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; | |
538 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; | |
539 | clock-names = "sci_ick"; | |
540 | status = "disabled"; | |
541 | }; | |
542 | ||
543 | scifa4: serial@e6c78000 { | |
544 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
545 | reg = <0 0xe6c78000 0 64>; |
546 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; | |
547 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; | |
548 | clock-names = "sci_ick"; | |
549 | status = "disabled"; | |
550 | }; | |
551 | ||
552 | scifa5: serial@e6c80000 { | |
553 | compatible = "renesas,scifa-r8a7791", "renesas,scifa"; | |
9640cf25 LP |
554 | reg = <0 0xe6c80000 0 64>; |
555 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; | |
556 | clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; | |
557 | clock-names = "sci_ick"; | |
558 | status = "disabled"; | |
559 | }; | |
560 | ||
561 | scifb0: serial@e6c20000 { | |
562 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
9640cf25 LP |
563 | reg = <0 0xe6c20000 0 64>; |
564 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; | |
565 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; | |
566 | clock-names = "sci_ick"; | |
567 | status = "disabled"; | |
568 | }; | |
569 | ||
570 | scifb1: serial@e6c30000 { | |
571 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
9640cf25 LP |
572 | reg = <0 0xe6c30000 0 64>; |
573 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; | |
574 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; | |
575 | clock-names = "sci_ick"; | |
576 | status = "disabled"; | |
577 | }; | |
578 | ||
579 | scifb2: serial@e6ce0000 { | |
580 | compatible = "renesas,scifb-r8a7791", "renesas,scifb"; | |
9640cf25 LP |
581 | reg = <0 0xe6ce0000 0 64>; |
582 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; | |
583 | clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; | |
584 | clock-names = "sci_ick"; | |
585 | status = "disabled"; | |
586 | }; | |
587 | ||
588 | scif0: serial@e6e60000 { | |
589 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
590 | reg = <0 0xe6e60000 0 64>; |
591 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; | |
592 | clocks = <&mstp7_clks R8A7791_CLK_SCIF0>; | |
593 | clock-names = "sci_ick"; | |
594 | status = "disabled"; | |
595 | }; | |
596 | ||
597 | scif1: serial@e6e68000 { | |
598 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
599 | reg = <0 0xe6e68000 0 64>; |
600 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; | |
601 | clocks = <&mstp7_clks R8A7791_CLK_SCIF1>; | |
602 | clock-names = "sci_ick"; | |
603 | status = "disabled"; | |
604 | }; | |
605 | ||
606 | scif2: serial@e6e58000 { | |
607 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
608 | reg = <0 0xe6e58000 0 64>; |
609 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; | |
610 | clocks = <&mstp7_clks R8A7791_CLK_SCIF2>; | |
611 | clock-names = "sci_ick"; | |
612 | status = "disabled"; | |
613 | }; | |
614 | ||
615 | scif3: serial@e6ea8000 { | |
616 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
617 | reg = <0 0xe6ea8000 0 64>; |
618 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; | |
619 | clocks = <&mstp7_clks R8A7791_CLK_SCIF3>; | |
620 | clock-names = "sci_ick"; | |
621 | status = "disabled"; | |
622 | }; | |
623 | ||
624 | scif4: serial@e6ee0000 { | |
625 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
626 | reg = <0 0xe6ee0000 0 64>; |
627 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; | |
628 | clocks = <&mstp7_clks R8A7791_CLK_SCIF4>; | |
629 | clock-names = "sci_ick"; | |
630 | status = "disabled"; | |
631 | }; | |
632 | ||
633 | scif5: serial@e6ee8000 { | |
634 | compatible = "renesas,scif-r8a7791", "renesas,scif"; | |
9640cf25 LP |
635 | reg = <0 0xe6ee8000 0 64>; |
636 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; | |
637 | clocks = <&mstp7_clks R8A7791_CLK_SCIF5>; | |
638 | clock-names = "sci_ick"; | |
639 | status = "disabled"; | |
640 | }; | |
641 | ||
642 | hscif0: serial@e62c0000 { | |
643 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
9640cf25 LP |
644 | reg = <0 0xe62c0000 0 96>; |
645 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; | |
646 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>; | |
647 | clock-names = "sci_ick"; | |
648 | status = "disabled"; | |
649 | }; | |
650 | ||
651 | hscif1: serial@e62c8000 { | |
652 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
9640cf25 LP |
653 | reg = <0 0xe62c8000 0 96>; |
654 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; | |
655 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>; | |
656 | clock-names = "sci_ick"; | |
657 | status = "disabled"; | |
658 | }; | |
659 | ||
660 | hscif2: serial@e62d0000 { | |
661 | compatible = "renesas,hscif-r8a7791", "renesas,hscif"; | |
9640cf25 LP |
662 | reg = <0 0xe62d0000 0 96>; |
663 | interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; | |
664 | clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>; | |
665 | clock-names = "sci_ick"; | |
666 | status = "disabled"; | |
667 | }; | |
668 | ||
2e5d55ce SS |
669 | ether: ethernet@ee700000 { |
670 | compatible = "renesas,ether-r8a7791"; | |
671 | reg = <0 0xee700000 0 0x400>; | |
672 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; | |
673 | clocks = <&mstp8_clks R8A7791_CLK_ETHER>; | |
674 | phy-mode = "rmii"; | |
675 | #address-cells = <1>; | |
676 | #size-cells = <0>; | |
677 | status = "disabled"; | |
678 | }; | |
679 | ||
b8532c69 VB |
680 | sata0: sata@ee300000 { |
681 | compatible = "renesas,sata-r8a7791"; | |
682 | reg = <0 0xee300000 0 0x2000>; | |
b8532c69 VB |
683 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; |
684 | clocks = <&mstp8_clks R8A7791_CLK_SATA0>; | |
685 | status = "disabled"; | |
686 | }; | |
687 | ||
688 | sata1: sata@ee500000 { | |
689 | compatible = "renesas,sata-r8a7791"; | |
690 | reg = <0 0xee500000 0 0x2000>; | |
b8532c69 VB |
691 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
692 | clocks = <&mstp8_clks R8A7791_CLK_SATA1>; | |
693 | status = "disabled"; | |
694 | }; | |
695 | ||
1c1fee7c YS |
696 | hsusb: usb@e6590000 { |
697 | compatible = "renesas,usbhs-r8a7791"; | |
698 | reg = <0 0xe6590000 0 0x100>; | |
699 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; | |
700 | clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; | |
701 | renesas,buswait = <4>; | |
702 | phys = <&usb0 1>; | |
703 | phy-names = "usb"; | |
704 | status = "disabled"; | |
705 | }; | |
706 | ||
3b7e530d SS |
707 | usbphy: usb-phy@e6590100 { |
708 | compatible = "renesas,usb-phy-r8a7791"; | |
709 | reg = <0 0xe6590100 0 0x100>; | |
710 | #address-cells = <1>; | |
711 | #size-cells = <0>; | |
712 | clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; | |
713 | clock-names = "usbhs"; | |
714 | status = "disabled"; | |
715 | ||
716 | usb0: usb-channel@0 { | |
717 | reg = <0>; | |
718 | #phy-cells = <1>; | |
719 | }; | |
720 | usb2: usb-channel@2 { | |
721 | reg = <2>; | |
722 | #phy-cells = <1>; | |
723 | }; | |
724 | }; | |
725 | ||
0b8d1d57 SS |
726 | vin0: video@e6ef0000 { |
727 | compatible = "renesas,vin-r8a7791"; | |
728 | clocks = <&mstp8_clks R8A7791_CLK_VIN0>; | |
729 | reg = <0 0xe6ef0000 0 0x1000>; | |
730 | interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; | |
731 | status = "disabled"; | |
732 | }; | |
733 | ||
734 | vin1: video@e6ef1000 { | |
735 | compatible = "renesas,vin-r8a7791"; | |
736 | clocks = <&mstp8_clks R8A7791_CLK_VIN1>; | |
737 | reg = <0 0xe6ef1000 0 0x1000>; | |
738 | interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; | |
739 | status = "disabled"; | |
740 | }; | |
741 | ||
742 | vin2: video@e6ef2000 { | |
743 | compatible = "renesas,vin-r8a7791"; | |
744 | clocks = <&mstp8_clks R8A7791_CLK_VIN2>; | |
745 | reg = <0 0xe6ef2000 0 0x1000>; | |
746 | interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; | |
747 | status = "disabled"; | |
748 | }; | |
749 | ||
8eefac2d LP |
750 | vsp1@fe928000 { |
751 | compatible = "renesas,vsp1"; | |
752 | reg = <0 0xfe928000 0 0x8000>; | |
753 | interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; | |
754 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; | |
755 | ||
756 | renesas,has-lut; | |
757 | renesas,has-sru; | |
758 | renesas,#rpf = <5>; | |
759 | renesas,#uds = <3>; | |
760 | renesas,#wpf = <4>; | |
761 | }; | |
762 | ||
763 | vsp1@fe930000 { | |
764 | compatible = "renesas,vsp1"; | |
765 | reg = <0 0xfe930000 0 0x8000>; | |
766 | interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; | |
767 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; | |
768 | ||
769 | renesas,has-lif; | |
770 | renesas,has-lut; | |
771 | renesas,#rpf = <4>; | |
772 | renesas,#uds = <1>; | |
773 | renesas,#wpf = <4>; | |
774 | }; | |
775 | ||
776 | vsp1@fe938000 { | |
777 | compatible = "renesas,vsp1"; | |
778 | reg = <0 0xfe938000 0 0x8000>; | |
779 | interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; | |
780 | clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; | |
781 | ||
782 | renesas,has-lif; | |
783 | renesas,has-lut; | |
784 | renesas,#rpf = <4>; | |
785 | renesas,#uds = <1>; | |
786 | renesas,#wpf = <4>; | |
787 | }; | |
788 | ||
789 | du: display@feb00000 { | |
790 | compatible = "renesas,du-r8a7791"; | |
791 | reg = <0 0xfeb00000 0 0x40000>, | |
792 | <0 0xfeb90000 0 0x1c>; | |
793 | reg-names = "du", "lvds.0"; | |
794 | interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, | |
795 | <0 268 IRQ_TYPE_LEVEL_HIGH>; | |
796 | clocks = <&mstp7_clks R8A7791_CLK_DU0>, | |
797 | <&mstp7_clks R8A7791_CLK_DU1>, | |
798 | <&mstp7_clks R8A7791_CLK_LVDS0>; | |
799 | clock-names = "du.0", "du.1", "lvds.0"; | |
800 | status = "disabled"; | |
801 | ||
802 | ports { | |
803 | #address-cells = <1>; | |
804 | #size-cells = <0>; | |
805 | ||
806 | port@0 { | |
807 | reg = <0>; | |
808 | du_out_rgb: endpoint { | |
809 | }; | |
810 | }; | |
811 | port@1 { | |
812 | reg = <1>; | |
813 | du_out_lvds0: endpoint { | |
814 | }; | |
815 | }; | |
816 | }; | |
817 | }; | |
818 | ||
59e79895 LP |
819 | clocks { |
820 | #address-cells = <2>; | |
821 | #size-cells = <2>; | |
822 | ranges; | |
823 | ||
824 | /* External root clock */ | |
825 | extal_clk: extal_clk { | |
826 | compatible = "fixed-clock"; | |
827 | #clock-cells = <0>; | |
828 | /* This value must be overriden by the board. */ | |
829 | clock-frequency = <0>; | |
830 | clock-output-names = "extal"; | |
831 | }; | |
832 | ||
0d3dbde8 KM |
833 | /* |
834 | * The external audio clocks are configured as 0 Hz fixed frequency clocks by | |
835 | * default. Boards that provide audio clocks should override them. | |
836 | */ | |
837 | audio_clk_a: audio_clk_a { | |
838 | compatible = "fixed-clock"; | |
839 | #clock-cells = <0>; | |
840 | clock-frequency = <0>; | |
841 | clock-output-names = "audio_clk_a"; | |
842 | }; | |
843 | audio_clk_b: audio_clk_b { | |
844 | compatible = "fixed-clock"; | |
845 | #clock-cells = <0>; | |
846 | clock-frequency = <0>; | |
847 | clock-output-names = "audio_clk_b"; | |
848 | }; | |
849 | audio_clk_c: audio_clk_c { | |
850 | compatible = "fixed-clock"; | |
851 | #clock-cells = <0>; | |
852 | clock-frequency = <0>; | |
853 | clock-output-names = "audio_clk_c"; | |
854 | }; | |
855 | ||
66c405e7 PE |
856 | /* External PCIe clock - can be overridden by the board */ |
857 | pcie_bus_clk: pcie_bus_clk { | |
858 | compatible = "fixed-clock"; | |
859 | #clock-cells = <0>; | |
860 | clock-frequency = <100000000>; | |
861 | clock-output-names = "pcie_bus"; | |
862 | status = "disabled"; | |
863 | }; | |
864 | ||
59e79895 LP |
865 | /* Special CPG clocks */ |
866 | cpg_clocks: cpg_clocks@e6150000 { | |
867 | compatible = "renesas,r8a7791-cpg-clocks", | |
868 | "renesas,rcar-gen2-cpg-clocks"; | |
869 | reg = <0 0xe6150000 0 0x1000>; | |
870 | clocks = <&extal_clk>; | |
871 | #clock-cells = <1>; | |
872 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
873 | "lb", "qspi", "sdh", "sd0", "z"; | |
874 | }; | |
875 | ||
876 | /* Variable factor clocks */ | |
877 | sd1_clk: sd2_clk@e6150078 { | |
878 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
879 | reg = <0 0xe6150078 0 4>; | |
880 | clocks = <&pll1_div2_clk>; | |
881 | #clock-cells = <0>; | |
882 | clock-output-names = "sd1"; | |
883 | }; | |
c9b22772 | 884 | sd2_clk: sd3_clk@e615026c { |
59e79895 | 885 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; |
c9b22772 | 886 | reg = <0 0xe615026c 0 4>; |
59e79895 LP |
887 | clocks = <&pll1_div2_clk>; |
888 | #clock-cells = <0>; | |
889 | clock-output-names = "sd2"; | |
890 | }; | |
891 | mmc0_clk: mmc0_clk@e6150240 { | |
892 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
893 | reg = <0 0xe6150240 0 4>; | |
894 | clocks = <&pll1_div2_clk>; | |
895 | #clock-cells = <0>; | |
896 | clock-output-names = "mmc0"; | |
897 | }; | |
898 | ssp_clk: ssp_clk@e6150248 { | |
899 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
900 | reg = <0 0xe6150248 0 4>; | |
901 | clocks = <&pll1_div2_clk>; | |
902 | #clock-cells = <0>; | |
903 | clock-output-names = "ssp"; | |
904 | }; | |
905 | ssprs_clk: ssprs_clk@e615024c { | |
906 | compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; | |
907 | reg = <0 0xe615024c 0 4>; | |
908 | clocks = <&pll1_div2_clk>; | |
909 | #clock-cells = <0>; | |
910 | clock-output-names = "ssprs"; | |
911 | }; | |
912 | ||
913 | /* Fixed factor clocks */ | |
914 | pll1_div2_clk: pll1_div2_clk { | |
915 | compatible = "fixed-factor-clock"; | |
916 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
917 | #clock-cells = <0>; | |
918 | clock-div = <2>; | |
919 | clock-mult = <1>; | |
920 | clock-output-names = "pll1_div2"; | |
921 | }; | |
922 | zg_clk: zg_clk { | |
923 | compatible = "fixed-factor-clock"; | |
924 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
925 | #clock-cells = <0>; | |
926 | clock-div = <3>; | |
927 | clock-mult = <1>; | |
928 | clock-output-names = "zg"; | |
929 | }; | |
930 | zx_clk: zx_clk { | |
931 | compatible = "fixed-factor-clock"; | |
932 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
933 | #clock-cells = <0>; | |
934 | clock-div = <3>; | |
935 | clock-mult = <1>; | |
936 | clock-output-names = "zx"; | |
937 | }; | |
938 | zs_clk: zs_clk { | |
939 | compatible = "fixed-factor-clock"; | |
940 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
941 | #clock-cells = <0>; | |
942 | clock-div = <6>; | |
943 | clock-mult = <1>; | |
944 | clock-output-names = "zs"; | |
945 | }; | |
946 | hp_clk: hp_clk { | |
947 | compatible = "fixed-factor-clock"; | |
948 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
949 | #clock-cells = <0>; | |
950 | clock-div = <12>; | |
951 | clock-mult = <1>; | |
952 | clock-output-names = "hp"; | |
953 | }; | |
954 | i_clk: i_clk { | |
955 | compatible = "fixed-factor-clock"; | |
956 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
957 | #clock-cells = <0>; | |
958 | clock-div = <2>; | |
959 | clock-mult = <1>; | |
960 | clock-output-names = "i"; | |
961 | }; | |
962 | b_clk: b_clk { | |
963 | compatible = "fixed-factor-clock"; | |
964 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
965 | #clock-cells = <0>; | |
966 | clock-div = <12>; | |
967 | clock-mult = <1>; | |
968 | clock-output-names = "b"; | |
969 | }; | |
970 | p_clk: p_clk { | |
971 | compatible = "fixed-factor-clock"; | |
972 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
973 | #clock-cells = <0>; | |
974 | clock-div = <24>; | |
975 | clock-mult = <1>; | |
976 | clock-output-names = "p"; | |
977 | }; | |
978 | cl_clk: cl_clk { | |
979 | compatible = "fixed-factor-clock"; | |
980 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
981 | #clock-cells = <0>; | |
982 | clock-div = <48>; | |
983 | clock-mult = <1>; | |
984 | clock-output-names = "cl"; | |
985 | }; | |
986 | m2_clk: m2_clk { | |
987 | compatible = "fixed-factor-clock"; | |
988 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
989 | #clock-cells = <0>; | |
990 | clock-div = <8>; | |
991 | clock-mult = <1>; | |
992 | clock-output-names = "m2"; | |
993 | }; | |
994 | imp_clk: imp_clk { | |
995 | compatible = "fixed-factor-clock"; | |
996 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
997 | #clock-cells = <0>; | |
998 | clock-div = <4>; | |
999 | clock-mult = <1>; | |
1000 | clock-output-names = "imp"; | |
1001 | }; | |
1002 | rclk_clk: rclk_clk { | |
1003 | compatible = "fixed-factor-clock"; | |
1004 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
1005 | #clock-cells = <0>; | |
1006 | clock-div = <(48 * 1024)>; | |
1007 | clock-mult = <1>; | |
1008 | clock-output-names = "rclk"; | |
1009 | }; | |
1010 | oscclk_clk: oscclk_clk { | |
1011 | compatible = "fixed-factor-clock"; | |
1012 | clocks = <&cpg_clocks R8A7791_CLK_PLL1>; | |
1013 | #clock-cells = <0>; | |
1014 | clock-div = <(12 * 1024)>; | |
1015 | clock-mult = <1>; | |
1016 | clock-output-names = "oscclk"; | |
1017 | }; | |
1018 | zb3_clk: zb3_clk { | |
1019 | compatible = "fixed-factor-clock"; | |
1020 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
1021 | #clock-cells = <0>; | |
1022 | clock-div = <4>; | |
1023 | clock-mult = <1>; | |
1024 | clock-output-names = "zb3"; | |
1025 | }; | |
1026 | zb3d2_clk: zb3d2_clk { | |
1027 | compatible = "fixed-factor-clock"; | |
1028 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
1029 | #clock-cells = <0>; | |
1030 | clock-div = <8>; | |
1031 | clock-mult = <1>; | |
1032 | clock-output-names = "zb3d2"; | |
1033 | }; | |
1034 | ddr_clk: ddr_clk { | |
1035 | compatible = "fixed-factor-clock"; | |
1036 | clocks = <&cpg_clocks R8A7791_CLK_PLL3>; | |
1037 | #clock-cells = <0>; | |
1038 | clock-div = <8>; | |
1039 | clock-mult = <1>; | |
1040 | clock-output-names = "ddr"; | |
1041 | }; | |
1042 | mp_clk: mp_clk { | |
1043 | compatible = "fixed-factor-clock"; | |
1044 | clocks = <&pll1_div2_clk>; | |
1045 | #clock-cells = <0>; | |
1046 | clock-div = <15>; | |
1047 | clock-mult = <1>; | |
1048 | clock-output-names = "mp"; | |
1049 | }; | |
1050 | cp_clk: cp_clk { | |
1051 | compatible = "fixed-factor-clock"; | |
1052 | clocks = <&extal_clk>; | |
1053 | #clock-cells = <0>; | |
1054 | clock-div = <2>; | |
1055 | clock-mult = <1>; | |
1056 | clock-output-names = "cp"; | |
1057 | }; | |
1058 | ||
1059 | /* Gate clocks */ | |
cded80f8 LP |
1060 | mstp0_clks: mstp0_clks@e6150130 { |
1061 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1062 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; | |
1063 | clocks = <&mp_clk>; | |
1064 | #clock-cells = <1>; | |
cb0bf851 | 1065 | clock-indices = <R8A7791_CLK_MSIOF0>; |
cded80f8 LP |
1066 | clock-output-names = "msiof0"; |
1067 | }; | |
59e79895 LP |
1068 | mstp1_clks: mstp1_clks@e6150134 { |
1069 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1070 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
74d89d25 YH |
1071 | clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>, |
1072 | <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, | |
1073 | <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, | |
1074 | <&zs_clk>; | |
59e79895 | 1075 | #clock-cells = <1>; |
cb0bf851 | 1076 | clock-indices = < |
74d89d25 YH |
1077 | R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU |
1078 | R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG | |
1079 | R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 | |
1080 | R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 | |
1081 | R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0 | |
1082 | R8A7791_CLK_VSP1_S | |
59e79895 LP |
1083 | >; |
1084 | clock-output-names = | |
74d89d25 YH |
1085 | "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg", |
1086 | "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0", | |
1087 | "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy"; | |
59e79895 LP |
1088 | }; |
1089 | mstp2_clks: mstp2_clks@e6150138 { | |
1090 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1091 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
1092 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
4e074bc8 GU |
1093 | <&mp_clk>, <&mp_clk>, <&mp_clk>, |
1094 | <&zs_clk>, <&zs_clk>; | |
59e79895 | 1095 | #clock-cells = <1>; |
cb0bf851 | 1096 | clock-indices = < |
59e79895 | 1097 | R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 |
cded80f8 LP |
1098 | R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 |
1099 | R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 | |
4e074bc8 | 1100 | R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 |
59e79895 LP |
1101 | >; |
1102 | clock-output-names = | |
0c002ef8 | 1103 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
4e074bc8 GU |
1104 | "scifb1", "msiof1", "scifb2", |
1105 | "sys-dmac1", "sys-dmac0"; | |
59e79895 LP |
1106 | }; |
1107 | mstp3_clks: mstp3_clks@e615013c { | |
1108 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1109 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
c08691b5 | 1110 | clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, |
b9473d9f YS |
1111 | <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, |
1112 | <&hp_clk>, <&hp_clk>; | |
59e79895 | 1113 | #clock-cells = <1>; |
cb0bf851 | 1114 | clock-indices = < |
c08691b5 | 1115 | R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 |
4bfb3767 PE |
1116 | R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 |
1117 | R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 | |
b9473d9f | 1118 | R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1 |
59e79895 LP |
1119 | >; |
1120 | clock-output-names = | |
c08691b5 | 1121 | "tpu0", "sdhi2", "sdhi1", "sdhi0", |
b9473d9f YS |
1122 | "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1", |
1123 | "usbdmac0", "usbdmac1"; | |
59e79895 LP |
1124 | }; |
1125 | mstp5_clks: mstp5_clks@e6150144 { | |
1126 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1127 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; | |
8994fff6 | 1128 | clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; |
59e79895 | 1129 | #clock-cells = <1>; |
cb0bf851 BD |
1130 | clock-indices = < |
1131 | R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 | |
1132 | R8A7791_CLK_THERMAL R8A7791_CLK_PWM | |
1133 | >; | |
8994fff6 | 1134 | clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; |
59e79895 LP |
1135 | }; |
1136 | mstp7_clks: mstp7_clks@e615014c { | |
1137 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1138 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
6225b99a | 1139 | clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, |
59e79895 LP |
1140 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
1141 | <&zx_clk>, <&zx_clk>, <&zx_clk>; | |
1142 | #clock-cells = <1>; | |
cb0bf851 | 1143 | clock-indices = < |
6225b99a | 1144 | R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 |
59e79895 LP |
1145 | R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 |
1146 | R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 | |
1147 | R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 | |
1148 | R8A7791_CLK_LVDS0 | |
1149 | >; | |
1150 | clock-output-names = | |
6225b99a | 1151 | "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", |
59e79895 LP |
1152 | "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; |
1153 | }; | |
1154 | mstp8_clks: mstp8_clks@e6150990 { | |
1155 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1156 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
ce85ad47 RK |
1157 | clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, |
1158 | <&zs_clk>, <&zs_clk>; | |
59e79895 | 1159 | #clock-cells = <1>; |
cb0bf851 | 1160 | clock-indices = < |
ce85ad47 | 1161 | R8A7791_CLK_IPMMU_SGX |
09c98346 | 1162 | R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 |
65f05c38 | 1163 | R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 |
09c98346 | 1164 | >; |
65f05c38 | 1165 | clock-output-names = |
ce85ad47 RK |
1166 | "ipmmu_sgx", "vin2", "vin1", "vin0", "ether", "sata1", |
1167 | "sata0"; | |
59e79895 LP |
1168 | }; |
1169 | mstp9_clks: mstp9_clks@e6150994 { | |
1170 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1171 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
4faf9c5e GU |
1172 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
1173 | <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, | |
1174 | <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, | |
11b48db9 LP |
1175 | <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, |
1176 | <&hp_clk>, <&hp_clk>; | |
59e79895 | 1177 | #clock-cells = <1>; |
cb0bf851 | 1178 | clock-indices = < |
4faf9c5e GU |
1179 | R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 |
1180 | R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 | |
c08691b5 WS |
1181 | R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 |
1182 | R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 | |
1183 | R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 | |
59e79895 LP |
1184 | >; |
1185 | clock-output-names = | |
4faf9c5e GU |
1186 | "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", |
1187 | "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", | |
1188 | "i2c1", "i2c0"; | |
59e79895 | 1189 | }; |
ee914152 KM |
1190 | mstp10_clks: mstp10_clks@e6150998 { |
1191 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1192 | reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; | |
1193 | clocks = <&p_clk>, | |
1194 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
1195 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
1196 | <&p_clk>, | |
1197 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
1198 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
1199 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
1200 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
1201 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, | |
1202 | <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; | |
1203 | ||
1204 | #clock-cells = <1>; | |
1205 | clock-indices = < | |
1206 | R8A7791_CLK_SSI_ALL | |
1207 | R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 | |
1208 | R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 | |
1209 | R8A7791_CLK_SCU_ALL | |
1210 | R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 | |
1211 | R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 | |
1212 | R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 | |
1213 | >; | |
1214 | clock-output-names = | |
1215 | "ssi-all", | |
1216 | "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", | |
1217 | "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", | |
1218 | "scu-all", | |
1219 | "scu-dvc1", "scu-dvc0", | |
1220 | "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", | |
1221 | "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; | |
1222 | }; | |
59e79895 LP |
1223 | mstp11_clks: mstp11_clks@e615099c { |
1224 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1225 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; | |
1226 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; | |
1227 | #clock-cells = <1>; | |
cb0bf851 | 1228 | clock-indices = < |
59e79895 LP |
1229 | R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 |
1230 | >; | |
1231 | clock-output-names = "scifa3", "scifa4", "scifa5"; | |
1232 | }; | |
1233 | }; | |
4d5b59cd | 1234 | |
6f3e4ee3 | 1235 | qspi: spi@e6b10000 { |
4d5b59cd GU |
1236 | compatible = "renesas,qspi-r8a7791", "renesas,qspi"; |
1237 | reg = <0 0xe6b10000 0 0x2c>; | |
4d5b59cd GU |
1238 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
1239 | clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; | |
591f2fa4 GU |
1240 | dmas = <&dmac0 0x17>, <&dmac0 0x18>; |
1241 | dma-names = "tx", "rx"; | |
4d5b59cd GU |
1242 | num-cs = <1>; |
1243 | #address-cells = <1>; | |
1244 | #size-cells = <0>; | |
1245 | status = "disabled"; | |
1246 | }; | |
7713d3ab GU |
1247 | |
1248 | msiof0: spi@e6e20000 { | |
1249 | compatible = "renesas,msiof-r8a7791"; | |
a5ce27f5 | 1250 | reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; |
7713d3ab GU |
1251 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; |
1252 | clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; | |
a5ce27f5 GU |
1253 | dmas = <&dmac0 0x51>, <&dmac0 0x52>; |
1254 | dma-names = "tx", "rx"; | |
7713d3ab GU |
1255 | #address-cells = <1>; |
1256 | #size-cells = <0>; | |
1257 | status = "disabled"; | |
1258 | }; | |
1259 | ||
1260 | msiof1: spi@e6e10000 { | |
1261 | compatible = "renesas,msiof-r8a7791"; | |
a5ce27f5 | 1262 | reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>; |
7713d3ab GU |
1263 | interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; |
1264 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; | |
a5ce27f5 GU |
1265 | dmas = <&dmac0 0x55>, <&dmac0 0x56>; |
1266 | dma-names = "tx", "rx"; | |
7713d3ab GU |
1267 | #address-cells = <1>; |
1268 | #size-cells = <0>; | |
1269 | status = "disabled"; | |
1270 | }; | |
1271 | ||
1272 | msiof2: spi@e6e00000 { | |
1273 | compatible = "renesas,msiof-r8a7791"; | |
a5ce27f5 | 1274 | reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>; |
7713d3ab GU |
1275 | interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; |
1276 | clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; | |
a5ce27f5 GU |
1277 | dmas = <&dmac0 0x41>, <&dmac0 0x42>; |
1278 | dma-names = "tx", "rx"; | |
7713d3ab GU |
1279 | #address-cells = <1>; |
1280 | #size-cells = <0>; | |
1281 | status = "disabled"; | |
1282 | }; | |
811cdfae | 1283 | |
c196931e YS |
1284 | xhci: usb@ee000000 { |
1285 | compatible = "renesas,xhci-r8a7791"; | |
1286 | reg = <0 0xee000000 0 0xc00>; | |
1287 | interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; | |
1288 | clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; | |
1289 | phys = <&usb2 1>; | |
1290 | phy-names = "usb"; | |
1291 | status = "disabled"; | |
1292 | }; | |
1293 | ||
aace0809 SS |
1294 | pci0: pci@ee090000 { |
1295 | compatible = "renesas,pci-r8a7791"; | |
1296 | device_type = "pci"; | |
1297 | clocks = <&mstp7_clks R8A7791_CLK_EHCI>; | |
1298 | reg = <0 0xee090000 0 0xc00>, | |
1299 | <0 0xee080000 0 0x1100>; | |
1300 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | |
1301 | status = "disabled"; | |
1302 | ||
1303 | bus-range = <0 0>; | |
1304 | #address-cells = <3>; | |
1305 | #size-cells = <2>; | |
1306 | #interrupt-cells = <1>; | |
1307 | ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; | |
1308 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
1309 | interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH | |
1310 | 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH | |
1311 | 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; | |
e1bce124 SS |
1312 | |
1313 | usb@0,1 { | |
1314 | reg = <0x800 0 0 0 0>; | |
1315 | device_type = "pci"; | |
1316 | phys = <&usb0 0>; | |
1317 | phy-names = "usb"; | |
1318 | }; | |
1319 | ||
1320 | usb@0,2 { | |
1321 | reg = <0x1000 0 0 0 0>; | |
1322 | device_type = "pci"; | |
1323 | phys = <&usb0 0>; | |
1324 | phy-names = "usb"; | |
1325 | }; | |
aace0809 SS |
1326 | }; |
1327 | ||
1328 | pci1: pci@ee0d0000 { | |
1329 | compatible = "renesas,pci-r8a7791"; | |
1330 | device_type = "pci"; | |
1331 | clocks = <&mstp7_clks R8A7791_CLK_EHCI>; | |
1332 | reg = <0 0xee0d0000 0 0xc00>, | |
1333 | <0 0xee0c0000 0 0x1100>; | |
1334 | interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; | |
1335 | status = "disabled"; | |
1336 | ||
1337 | bus-range = <1 1>; | |
1338 | #address-cells = <3>; | |
1339 | #size-cells = <2>; | |
1340 | #interrupt-cells = <1>; | |
1341 | ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; | |
1342 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
1343 | interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH | |
1344 | 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH | |
1345 | 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; | |
e1bce124 SS |
1346 | |
1347 | usb@0,1 { | |
1348 | reg = <0x800 0 0 0 0>; | |
1349 | device_type = "pci"; | |
1350 | phys = <&usb2 0>; | |
1351 | phy-names = "usb"; | |
1352 | }; | |
1353 | ||
1354 | usb@0,2 { | |
1355 | reg = <0x1000 0 0 0 0>; | |
1356 | device_type = "pci"; | |
1357 | phys = <&usb2 0>; | |
1358 | phy-names = "usb"; | |
1359 | }; | |
aace0809 SS |
1360 | }; |
1361 | ||
811cdfae PE |
1362 | pciec: pcie@fe000000 { |
1363 | compatible = "renesas,pcie-r8a7791"; | |
1364 | reg = <0 0xfe000000 0 0x80000>; | |
1365 | #address-cells = <3>; | |
1366 | #size-cells = <2>; | |
1367 | bus-range = <0x00 0xff>; | |
1368 | device_type = "pci"; | |
1369 | ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 | |
1370 | 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 | |
1371 | 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 | |
1372 | 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; | |
1373 | /* Map all possible DDR as inbound ranges */ | |
1374 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 | |
1375 | 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; | |
1376 | interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, | |
1377 | <0 117 IRQ_TYPE_LEVEL_HIGH>, | |
1378 | <0 118 IRQ_TYPE_LEVEL_HIGH>; | |
1379 | #interrupt-cells = <1>; | |
1380 | interrupt-map-mask = <0 0 0 0>; | |
1381 | interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; | |
1382 | clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; | |
1383 | clock-names = "pcie", "pcie_bus"; | |
1384 | status = "disabled"; | |
1385 | }; | |
09abd1fd | 1386 | |
6b83dc1d | 1387 | rcar_sound: rcar_sound@ec500000 { |
09abd1fd KM |
1388 | #sound-dai-cells = <1>; |
1389 | compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; | |
09abd1fd KM |
1390 | reg = <0 0xec500000 0 0x1000>, /* SCU */ |
1391 | <0 0xec5a0000 0 0x100>, /* ADG */ | |
1392 | <0 0xec540000 0 0x1000>, /* SSIU */ | |
1393 | <0 0xec541000 0 0x1280>; /* SSI */ | |
1394 | clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, | |
1395 | <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, | |
1396 | <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>, | |
1397 | <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>, | |
1398 | <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>, | |
1399 | <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>, | |
1400 | <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>, | |
1401 | <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>, | |
1402 | <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, | |
1403 | <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, | |
1404 | <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, | |
150c8ad4 | 1405 | <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, |
09abd1fd KM |
1406 | <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; |
1407 | clock-names = "ssi-all", | |
1408 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", | |
1409 | "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", | |
1410 | "src.9", "src.8", "src.7", "src.6", "src.5", | |
1411 | "src.4", "src.3", "src.2", "src.1", "src.0", | |
150c8ad4 | 1412 | "dvc.0", "dvc.1", |
09abd1fd KM |
1413 | "clk_a", "clk_b", "clk_c", "clk_i"; |
1414 | ||
1415 | status = "disabled"; | |
1416 | ||
150c8ad4 KM |
1417 | rcar_sound,dvc { |
1418 | dvc0: dvc@0 { }; | |
1419 | dvc1: dvc@1 { }; | |
1420 | }; | |
1421 | ||
09abd1fd KM |
1422 | rcar_sound,src { |
1423 | src0: src@0 { }; | |
1424 | src1: src@1 { }; | |
1425 | src2: src@2 { }; | |
1426 | src3: src@3 { }; | |
1427 | src4: src@4 { }; | |
1428 | src5: src@5 { }; | |
1429 | src6: src@6 { }; | |
1430 | src7: src@7 { }; | |
1431 | src8: src@8 { }; | |
1432 | src9: src@9 { }; | |
1433 | }; | |
1434 | ||
1435 | rcar_sound,ssi { | |
1436 | ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; }; | |
1437 | ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; }; | |
1438 | ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; }; | |
1439 | ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; }; | |
1440 | ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; }; | |
1441 | ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; }; | |
1442 | ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; }; | |
1443 | ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; }; | |
1444 | ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; }; | |
1445 | ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; }; | |
1446 | }; | |
1447 | }; | |
0d0771ab | 1448 | }; |