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7c4163aa SS |
1 | /* |
2 | * Device Tree Source for the r8a7792 SoC | |
3 | * | |
4 | * Copyright (C) 2016 Cogent Embedded Inc. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <dt-bindings/clock/r8a7792-clock.h> | |
12 | #include <dt-bindings/interrupt-controller/irq.h> | |
13 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
14 | #include <dt-bindings/power/r8a7792-sysc.h> | |
15 | ||
16 | / { | |
17 | compatible = "renesas,r8a7792"; | |
18 | #address-cells = <2>; | |
19 | #size-cells = <2>; | |
20 | ||
21 | cpus { | |
22 | #address-cells = <1>; | |
23 | #size-cells = <0>; | |
8fd763c7 | 24 | enable-method = "renesas,apmu"; |
7c4163aa SS |
25 | |
26 | cpu0: cpu@0 { | |
27 | device_type = "cpu"; | |
28 | compatible = "arm,cortex-a15"; | |
29 | reg = <0>; | |
30 | clock-frequency = <1000000000>; | |
31 | clocks = <&cpg_clocks R8A7792_CLK_Z>; | |
32 | power-domains = <&sysc R8A7792_PD_CA15_CPU0>; | |
33 | next-level-cache = <&L2_CA15>; | |
34 | }; | |
35 | ||
8fd763c7 SS |
36 | cpu1: cpu@1 { |
37 | device_type = "cpu"; | |
38 | compatible = "arm,cortex-a15"; | |
39 | reg = <1>; | |
40 | clock-frequency = <1000000000>; | |
41 | power-domains = <&sysc R8A7792_PD_CA15_CPU1>; | |
42 | next-level-cache = <&L2_CA15>; | |
43 | }; | |
44 | ||
7c4163aa SS |
45 | L2_CA15: cache-controller@0 { |
46 | compatible = "cache"; | |
47 | reg = <0>; | |
48 | cache-unified; | |
49 | cache-level = <2>; | |
50 | power-domains = <&sysc R8A7792_PD_CA15_SCU>; | |
51 | }; | |
52 | }; | |
53 | ||
54 | soc { | |
55 | compatible = "simple-bus"; | |
56 | interrupt-parent = <&gic>; | |
57 | ||
58 | #address-cells = <2>; | |
59 | #size-cells = <2>; | |
60 | ranges; | |
61 | ||
8fd763c7 SS |
62 | apmu@e6152000 { |
63 | compatible = "renesas,r8a7792-apmu", "renesas,apmu"; | |
64 | reg = <0 0xe6152000 0 0x188>; | |
65 | cpus = <&cpu0 &cpu1>; | |
66 | }; | |
67 | ||
7c4163aa SS |
68 | gic: interrupt-controller@f1001000 { |
69 | compatible = "arm,gic-400"; | |
70 | #interrupt-cells = <3>; | |
71 | interrupt-controller; | |
72 | reg = <0 0xf1001000 0 0x1000>, | |
73 | <0 0xf1002000 0 0x1000>, | |
74 | <0 0xf1004000 0 0x2000>, | |
75 | <0 0xf1006000 0 0x2000>; | |
76 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | | |
77 | IRQ_TYPE_LEVEL_HIGH)>; | |
78 | }; | |
79 | ||
56efdbe5 SS |
80 | irqc: interrupt-controller@e61c0000 { |
81 | compatible = "renesas,irqc-r8a7792", "renesas,irqc"; | |
82 | #interrupt-cells = <2>; | |
83 | interrupt-controller; | |
84 | reg = <0 0xe61c0000 0 0x200>; | |
85 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
86 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
87 | <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
88 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
89 | clocks = <&mstp4_clks R8A7792_CLK_IRQC>; | |
90 | power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; | |
91 | }; | |
92 | ||
7c4163aa SS |
93 | timer { |
94 | compatible = "arm,armv7-timer"; | |
95 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | | |
96 | IRQ_TYPE_LEVEL_LOW)>, | |
97 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | | |
98 | IRQ_TYPE_LEVEL_LOW)>, | |
99 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | | |
100 | IRQ_TYPE_LEVEL_LOW)>, | |
101 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | | |
102 | IRQ_TYPE_LEVEL_LOW)>; | |
103 | }; | |
104 | ||
105 | sysc: system-controller@e6180000 { | |
106 | compatible = "renesas,r8a7792-sysc"; | |
107 | reg = <0 0xe6180000 0 0x0200>; | |
108 | #power-domain-cells = <1>; | |
109 | }; | |
110 | ||
fdf8ec0a SS |
111 | dmac0: dma-controller@e6700000 { |
112 | compatible = "renesas,dmac-r8a7792", | |
113 | "renesas,rcar-dmac"; | |
114 | reg = <0 0xe6700000 0 0x20000>; | |
115 | interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH | |
116 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH | |
117 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH | |
118 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH | |
119 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH | |
120 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH | |
121 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH | |
122 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH | |
123 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH | |
124 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH | |
125 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH | |
126 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH | |
127 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH | |
128 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH | |
129 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH | |
130 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; | |
131 | interrupt-names = "error", | |
132 | "ch0", "ch1", "ch2", "ch3", | |
133 | "ch4", "ch5", "ch6", "ch7", | |
134 | "ch8", "ch9", "ch10", "ch11", | |
135 | "ch12", "ch13", "ch14"; | |
136 | clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>; | |
137 | clock-names = "fck"; | |
138 | power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; | |
139 | #dma-cells = <1>; | |
140 | dma-channels = <15>; | |
141 | }; | |
142 | ||
143 | dmac1: dma-controller@e6720000 { | |
144 | compatible = "renesas,dmac-r8a7792", | |
145 | "renesas,rcar-dmac"; | |
146 | reg = <0 0xe6720000 0 0x20000>; | |
147 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH | |
148 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH | |
149 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH | |
150 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH | |
151 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH | |
152 | GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH | |
153 | GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH | |
154 | GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH | |
155 | GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH | |
156 | GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH | |
157 | GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH | |
158 | GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH | |
159 | GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH | |
160 | GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH | |
161 | GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH | |
162 | GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; | |
163 | interrupt-names = "error", | |
164 | "ch0", "ch1", "ch2", "ch3", | |
165 | "ch4", "ch5", "ch6", "ch7", | |
166 | "ch8", "ch9", "ch10", "ch11", | |
167 | "ch12", "ch13", "ch14"; | |
168 | clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>; | |
169 | clock-names = "fck"; | |
170 | power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; | |
171 | #dma-cells = <1>; | |
172 | dma-channels = <15>; | |
173 | }; | |
174 | ||
e66796b9 SS |
175 | scif0: serial@e6e60000 { |
176 | compatible = "renesas,scif-r8a7792", | |
177 | "renesas,rcar-gen2-scif", "renesas,scif"; | |
178 | reg = <0 0xe6e60000 0 64>; | |
179 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
180 | clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>, | |
181 | <&scif_clk>; | |
182 | clock-names = "fck", "brg_int", "scif_clk"; | |
183 | dmas = <&dmac0 0x29>, <&dmac0 0x2a>, | |
184 | <&dmac1 0x29>, <&dmac1 0x2a>; | |
185 | dma-names = "tx", "rx", "tx", "rx"; | |
186 | power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; | |
187 | status = "disabled"; | |
188 | }; | |
189 | ||
190 | scif1: serial@e6e68000 { | |
191 | compatible = "renesas,scif-r8a7792", | |
192 | "renesas,rcar-gen2-scif", "renesas,scif"; | |
193 | reg = <0 0xe6e68000 0 64>; | |
194 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; | |
195 | clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>, | |
196 | <&scif_clk>; | |
197 | clock-names = "fck", "brg_int", "scif_clk"; | |
198 | dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, | |
199 | <&dmac1 0x2d>, <&dmac1 0x2e>; | |
200 | dma-names = "tx", "rx", "tx", "rx"; | |
201 | power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; | |
202 | status = "disabled"; | |
203 | }; | |
204 | ||
205 | scif2: serial@e6e58000 { | |
206 | compatible = "renesas,scif-r8a7792", | |
207 | "renesas,rcar-gen2-scif", "renesas,scif"; | |
208 | reg = <0 0xe6e58000 0 64>; | |
209 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
210 | clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>, | |
211 | <&scif_clk>; | |
212 | clock-names = "fck", "brg_int", "scif_clk"; | |
213 | dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, | |
214 | <&dmac1 0x2b>, <&dmac1 0x2c>; | |
215 | dma-names = "tx", "rx", "tx", "rx"; | |
216 | power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; | |
217 | status = "disabled"; | |
218 | }; | |
219 | ||
220 | scif3: serial@e6ea8000 { | |
221 | compatible = "renesas,scif-r8a7792", | |
222 | "renesas,rcar-gen2-scif", "renesas,scif"; | |
223 | reg = <0 0xe6ea8000 0 64>; | |
224 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
225 | clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>, | |
226 | <&scif_clk>; | |
227 | clock-names = "fck", "brg_int", "scif_clk"; | |
228 | dmas = <&dmac0 0x2f>, <&dmac0 0x30>, | |
229 | <&dmac1 0x2f>, <&dmac1 0x30>; | |
230 | dma-names = "tx", "rx", "tx", "rx"; | |
231 | power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; | |
232 | status = "disabled"; | |
233 | }; | |
234 | ||
235 | hscif0: serial@e62c0000 { | |
236 | compatible = "renesas,hscif-r8a7792", | |
237 | "renesas,rcar-gen2-hscif", "renesas,hscif"; | |
238 | reg = <0 0xe62c0000 0 96>; | |
239 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
240 | clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>, | |
241 | <&scif_clk>; | |
242 | clock-names = "fck", "brg_int", "scif_clk"; | |
243 | dmas = <&dmac0 0x39>, <&dmac0 0x3a>, | |
244 | <&dmac1 0x39>, <&dmac1 0x3a>; | |
245 | dma-names = "tx", "rx", "tx", "rx"; | |
246 | power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; | |
247 | status = "disabled"; | |
248 | }; | |
249 | ||
250 | hscif1: serial@e62c8000 { | |
251 | compatible = "renesas,hscif-r8a7792", | |
252 | "renesas,rcar-gen2-hscif", "renesas,hscif"; | |
253 | reg = <0 0xe62c8000 0 96>; | |
254 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; | |
255 | clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>, | |
256 | <&scif_clk>; | |
257 | clock-names = "fck", "brg_int", "scif_clk"; | |
258 | dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, | |
259 | <&dmac1 0x4d>, <&dmac1 0x4e>; | |
260 | dma-names = "tx", "rx", "tx", "rx"; | |
261 | power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; | |
262 | status = "disabled"; | |
263 | }; | |
264 | ||
3e1839e9 SS |
265 | jpu: jpeg-codec@fe980000 { |
266 | compatible = "renesas,jpu-r8a7792", | |
267 | "renesas,rcar-gen2-jpu"; | |
268 | reg = <0 0xfe980000 0 0x10300>; | |
269 | interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; | |
270 | clocks = <&mstp1_clks R8A7792_CLK_JPU>; | |
271 | power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; | |
272 | }; | |
273 | ||
7c4163aa SS |
274 | /* Special CPG clocks */ |
275 | cpg_clocks: cpg_clocks@e6150000 { | |
276 | compatible = "renesas,r8a7792-cpg-clocks", | |
277 | "renesas,rcar-gen2-cpg-clocks"; | |
278 | reg = <0 0xe6150000 0 0x1000>; | |
279 | clocks = <&extal_clk>; | |
280 | #clock-cells = <1>; | |
281 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
e0c3f92a | 282 | "lb", "qspi", "z"; |
7c4163aa SS |
283 | #power-domain-cells = <0>; |
284 | }; | |
285 | ||
286 | /* Fixed factor clocks */ | |
4b9b7b3a SS |
287 | pll1_div2_clk: pll1_div2 { |
288 | compatible = "fixed-factor-clock"; | |
289 | clocks = <&cpg_clocks R8A7792_CLK_PLL1>; | |
290 | #clock-cells = <0>; | |
291 | clock-div = <2>; | |
292 | clock-mult = <1>; | |
293 | }; | |
7c4163aa SS |
294 | zs_clk: zs { |
295 | compatible = "fixed-factor-clock"; | |
296 | clocks = <&cpg_clocks R8A7792_CLK_PLL1>; | |
297 | #clock-cells = <0>; | |
298 | clock-div = <6>; | |
299 | clock-mult = <1>; | |
300 | }; | |
301 | p_clk: p { | |
302 | compatible = "fixed-factor-clock"; | |
303 | clocks = <&cpg_clocks R8A7792_CLK_PLL1>; | |
304 | #clock-cells = <0>; | |
305 | clock-div = <24>; | |
306 | clock-mult = <1>; | |
307 | }; | |
308 | cp_clk: cp { | |
309 | compatible = "fixed-factor-clock"; | |
310 | clocks = <&cpg_clocks R8A7792_CLK_PLL1>; | |
311 | #clock-cells = <0>; | |
312 | clock-div = <48>; | |
313 | clock-mult = <1>; | |
314 | }; | |
eebc8e2c SS |
315 | m2_clk: m2 { |
316 | compatible = "fixed-factor-clock"; | |
317 | clocks = <&cpg_clocks R8A7792_CLK_PLL1>; | |
318 | #clock-cells = <0>; | |
319 | clock-div = <8>; | |
320 | clock-mult = <1>; | |
321 | }; | |
7c4163aa SS |
322 | |
323 | /* Gate clocks */ | |
eebc8e2c SS |
324 | mstp1_clks: mstp1_clks@e6150134 { |
325 | compatible = "renesas,r8a7792-mstp-clocks", | |
326 | "renesas,cpg-mstp-clocks"; | |
327 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
328 | clocks = <&m2_clk>; | |
329 | #clock-cells = <1>; | |
330 | clock-indices = <R8A7792_CLK_JPU>; | |
331 | clock-output-names = "jpu"; | |
332 | }; | |
7c4163aa SS |
333 | mstp2_clks: mstp2_clks@e6150138 { |
334 | compatible = "renesas,r8a7792-mstp-clocks", | |
335 | "renesas,cpg-mstp-clocks"; | |
336 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
337 | clocks = <&zs_clk>, <&zs_clk>; | |
338 | #clock-cells = <1>; | |
339 | clock-indices = < | |
340 | R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0 | |
341 | >; | |
342 | clock-output-names = "sys-dmac1", "sys-dmac0"; | |
343 | }; | |
344 | mstp4_clks: mstp4_clks@e6150140 { | |
345 | compatible = "renesas,r8a7792-mstp-clocks", | |
346 | "renesas,cpg-mstp-clocks"; | |
347 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; | |
348 | clocks = <&cp_clk>; | |
349 | #clock-cells = <1>; | |
350 | clock-indices = <R8A7792_CLK_IRQC>; | |
351 | clock-output-names = "irqc"; | |
352 | }; | |
353 | mstp7_clks: mstp7_clks@e615014c { | |
354 | compatible = "renesas,r8a7792-mstp-clocks", | |
355 | "renesas,cpg-mstp-clocks"; | |
356 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
357 | clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, | |
358 | <&p_clk>, <&p_clk>; | |
359 | #clock-cells = <1>; | |
360 | clock-indices = < | |
361 | R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0 | |
362 | R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2 | |
363 | R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0 | |
364 | >; | |
365 | clock-output-names = "hscif1", "hscif0", "scif3", | |
366 | "scif2", "scif1", "scif0"; | |
367 | }; | |
368 | }; | |
369 | ||
370 | /* External root clock */ | |
371 | extal_clk: extal { | |
372 | compatible = "fixed-clock"; | |
373 | #clock-cells = <0>; | |
374 | /* This value must be overridden by the board. */ | |
375 | clock-frequency = <0>; | |
376 | }; | |
377 | ||
378 | /* External SCIF clock */ | |
379 | scif_clk: scif { | |
380 | compatible = "fixed-clock"; | |
381 | #clock-cells = <0>; | |
382 | /* This value must be overridden by the board. */ | |
383 | clock-frequency = <0>; | |
384 | }; | |
385 | }; |