ARM: dts: r8a7794: Add BRG support for (H)SCIF
[deliverable/linux.git] / arch / arm / boot / dts / r8a7794-alt.dts
CommitLineData
a742795b
UH
1/*
2 * Device Tree Source for the Alt board
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "r8a7794.dtsi"
13
14/ {
15 model = "Alt";
16 compatible = "renesas,alt", "renesas,r8a7794";
17
18 aliases {
19 serial0 = &scif2;
20 };
21
22 chosen {
89aeff99 23 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
b575f994 24 stdout-path = "serial0:115200n8";
a742795b
UH
25 };
26
27 memory@40000000 {
28 device_type = "memory";
29 reg = <0 0x40000000 0 0x40000000>;
30 };
31
32 lbsc {
33 #address-cells = <1>;
34 #size-cells = <1>;
35 };
876e7fb9
MD
36
37 vga-encoder {
38 compatible = "adi,adv7123";
39
40 ports {
41 #address-cells = <1>;
42 #size-cells = <0>;
43
44 port@0 {
45 reg = <0>;
46 adv7123_in: endpoint {
47 remote-endpoint = <&du_out_rgb1>;
48 };
49 };
50 port@1 {
51 reg = <1>;
52 adv7123_out: endpoint {
53 remote-endpoint = <&vga_in>;
54 };
55 };
56 };
57 };
58
59 vga {
60 compatible = "vga-connector";
61
62 port {
63 vga_in: endpoint {
64 remote-endpoint = <&adv7123_out>;
65 };
66 };
67 };
68
69 x2_clk: x2-clock {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <74250000>;
73 };
74
75 x13_clk: x13-clock {
76 compatible = "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <148500000>;
79 };
80};
81
82&du {
13b8b8e8
MD
83 pinctrl-0 = <&du_pins>;
84 pinctrl-names = "default";
876e7fb9
MD
85 status = "okay";
86
87 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
88 <&mstp7_clks R8A7794_CLK_DU0>,
89 <&x13_clk>, <&x2_clk>;
90 clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
91
92 ports {
93 port@1 {
94 endpoint {
95 remote-endpoint = <&adv7123_in>;
96 };
97 };
98 };
a742795b
UH
99};
100
101&extal_clk {
102 clock-frequency = <20000000>;
103};
104
22b16071 105&pfc {
13b8b8e8
MD
106 du_pins: du {
107 renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
108 renesas,function = "du";
109 };
110
22b16071
SH
111 scif2_pins: serial2 {
112 renesas,groups = "scif2_data";
113 renesas,function = "scif2";
114 };
115
116 ether_pins: ether {
117 renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
118 renesas,function = "eth";
119 };
120
c175e7ab
SH
121 phy1_pins: phy1 {
122 renesas,groups = "intc_irq8";
123 renesas,function = "intc";
22b16071 124 };
7f81bf72
UH
125
126 i2c1_pins: i2c1 {
127 renesas,groups = "i2c1";
128 renesas,function = "i2c1";
129 };
d537543b
UH
130
131 vin0_pins: vin0 {
132 renesas,groups = "vin0_data8", "vin0_clk";
133 renesas,function = "vin0";
134 };
22b16071
SH
135};
136
a742795b 137&cmt0 {
38e02908 138 status = "okay";
a742795b
UH
139};
140
6b78e6ae
SH
141&pfc {
142 qspi_pins: spi0 {
143 renesas,groups = "qspi_ctrl", "qspi_data4";
144 renesas,function = "qspi";
145 };
146};
147
a895b7cd 148&ether {
c175e7ab
SH
149 pinctrl-0 = <&ether_pins &phy1_pins>;
150 pinctrl-names = "default";
151
a895b7cd
LP
152 phy-handle = <&phy1>;
153 renesas,ether-link-active-low;
154 status = "okay";
155
156 phy1: ethernet-phy@1 {
157 reg = <1>;
158 interrupt-parent = <&irqc0>;
1fc58015 159 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
a895b7cd
LP
160 micrel,led-mode = <1>;
161 };
162};
163
7f81bf72
UH
164&i2c1 {
165 pinctrl-0 = <&i2c1_pins>;
166 pinctrl-names = "default";
167
168 status = "okay";
169 clock-frequency = <400000>;
d537543b
UH
170
171 composite-in@20 {
172 compatible = "adi,adv7180";
173 reg = <0x20>;
174 remote = <&vin0>;
175
176 port {
177 adv7180: endpoint {
178 bus-width = <8>;
179 remote-endpoint = <&vin0ep>;
180 };
181 };
182 };
183};
184
185&vin0 {
186 status = "okay";
187 pinctrl-0 = <&vin0_pins>;
188 pinctrl-names = "default";
189
190 port {
191 #address-cells = <1>;
192 #size-cells = <0>;
193
194 vin0ep: endpoint {
195 remote-endpoint = <&adv7180>;
196 bus-width = <8>;
197 };
198 };
7f81bf72
UH
199};
200
a742795b 201&scif2 {
7256587c
SH
202 pinctrl-0 = <&scif2_pins>;
203 pinctrl-names = "default";
204
38e02908 205 status = "okay";
a742795b 206};
6b78e6ae
SH
207
208&qspi {
209 pinctrl-0 = <&qspi_pins>;
210 pinctrl-names = "default";
211
212 status = "okay";
213
214 flash@0 {
215 compatible = "spansion,s25fl512s", "jedec,spi-nor";
216 reg = <0>;
217 spi-max-frequency = <30000000>;
218 spi-tx-bus-width = <4>;
219 spi-rx-bus-width = <4>;
220 spi-cpol;
221 spi-cpha;
222 m25p,fast-read;
223
224 partitions {
225 compatible = "fixed-partitions";
226 #address-cells = <1>;
227 #size-cells = <1>;
228
229 partition@0 {
230 label = "loader";
231 reg = <0x00000000 0x00040000>;
232 read-only;
233 };
234 partition@40000 {
235 label = "system";
236 reg = <0x00040000 0x00040000>;
237 read-only;
238 };
239 partition@80000 {
240 label = "user";
241 reg = <0x00080000 0x03f80000>;
242 };
243 };
244 };
245};
This page took 0.102812 seconds and 5 git commands to generate.