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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
[deliverable/linux.git] / arch / arm / boot / dts / r8a7794.dtsi
CommitLineData
0dce5454
UH		 1/*
2 * Device Tree Source for the r8a7794 SoC
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <dt-bindings/clock/r8a7794-clock.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
16/ {
17 compatible = "renesas,r8a7794";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
740b4a9f 22 aliases {
5428521b
SS		 23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
aa9b992e
SH		 29 i2c6 = &i2c6;
30 i2c7 = &i2c7;
740b4a9f 31 spi0 = &qspi;
1afe77ca
SS		 32 vin0 = &vin0;
33 vin1 = &vin1;
740b4a9f
SS		 34 };
35
0dce5454
UH		 36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a7";
43 reg = <0>;
44 clock-frequency = <1000000000>;
d12a384a 45 next-level-cache = <&L2_CA7>;
0dce5454
UH		 46 };
47
48 cpu1: cpu@1 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a7";
51 reg = <1>;
52 clock-frequency = <1000000000>;
d12a384a 53 next-level-cache = <&L2_CA7>;
0dce5454
UH		 54 };
55 };
56
d12a384a
GU		 57 L2_CA7: cache-controller@1 {
58 compatible = "cache";
59 cache-unified;
60 cache-level = <2>;
61 };
62
0dce5454 63 gic: interrupt-controller@f1001000 {
c73ddf42 64 compatible = "arm,gic-400";
0dce5454
UH		 65 #interrupt-cells = <3>;
66 #address-cells = <0>;
67 interrupt-controller;
68 reg = <0 0xf1001000 0 0x1000>,
69 <0 0xf1002000 0 0x1000>,
70 <0 0xf1004000 0 0x2000>,
71 <0 0xf1006000 0 0x2000>;
8d47e6af 72 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0dce5454
UH		 73 };
74
e8f5de3b
SS		 75 gpio0: gpio@e6050000 {
76 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
77 reg = <0 0xe6050000 0 0x50>;
8d47e6af 78 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
e8f5de3b
SS		 79 #gpio-cells = <2>;
80 gpio-controller;
81 gpio-ranges = <&pfc 0 0 32>;
82 #interrupt-cells = <2>;
83 interrupt-controller;
84 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
85 power-domains = <&cpg_clocks>;
86 };
87
88 gpio1: gpio@e6051000 {
89 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
90 reg = <0 0xe6051000 0 0x50>;
8d47e6af 91 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
e8f5de3b
SS		 92 #gpio-cells = <2>;
93 gpio-controller;
94 gpio-ranges = <&pfc 0 32 26>;
95 #interrupt-cells = <2>;
96 interrupt-controller;
97 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
98 power-domains = <&cpg_clocks>;
99 };
100
101 gpio2: gpio@e6052000 {
102 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
103 reg = <0 0xe6052000 0 0x50>;
8d47e6af 104 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
e8f5de3b
SS		 105 #gpio-cells = <2>;
106 gpio-controller;
107 gpio-ranges = <&pfc 0 64 32>;
108 #interrupt-cells = <2>;
109 interrupt-controller;
110 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
111 power-domains = <&cpg_clocks>;
112 };
113
114 gpio3: gpio@e6053000 {
115 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
116 reg = <0 0xe6053000 0 0x50>;
8d47e6af 117 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
e8f5de3b
SS		 118 #gpio-cells = <2>;
119 gpio-controller;
120 gpio-ranges = <&pfc 0 96 32>;
121 #interrupt-cells = <2>;
122 interrupt-controller;
123 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
124 power-domains = <&cpg_clocks>;
125 };
126
127 gpio4: gpio@e6054000 {
128 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
129 reg = <0 0xe6054000 0 0x50>;
8d47e6af 130 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
e8f5de3b
SS		 131 #gpio-cells = <2>;
132 gpio-controller;
133 gpio-ranges = <&pfc 0 128 32>;
134 #interrupt-cells = <2>;
135 interrupt-controller;
136 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
137 power-domains = <&cpg_clocks>;
138 };
139
140 gpio5: gpio@e6055000 {
141 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
142 reg = <0 0xe6055000 0 0x50>;
8d47e6af 143 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
e8f5de3b
SS		 144 #gpio-cells = <2>;
145 gpio-controller;
146 gpio-ranges = <&pfc 0 160 28>;
147 #interrupt-cells = <2>;
148 interrupt-controller;
149 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
150 power-domains = <&cpg_clocks>;
151 };
152
153 gpio6: gpio@e6055400 {
154 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
155 reg = <0 0xe6055400 0 0x50>;
8d47e6af 156 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
e8f5de3b
SS		 157 #gpio-cells = <2>;
158 gpio-controller;
159 gpio-ranges = <&pfc 0 192 26>;
160 #interrupt-cells = <2>;
161 interrupt-controller;
162 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
163 power-domains = <&cpg_clocks>;
164 };
165
0dce5454
UH		 166 cmt0: timer@ffca0000 {
167 compatible = "renesas,cmt-48-gen2";
168 reg = <0 0xffca0000 0 0x1004>;
8d47e6af
SH		 169 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0dce5454
UH		 171 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
172 clock-names = "fck";
60c0745a 173 power-domains = <&cpg_clocks>;
0dce5454
UH		 174
175 renesas,channels-mask = <0x60>;
176
177 status = "disabled";
178 };
179
180 cmt1: timer@e6130000 {
181 compatible = "renesas,cmt-48-gen2";
182 reg = <0 0xe6130000 0 0x1004>;
8d47e6af
SH		 183 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
0dce5454
UH		 191 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
192 clock-names = "fck";
60c0745a 193 power-domains = <&cpg_clocks>;
0dce5454
UH		 194
195 renesas,channels-mask = <0xff>;
196
197 status = "disabled";
198 };
199
da33648c
HN		 200 timer {
201 compatible = "arm,armv7-timer";
8d47e6af
SH		 202 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
203 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
204 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
205 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
da33648c
HN		 206 };
207
0dce5454
UH		 208 irqc0: interrupt-controller@e61c0000 {
209 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
210 #interrupt-cells = <2>;
211 interrupt-controller;
212 reg = <0 0xe61c0000 0 0x200>;
8d47e6af
SH		 213 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1c5ca5db 223 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
60c0745a 224 power-domains = <&cpg_clocks>;
0dce5454
UH		 225 };
226
fd1683c1
SS		 227 pfc: pin-controller@e6060000 {
228 compatible = "renesas,pfc-r8a7794";
229 reg = <0 0xe6060000 0 0x11c>;
fd1683c1
SS		 230 };
231
bd847485 232 dmac0: dma-controller@e6700000 {
0a3d058b 233 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
bd847485 234 reg = <0 0xe6700000 0 0x20000>;
8d47e6af
SH		 235 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
236 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
237 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
238 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
239 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
240 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
241 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
242 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
243 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
244 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
245 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
246 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
247 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
248 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
249 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
250 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
bd847485
LP		 251 interrupt-names = "error",
252 "ch0", "ch1", "ch2", "ch3",
253 "ch4", "ch5", "ch6", "ch7",
254 "ch8", "ch9", "ch10", "ch11",
255 "ch12", "ch13", "ch14";
256 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
257 clock-names = "fck";
60c0745a 258 power-domains = <&cpg_clocks>;
bd847485
LP		 259 #dma-cells = <1>;
260 dma-channels = <15>;
261 };
262
263 dmac1: dma-controller@e6720000 {
0a3d058b 264 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
bd847485 265 reg = <0 0xe6720000 0 0x20000>;
8d47e6af
SH		 266 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
267 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
268 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
269 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
270 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
271 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
272 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
273 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
274 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
275 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
276 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
277 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
278 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
279 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
280 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
281 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
bd847485
LP		 282 interrupt-names = "error",
283 "ch0", "ch1", "ch2", "ch3",
284 "ch4", "ch5", "ch6", "ch7",
285 "ch8", "ch9", "ch10", "ch11",
286 "ch12", "ch13", "ch14";
287 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
288 clock-names = "fck";
60c0745a 289 power-domains = <&cpg_clocks>;
bd847485
LP		 290 #dma-cells = <1>;
291 dma-channels = <15>;
292 };
293
0dce5454 294 scifa0: serial@e6c40000 {
06930a1f
GU		 295 compatible = "renesas,scifa-r8a7794",
296 "renesas,rcar-gen2-scifa", "renesas,scifa";
0dce5454 297 reg = <0 0xe6c40000 0 64>;
8d47e6af 298 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 299 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
1b463bd5 300 clock-names = "fck";
8233a0de
GU		 301 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
302 dma-names = "tx", "rx";
60c0745a 303 power-domains = <&cpg_clocks>;
0dce5454
UH		 304 status = "disabled";
305 };
306
307 scifa1: serial@e6c50000 {
06930a1f
GU		 308 compatible = "renesas,scifa-r8a7794",
309 "renesas,rcar-gen2-scifa", "renesas,scifa";
0dce5454 310 reg = <0 0xe6c50000 0 64>;
8d47e6af 311 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 312 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
1b463bd5 313 clock-names = "fck";
8233a0de
GU		 314 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
315 dma-names = "tx", "rx";
60c0745a 316 power-domains = <&cpg_clocks>;
0dce5454
UH		 317 status = "disabled";
318 };
319
320 scifa2: serial@e6c60000 {
06930a1f
GU		 321 compatible = "renesas,scifa-r8a7794",
322 "renesas,rcar-gen2-scifa", "renesas,scifa";
0dce5454 323 reg = <0 0xe6c60000 0 64>;
8d47e6af 324 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 325 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
1b463bd5 326 clock-names = "fck";
8233a0de
GU		 327 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
328 dma-names = "tx", "rx";
60c0745a 329 power-domains = <&cpg_clocks>;
0dce5454
UH		 330 status = "disabled";
331 };
332
333 scifa3: serial@e6c70000 {
06930a1f
GU		 334 compatible = "renesas,scifa-r8a7794",
335 "renesas,rcar-gen2-scifa", "renesas,scifa";
0dce5454 336 reg = <0 0xe6c70000 0 64>;
8d47e6af 337 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 338 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
1b463bd5 339 clock-names = "fck";
8233a0de
GU		 340 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
341 dma-names = "tx", "rx";
60c0745a 342 power-domains = <&cpg_clocks>;
0dce5454
UH		 343 status = "disabled";
344 };
345
346 scifa4: serial@e6c78000 {
06930a1f
GU		 347 compatible = "renesas,scifa-r8a7794",
348 "renesas,rcar-gen2-scifa", "renesas,scifa";
0dce5454 349 reg = <0 0xe6c78000 0 64>;
8d47e6af 350 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 351 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
1b463bd5 352 clock-names = "fck";
8233a0de
GU		 353 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
354 dma-names = "tx", "rx";
60c0745a 355 power-domains = <&cpg_clocks>;
0dce5454
UH		 356 status = "disabled";
357 };
358
359 scifa5: serial@e6c80000 {
06930a1f
GU		 360 compatible = "renesas,scifa-r8a7794",
361 "renesas,rcar-gen2-scifa", "renesas,scifa";
0dce5454 362 reg = <0 0xe6c80000 0 64>;
8d47e6af 363 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 364 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
1b463bd5 365 clock-names = "fck";
8233a0de
GU		 366 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
367 dma-names = "tx", "rx";
60c0745a 368 power-domains = <&cpg_clocks>;
0dce5454
UH		 369 status = "disabled";
370 };
371
372 scifb0: serial@e6c20000 {
06930a1f
GU		 373 compatible = "renesas,scifb-r8a7794",
374 "renesas,rcar-gen2-scifb", "renesas,scifb";
0dce5454 375 reg = <0 0xe6c20000 0 64>;
8d47e6af 376 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 377 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
1b463bd5 378 clock-names = "fck";
8233a0de
GU		 379 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
380 dma-names = "tx", "rx";
60c0745a 381 power-domains = <&cpg_clocks>;
0dce5454
UH		 382 status = "disabled";
383 };
384
385 scifb1: serial@e6c30000 {
06930a1f
GU		 386 compatible = "renesas,scifb-r8a7794",
387 "renesas,rcar-gen2-scifb", "renesas,scifb";
0dce5454 388 reg = <0 0xe6c30000 0 64>;
8d47e6af 389 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 390 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
1b463bd5 391 clock-names = "fck";
8233a0de
GU		 392 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
393 dma-names = "tx", "rx";
60c0745a 394 power-domains = <&cpg_clocks>;
0dce5454
UH		 395 status = "disabled";
396 };
397
398 scifb2: serial@e6ce0000 {
06930a1f
GU		 399 compatible = "renesas,scifb-r8a7794",
400 "renesas,rcar-gen2-scifb", "renesas,scifb";
0dce5454 401 reg = <0 0xe6ce0000 0 64>;
8d47e6af 402 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 403 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
1b463bd5 404 clock-names = "fck";
8233a0de
GU		 405 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
406 dma-names = "tx", "rx";
60c0745a 407 power-domains = <&cpg_clocks>;
0dce5454
UH		 408 status = "disabled";
409 };
410
411 scif0: serial@e6e60000 {
06930a1f
GU		 412 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
413 "renesas,scif";
0dce5454 414 reg = <0 0xe6e60000 0 64>;
8d47e6af 415 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 416 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
417 <&scif_clk>;
418 clock-names = "fck", "brg_int", "scif_clk";
8233a0de
GU		 419 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
420 dma-names = "tx", "rx";
60c0745a 421 power-domains = <&cpg_clocks>;
0dce5454
UH		 422 status = "disabled";
423 };
424
425 scif1: serial@e6e68000 {
06930a1f
GU		 426 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
427 "renesas,scif";
0dce5454 428 reg = <0 0xe6e68000 0 64>;
8d47e6af 429 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 430 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
431 <&scif_clk>;
432 clock-names = "fck", "brg_int", "scif_clk";
8233a0de
GU		 433 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
434 dma-names = "tx", "rx";
60c0745a 435 power-domains = <&cpg_clocks>;
0dce5454
UH		 436 status = "disabled";
437 };
438
439 scif2: serial@e6e58000 {
06930a1f
GU		 440 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
441 "renesas,scif";
0dce5454 442 reg = <0 0xe6e58000 0 64>;
8d47e6af 443 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 444 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
445 <&scif_clk>;
446 clock-names = "fck", "brg_int", "scif_clk";
8233a0de
GU		 447 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
448 dma-names = "tx", "rx";
60c0745a 449 power-domains = <&cpg_clocks>;
0dce5454
UH		 450 status = "disabled";
451 };
452
453 scif3: serial@e6ea8000 {
06930a1f
GU		 454 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
455 "renesas,scif";
0dce5454 456 reg = <0 0xe6ea8000 0 64>;
8d47e6af 457 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 458 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
459 <&scif_clk>;
460 clock-names = "fck", "brg_int", "scif_clk";
8233a0de
GU		 461 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
462 dma-names = "tx", "rx";
60c0745a 463 power-domains = <&cpg_clocks>;
0dce5454
UH		 464 status = "disabled";
465 };
466
467 scif4: serial@e6ee0000 {
06930a1f
GU		 468 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
469 "renesas,scif";
0dce5454 470 reg = <0 0xe6ee0000 0 64>;
8d47e6af 471 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 472 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
473 <&scif_clk>;
474 clock-names = "fck", "brg_int", "scif_clk";
8233a0de
GU		 475 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
476 dma-names = "tx", "rx";
60c0745a 477 power-domains = <&cpg_clocks>;
0dce5454
UH		 478 status = "disabled";
479 };
480
481 scif5: serial@e6ee8000 {
06930a1f
GU		 482 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
483 "renesas,scif";
0dce5454 484 reg = <0 0xe6ee8000 0 64>;
8d47e6af 485 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 486 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
487 <&scif_clk>;
488 clock-names = "fck", "brg_int", "scif_clk";
8233a0de
GU		 489 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
490 dma-names = "tx", "rx";
60c0745a 491 power-domains = <&cpg_clocks>;
0dce5454
UH		 492 status = "disabled";
493 };
494
495 hscif0: serial@e62c0000 {
06930a1f
GU		 496 compatible = "renesas,hscif-r8a7794",
497 "renesas,rcar-gen2-hscif", "renesas,hscif";
0dce5454 498 reg = <0 0xe62c0000 0 96>;
8d47e6af 499 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 500 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
501 <&scif_clk>;
502 clock-names = "fck", "brg_int", "scif_clk";
8233a0de
GU		 503 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
504 dma-names = "tx", "rx";
60c0745a 505 power-domains = <&cpg_clocks>;
0dce5454
UH		 506 status = "disabled";
507 };
508
509 hscif1: serial@e62c8000 {
06930a1f
GU		 510 compatible = "renesas,hscif-r8a7794",
511 "renesas,rcar-gen2-hscif", "renesas,hscif";
0dce5454 512 reg = <0 0xe62c8000 0 96>;
8d47e6af 513 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 514 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
515 <&scif_clk>;
516 clock-names = "fck", "brg_int", "scif_clk";
8233a0de
GU		 517 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
518 dma-names = "tx", "rx";
60c0745a 519 power-domains = <&cpg_clocks>;
0dce5454
UH		 520 status = "disabled";
521 };
522
523 hscif2: serial@e62d0000 {
06930a1f
GU		 524 compatible = "renesas,hscif-r8a7794",
525 "renesas,rcar-gen2-hscif", "renesas,hscif";
0dce5454 526 reg = <0 0xe62d0000 0 96>;
8d47e6af 527 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 528 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
529 <&scif_clk>;
530 clock-names = "fck", "brg_int", "scif_clk";
8233a0de
GU		 531 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
532 dma-names = "tx", "rx";
60c0745a 533 power-domains = <&cpg_clocks>;
0dce5454
UH		 534 status = "disabled";
535 };
536
82818d34
LP		 537 ether: ethernet@ee700000 {
538 compatible = "renesas,ether-r8a7794";
539 reg = <0 0xee700000 0 0x400>;
8d47e6af 540 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
82818d34 541 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
60c0745a 542 power-domains = <&cpg_clocks>;
82818d34
LP		 543 phy-mode = "rmii";
544 #address-cells = <1>;
545 #size-cells = <0>;
546 status = "disabled";
547 };
548
89aac8af
SS		 549 avb: ethernet@e6800000 {
550 compatible = "renesas,etheravb-r8a7794",
551 "renesas,etheravb-rcar-gen2";
552 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
553 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
555 power-domains = <&cpg_clocks>;
556 #address-cells = <1>;
557 #size-cells = <0>;
558 status = "disabled";
559 };
560
5428521b
SS		 561 /* The memory map in the User's Manual maps the cores to bus numbers */
562 i2c0: i2c@e6508000 {
563 compatible = "renesas,i2c-r8a7794";
564 reg = <0 0xe6508000 0 0x40>;
8d47e6af 565 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
5428521b
SS		 566 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
567 power-domains = <&cpg_clocks>;
568 #address-cells = <1>;
569 #size-cells = <0>;
691cd0a6 570 i2c-scl-internal-delay-ns = <6>;
5428521b
SS		 571 status = "disabled";
572 };
573
574 i2c1: i2c@e6518000 {
575 compatible = "renesas,i2c-r8a7794";
576 reg = <0 0xe6518000 0 0x40>;
8d47e6af 577 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
5428521b
SS		 578 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
579 power-domains = <&cpg_clocks>;
580 #address-cells = <1>;
581 #size-cells = <0>;
691cd0a6 582 i2c-scl-internal-delay-ns = <6>;
5428521b
SS		 583 status = "disabled";
584 };
585
586 i2c2: i2c@e6530000 {
587 compatible = "renesas,i2c-r8a7794";
588 reg = <0 0xe6530000 0 0x40>;
8d47e6af 589 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
5428521b
SS		 590 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
591 power-domains = <&cpg_clocks>;
592 #address-cells = <1>;
593 #size-cells = <0>;
691cd0a6 594 i2c-scl-internal-delay-ns = <6>;
5428521b
SS		 595 status = "disabled";
596 };
597
598 i2c3: i2c@e6540000 {
599 compatible = "renesas,i2c-r8a7794";
600 reg = <0 0xe6540000 0 0x40>;
8d47e6af 601 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
5428521b
SS		 602 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
603 power-domains = <&cpg_clocks>;
604 #address-cells = <1>;
605 #size-cells = <0>;
691cd0a6 606 i2c-scl-internal-delay-ns = <6>;
5428521b
SS		 607 status = "disabled";
608 };
609
610 i2c4: i2c@e6520000 {
611 compatible = "renesas,i2c-r8a7794";
612 reg = <0 0xe6520000 0 0x40>;
8d47e6af 613 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5428521b
SS		 614 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
615 power-domains = <&cpg_clocks>;
616 #address-cells = <1>;
617 #size-cells = <0>;
691cd0a6 618 i2c-scl-internal-delay-ns = <6>;
5428521b
SS		 619 status = "disabled";
620 };
621
622 i2c5: i2c@e6528000 {
623 compatible = "renesas,i2c-r8a7794";
624 reg = <0 0xe6528000 0 0x40>;
8d47e6af 625 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
5428521b
SS		 626 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
627 power-domains = <&cpg_clocks>;
628 #address-cells = <1>;
629 #size-cells = <0>;
691cd0a6 630 i2c-scl-internal-delay-ns = <6>;
5428521b
SS		 631 status = "disabled";
632 };
633
aa9b992e
SH		 634 i2c6: i2c@e6500000 {
635 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
636 reg = <0 0xe6500000 0 0x425>;
637 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
639 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
640 dma-names = "tx", "rx";
641 power-domains = <&cpg_clocks>;
642 #address-cells = <1>;
643 #size-cells = <0>;
644 status = "disabled";
645 };
646
647 i2c7: i2c@e6510000 {
648 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
649 reg = <0 0xe6510000 0 0x425>;
650 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
652 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
653 dma-names = "tx", "rx";
654 power-domains = <&cpg_clocks>;
655 #address-cells = <1>;
656 #size-cells = <0>;
657 status = "disabled";
658 };
659
6cdf6ba1
SS		 660 mmcif0: mmc@ee200000 {
661 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
662 reg = <0 0xee200000 0 0x80>;
8d47e6af 663 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
6cdf6ba1
SS		 664 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
665 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
666 dma-names = "tx", "rx";
60c0745a 667 power-domains = <&cpg_clocks>;
6cdf6ba1
SS		 668 reg-io-width = <4>;
669 status = "disabled";
670 };
671
b8e8ea12
SS		 672 sdhi0: sd@ee100000 {
673 compatible = "renesas,sdhi-r8a7794";
674 reg = <0 0xee100000 0 0x200>;
8d47e6af 675 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
b8e8ea12 676 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
60c0745a 677 power-domains = <&cpg_clocks>;
b8e8ea12
SS		 678 status = "disabled";
679 };
680
681 sdhi1: sd@ee140000 {
682 compatible = "renesas,sdhi-r8a7794";
683 reg = <0 0xee140000 0 0x100>;
8d47e6af 684 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
b8e8ea12 685 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
60c0745a 686 power-domains = <&cpg_clocks>;
b8e8ea12
SS		 687 status = "disabled";
688 };
689
690 sdhi2: sd@ee160000 {
691 compatible = "renesas,sdhi-r8a7794";
692 reg = <0 0xee160000 0 0x100>;
8d47e6af 693 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
b8e8ea12 694 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
60c0745a 695 power-domains = <&cpg_clocks>;
b8e8ea12
SS		 696 status = "disabled";
697 };
698
740b4a9f
SS		 699 qspi: spi@e6b10000 {
700 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
701 reg = <0 0xe6b10000 0 0x2c>;
8d47e6af 702 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
740b4a9f
SS		 703 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
704 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
705 dma-names = "tx", "rx";
706 power-domains = <&cpg_clocks>;
707 num-cs = <1>;
708 #address-cells = <1>;
709 #size-cells = <0>;
710 status = "disabled";
711 };
712
1afe77ca
SS		 713 vin0: video@e6ef0000 {
714 compatible = "renesas,vin-r8a7794";
715 reg = <0 0xe6ef0000 0 0x1000>;
8d47e6af 716 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1afe77ca
SS		 717 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
718 power-domains = <&cpg_clocks>;
719 status = "disabled";
720 };
721
722 vin1: video@e6ef1000 {
723 compatible = "renesas,vin-r8a7794";
724 reg = <0 0xe6ef1000 0 0x1000>;
8d47e6af 725 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1afe77ca
SS		 726 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
727 power-domains = <&cpg_clocks>;
728 status = "disabled";
729 };
730
a6a130b3 731 pci0: pci@ee090000 {
c99fbe64 732 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
a6a130b3
SS		 733 device_type = "pci";
734 reg = <0 0xee090000 0 0xc00>,
735 <0 0xee080000 0 0x1100>;
8d47e6af 736 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
a6a130b3
SS		 737 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
738 power-domains = <&cpg_clocks>;
739 status = "disabled";
740
741 bus-range = <0 0>;
742 #address-cells = <3>;
743 #size-cells = <2>;
744 #interrupt-cells = <1>;
745 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
746 interrupt-map-mask = <0xff00 0 0 0x7>;
8d47e6af
SH		 747 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
748 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
749 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
45cb0bd7
SS		 750
751 usb@0,1 {
752 reg = <0x800 0 0 0 0>;
753 device_type = "pci";
754 phys = <&usb0 0>;
755 phy-names = "usb";
756 };
757
758 usb@0,2 {
759 reg = <0x1000 0 0 0 0>;
760 device_type = "pci";
761 phys = <&usb0 0>;
762 phy-names = "usb";
763 };
a6a130b3
SS		 764 };
765
766 pci1: pci@ee0d0000 {
c99fbe64 767 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
a6a130b3
SS		 768 device_type = "pci";
769 reg = <0 0xee0d0000 0 0xc00>,
770 <0 0xee0c0000 0 0x1100>;
8d47e6af 771 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
a6a130b3
SS		 772 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
773 power-domains = <&cpg_clocks>;
774 status = "disabled";
775
776 bus-range = <1 1>;
777 #address-cells = <3>;
778 #size-cells = <2>;
779 #interrupt-cells = <1>;
780 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
781 interrupt-map-mask = <0xff00 0 0 0x7>;
8d47e6af
SH		 782 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
783 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
784 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
45cb0bd7
SS		 785
786 usb@0,1 {
787 reg = <0x800 0 0 0 0>;
788 device_type = "pci";
789 phys = <&usb2 0>;
790 phy-names = "usb";
791 };
792
793 usb@0,2 {
794 reg = <0x1000 0 0 0 0>;
795 device_type = "pci";
796 phys = <&usb2 0>;
797 phy-names = "usb";
798 };
a6a130b3
SS		 799 };
800
2f33b9f7 801 hsusb: usb@e6590000 {
1472ffa8 802 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
2f33b9f7 803 reg = <0 0xe6590000 0 0x100>;
8d47e6af 804 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
2f33b9f7
SS		 805 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
806 power-domains = <&cpg_clocks>;
807 renesas,buswait = <4>;
808 phys = <&usb0 1>;
809 phy-names = "usb";
810 status = "disabled";
811 };
812
74ef4572
SS		 813 usbphy: usb-phy@e6590100 {
814 compatible = "renesas,usb-phy-r8a7794";
815 reg = <0 0xe6590100 0 0x100>;
816 #address-cells = <1>;
817 #size-cells = <0>;
818 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
819 clock-names = "usbhs";
820 power-domains = <&cpg_clocks>;
821 status = "disabled";
822
823 usb0: usb-channel@0 {
824 reg = <0>;
825 #phy-cells = <1>;
826 };
827 usb2: usb-channel@2 {
828 reg = <2>;
829 #phy-cells = <1>;
830 };
831 };
832
46c4f13d
LP		 833 du: display@feb00000 {
834 compatible = "renesas,du-r8a7794";
835 reg = <0 0xfeb00000 0 0x40000>;
836 reg-names = "du";
8d47e6af
SH		 837 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
838 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
46c4f13d
LP		 839 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
840 <&mstp7_clks R8A7794_CLK_DU0>;
841 clock-names = "du.0", "du.1";
842 status = "disabled";
843
844 ports {
845 #address-cells = <1>;
846 #size-cells = <0>;
847
848 port@0 {
849 reg = <0>;
850 du_out_rgb0: endpoint {
851 };
852 };
853 port@1 {
854 reg = <1>;
855 du_out_rgb1: endpoint {
856 };
857 };
858 };
859 };
860
9f1c1a2c
SH		 861 can0: can@e6e80000 {
862 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
863 reg = <0 0xe6e80000 0 0x1000>;
864 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
866 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
867 clock-names = "clkp1", "clkp2", "can_clk";
868 power-domains = <&cpg_clocks>;
869 status = "disabled";
870 };
871
872 can1: can@e6e88000 {
873 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
874 reg = <0 0xe6e88000 0 0x1000>;
875 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
877 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
878 clock-names = "clkp1", "clkp2", "can_clk";
879 power-domains = <&cpg_clocks>;
880 status = "disabled";
881 };
882
0dce5454
UH		 883 clocks {
884 #address-cells = <2>;
885 #size-cells = <2>;
886 ranges;
887
888 /* External root clock */
337f6bef 889 extal_clk: extal {
0dce5454
UH		 890 compatible = "fixed-clock";
891 #clock-cells = <0>;
892 /* This value must be overriden by the board. */
893 clock-frequency = <0>;
0dce5454
UH		 894 };
895
e980f941
SH		 896 /* External USB clock - can be overridden by the board */
897 usb_extal_clk: usb_extal {
898 compatible = "fixed-clock";
899 #clock-cells = <0>;
900 clock-frequency = <48000000>;
901 };
902
903 /* External CAN clock */
904 can_clk: can {
905 compatible = "fixed-clock";
906 #clock-cells = <0>;
907 /* This value must be overridden by the board. */
908 clock-frequency = <0>;
e980f941
SH		 909 };
910
a864446f
GU		 911 /* External SCIF clock */
912 scif_clk: scif {
913 compatible = "fixed-clock";
914 #clock-cells = <0>;
915 /* This value must be overridden by the board. */
916 clock-frequency = <0>;
a864446f
GU		 917 };
918
0dce5454
UH		 919 /* Special CPG clocks */
920 cpg_clocks: cpg_clocks@e6150000 {
921 compatible = "renesas,r8a7794-cpg-clocks",
922 "renesas,rcar-gen2-cpg-clocks";
923 reg = <0 0xe6150000 0 0x1000>;
e980f941 924 clocks = <&extal_clk &usb_extal_clk>;
0dce5454
UH		 925 #clock-cells = <1>;
926 clock-output-names = "main", "pll0", "pll1", "pll3",
e980f941
SH		 927 "lb", "qspi", "sdh", "sd0", "z",
928 "rcan";
60c0745a 929 #power-domain-cells = <0>;
0dce5454 930 };
8e181633 931 /* Variable factor clocks */
337f6bef 932 sd2_clk: sd2@e6150078 {
8e181633
SU		 933 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
934 reg = <0 0xe6150078 0 4>;
935 clocks = <&pll1_div2_clk>;
936 #clock-cells = <0>;
8e181633 937 };
337f6bef 938 sd3_clk: sd3@e615026c {
8e181633 939 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
5e7e1554 940 reg = <0 0xe615026c 0 4>;
8e181633
SU		 941 clocks = <&pll1_div2_clk>;
942 #clock-cells = <0>;
8e181633 943 };
337f6bef 944 mmc0_clk: mmc0@e6150240 {
deac150c
SU		 945 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
946 reg = <0 0xe6150240 0 4>;
947 clocks = <&pll1_div2_clk>;
948 #clock-cells = <0>;
deac150c 949 };
0dce5454
UH		 950
951 /* Fixed factor clocks */
337f6bef 952 pll1_div2_clk: pll1_div2 {
0dce5454
UH		 953 compatible = "fixed-factor-clock";
954 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
955 #clock-cells = <0>;
956 clock-div = <2>;
957 clock-mult = <1>;
0dce5454 958 };
337f6bef 959 zg_clk: zg {
0dce5454
UH		 960 compatible = "fixed-factor-clock";
961 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
962 #clock-cells = <0>;
963 clock-div = <6>;
964 clock-mult = <1>;
0dce5454 965 };
337f6bef 966 zx_clk: zx {
0dce5454
UH		 967 compatible = "fixed-factor-clock";
968 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
969 #clock-cells = <0>;
970 clock-div = <3>;
971 clock-mult = <1>;
0dce5454 972 };
337f6bef 973 zs_clk: zs {
0dce5454
UH		 974 compatible = "fixed-factor-clock";
975 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
976 #clock-cells = <0>;
977 clock-div = <6>;
978 clock-mult = <1>;
0dce5454 979 };
337f6bef 980 hp_clk: hp {
0dce5454
UH		 981 compatible = "fixed-factor-clock";
982 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
983 #clock-cells = <0>;
984 clock-div = <12>;
985 clock-mult = <1>;
0dce5454 986 };
337f6bef 987 i_clk: i {
0dce5454
UH		 988 compatible = "fixed-factor-clock";
989 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
990 #clock-cells = <0>;
991 clock-div = <2>;
992 clock-mult = <1>;
0dce5454 993 };
337f6bef 994 b_clk: b {
0dce5454
UH		 995 compatible = "fixed-factor-clock";
996 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
997 #clock-cells = <0>;
998 clock-div = <12>;
999 clock-mult = <1>;
0dce5454 1000 };
337f6bef 1001 p_clk: p {
0dce5454
UH		 1002 compatible = "fixed-factor-clock";
1003 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1004 #clock-cells = <0>;
1005 clock-div = <24>;
1006 clock-mult = <1>;
0dce5454 1007 };
337f6bef 1008 cl_clk: cl {
0dce5454
UH		 1009 compatible = "fixed-factor-clock";
1010 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1011 #clock-cells = <0>;
1012 clock-div = <48>;
1013 clock-mult = <1>;
0dce5454 1014 };
337f6bef 1015 m2_clk: m2 {
0dce5454
UH		 1016 compatible = "fixed-factor-clock";
1017 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1018 #clock-cells = <0>;
1019 clock-div = <8>;
1020 clock-mult = <1>;
0dce5454 1021 };
337f6bef 1022 rclk_clk: rclk {
0dce5454
UH		 1023 compatible = "fixed-factor-clock";
1024 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1025 #clock-cells = <0>;
1026 clock-div = <(48 * 1024)>;
1027 clock-mult = <1>;
0dce5454 1028 };
337f6bef 1029 oscclk_clk: oscclk {
0dce5454
UH		 1030 compatible = "fixed-factor-clock";
1031 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1032 #clock-cells = <0>;
1033 clock-div = <(12 * 1024)>;
1034 clock-mult = <1>;
0dce5454 1035 };
337f6bef 1036 zb3_clk: zb3 {
0dce5454
UH		 1037 compatible = "fixed-factor-clock";
1038 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1039 #clock-cells = <0>;
1040 clock-div = <4>;
1041 clock-mult = <1>;
0dce5454 1042 };
337f6bef 1043 zb3d2_clk: zb3d2 {
0dce5454
UH		 1044 compatible = "fixed-factor-clock";
1045 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1046 #clock-cells = <0>;
1047 clock-div = <8>;
1048 clock-mult = <1>;
0dce5454 1049 };
337f6bef 1050 ddr_clk: ddr {
0dce5454
UH		 1051 compatible = "fixed-factor-clock";
1052 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1053 #clock-cells = <0>;
1054 clock-div = <8>;
1055 clock-mult = <1>;
0dce5454 1056 };
337f6bef 1057 mp_clk: mp {
0dce5454
UH		 1058 compatible = "fixed-factor-clock";
1059 clocks = <&pll1_div2_clk>;
1060 #clock-cells = <0>;
1061 clock-div = <15>;
1062 clock-mult = <1>;
0dce5454 1063 };
337f6bef 1064 cp_clk: cp {
0dce5454
UH		 1065 compatible = "fixed-factor-clock";
1066 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1067 #clock-cells = <0>;
1068 clock-div = <48>;
1069 clock-mult = <1>;
0dce5454
UH		 1070 };
1071
337f6bef 1072 acp_clk: acp {
0dce5454
UH		 1073 compatible = "fixed-factor-clock";
1074 clocks = <&extal_clk>;
1075 #clock-cells = <0>;
1076 clock-div = <2>;
1077 clock-mult = <1>;
0dce5454
UH		 1078 };
1079
1080 /* Gate clocks */
1081 mstp0_clks: mstp0_clks@e6150130 {
1082 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1083 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1084 clocks = <&mp_clk>;
1085 #clock-cells = <1>;
1045d065 1086 clock-indices = <R8A7794_CLK_MSIOF0>;
0dce5454
UH		 1087 clock-output-names = "msiof0";
1088 };
1089 mstp1_clks: mstp1_clks@e6150134 {
1090 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1091 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
dc3cf93d
YH		 1092 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1093 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1094 <&zs_clk>, <&zs_clk>;
0dce5454 1095 #clock-cells = <1>;
1045d065 1096 clock-indices = <
dc3cf93d
YH		 1097 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1098 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1099 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1100 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
0dce5454
UH		 1101 >;
1102 clock-output-names =
dc3cf93d
YH		 1103 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1104 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
0dce5454
UH		 1105 };
1106 mstp2_clks: mstp2_clks@e6150138 {
1107 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1108 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1109 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
be16cd38
HY		 1110 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1111 <&zs_clk>, <&zs_clk>;
0dce5454 1112 #clock-cells = <1>;
1045d065 1113 clock-indices = <
0dce5454
UH		 1114 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1115 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1116 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
be16cd38 1117 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
0dce5454
UH		 1118 >;
1119 clock-output-names =
1120 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
be16cd38
HY		 1121 "scifb1", "msiof1", "scifb2",
1122 "sys-dmac1", "sys-dmac0";
0dce5454
UH		 1123 };
1124 mstp3_clks: mstp3_clks@e615013c {
1125 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1126 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
5e7e1554 1127 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
a856b195
SH		 1128 <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
1129 <&hp_clk>, <&hp_clk>;
0dce5454 1130 #clock-cells = <1>;
1045d065 1131 clock-indices = <
8e181633 1132 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
a856b195
SH		 1133 R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
1134 R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
deac150c 1135 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
0dce5454
UH		 1136 >;
1137 clock-output-names =
8e181633 1138 "sdhi2", "sdhi1", "sdhi0",
a856b195
SH		 1139 "mmcif0", "i2c6", "i2c7",
1140 "cmt1", "usbdmac0", "usbdmac1";
0dce5454 1141 };
1c5ca5db
GU		 1142 mstp4_clks: mstp4_clks@e6150140 {
1143 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1144 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1145 clocks = <&cp_clk>;
1146 #clock-cells = <1>;
1147 clock-indices = <R8A7794_CLK_IRQC>;
1148 clock-output-names = "irqc";
1149 };
0dce5454
UH		 1150 mstp7_clks: mstp7_clks@e615014c {
1151 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1152 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
c7bab9f9
SU		 1153 clocks = <&mp_clk>, <&mp_clk>,
1154 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
9859cd3b
LP		 1155 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1156 <&zx_clk>;
0dce5454 1157 #clock-cells = <1>;
1045d065 1158 clock-indices = <
c7bab9f9 1159 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
0dce5454
UH		 1160 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1161 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1162 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
9859cd3b 1163 R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
0dce5454
UH		 1164 >;
1165 clock-output-names =
c7bab9f9 1166 "ehci", "hsusb",
0dce5454 1167 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
9859cd3b 1168 "scif3", "scif2", "scif1", "scif0", "du0";
0dce5454
UH		 1169 };
1170 mstp8_clks: mstp8_clks@e6150990 {
1171 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1172 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
255a4042 1173 clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
0dce5454 1174 #clock-cells = <1>;
1045d065 1175 clock-indices = <
255a4042
SS		 1176 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
1177 R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
0dce5454
UH		 1178 >;
1179 clock-output-names =
255a4042 1180 "vin1", "vin0", "etheravb", "ether";
0dce5454 1181 };
3281480b
HN		 1182 mstp9_clks: mstp9_clks@e6150994 {
1183 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1184 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
3f37e018 1185 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
e980f941
SH		 1186 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
1187 <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
1188 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1189 <&hp_clk>, <&hp_clk>;
3281480b 1190 #clock-cells = <1>;
3f37e018
SS		 1191 clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1192 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1193 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
e980f941
SH		 1194 R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
1195 R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
3f37e018
SS		 1196 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1197 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1198 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
c5d82c99 1199 clock-output-names =
3f37e018 1200 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
e980f941 1201 "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
3f37e018 1202 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
3281480b 1203 };
0dce5454
UH		 1204 mstp11_clks: mstp11_clks@e615099c {
1205 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1206 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1207 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1208 #clock-cells = <1>;
1045d065 1209 clock-indices = <
0dce5454
UH		 1210 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1211 >;
1212 clock-output-names = "scifa3", "scifa4", "scifa5";
1213 };
1214 };
1cb2794f
LP		 1215
1216 ipmmu_sy0: mmu@e6280000 {
0da4cfd1 1217 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1cb2794f 1218 reg = <0 0xe6280000 0 0x1000>;
8d47e6af
SH		 1219 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1cb2794f
LP		 1221 #iommu-cells = <1>;
1222 status = "disabled";
1223 };
1224
1225 ipmmu_sy1: mmu@e6290000 {
0da4cfd1 1226 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1cb2794f 1227 reg = <0 0xe6290000 0 0x1000>;
8d47e6af 1228 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1cb2794f
LP		 1229 #iommu-cells = <1>;
1230 status = "disabled";
1231 };
1232
1233 ipmmu_ds: mmu@e6740000 {
0da4cfd1 1234 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1cb2794f 1235 reg = <0 0xe6740000 0 0x1000>;
8d47e6af
SH		 1236 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1cb2794f 1238 #iommu-cells = <1>;
832d3e4c 1239 status = "disabled";
1cb2794f
LP		 1240 };
1241
1242 ipmmu_mp: mmu@ec680000 {
0da4cfd1 1243 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1cb2794f 1244 reg = <0 0xec680000 0 0x1000>;
8d47e6af 1245 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1cb2794f
LP		 1246 #iommu-cells = <1>;
1247 status = "disabled";
1248 };
1249
1250 ipmmu_mx: mmu@fe951000 {
0da4cfd1 1251 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1cb2794f 1252 reg = <0 0xfe951000 0 0x1000>;
8d47e6af
SH		 1253 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1cb2794f 1255 #iommu-cells = <1>;
832d3e4c 1256 status = "disabled";
1cb2794f
LP		 1257 };
1258
1259 ipmmu_gp: mmu@e62a0000 {
0da4cfd1 1260 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1cb2794f 1261 reg = <0 0xe62a0000 0 0x1000>;
8d47e6af
SH		 1262 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1cb2794f
LP		 1264 #iommu-cells = <1>;
1265 status = "disabled";
1266 };
0dce5454 1267};
Linux kernel - Deliverables
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