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ARM: shmobile: r8a7794: Add IPMMU DT nodes
[deliverable/linux.git] / arch / arm / boot / dts / r8a7794.dtsi
CommitLineData
0dce5454
UH		 1/*
2 * Device Tree Source for the r8a7794 SoC
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <dt-bindings/clock/r8a7794-clock.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
16/ {
17 compatible = "renesas,r8a7794";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a7";
29 reg = <0>;
30 clock-frequency = <1000000000>;
31 };
32
33 cpu1: cpu@1 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a7";
36 reg = <1>;
37 clock-frequency = <1000000000>;
38 };
39 };
40
41 gic: interrupt-controller@f1001000 {
42 compatible = "arm,cortex-a7-gic";
43 #interrupt-cells = <3>;
44 #address-cells = <0>;
45 interrupt-controller;
46 reg = <0 0xf1001000 0 0x1000>,
47 <0 0xf1002000 0 0x1000>,
48 <0 0xf1004000 0 0x2000>,
49 <0 0xf1006000 0 0x2000>;
00add867 50 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0dce5454
UH		 51 };
52
53 cmt0: timer@ffca0000 {
54 compatible = "renesas,cmt-48-gen2";
55 reg = <0 0xffca0000 0 0x1004>;
56 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
57 <0 143 IRQ_TYPE_LEVEL_HIGH>;
58 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
59 clock-names = "fck";
60
61 renesas,channels-mask = <0x60>;
62
63 status = "disabled";
64 };
65
66 cmt1: timer@e6130000 {
67 compatible = "renesas,cmt-48-gen2";
68 reg = <0 0xe6130000 0 0x1004>;
69 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
70 <0 121 IRQ_TYPE_LEVEL_HIGH>,
71 <0 122 IRQ_TYPE_LEVEL_HIGH>,
72 <0 123 IRQ_TYPE_LEVEL_HIGH>,
73 <0 124 IRQ_TYPE_LEVEL_HIGH>,
74 <0 125 IRQ_TYPE_LEVEL_HIGH>,
75 <0 126 IRQ_TYPE_LEVEL_HIGH>,
76 <0 127 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
78 clock-names = "fck";
79
80 renesas,channels-mask = <0xff>;
81
82 status = "disabled";
83 };
84
da33648c
HN		 85 timer {
86 compatible = "arm,armv7-timer";
00add867
GU		 87 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
88 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
89 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
90 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
da33648c
HN		 91 };
92
0dce5454
UH		 93 irqc0: interrupt-controller@e61c0000 {
94 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
95 #interrupt-cells = <2>;
96 interrupt-controller;
97 reg = <0 0xe61c0000 0 0x200>;
98 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
99 <0 1 IRQ_TYPE_LEVEL_HIGH>,
100 <0 2 IRQ_TYPE_LEVEL_HIGH>,
101 <0 3 IRQ_TYPE_LEVEL_HIGH>,
102 <0 12 IRQ_TYPE_LEVEL_HIGH>,
103 <0 13 IRQ_TYPE_LEVEL_HIGH>,
104 <0 14 IRQ_TYPE_LEVEL_HIGH>,
105 <0 15 IRQ_TYPE_LEVEL_HIGH>,
106 <0 16 IRQ_TYPE_LEVEL_HIGH>,
107 <0 17 IRQ_TYPE_LEVEL_HIGH>;
108 };
109
bd847485
LP		 110 dmac0: dma-controller@e6700000 {
111 compatible = "renesas,rcar-dmac";
112 reg = <0 0xe6700000 0 0x20000>;
113 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
114 0 200 IRQ_TYPE_LEVEL_HIGH
115 0 201 IRQ_TYPE_LEVEL_HIGH
116 0 202 IRQ_TYPE_LEVEL_HIGH
117 0 203 IRQ_TYPE_LEVEL_HIGH
118 0 204 IRQ_TYPE_LEVEL_HIGH
119 0 205 IRQ_TYPE_LEVEL_HIGH
120 0 206 IRQ_TYPE_LEVEL_HIGH
121 0 207 IRQ_TYPE_LEVEL_HIGH
122 0 208 IRQ_TYPE_LEVEL_HIGH
123 0 209 IRQ_TYPE_LEVEL_HIGH
124 0 210 IRQ_TYPE_LEVEL_HIGH
125 0 211 IRQ_TYPE_LEVEL_HIGH
126 0 212 IRQ_TYPE_LEVEL_HIGH
127 0 213 IRQ_TYPE_LEVEL_HIGH
128 0 214 IRQ_TYPE_LEVEL_HIGH>;
129 interrupt-names = "error",
130 "ch0", "ch1", "ch2", "ch3",
131 "ch4", "ch5", "ch6", "ch7",
132 "ch8", "ch9", "ch10", "ch11",
133 "ch12", "ch13", "ch14";
134 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
135 clock-names = "fck";
136 #dma-cells = <1>;
137 dma-channels = <15>;
138 };
139
140 dmac1: dma-controller@e6720000 {
141 compatible = "renesas,rcar-dmac";
142 reg = <0 0xe6720000 0 0x20000>;
143 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
144 0 216 IRQ_TYPE_LEVEL_HIGH
145 0 217 IRQ_TYPE_LEVEL_HIGH
146 0 218 IRQ_TYPE_LEVEL_HIGH
147 0 219 IRQ_TYPE_LEVEL_HIGH
148 0 308 IRQ_TYPE_LEVEL_HIGH
149 0 309 IRQ_TYPE_LEVEL_HIGH
150 0 310 IRQ_TYPE_LEVEL_HIGH
151 0 311 IRQ_TYPE_LEVEL_HIGH
152 0 312 IRQ_TYPE_LEVEL_HIGH
153 0 313 IRQ_TYPE_LEVEL_HIGH
154 0 314 IRQ_TYPE_LEVEL_HIGH
155 0 315 IRQ_TYPE_LEVEL_HIGH
156 0 316 IRQ_TYPE_LEVEL_HIGH
157 0 317 IRQ_TYPE_LEVEL_HIGH
158 0 318 IRQ_TYPE_LEVEL_HIGH>;
159 interrupt-names = "error",
160 "ch0", "ch1", "ch2", "ch3",
161 "ch4", "ch5", "ch6", "ch7",
162 "ch8", "ch9", "ch10", "ch11",
163 "ch12", "ch13", "ch14";
164 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
165 clock-names = "fck";
166 #dma-cells = <1>;
167 dma-channels = <15>;
168 };
169
0dce5454
UH		 170 scifa0: serial@e6c40000 {
171 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
172 reg = <0 0xe6c40000 0 64>;
173 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
175 clock-names = "sci_ick";
176 status = "disabled";
177 };
178
179 scifa1: serial@e6c50000 {
180 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
181 reg = <0 0xe6c50000 0 64>;
182 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
184 clock-names = "sci_ick";
185 status = "disabled";
186 };
187
188 scifa2: serial@e6c60000 {
189 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
190 reg = <0 0xe6c60000 0 64>;
191 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
193 clock-names = "sci_ick";
194 status = "disabled";
195 };
196
197 scifa3: serial@e6c70000 {
198 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
199 reg = <0 0xe6c70000 0 64>;
200 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
202 clock-names = "sci_ick";
203 status = "disabled";
204 };
205
206 scifa4: serial@e6c78000 {
207 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
208 reg = <0 0xe6c78000 0 64>;
209 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
211 clock-names = "sci_ick";
212 status = "disabled";
213 };
214
215 scifa5: serial@e6c80000 {
216 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
217 reg = <0 0xe6c80000 0 64>;
218 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
220 clock-names = "sci_ick";
221 status = "disabled";
222 };
223
224 scifb0: serial@e6c20000 {
225 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
226 reg = <0 0xe6c20000 0 64>;
227 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
229 clock-names = "sci_ick";
230 status = "disabled";
231 };
232
233 scifb1: serial@e6c30000 {
234 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
235 reg = <0 0xe6c30000 0 64>;
236 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
238 clock-names = "sci_ick";
239 status = "disabled";
240 };
241
242 scifb2: serial@e6ce0000 {
243 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
244 reg = <0 0xe6ce0000 0 64>;
245 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
247 clock-names = "sci_ick";
248 status = "disabled";
249 };
250
251 scif0: serial@e6e60000 {
252 compatible = "renesas,scif-r8a7794", "renesas,scif";
253 reg = <0 0xe6e60000 0 64>;
254 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
256 clock-names = "sci_ick";
257 status = "disabled";
258 };
259
260 scif1: serial@e6e68000 {
261 compatible = "renesas,scif-r8a7794", "renesas,scif";
262 reg = <0 0xe6e68000 0 64>;
263 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
265 clock-names = "sci_ick";
266 status = "disabled";
267 };
268
269 scif2: serial@e6e58000 {
270 compatible = "renesas,scif-r8a7794", "renesas,scif";
271 reg = <0 0xe6e58000 0 64>;
272 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
274 clock-names = "sci_ick";
275 status = "disabled";
276 };
277
278 scif3: serial@e6ea8000 {
279 compatible = "renesas,scif-r8a7794", "renesas,scif";
280 reg = <0 0xe6ea8000 0 64>;
281 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
283 clock-names = "sci_ick";
284 status = "disabled";
285 };
286
287 scif4: serial@e6ee0000 {
288 compatible = "renesas,scif-r8a7794", "renesas,scif";
289 reg = <0 0xe6ee0000 0 64>;
290 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
292 clock-names = "sci_ick";
293 status = "disabled";
294 };
295
296 scif5: serial@e6ee8000 {
297 compatible = "renesas,scif-r8a7794", "renesas,scif";
298 reg = <0 0xe6ee8000 0 64>;
299 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
301 clock-names = "sci_ick";
302 status = "disabled";
303 };
304
305 hscif0: serial@e62c0000 {
306 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
307 reg = <0 0xe62c0000 0 96>;
308 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
310 clock-names = "sci_ick";
311 status = "disabled";
312 };
313
314 hscif1: serial@e62c8000 {
315 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
316 reg = <0 0xe62c8000 0 96>;
317 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
319 clock-names = "sci_ick";
320 status = "disabled";
321 };
322
323 hscif2: serial@e62d0000 {
324 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
325 reg = <0 0xe62d0000 0 96>;
326 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
328 clock-names = "sci_ick";
329 status = "disabled";
330 };
331
332 clocks {
333 #address-cells = <2>;
334 #size-cells = <2>;
335 ranges;
336
337 /* External root clock */
338 extal_clk: extal_clk {
339 compatible = "fixed-clock";
340 #clock-cells = <0>;
341 /* This value must be overriden by the board. */
342 clock-frequency = <0>;
343 clock-output-names = "extal";
344 };
345
346 /* Special CPG clocks */
347 cpg_clocks: cpg_clocks@e6150000 {
348 compatible = "renesas,r8a7794-cpg-clocks",
349 "renesas,rcar-gen2-cpg-clocks";
350 reg = <0 0xe6150000 0 0x1000>;
351 clocks = <&extal_clk>;
352 #clock-cells = <1>;
353 clock-output-names = "main", "pll0", "pll1", "pll3",
354 "lb", "qspi", "sdh", "sd0", "z";
355 };
8e181633
SU		 356 /* Variable factor clocks */
357 sd1_clk: sd2_clk@e6150078 {
358 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
359 reg = <0 0xe6150078 0 4>;
360 clocks = <&pll1_div2_clk>;
361 #clock-cells = <0>;
362 clock-output-names = "sd1";
363 };
364 sd2_clk: sd3_clk@e615007c {
365 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
366 reg = <0 0xe615007c 0 4>;
367 clocks = <&pll1_div2_clk>;
368 #clock-cells = <0>;
369 clock-output-names = "sd2";
370 };
deac150c
SU		 371 mmc0_clk: mmc0_clk@e6150240 {
372 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
373 reg = <0 0xe6150240 0 4>;
374 clocks = <&pll1_div2_clk>;
375 #clock-cells = <0>;
376 clock-output-names = "mmc0";
377 };
0dce5454
UH		 378
379 /* Fixed factor clocks */
380 pll1_div2_clk: pll1_div2_clk {
381 compatible = "fixed-factor-clock";
382 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
383 #clock-cells = <0>;
384 clock-div = <2>;
385 clock-mult = <1>;
386 clock-output-names = "pll1_div2";
387 };
388 zg_clk: zg_clk {
389 compatible = "fixed-factor-clock";
390 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
391 #clock-cells = <0>;
392 clock-div = <6>;
393 clock-mult = <1>;
394 clock-output-names = "zg";
395 };
396 zx_clk: zx_clk {
397 compatible = "fixed-factor-clock";
398 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
399 #clock-cells = <0>;
400 clock-div = <3>;
401 clock-mult = <1>;
402 clock-output-names = "zx";
403 };
404 zs_clk: zs_clk {
405 compatible = "fixed-factor-clock";
406 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
407 #clock-cells = <0>;
408 clock-div = <6>;
409 clock-mult = <1>;
410 clock-output-names = "zs";
411 };
412 hp_clk: hp_clk {
413 compatible = "fixed-factor-clock";
414 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
415 #clock-cells = <0>;
416 clock-div = <12>;
417 clock-mult = <1>;
418 clock-output-names = "hp";
419 };
420 i_clk: i_clk {
421 compatible = "fixed-factor-clock";
422 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
423 #clock-cells = <0>;
424 clock-div = <2>;
425 clock-mult = <1>;
426 clock-output-names = "i";
427 };
428 b_clk: b_clk {
429 compatible = "fixed-factor-clock";
430 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
431 #clock-cells = <0>;
432 clock-div = <12>;
433 clock-mult = <1>;
434 clock-output-names = "b";
435 };
436 p_clk: p_clk {
437 compatible = "fixed-factor-clock";
438 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
439 #clock-cells = <0>;
440 clock-div = <24>;
441 clock-mult = <1>;
442 clock-output-names = "p";
443 };
444 cl_clk: cl_clk {
445 compatible = "fixed-factor-clock";
446 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
447 #clock-cells = <0>;
448 clock-div = <48>;
449 clock-mult = <1>;
450 clock-output-names = "cl";
451 };
452 m2_clk: m2_clk {
453 compatible = "fixed-factor-clock";
454 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
455 #clock-cells = <0>;
456 clock-div = <8>;
457 clock-mult = <1>;
458 clock-output-names = "m2";
459 };
460 imp_clk: imp_clk {
461 compatible = "fixed-factor-clock";
462 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
463 #clock-cells = <0>;
464 clock-div = <4>;
465 clock-mult = <1>;
466 clock-output-names = "imp";
467 };
468 rclk_clk: rclk_clk {
469 compatible = "fixed-factor-clock";
470 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
471 #clock-cells = <0>;
472 clock-div = <(48 * 1024)>;
473 clock-mult = <1>;
474 clock-output-names = "rclk";
475 };
476 oscclk_clk: oscclk_clk {
477 compatible = "fixed-factor-clock";
478 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
479 #clock-cells = <0>;
480 clock-div = <(12 * 1024)>;
481 clock-mult = <1>;
482 clock-output-names = "oscclk";
483 };
484 zb3_clk: zb3_clk {
485 compatible = "fixed-factor-clock";
486 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
487 #clock-cells = <0>;
488 clock-div = <4>;
489 clock-mult = <1>;
490 clock-output-names = "zb3";
491 };
492 zb3d2_clk: zb3d2_clk {
493 compatible = "fixed-factor-clock";
494 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
495 #clock-cells = <0>;
496 clock-div = <8>;
497 clock-mult = <1>;
498 clock-output-names = "zb3d2";
499 };
500 ddr_clk: ddr_clk {
501 compatible = "fixed-factor-clock";
502 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
503 #clock-cells = <0>;
504 clock-div = <8>;
505 clock-mult = <1>;
506 clock-output-names = "ddr";
507 };
508 mp_clk: mp_clk {
509 compatible = "fixed-factor-clock";
510 clocks = <&pll1_div2_clk>;
511 #clock-cells = <0>;
512 clock-div = <15>;
513 clock-mult = <1>;
514 clock-output-names = "mp";
515 };
516 cp_clk: cp_clk {
517 compatible = "fixed-factor-clock";
518 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
519 #clock-cells = <0>;
520 clock-div = <48>;
521 clock-mult = <1>;
522 clock-output-names = "cp";
523 };
524
525 acp_clk: acp_clk {
526 compatible = "fixed-factor-clock";
527 clocks = <&extal_clk>;
528 #clock-cells = <0>;
529 clock-div = <2>;
530 clock-mult = <1>;
531 clock-output-names = "acp";
532 };
533
534 /* Gate clocks */
535 mstp0_clks: mstp0_clks@e6150130 {
536 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
537 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
538 clocks = <&mp_clk>;
539 #clock-cells = <1>;
1045d065 540 clock-indices = <R8A7794_CLK_MSIOF0>;
0dce5454
UH		 541 clock-output-names = "msiof0";
542 };
543 mstp1_clks: mstp1_clks@e6150134 {
544 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
545 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
dc3cf93d
YH		 546 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
547 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
548 <&zs_clk>, <&zs_clk>;
0dce5454 549 #clock-cells = <1>;
1045d065 550 clock-indices = <
dc3cf93d
YH		 551 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
552 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
553 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
554 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
0dce5454
UH		 555 >;
556 clock-output-names =
dc3cf93d
YH		 557 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
558 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
0dce5454
UH		 559 };
560 mstp2_clks: mstp2_clks@e6150138 {
561 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
562 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
563 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
be16cd38
HY		 564 <&mp_clk>, <&mp_clk>, <&mp_clk>,
565 <&zs_clk>, <&zs_clk>;
0dce5454 566 #clock-cells = <1>;
1045d065 567 clock-indices = <
0dce5454
UH		 568 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
569 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
570 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
be16cd38 571 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
0dce5454
UH		 572 >;
573 clock-output-names =
574 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
be16cd38
HY		 575 "scifb1", "msiof1", "scifb2",
576 "sys-dmac1", "sys-dmac0";
0dce5454
UH		 577 };
578 mstp3_clks: mstp3_clks@e615013c {
579 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
580 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
8e181633 581 clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
deac150c 582 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
0dce5454 583 #clock-cells = <1>;
1045d065 584 clock-indices = <
8e181633 585 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
deac150c
SU		 586 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
587 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
0dce5454
UH		 588 >;
589 clock-output-names =
8e181633 590 "sdhi2", "sdhi1", "sdhi0",
deac150c 591 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
0dce5454
UH		 592 };
593 mstp7_clks: mstp7_clks@e615014c {
594 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
595 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
c7bab9f9
SU		 596 clocks = <&mp_clk>, <&mp_clk>,
597 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
0dce5454
UH		 598 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
599 #clock-cells = <1>;
1045d065 600 clock-indices = <
c7bab9f9 601 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
0dce5454
UH		 602 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
603 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
604 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
605 R8A7794_CLK_SCIF0
606 >;
607 clock-output-names =
c7bab9f9 608 "ehci", "hsusb",
0dce5454
UH		 609 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
610 "scif3", "scif2", "scif1", "scif0";
611 };
612 mstp8_clks: mstp8_clks@e6150990 {
613 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
614 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
148ebf47 615 clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
0dce5454 616 #clock-cells = <1>;
1045d065 617 clock-indices = <
148ebf47 618 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
0dce5454
UH		 619 >;
620 clock-output-names =
148ebf47 621 "vin1", "vin0", "ether";
0dce5454 622 };
3281480b
HN		 623 mstp9_clks: mstp9_clks@e6150994 {
624 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
625 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
c5d82c99
KM		 626 clocks = <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
627 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
3281480b 628 #clock-cells = <1>;
c5d82c99
KM		 629 clock-indices = <
630 R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
631 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1
632 R8A7794_CLK_I2C0
633 >;
634 clock-output-names =
635 "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
3281480b 636 };
0dce5454
UH		 637 mstp11_clks: mstp11_clks@e615099c {
638 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
639 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
640 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
641 #clock-cells = <1>;
1045d065 642 clock-indices = <
0dce5454
UH		 643 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
644 >;
645 clock-output-names = "scifa3", "scifa4", "scifa5";
646 };
647 };
1cb2794f
LP		 648
649 ipmmu_sy0: mmu@e6280000 {
650 compatible = "renesas,ipmmu-vmsa";
651 reg = <0 0xe6280000 0 0x1000>;
652 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
653 <0 224 IRQ_TYPE_LEVEL_HIGH>;
654 #iommu-cells = <1>;
655 status = "disabled";
656 };
657
658 ipmmu_sy1: mmu@e6290000 {
659 compatible = "renesas,ipmmu-vmsa";
660 reg = <0 0xe6290000 0 0x1000>;
661 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
662 #iommu-cells = <1>;
663 status = "disabled";
664 };
665
666 ipmmu_ds: mmu@e6740000 {
667 compatible = "renesas,ipmmu-vmsa";
668 reg = <0 0xe6740000 0 0x1000>;
669 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
670 <0 199 IRQ_TYPE_LEVEL_HIGH>;
671 #iommu-cells = <1>;
672 };
673
674 ipmmu_mp: mmu@ec680000 {
675 compatible = "renesas,ipmmu-vmsa";
676 reg = <0 0xec680000 0 0x1000>;
677 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
678 #iommu-cells = <1>;
679 status = "disabled";
680 };
681
682 ipmmu_mx: mmu@fe951000 {
683 compatible = "renesas,ipmmu-vmsa";
684 reg = <0 0xfe951000 0 0x1000>;
685 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
686 <0 221 IRQ_TYPE_LEVEL_HIGH>;
687 #iommu-cells = <1>;
688 };
689
690 ipmmu_gp: mmu@e62a0000 {
691 compatible = "renesas,ipmmu-vmsa";
692 reg = <0 0xe62a0000 0 0x1000>;
693 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
694 <0 261 IRQ_TYPE_LEVEL_HIGH>;
695 #iommu-cells = <1>;
696 status = "disabled";
697 };
0dce5454 698};
Linux kernel - Deliverables
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