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ARM: shmobile: r8a7791: dtsi: add internal delay for i2c IPs
[deliverable/linux.git] / arch / arm / boot / dts / r8a7794.dtsi
CommitLineData
0dce5454
UH		 1/*
2 * Device Tree Source for the r8a7794 SoC
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <dt-bindings/clock/r8a7794-clock.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
16/ {
17 compatible = "renesas,r8a7794";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
740b4a9f 22 aliases {
5428521b
SS		 23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
740b4a9f 29 spi0 = &qspi;
1afe77ca
SS		 30 vin0 = &vin0;
31 vin1 = &vin1;
740b4a9f
SS		 32 };
33
0dce5454
UH		 34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu0: cpu@0 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a7";
41 reg = <0>;
42 clock-frequency = <1000000000>;
43 };
44
45 cpu1: cpu@1 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a7";
48 reg = <1>;
49 clock-frequency = <1000000000>;
50 };
51 };
52
53 gic: interrupt-controller@f1001000 {
c73ddf42 54 compatible = "arm,gic-400";
0dce5454
UH		 55 #interrupt-cells = <3>;
56 #address-cells = <0>;
57 interrupt-controller;
58 reg = <0 0xf1001000 0 0x1000>,
59 <0 0xf1002000 0 0x1000>,
60 <0 0xf1004000 0 0x2000>,
61 <0 0xf1006000 0 0x2000>;
00add867 62 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0dce5454
UH		 63 };
64
e8f5de3b
SS		 65 gpio0: gpio@e6050000 {
66 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
67 reg = <0 0xe6050000 0 0x50>;
68 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
69 #gpio-cells = <2>;
70 gpio-controller;
71 gpio-ranges = <&pfc 0 0 32>;
72 #interrupt-cells = <2>;
73 interrupt-controller;
74 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
75 power-domains = <&cpg_clocks>;
76 };
77
78 gpio1: gpio@e6051000 {
79 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
80 reg = <0 0xe6051000 0 0x50>;
81 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
82 #gpio-cells = <2>;
83 gpio-controller;
84 gpio-ranges = <&pfc 0 32 26>;
85 #interrupt-cells = <2>;
86 interrupt-controller;
87 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
88 power-domains = <&cpg_clocks>;
89 };
90
91 gpio2: gpio@e6052000 {
92 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
93 reg = <0 0xe6052000 0 0x50>;
94 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
95 #gpio-cells = <2>;
96 gpio-controller;
97 gpio-ranges = <&pfc 0 64 32>;
98 #interrupt-cells = <2>;
99 interrupt-controller;
100 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
101 power-domains = <&cpg_clocks>;
102 };
103
104 gpio3: gpio@e6053000 {
105 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
106 reg = <0 0xe6053000 0 0x50>;
107 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
108 #gpio-cells = <2>;
109 gpio-controller;
110 gpio-ranges = <&pfc 0 96 32>;
111 #interrupt-cells = <2>;
112 interrupt-controller;
113 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
114 power-domains = <&cpg_clocks>;
115 };
116
117 gpio4: gpio@e6054000 {
118 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
119 reg = <0 0xe6054000 0 0x50>;
120 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
121 #gpio-cells = <2>;
122 gpio-controller;
123 gpio-ranges = <&pfc 0 128 32>;
124 #interrupt-cells = <2>;
125 interrupt-controller;
126 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
127 power-domains = <&cpg_clocks>;
128 };
129
130 gpio5: gpio@e6055000 {
131 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
132 reg = <0 0xe6055000 0 0x50>;
133 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
134 #gpio-cells = <2>;
135 gpio-controller;
136 gpio-ranges = <&pfc 0 160 28>;
137 #interrupt-cells = <2>;
138 interrupt-controller;
139 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
140 power-domains = <&cpg_clocks>;
141 };
142
143 gpio6: gpio@e6055400 {
144 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
145 reg = <0 0xe6055400 0 0x50>;
146 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
147 #gpio-cells = <2>;
148 gpio-controller;
149 gpio-ranges = <&pfc 0 192 26>;
150 #interrupt-cells = <2>;
151 interrupt-controller;
152 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
153 power-domains = <&cpg_clocks>;
154 };
155
0dce5454
UH		 156 cmt0: timer@ffca0000 {
157 compatible = "renesas,cmt-48-gen2";
158 reg = <0 0xffca0000 0 0x1004>;
159 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
160 <0 143 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
162 clock-names = "fck";
60c0745a 163 power-domains = <&cpg_clocks>;
0dce5454
UH		 164
165 renesas,channels-mask = <0x60>;
166
167 status = "disabled";
168 };
169
170 cmt1: timer@e6130000 {
171 compatible = "renesas,cmt-48-gen2";
172 reg = <0 0xe6130000 0 0x1004>;
173 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
174 <0 121 IRQ_TYPE_LEVEL_HIGH>,
175 <0 122 IRQ_TYPE_LEVEL_HIGH>,
176 <0 123 IRQ_TYPE_LEVEL_HIGH>,
177 <0 124 IRQ_TYPE_LEVEL_HIGH>,
178 <0 125 IRQ_TYPE_LEVEL_HIGH>,
179 <0 126 IRQ_TYPE_LEVEL_HIGH>,
180 <0 127 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
182 clock-names = "fck";
60c0745a 183 power-domains = <&cpg_clocks>;
0dce5454
UH		 184
185 renesas,channels-mask = <0xff>;
186
187 status = "disabled";
188 };
189
da33648c
HN		 190 timer {
191 compatible = "arm,armv7-timer";
00add867
GU		 192 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
193 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
194 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
195 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
da33648c
HN		 196 };
197
0dce5454
UH		 198 irqc0: interrupt-controller@e61c0000 {
199 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
200 #interrupt-cells = <2>;
201 interrupt-controller;
202 reg = <0 0xe61c0000 0 0x200>;
203 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
204 <0 1 IRQ_TYPE_LEVEL_HIGH>,
205 <0 2 IRQ_TYPE_LEVEL_HIGH>,
206 <0 3 IRQ_TYPE_LEVEL_HIGH>,
207 <0 12 IRQ_TYPE_LEVEL_HIGH>,
208 <0 13 IRQ_TYPE_LEVEL_HIGH>,
209 <0 14 IRQ_TYPE_LEVEL_HIGH>,
210 <0 15 IRQ_TYPE_LEVEL_HIGH>,
211 <0 16 IRQ_TYPE_LEVEL_HIGH>,
212 <0 17 IRQ_TYPE_LEVEL_HIGH>;
1c5ca5db 213 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
60c0745a 214 power-domains = <&cpg_clocks>;
0dce5454
UH		 215 };
216
fd1683c1
SS		 217 pfc: pin-controller@e6060000 {
218 compatible = "renesas,pfc-r8a7794";
219 reg = <0 0xe6060000 0 0x11c>;
fd1683c1
SS		 220 };
221
bd847485 222 dmac0: dma-controller@e6700000 {
0a3d058b 223 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
bd847485
LP		 224 reg = <0 0xe6700000 0 0x20000>;
225 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
226 0 200 IRQ_TYPE_LEVEL_HIGH
227 0 201 IRQ_TYPE_LEVEL_HIGH
228 0 202 IRQ_TYPE_LEVEL_HIGH
229 0 203 IRQ_TYPE_LEVEL_HIGH
230 0 204 IRQ_TYPE_LEVEL_HIGH
231 0 205 IRQ_TYPE_LEVEL_HIGH
232 0 206 IRQ_TYPE_LEVEL_HIGH
233 0 207 IRQ_TYPE_LEVEL_HIGH
234 0 208 IRQ_TYPE_LEVEL_HIGH
235 0 209 IRQ_TYPE_LEVEL_HIGH
236 0 210 IRQ_TYPE_LEVEL_HIGH
237 0 211 IRQ_TYPE_LEVEL_HIGH
238 0 212 IRQ_TYPE_LEVEL_HIGH
239 0 213 IRQ_TYPE_LEVEL_HIGH
240 0 214 IRQ_TYPE_LEVEL_HIGH>;
241 interrupt-names = "error",
242 "ch0", "ch1", "ch2", "ch3",
243 "ch4", "ch5", "ch6", "ch7",
244 "ch8", "ch9", "ch10", "ch11",
245 "ch12", "ch13", "ch14";
246 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
247 clock-names = "fck";
60c0745a 248 power-domains = <&cpg_clocks>;
bd847485
LP		 249 #dma-cells = <1>;
250 dma-channels = <15>;
251 };
252
253 dmac1: dma-controller@e6720000 {
0a3d058b 254 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
bd847485
LP		 255 reg = <0 0xe6720000 0 0x20000>;
256 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
257 0 216 IRQ_TYPE_LEVEL_HIGH
258 0 217 IRQ_TYPE_LEVEL_HIGH
259 0 218 IRQ_TYPE_LEVEL_HIGH
260 0 219 IRQ_TYPE_LEVEL_HIGH
261 0 308 IRQ_TYPE_LEVEL_HIGH
262 0 309 IRQ_TYPE_LEVEL_HIGH
263 0 310 IRQ_TYPE_LEVEL_HIGH
264 0 311 IRQ_TYPE_LEVEL_HIGH
265 0 312 IRQ_TYPE_LEVEL_HIGH
266 0 313 IRQ_TYPE_LEVEL_HIGH
267 0 314 IRQ_TYPE_LEVEL_HIGH
268 0 315 IRQ_TYPE_LEVEL_HIGH
269 0 316 IRQ_TYPE_LEVEL_HIGH
270 0 317 IRQ_TYPE_LEVEL_HIGH
271 0 318 IRQ_TYPE_LEVEL_HIGH>;
272 interrupt-names = "error",
273 "ch0", "ch1", "ch2", "ch3",
274 "ch4", "ch5", "ch6", "ch7",
275 "ch8", "ch9", "ch10", "ch11",
276 "ch12", "ch13", "ch14";
277 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
278 clock-names = "fck";
60c0745a 279 power-domains = <&cpg_clocks>;
bd847485
LP		 280 #dma-cells = <1>;
281 dma-channels = <15>;
282 };
283
0dce5454
UH		 284 scifa0: serial@e6c40000 {
285 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
286 reg = <0 0xe6c40000 0 64>;
287 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
289 clock-names = "sci_ick";
8233a0de
GU		 290 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
291 dma-names = "tx", "rx";
60c0745a 292 power-domains = <&cpg_clocks>;
0dce5454
UH		 293 status = "disabled";
294 };
295
296 scifa1: serial@e6c50000 {
297 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
298 reg = <0 0xe6c50000 0 64>;
299 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
301 clock-names = "sci_ick";
8233a0de
GU		 302 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
303 dma-names = "tx", "rx";
60c0745a 304 power-domains = <&cpg_clocks>;
0dce5454
UH		 305 status = "disabled";
306 };
307
308 scifa2: serial@e6c60000 {
309 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
310 reg = <0 0xe6c60000 0 64>;
311 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
313 clock-names = "sci_ick";
8233a0de
GU		 314 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
315 dma-names = "tx", "rx";
60c0745a 316 power-domains = <&cpg_clocks>;
0dce5454
UH		 317 status = "disabled";
318 };
319
320 scifa3: serial@e6c70000 {
321 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
322 reg = <0 0xe6c70000 0 64>;
323 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
325 clock-names = "sci_ick";
8233a0de
GU		 326 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
327 dma-names = "tx", "rx";
60c0745a 328 power-domains = <&cpg_clocks>;
0dce5454
UH		 329 status = "disabled";
330 };
331
332 scifa4: serial@e6c78000 {
333 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
334 reg = <0 0xe6c78000 0 64>;
335 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
337 clock-names = "sci_ick";
8233a0de
GU		 338 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
339 dma-names = "tx", "rx";
60c0745a 340 power-domains = <&cpg_clocks>;
0dce5454
UH		 341 status = "disabled";
342 };
343
344 scifa5: serial@e6c80000 {
345 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
346 reg = <0 0xe6c80000 0 64>;
347 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
349 clock-names = "sci_ick";
8233a0de
GU		 350 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
351 dma-names = "tx", "rx";
60c0745a 352 power-domains = <&cpg_clocks>;
0dce5454
UH		 353 status = "disabled";
354 };
355
356 scifb0: serial@e6c20000 {
357 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
358 reg = <0 0xe6c20000 0 64>;
359 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
361 clock-names = "sci_ick";
8233a0de
GU		 362 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
363 dma-names = "tx", "rx";
60c0745a 364 power-domains = <&cpg_clocks>;
0dce5454
UH		 365 status = "disabled";
366 };
367
368 scifb1: serial@e6c30000 {
369 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
370 reg = <0 0xe6c30000 0 64>;
371 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
373 clock-names = "sci_ick";
8233a0de
GU		 374 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
375 dma-names = "tx", "rx";
60c0745a 376 power-domains = <&cpg_clocks>;
0dce5454
UH		 377 status = "disabled";
378 };
379
380 scifb2: serial@e6ce0000 {
381 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
382 reg = <0 0xe6ce0000 0 64>;
383 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
385 clock-names = "sci_ick";
8233a0de
GU		 386 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
387 dma-names = "tx", "rx";
60c0745a 388 power-domains = <&cpg_clocks>;
0dce5454
UH		 389 status = "disabled";
390 };
391
392 scif0: serial@e6e60000 {
393 compatible = "renesas,scif-r8a7794", "renesas,scif";
394 reg = <0 0xe6e60000 0 64>;
395 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
397 clock-names = "sci_ick";
8233a0de
GU		 398 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
399 dma-names = "tx", "rx";
60c0745a 400 power-domains = <&cpg_clocks>;
0dce5454
UH		 401 status = "disabled";
402 };
403
404 scif1: serial@e6e68000 {
405 compatible = "renesas,scif-r8a7794", "renesas,scif";
406 reg = <0 0xe6e68000 0 64>;
407 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
409 clock-names = "sci_ick";
8233a0de
GU		 410 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
411 dma-names = "tx", "rx";
60c0745a 412 power-domains = <&cpg_clocks>;
0dce5454
UH		 413 status = "disabled";
414 };
415
416 scif2: serial@e6e58000 {
417 compatible = "renesas,scif-r8a7794", "renesas,scif";
418 reg = <0 0xe6e58000 0 64>;
419 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
421 clock-names = "sci_ick";
8233a0de
GU		 422 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
423 dma-names = "tx", "rx";
60c0745a 424 power-domains = <&cpg_clocks>;
0dce5454
UH		 425 status = "disabled";
426 };
427
428 scif3: serial@e6ea8000 {
429 compatible = "renesas,scif-r8a7794", "renesas,scif";
430 reg = <0 0xe6ea8000 0 64>;
431 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
433 clock-names = "sci_ick";
8233a0de
GU		 434 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
435 dma-names = "tx", "rx";
60c0745a 436 power-domains = <&cpg_clocks>;
0dce5454
UH		 437 status = "disabled";
438 };
439
440 scif4: serial@e6ee0000 {
441 compatible = "renesas,scif-r8a7794", "renesas,scif";
442 reg = <0 0xe6ee0000 0 64>;
443 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
445 clock-names = "sci_ick";
8233a0de
GU		 446 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
447 dma-names = "tx", "rx";
60c0745a 448 power-domains = <&cpg_clocks>;
0dce5454
UH		 449 status = "disabled";
450 };
451
452 scif5: serial@e6ee8000 {
453 compatible = "renesas,scif-r8a7794", "renesas,scif";
454 reg = <0 0xe6ee8000 0 64>;
455 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
457 clock-names = "sci_ick";
8233a0de
GU		 458 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
459 dma-names = "tx", "rx";
60c0745a 460 power-domains = <&cpg_clocks>;
0dce5454
UH		 461 status = "disabled";
462 };
463
464 hscif0: serial@e62c0000 {
465 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
466 reg = <0 0xe62c0000 0 96>;
467 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
469 clock-names = "sci_ick";
8233a0de
GU		 470 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
471 dma-names = "tx", "rx";
60c0745a 472 power-domains = <&cpg_clocks>;
0dce5454
UH		 473 status = "disabled";
474 };
475
476 hscif1: serial@e62c8000 {
477 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
478 reg = <0 0xe62c8000 0 96>;
479 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
481 clock-names = "sci_ick";
8233a0de
GU		 482 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
483 dma-names = "tx", "rx";
60c0745a 484 power-domains = <&cpg_clocks>;
0dce5454
UH		 485 status = "disabled";
486 };
487
488 hscif2: serial@e62d0000 {
489 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
490 reg = <0 0xe62d0000 0 96>;
491 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
493 clock-names = "sci_ick";
8233a0de
GU		 494 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
495 dma-names = "tx", "rx";
60c0745a 496 power-domains = <&cpg_clocks>;
0dce5454
UH		 497 status = "disabled";
498 };
499
82818d34
LP		 500 ether: ethernet@ee700000 {
501 compatible = "renesas,ether-r8a7794";
502 reg = <0 0xee700000 0 0x400>;
503 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
60c0745a 505 power-domains = <&cpg_clocks>;
82818d34
LP		 506 phy-mode = "rmii";
507 #address-cells = <1>;
508 #size-cells = <0>;
509 status = "disabled";
510 };
511
5428521b
SS		 512 /* The memory map in the User's Manual maps the cores to bus numbers */
513 i2c0: i2c@e6508000 {
514 compatible = "renesas,i2c-r8a7794";
515 reg = <0 0xe6508000 0 0x40>;
516 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
518 power-domains = <&cpg_clocks>;
519 #address-cells = <1>;
520 #size-cells = <0>;
521 status = "disabled";
522 };
523
524 i2c1: i2c@e6518000 {
525 compatible = "renesas,i2c-r8a7794";
526 reg = <0 0xe6518000 0 0x40>;
527 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
529 power-domains = <&cpg_clocks>;
530 #address-cells = <1>;
531 #size-cells = <0>;
532 status = "disabled";
533 };
534
535 i2c2: i2c@e6530000 {
536 compatible = "renesas,i2c-r8a7794";
537 reg = <0 0xe6530000 0 0x40>;
538 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
540 power-domains = <&cpg_clocks>;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 status = "disabled";
544 };
545
546 i2c3: i2c@e6540000 {
547 compatible = "renesas,i2c-r8a7794";
548 reg = <0 0xe6540000 0 0x40>;
549 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
551 power-domains = <&cpg_clocks>;
552 #address-cells = <1>;
553 #size-cells = <0>;
554 status = "disabled";
555 };
556
557 i2c4: i2c@e6520000 {
558 compatible = "renesas,i2c-r8a7794";
559 reg = <0 0xe6520000 0 0x40>;
560 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
562 power-domains = <&cpg_clocks>;
563 #address-cells = <1>;
564 #size-cells = <0>;
565 status = "disabled";
566 };
567
568 i2c5: i2c@e6528000 {
569 compatible = "renesas,i2c-r8a7794";
570 reg = <0 0xe6528000 0 0x40>;
571 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
573 power-domains = <&cpg_clocks>;
574 #address-cells = <1>;
575 #size-cells = <0>;
576 status = "disabled";
577 };
578
6cdf6ba1
SS		 579 mmcif0: mmc@ee200000 {
580 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
581 reg = <0 0xee200000 0 0x80>;
582 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
584 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
585 dma-names = "tx", "rx";
60c0745a 586 power-domains = <&cpg_clocks>;
6cdf6ba1
SS		 587 reg-io-width = <4>;
588 status = "disabled";
589 };
590
b8e8ea12
SS		 591 sdhi0: sd@ee100000 {
592 compatible = "renesas,sdhi-r8a7794";
593 reg = <0 0xee100000 0 0x200>;
594 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
60c0745a 596 power-domains = <&cpg_clocks>;
b8e8ea12
SS		 597 status = "disabled";
598 };
599
600 sdhi1: sd@ee140000 {
601 compatible = "renesas,sdhi-r8a7794";
602 reg = <0 0xee140000 0 0x100>;
603 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
60c0745a 605 power-domains = <&cpg_clocks>;
b8e8ea12
SS		 606 status = "disabled";
607 };
608
609 sdhi2: sd@ee160000 {
610 compatible = "renesas,sdhi-r8a7794";
611 reg = <0 0xee160000 0 0x100>;
612 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
60c0745a 614 power-domains = <&cpg_clocks>;
b8e8ea12
SS		 615 status = "disabled";
616 };
617
740b4a9f
SS		 618 qspi: spi@e6b10000 {
619 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
620 reg = <0 0xe6b10000 0 0x2c>;
621 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
623 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
624 dma-names = "tx", "rx";
625 power-domains = <&cpg_clocks>;
626 num-cs = <1>;
627 #address-cells = <1>;
628 #size-cells = <0>;
629 status = "disabled";
630 };
631
1afe77ca
SS		 632 vin0: video@e6ef0000 {
633 compatible = "renesas,vin-r8a7794";
634 reg = <0 0xe6ef0000 0 0x1000>;
635 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
637 power-domains = <&cpg_clocks>;
638 status = "disabled";
639 };
640
641 vin1: video@e6ef1000 {
642 compatible = "renesas,vin-r8a7794";
643 reg = <0 0xe6ef1000 0 0x1000>;
644 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
646 power-domains = <&cpg_clocks>;
647 status = "disabled";
648 };
649
a6a130b3
SS		 650 pci0: pci@ee090000 {
651 compatible = "renesas,pci-r8a7794";
652 device_type = "pci";
653 reg = <0 0xee090000 0 0xc00>,
654 <0 0xee080000 0 0x1100>;
655 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
657 power-domains = <&cpg_clocks>;
658 status = "disabled";
659
660 bus-range = <0 0>;
661 #address-cells = <3>;
662 #size-cells = <2>;
663 #interrupt-cells = <1>;
664 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
665 interrupt-map-mask = <0xff00 0 0 0x7>;
666 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
667 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
668 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
45cb0bd7
SS		 669
670 usb@0,1 {
671 reg = <0x800 0 0 0 0>;
672 device_type = "pci";
673 phys = <&usb0 0>;
674 phy-names = "usb";
675 };
676
677 usb@0,2 {
678 reg = <0x1000 0 0 0 0>;
679 device_type = "pci";
680 phys = <&usb0 0>;
681 phy-names = "usb";
682 };
a6a130b3
SS		 683 };
684
685 pci1: pci@ee0d0000 {
686 compatible = "renesas,pci-r8a7794";
687 device_type = "pci";
688 reg = <0 0xee0d0000 0 0xc00>,
689 <0 0xee0c0000 0 0x1100>;
690 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
692 power-domains = <&cpg_clocks>;
693 status = "disabled";
694
695 bus-range = <1 1>;
696 #address-cells = <3>;
697 #size-cells = <2>;
698 #interrupt-cells = <1>;
699 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
700 interrupt-map-mask = <0xff00 0 0 0x7>;
701 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
702 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
703 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
45cb0bd7
SS		 704
705 usb@0,1 {
706 reg = <0x800 0 0 0 0>;
707 device_type = "pci";
708 phys = <&usb2 0>;
709 phy-names = "usb";
710 };
711
712 usb@0,2 {
713 reg = <0x1000 0 0 0 0>;
714 device_type = "pci";
715 phys = <&usb2 0>;
716 phy-names = "usb";
717 };
a6a130b3
SS		 718 };
719
2f33b9f7
SS		 720 hsusb: usb@e6590000 {
721 compatible = "renesas,usbhs-r8a7794";
722 reg = <0 0xe6590000 0 0x100>;
723 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
725 power-domains = <&cpg_clocks>;
726 renesas,buswait = <4>;
727 phys = <&usb0 1>;
728 phy-names = "usb";
729 status = "disabled";
730 };
731
74ef4572
SS		 732 usbphy: usb-phy@e6590100 {
733 compatible = "renesas,usb-phy-r8a7794";
734 reg = <0 0xe6590100 0 0x100>;
735 #address-cells = <1>;
736 #size-cells = <0>;
737 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
738 clock-names = "usbhs";
739 power-domains = <&cpg_clocks>;
740 status = "disabled";
741
742 usb0: usb-channel@0 {
743 reg = <0>;
744 #phy-cells = <1>;
745 };
746 usb2: usb-channel@2 {
747 reg = <2>;
748 #phy-cells = <1>;
749 };
750 };
751
46c4f13d
LP		 752 du: display@feb00000 {
753 compatible = "renesas,du-r8a7794";
754 reg = <0 0xfeb00000 0 0x40000>;
755 reg-names = "du";
756 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
757 <0 268 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
759 <&mstp7_clks R8A7794_CLK_DU0>;
760 clock-names = "du.0", "du.1";
761 status = "disabled";
762
763 ports {
764 #address-cells = <1>;
765 #size-cells = <0>;
766
767 port@0 {
768 reg = <0>;
769 du_out_rgb0: endpoint {
770 };
771 };
772 port@1 {
773 reg = <1>;
774 du_out_rgb1: endpoint {
775 };
776 };
777 };
778 };
779
0dce5454
UH		 780 clocks {
781 #address-cells = <2>;
782 #size-cells = <2>;
783 ranges;
784
785 /* External root clock */
786 extal_clk: extal_clk {
787 compatible = "fixed-clock";
788 #clock-cells = <0>;
789 /* This value must be overriden by the board. */
790 clock-frequency = <0>;
791 clock-output-names = "extal";
792 };
793
794 /* Special CPG clocks */
795 cpg_clocks: cpg_clocks@e6150000 {
796 compatible = "renesas,r8a7794-cpg-clocks",
797 "renesas,rcar-gen2-cpg-clocks";
798 reg = <0 0xe6150000 0 0x1000>;
799 clocks = <&extal_clk>;
800 #clock-cells = <1>;
801 clock-output-names = "main", "pll0", "pll1", "pll3",
802 "lb", "qspi", "sdh", "sd0", "z";
60c0745a 803 #power-domain-cells = <0>;
0dce5454 804 };
8e181633 805 /* Variable factor clocks */
5e7e1554 806 sd2_clk: sd2_clk@e6150078 {
8e181633
SU		 807 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
808 reg = <0 0xe6150078 0 4>;
809 clocks = <&pll1_div2_clk>;
810 #clock-cells = <0>;
5e7e1554 811 clock-output-names = "sd2";
8e181633 812 };
5e7e1554 813 sd3_clk: sd3_clk@e615026c {
8e181633 814 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
5e7e1554 815 reg = <0 0xe615026c 0 4>;
8e181633
SU		 816 clocks = <&pll1_div2_clk>;
817 #clock-cells = <0>;
5e7e1554 818 clock-output-names = "sd3";
8e181633 819 };
deac150c
SU		 820 mmc0_clk: mmc0_clk@e6150240 {
821 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
822 reg = <0 0xe6150240 0 4>;
823 clocks = <&pll1_div2_clk>;
824 #clock-cells = <0>;
825 clock-output-names = "mmc0";
826 };
0dce5454
UH		 827
828 /* Fixed factor clocks */
829 pll1_div2_clk: pll1_div2_clk {
830 compatible = "fixed-factor-clock";
831 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
832 #clock-cells = <0>;
833 clock-div = <2>;
834 clock-mult = <1>;
835 clock-output-names = "pll1_div2";
836 };
837 zg_clk: zg_clk {
838 compatible = "fixed-factor-clock";
839 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
840 #clock-cells = <0>;
841 clock-div = <6>;
842 clock-mult = <1>;
843 clock-output-names = "zg";
844 };
845 zx_clk: zx_clk {
846 compatible = "fixed-factor-clock";
847 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
848 #clock-cells = <0>;
849 clock-div = <3>;
850 clock-mult = <1>;
851 clock-output-names = "zx";
852 };
853 zs_clk: zs_clk {
854 compatible = "fixed-factor-clock";
855 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
856 #clock-cells = <0>;
857 clock-div = <6>;
858 clock-mult = <1>;
859 clock-output-names = "zs";
860 };
861 hp_clk: hp_clk {
862 compatible = "fixed-factor-clock";
863 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
864 #clock-cells = <0>;
865 clock-div = <12>;
866 clock-mult = <1>;
867 clock-output-names = "hp";
868 };
869 i_clk: i_clk {
870 compatible = "fixed-factor-clock";
871 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
872 #clock-cells = <0>;
873 clock-div = <2>;
874 clock-mult = <1>;
875 clock-output-names = "i";
876 };
877 b_clk: b_clk {
878 compatible = "fixed-factor-clock";
879 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
880 #clock-cells = <0>;
881 clock-div = <12>;
882 clock-mult = <1>;
883 clock-output-names = "b";
884 };
885 p_clk: p_clk {
886 compatible = "fixed-factor-clock";
887 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
888 #clock-cells = <0>;
889 clock-div = <24>;
890 clock-mult = <1>;
891 clock-output-names = "p";
892 };
893 cl_clk: cl_clk {
894 compatible = "fixed-factor-clock";
895 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
896 #clock-cells = <0>;
897 clock-div = <48>;
898 clock-mult = <1>;
899 clock-output-names = "cl";
900 };
901 m2_clk: m2_clk {
902 compatible = "fixed-factor-clock";
903 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
904 #clock-cells = <0>;
905 clock-div = <8>;
906 clock-mult = <1>;
907 clock-output-names = "m2";
908 };
0dce5454
UH		 909 rclk_clk: rclk_clk {
910 compatible = "fixed-factor-clock";
911 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
912 #clock-cells = <0>;
913 clock-div = <(48 * 1024)>;
914 clock-mult = <1>;
915 clock-output-names = "rclk";
916 };
917 oscclk_clk: oscclk_clk {
918 compatible = "fixed-factor-clock";
919 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
920 #clock-cells = <0>;
921 clock-div = <(12 * 1024)>;
922 clock-mult = <1>;
923 clock-output-names = "oscclk";
924 };
925 zb3_clk: zb3_clk {
926 compatible = "fixed-factor-clock";
927 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
928 #clock-cells = <0>;
929 clock-div = <4>;
930 clock-mult = <1>;
931 clock-output-names = "zb3";
932 };
933 zb3d2_clk: zb3d2_clk {
934 compatible = "fixed-factor-clock";
935 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
936 #clock-cells = <0>;
937 clock-div = <8>;
938 clock-mult = <1>;
939 clock-output-names = "zb3d2";
940 };
941 ddr_clk: ddr_clk {
942 compatible = "fixed-factor-clock";
943 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
944 #clock-cells = <0>;
945 clock-div = <8>;
946 clock-mult = <1>;
947 clock-output-names = "ddr";
948 };
949 mp_clk: mp_clk {
950 compatible = "fixed-factor-clock";
951 clocks = <&pll1_div2_clk>;
952 #clock-cells = <0>;
953 clock-div = <15>;
954 clock-mult = <1>;
955 clock-output-names = "mp";
956 };
957 cp_clk: cp_clk {
958 compatible = "fixed-factor-clock";
959 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
960 #clock-cells = <0>;
961 clock-div = <48>;
962 clock-mult = <1>;
963 clock-output-names = "cp";
964 };
965
966 acp_clk: acp_clk {
967 compatible = "fixed-factor-clock";
968 clocks = <&extal_clk>;
969 #clock-cells = <0>;
970 clock-div = <2>;
971 clock-mult = <1>;
972 clock-output-names = "acp";
973 };
974
975 /* Gate clocks */
976 mstp0_clks: mstp0_clks@e6150130 {
977 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
978 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
979 clocks = <&mp_clk>;
980 #clock-cells = <1>;
1045d065 981 clock-indices = <R8A7794_CLK_MSIOF0>;
0dce5454
UH		 982 clock-output-names = "msiof0";
983 };
984 mstp1_clks: mstp1_clks@e6150134 {
985 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
986 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
dc3cf93d
YH		 987 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
988 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
989 <&zs_clk>, <&zs_clk>;
0dce5454 990 #clock-cells = <1>;
1045d065 991 clock-indices = <
dc3cf93d
YH		 992 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
993 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
994 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
995 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
0dce5454
UH		 996 >;
997 clock-output-names =
dc3cf93d
YH		 998 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
999 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
0dce5454
UH		 1000 };
1001 mstp2_clks: mstp2_clks@e6150138 {
1002 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1003 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1004 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
be16cd38
HY		 1005 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1006 <&zs_clk>, <&zs_clk>;
0dce5454 1007 #clock-cells = <1>;
1045d065 1008 clock-indices = <
0dce5454
UH		 1009 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1010 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1011 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
be16cd38 1012 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
0dce5454
UH		 1013 >;
1014 clock-output-names =
1015 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
be16cd38
HY		 1016 "scifb1", "msiof1", "scifb2",
1017 "sys-dmac1", "sys-dmac0";
0dce5454
UH		 1018 };
1019 mstp3_clks: mstp3_clks@e615013c {
1020 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1021 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
5e7e1554 1022 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
deac150c 1023 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
0dce5454 1024 #clock-cells = <1>;
1045d065 1025 clock-indices = <
8e181633 1026 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
deac150c
SU		 1027 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
1028 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
0dce5454
UH		 1029 >;
1030 clock-output-names =
8e181633 1031 "sdhi2", "sdhi1", "sdhi0",
deac150c 1032 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
0dce5454 1033 };
1c5ca5db
GU		 1034 mstp4_clks: mstp4_clks@e6150140 {
1035 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1036 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1037 clocks = <&cp_clk>;
1038 #clock-cells = <1>;
1039 clock-indices = <R8A7794_CLK_IRQC>;
1040 clock-output-names = "irqc";
1041 };
0dce5454
UH		 1042 mstp7_clks: mstp7_clks@e615014c {
1043 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1044 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
c7bab9f9
SU		 1045 clocks = <&mp_clk>, <&mp_clk>,
1046 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
9859cd3b
LP		 1047 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1048 <&zx_clk>;
0dce5454 1049 #clock-cells = <1>;
1045d065 1050 clock-indices = <
c7bab9f9 1051 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
0dce5454
UH		 1052 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1053 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1054 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
9859cd3b 1055 R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
0dce5454
UH		 1056 >;
1057 clock-output-names =
c7bab9f9 1058 "ehci", "hsusb",
0dce5454 1059 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
9859cd3b 1060 "scif3", "scif2", "scif1", "scif0", "du0";
0dce5454
UH		 1061 };
1062 mstp8_clks: mstp8_clks@e6150990 {
1063 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1064 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
148ebf47 1065 clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
0dce5454 1066 #clock-cells = <1>;
1045d065 1067 clock-indices = <
148ebf47 1068 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
0dce5454
UH		 1069 >;
1070 clock-output-names =
148ebf47 1071 "vin1", "vin0", "ether";
0dce5454 1072 };
3281480b
HN		 1073 mstp9_clks: mstp9_clks@e6150994 {
1074 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1075 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
3f37e018
SS		 1076 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1077 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1078 <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
1079 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
3281480b 1080 #clock-cells = <1>;
3f37e018
SS		 1081 clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1082 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1083 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1084 R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD
1085 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1086 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1087 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
c5d82c99 1088 clock-output-names =
3f37e018
SS		 1089 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1090 "gpio1", "gpio0", "qspi_mod",
1091 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
3281480b 1092 };
0dce5454
UH		 1093 mstp11_clks: mstp11_clks@e615099c {
1094 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1095 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1096 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1097 #clock-cells = <1>;
1045d065 1098 clock-indices = <
0dce5454
UH		 1099 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1100 >;
1101 clock-output-names = "scifa3", "scifa4", "scifa5";
1102 };
1103 };
1cb2794f
LP		 1104
1105 ipmmu_sy0: mmu@e6280000 {
1106 compatible = "renesas,ipmmu-vmsa";
1107 reg = <0 0xe6280000 0 0x1000>;
1108 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1109 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1110 #iommu-cells = <1>;
1111 status = "disabled";
1112 };
1113
1114 ipmmu_sy1: mmu@e6290000 {
1115 compatible = "renesas,ipmmu-vmsa";
1116 reg = <0 0xe6290000 0 0x1000>;
1117 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1118 #iommu-cells = <1>;
1119 status = "disabled";
1120 };
1121
1122 ipmmu_ds: mmu@e6740000 {
1123 compatible = "renesas,ipmmu-vmsa";
1124 reg = <0 0xe6740000 0 0x1000>;
1125 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1126 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1127 #iommu-cells = <1>;
832d3e4c 1128 status = "disabled";
1cb2794f
LP		 1129 };
1130
1131 ipmmu_mp: mmu@ec680000 {
1132 compatible = "renesas,ipmmu-vmsa";
1133 reg = <0 0xec680000 0 0x1000>;
1134 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1135 #iommu-cells = <1>;
1136 status = "disabled";
1137 };
1138
1139 ipmmu_mx: mmu@fe951000 {
1140 compatible = "renesas,ipmmu-vmsa";
1141 reg = <0 0xfe951000 0 0x1000>;
1142 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1143 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1144 #iommu-cells = <1>;
832d3e4c 1145 status = "disabled";
1cb2794f
LP		 1146 };
1147
1148 ipmmu_gp: mmu@e62a0000 {
1149 compatible = "renesas,ipmmu-vmsa";
1150 reg = <0 0xe62a0000 0 0x1000>;
1151 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
1152 <0 261 IRQ_TYPE_LEVEL_HIGH>;
1153 #iommu-cells = <1>;
1154 status = "disabled";
1155 };
0dce5454 1156};
Linux kernel - Deliverables
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