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0dce5454 UH |
1 | /* |
2 | * Device Tree Source for the r8a7794 SoC | |
3 | * | |
4 | * Copyright (C) 2014 Renesas Electronics Corporation | |
5 | * Copyright (C) 2014 Ulrich Hecht | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <dt-bindings/clock/r8a7794-clock.h> | |
13 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
14 | #include <dt-bindings/interrupt-controller/irq.h> | |
15 | ||
16 | / { | |
17 | compatible = "renesas,r8a7794"; | |
18 | interrupt-parent = <&gic>; | |
19 | #address-cells = <2>; | |
20 | #size-cells = <2>; | |
21 | ||
22 | cpus { | |
23 | #address-cells = <1>; | |
24 | #size-cells = <0>; | |
25 | ||
26 | cpu0: cpu@0 { | |
27 | device_type = "cpu"; | |
28 | compatible = "arm,cortex-a7"; | |
29 | reg = <0>; | |
30 | clock-frequency = <1000000000>; | |
31 | }; | |
32 | ||
33 | cpu1: cpu@1 { | |
34 | device_type = "cpu"; | |
35 | compatible = "arm,cortex-a7"; | |
36 | reg = <1>; | |
37 | clock-frequency = <1000000000>; | |
38 | }; | |
39 | }; | |
40 | ||
41 | gic: interrupt-controller@f1001000 { | |
c73ddf42 | 42 | compatible = "arm,gic-400"; |
0dce5454 UH |
43 | #interrupt-cells = <3>; |
44 | #address-cells = <0>; | |
45 | interrupt-controller; | |
46 | reg = <0 0xf1001000 0 0x1000>, | |
47 | <0 0xf1002000 0 0x1000>, | |
48 | <0 0xf1004000 0 0x2000>, | |
49 | <0 0xf1006000 0 0x2000>; | |
00add867 | 50 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
0dce5454 UH |
51 | }; |
52 | ||
53 | cmt0: timer@ffca0000 { | |
54 | compatible = "renesas,cmt-48-gen2"; | |
55 | reg = <0 0xffca0000 0 0x1004>; | |
56 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, | |
57 | <0 143 IRQ_TYPE_LEVEL_HIGH>; | |
58 | clocks = <&mstp1_clks R8A7794_CLK_CMT0>; | |
59 | clock-names = "fck"; | |
60 | ||
61 | renesas,channels-mask = <0x60>; | |
62 | ||
63 | status = "disabled"; | |
64 | }; | |
65 | ||
66 | cmt1: timer@e6130000 { | |
67 | compatible = "renesas,cmt-48-gen2"; | |
68 | reg = <0 0xe6130000 0 0x1004>; | |
69 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, | |
70 | <0 121 IRQ_TYPE_LEVEL_HIGH>, | |
71 | <0 122 IRQ_TYPE_LEVEL_HIGH>, | |
72 | <0 123 IRQ_TYPE_LEVEL_HIGH>, | |
73 | <0 124 IRQ_TYPE_LEVEL_HIGH>, | |
74 | <0 125 IRQ_TYPE_LEVEL_HIGH>, | |
75 | <0 126 IRQ_TYPE_LEVEL_HIGH>, | |
76 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
77 | clocks = <&mstp3_clks R8A7794_CLK_CMT1>; | |
78 | clock-names = "fck"; | |
79 | ||
80 | renesas,channels-mask = <0xff>; | |
81 | ||
82 | status = "disabled"; | |
83 | }; | |
84 | ||
da33648c HN |
85 | timer { |
86 | compatible = "arm,armv7-timer"; | |
00add867 GU |
87 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
88 | <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
89 | <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
90 | <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
da33648c HN |
91 | }; |
92 | ||
0dce5454 UH |
93 | irqc0: interrupt-controller@e61c0000 { |
94 | compatible = "renesas,irqc-r8a7794", "renesas,irqc"; | |
95 | #interrupt-cells = <2>; | |
96 | interrupt-controller; | |
97 | reg = <0 0xe61c0000 0 0x200>; | |
98 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, | |
99 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | |
100 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | |
101 | <0 3 IRQ_TYPE_LEVEL_HIGH>, | |
102 | <0 12 IRQ_TYPE_LEVEL_HIGH>, | |
103 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
104 | <0 14 IRQ_TYPE_LEVEL_HIGH>, | |
105 | <0 15 IRQ_TYPE_LEVEL_HIGH>, | |
106 | <0 16 IRQ_TYPE_LEVEL_HIGH>, | |
107 | <0 17 IRQ_TYPE_LEVEL_HIGH>; | |
1c5ca5db | 108 | clocks = <&mstp4_clks R8A7794_CLK_IRQC>; |
0dce5454 UH |
109 | }; |
110 | ||
fd1683c1 SS |
111 | pfc: pin-controller@e6060000 { |
112 | compatible = "renesas,pfc-r8a7794"; | |
113 | reg = <0 0xe6060000 0 0x11c>; | |
114 | #gpio-range-cells = <3>; | |
115 | }; | |
116 | ||
bd847485 LP |
117 | dmac0: dma-controller@e6700000 { |
118 | compatible = "renesas,rcar-dmac"; | |
119 | reg = <0 0xe6700000 0 0x20000>; | |
120 | interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH | |
121 | 0 200 IRQ_TYPE_LEVEL_HIGH | |
122 | 0 201 IRQ_TYPE_LEVEL_HIGH | |
123 | 0 202 IRQ_TYPE_LEVEL_HIGH | |
124 | 0 203 IRQ_TYPE_LEVEL_HIGH | |
125 | 0 204 IRQ_TYPE_LEVEL_HIGH | |
126 | 0 205 IRQ_TYPE_LEVEL_HIGH | |
127 | 0 206 IRQ_TYPE_LEVEL_HIGH | |
128 | 0 207 IRQ_TYPE_LEVEL_HIGH | |
129 | 0 208 IRQ_TYPE_LEVEL_HIGH | |
130 | 0 209 IRQ_TYPE_LEVEL_HIGH | |
131 | 0 210 IRQ_TYPE_LEVEL_HIGH | |
132 | 0 211 IRQ_TYPE_LEVEL_HIGH | |
133 | 0 212 IRQ_TYPE_LEVEL_HIGH | |
134 | 0 213 IRQ_TYPE_LEVEL_HIGH | |
135 | 0 214 IRQ_TYPE_LEVEL_HIGH>; | |
136 | interrupt-names = "error", | |
137 | "ch0", "ch1", "ch2", "ch3", | |
138 | "ch4", "ch5", "ch6", "ch7", | |
139 | "ch8", "ch9", "ch10", "ch11", | |
140 | "ch12", "ch13", "ch14"; | |
141 | clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; | |
142 | clock-names = "fck"; | |
143 | #dma-cells = <1>; | |
144 | dma-channels = <15>; | |
145 | }; | |
146 | ||
147 | dmac1: dma-controller@e6720000 { | |
148 | compatible = "renesas,rcar-dmac"; | |
149 | reg = <0 0xe6720000 0 0x20000>; | |
150 | interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH | |
151 | 0 216 IRQ_TYPE_LEVEL_HIGH | |
152 | 0 217 IRQ_TYPE_LEVEL_HIGH | |
153 | 0 218 IRQ_TYPE_LEVEL_HIGH | |
154 | 0 219 IRQ_TYPE_LEVEL_HIGH | |
155 | 0 308 IRQ_TYPE_LEVEL_HIGH | |
156 | 0 309 IRQ_TYPE_LEVEL_HIGH | |
157 | 0 310 IRQ_TYPE_LEVEL_HIGH | |
158 | 0 311 IRQ_TYPE_LEVEL_HIGH | |
159 | 0 312 IRQ_TYPE_LEVEL_HIGH | |
160 | 0 313 IRQ_TYPE_LEVEL_HIGH | |
161 | 0 314 IRQ_TYPE_LEVEL_HIGH | |
162 | 0 315 IRQ_TYPE_LEVEL_HIGH | |
163 | 0 316 IRQ_TYPE_LEVEL_HIGH | |
164 | 0 317 IRQ_TYPE_LEVEL_HIGH | |
165 | 0 318 IRQ_TYPE_LEVEL_HIGH>; | |
166 | interrupt-names = "error", | |
167 | "ch0", "ch1", "ch2", "ch3", | |
168 | "ch4", "ch5", "ch6", "ch7", | |
169 | "ch8", "ch9", "ch10", "ch11", | |
170 | "ch12", "ch13", "ch14"; | |
171 | clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; | |
172 | clock-names = "fck"; | |
173 | #dma-cells = <1>; | |
174 | dma-channels = <15>; | |
175 | }; | |
176 | ||
0dce5454 UH |
177 | scifa0: serial@e6c40000 { |
178 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
179 | reg = <0 0xe6c40000 0 64>; | |
180 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; | |
181 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; | |
182 | clock-names = "sci_ick"; | |
8233a0de GU |
183 | dmas = <&dmac0 0x21>, <&dmac0 0x22>; |
184 | dma-names = "tx", "rx"; | |
0dce5454 UH |
185 | status = "disabled"; |
186 | }; | |
187 | ||
188 | scifa1: serial@e6c50000 { | |
189 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
190 | reg = <0 0xe6c50000 0 64>; | |
191 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; | |
192 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; | |
193 | clock-names = "sci_ick"; | |
8233a0de GU |
194 | dmas = <&dmac0 0x25>, <&dmac0 0x26>; |
195 | dma-names = "tx", "rx"; | |
0dce5454 UH |
196 | status = "disabled"; |
197 | }; | |
198 | ||
199 | scifa2: serial@e6c60000 { | |
200 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
201 | reg = <0 0xe6c60000 0 64>; | |
202 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; | |
203 | clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; | |
204 | clock-names = "sci_ick"; | |
8233a0de GU |
205 | dmas = <&dmac0 0x27>, <&dmac0 0x28>; |
206 | dma-names = "tx", "rx"; | |
0dce5454 UH |
207 | status = "disabled"; |
208 | }; | |
209 | ||
210 | scifa3: serial@e6c70000 { | |
211 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
212 | reg = <0 0xe6c70000 0 64>; | |
213 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; | |
214 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; | |
215 | clock-names = "sci_ick"; | |
8233a0de GU |
216 | dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; |
217 | dma-names = "tx", "rx"; | |
0dce5454 UH |
218 | status = "disabled"; |
219 | }; | |
220 | ||
221 | scifa4: serial@e6c78000 { | |
222 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
223 | reg = <0 0xe6c78000 0 64>; | |
224 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; | |
225 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; | |
226 | clock-names = "sci_ick"; | |
8233a0de GU |
227 | dmas = <&dmac0 0x1f>, <&dmac0 0x20>; |
228 | dma-names = "tx", "rx"; | |
0dce5454 UH |
229 | status = "disabled"; |
230 | }; | |
231 | ||
232 | scifa5: serial@e6c80000 { | |
233 | compatible = "renesas,scifa-r8a7794", "renesas,scifa"; | |
234 | reg = <0 0xe6c80000 0 64>; | |
235 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; | |
236 | clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; | |
237 | clock-names = "sci_ick"; | |
8233a0de GU |
238 | dmas = <&dmac0 0x23>, <&dmac0 0x24>; |
239 | dma-names = "tx", "rx"; | |
0dce5454 UH |
240 | status = "disabled"; |
241 | }; | |
242 | ||
243 | scifb0: serial@e6c20000 { | |
244 | compatible = "renesas,scifb-r8a7794", "renesas,scifb"; | |
245 | reg = <0 0xe6c20000 0 64>; | |
246 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; | |
247 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; | |
248 | clock-names = "sci_ick"; | |
8233a0de GU |
249 | dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; |
250 | dma-names = "tx", "rx"; | |
0dce5454 UH |
251 | status = "disabled"; |
252 | }; | |
253 | ||
254 | scifb1: serial@e6c30000 { | |
255 | compatible = "renesas,scifb-r8a7794", "renesas,scifb"; | |
256 | reg = <0 0xe6c30000 0 64>; | |
257 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; | |
258 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; | |
259 | clock-names = "sci_ick"; | |
8233a0de GU |
260 | dmas = <&dmac0 0x19>, <&dmac0 0x1a>; |
261 | dma-names = "tx", "rx"; | |
0dce5454 UH |
262 | status = "disabled"; |
263 | }; | |
264 | ||
265 | scifb2: serial@e6ce0000 { | |
266 | compatible = "renesas,scifb-r8a7794", "renesas,scifb"; | |
267 | reg = <0 0xe6ce0000 0 64>; | |
268 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; | |
269 | clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; | |
270 | clock-names = "sci_ick"; | |
8233a0de GU |
271 | dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; |
272 | dma-names = "tx", "rx"; | |
0dce5454 UH |
273 | status = "disabled"; |
274 | }; | |
275 | ||
276 | scif0: serial@e6e60000 { | |
277 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
278 | reg = <0 0xe6e60000 0 64>; | |
279 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; | |
280 | clocks = <&mstp7_clks R8A7794_CLK_SCIF0>; | |
281 | clock-names = "sci_ick"; | |
8233a0de GU |
282 | dmas = <&dmac0 0x29>, <&dmac0 0x2a>; |
283 | dma-names = "tx", "rx"; | |
0dce5454 UH |
284 | status = "disabled"; |
285 | }; | |
286 | ||
287 | scif1: serial@e6e68000 { | |
288 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
289 | reg = <0 0xe6e68000 0 64>; | |
290 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; | |
291 | clocks = <&mstp7_clks R8A7794_CLK_SCIF1>; | |
292 | clock-names = "sci_ick"; | |
8233a0de GU |
293 | dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; |
294 | dma-names = "tx", "rx"; | |
0dce5454 UH |
295 | status = "disabled"; |
296 | }; | |
297 | ||
298 | scif2: serial@e6e58000 { | |
299 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
300 | reg = <0 0xe6e58000 0 64>; | |
301 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; | |
302 | clocks = <&mstp7_clks R8A7794_CLK_SCIF2>; | |
303 | clock-names = "sci_ick"; | |
8233a0de GU |
304 | dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; |
305 | dma-names = "tx", "rx"; | |
0dce5454 UH |
306 | status = "disabled"; |
307 | }; | |
308 | ||
309 | scif3: serial@e6ea8000 { | |
310 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
311 | reg = <0 0xe6ea8000 0 64>; | |
312 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; | |
313 | clocks = <&mstp7_clks R8A7794_CLK_SCIF3>; | |
314 | clock-names = "sci_ick"; | |
8233a0de GU |
315 | dmas = <&dmac0 0x2f>, <&dmac0 0x30>; |
316 | dma-names = "tx", "rx"; | |
0dce5454 UH |
317 | status = "disabled"; |
318 | }; | |
319 | ||
320 | scif4: serial@e6ee0000 { | |
321 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
322 | reg = <0 0xe6ee0000 0 64>; | |
323 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; | |
324 | clocks = <&mstp7_clks R8A7794_CLK_SCIF4>; | |
325 | clock-names = "sci_ick"; | |
8233a0de GU |
326 | dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; |
327 | dma-names = "tx", "rx"; | |
0dce5454 UH |
328 | status = "disabled"; |
329 | }; | |
330 | ||
331 | scif5: serial@e6ee8000 { | |
332 | compatible = "renesas,scif-r8a7794", "renesas,scif"; | |
333 | reg = <0 0xe6ee8000 0 64>; | |
334 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; | |
335 | clocks = <&mstp7_clks R8A7794_CLK_SCIF5>; | |
336 | clock-names = "sci_ick"; | |
8233a0de GU |
337 | dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; |
338 | dma-names = "tx", "rx"; | |
0dce5454 UH |
339 | status = "disabled"; |
340 | }; | |
341 | ||
342 | hscif0: serial@e62c0000 { | |
343 | compatible = "renesas,hscif-r8a7794", "renesas,hscif"; | |
344 | reg = <0 0xe62c0000 0 96>; | |
345 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; | |
346 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>; | |
347 | clock-names = "sci_ick"; | |
8233a0de GU |
348 | dmas = <&dmac0 0x39>, <&dmac0 0x3a>; |
349 | dma-names = "tx", "rx"; | |
0dce5454 UH |
350 | status = "disabled"; |
351 | }; | |
352 | ||
353 | hscif1: serial@e62c8000 { | |
354 | compatible = "renesas,hscif-r8a7794", "renesas,hscif"; | |
355 | reg = <0 0xe62c8000 0 96>; | |
356 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; | |
357 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>; | |
358 | clock-names = "sci_ick"; | |
8233a0de GU |
359 | dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; |
360 | dma-names = "tx", "rx"; | |
0dce5454 UH |
361 | status = "disabled"; |
362 | }; | |
363 | ||
364 | hscif2: serial@e62d0000 { | |
365 | compatible = "renesas,hscif-r8a7794", "renesas,hscif"; | |
366 | reg = <0 0xe62d0000 0 96>; | |
367 | interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; | |
368 | clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>; | |
369 | clock-names = "sci_ick"; | |
8233a0de GU |
370 | dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; |
371 | dma-names = "tx", "rx"; | |
0dce5454 UH |
372 | status = "disabled"; |
373 | }; | |
374 | ||
82818d34 LP |
375 | ether: ethernet@ee700000 { |
376 | compatible = "renesas,ether-r8a7794"; | |
377 | reg = <0 0xee700000 0 0x400>; | |
378 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; | |
379 | clocks = <&mstp8_clks R8A7794_CLK_ETHER>; | |
380 | phy-mode = "rmii"; | |
381 | #address-cells = <1>; | |
382 | #size-cells = <0>; | |
383 | status = "disabled"; | |
384 | }; | |
385 | ||
6cdf6ba1 SS |
386 | mmcif0: mmc@ee200000 { |
387 | compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; | |
388 | reg = <0 0xee200000 0 0x80>; | |
389 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; | |
390 | clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; | |
391 | dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; | |
392 | dma-names = "tx", "rx"; | |
393 | reg-io-width = <4>; | |
394 | status = "disabled"; | |
395 | }; | |
396 | ||
b8e8ea12 SS |
397 | sdhi0: sd@ee100000 { |
398 | compatible = "renesas,sdhi-r8a7794"; | |
399 | reg = <0 0xee100000 0 0x200>; | |
400 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; | |
401 | clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; | |
402 | status = "disabled"; | |
403 | }; | |
404 | ||
405 | sdhi1: sd@ee140000 { | |
406 | compatible = "renesas,sdhi-r8a7794"; | |
407 | reg = <0 0xee140000 0 0x100>; | |
408 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; | |
409 | clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; | |
410 | status = "disabled"; | |
411 | }; | |
412 | ||
413 | sdhi2: sd@ee160000 { | |
414 | compatible = "renesas,sdhi-r8a7794"; | |
415 | reg = <0 0xee160000 0 0x100>; | |
416 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; | |
417 | clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; | |
418 | status = "disabled"; | |
419 | }; | |
420 | ||
0dce5454 UH |
421 | clocks { |
422 | #address-cells = <2>; | |
423 | #size-cells = <2>; | |
424 | ranges; | |
425 | ||
426 | /* External root clock */ | |
427 | extal_clk: extal_clk { | |
428 | compatible = "fixed-clock"; | |
429 | #clock-cells = <0>; | |
430 | /* This value must be overriden by the board. */ | |
431 | clock-frequency = <0>; | |
432 | clock-output-names = "extal"; | |
433 | }; | |
434 | ||
435 | /* Special CPG clocks */ | |
436 | cpg_clocks: cpg_clocks@e6150000 { | |
437 | compatible = "renesas,r8a7794-cpg-clocks", | |
438 | "renesas,rcar-gen2-cpg-clocks"; | |
439 | reg = <0 0xe6150000 0 0x1000>; | |
440 | clocks = <&extal_clk>; | |
441 | #clock-cells = <1>; | |
442 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
443 | "lb", "qspi", "sdh", "sd0", "z"; | |
444 | }; | |
8e181633 | 445 | /* Variable factor clocks */ |
5e7e1554 | 446 | sd2_clk: sd2_clk@e6150078 { |
8e181633 SU |
447 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
448 | reg = <0 0xe6150078 0 4>; | |
449 | clocks = <&pll1_div2_clk>; | |
450 | #clock-cells = <0>; | |
5e7e1554 | 451 | clock-output-names = "sd2"; |
8e181633 | 452 | }; |
5e7e1554 | 453 | sd3_clk: sd3_clk@e615026c { |
8e181633 | 454 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; |
5e7e1554 | 455 | reg = <0 0xe615026c 0 4>; |
8e181633 SU |
456 | clocks = <&pll1_div2_clk>; |
457 | #clock-cells = <0>; | |
5e7e1554 | 458 | clock-output-names = "sd3"; |
8e181633 | 459 | }; |
deac150c SU |
460 | mmc0_clk: mmc0_clk@e6150240 { |
461 | compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; | |
462 | reg = <0 0xe6150240 0 4>; | |
463 | clocks = <&pll1_div2_clk>; | |
464 | #clock-cells = <0>; | |
465 | clock-output-names = "mmc0"; | |
466 | }; | |
0dce5454 UH |
467 | |
468 | /* Fixed factor clocks */ | |
469 | pll1_div2_clk: pll1_div2_clk { | |
470 | compatible = "fixed-factor-clock"; | |
471 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
472 | #clock-cells = <0>; | |
473 | clock-div = <2>; | |
474 | clock-mult = <1>; | |
475 | clock-output-names = "pll1_div2"; | |
476 | }; | |
477 | zg_clk: zg_clk { | |
478 | compatible = "fixed-factor-clock"; | |
479 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
480 | #clock-cells = <0>; | |
481 | clock-div = <6>; | |
482 | clock-mult = <1>; | |
483 | clock-output-names = "zg"; | |
484 | }; | |
485 | zx_clk: zx_clk { | |
486 | compatible = "fixed-factor-clock"; | |
487 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
488 | #clock-cells = <0>; | |
489 | clock-div = <3>; | |
490 | clock-mult = <1>; | |
491 | clock-output-names = "zx"; | |
492 | }; | |
493 | zs_clk: zs_clk { | |
494 | compatible = "fixed-factor-clock"; | |
495 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
496 | #clock-cells = <0>; | |
497 | clock-div = <6>; | |
498 | clock-mult = <1>; | |
499 | clock-output-names = "zs"; | |
500 | }; | |
501 | hp_clk: hp_clk { | |
502 | compatible = "fixed-factor-clock"; | |
503 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
504 | #clock-cells = <0>; | |
505 | clock-div = <12>; | |
506 | clock-mult = <1>; | |
507 | clock-output-names = "hp"; | |
508 | }; | |
509 | i_clk: i_clk { | |
510 | compatible = "fixed-factor-clock"; | |
511 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
512 | #clock-cells = <0>; | |
513 | clock-div = <2>; | |
514 | clock-mult = <1>; | |
515 | clock-output-names = "i"; | |
516 | }; | |
517 | b_clk: b_clk { | |
518 | compatible = "fixed-factor-clock"; | |
519 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
520 | #clock-cells = <0>; | |
521 | clock-div = <12>; | |
522 | clock-mult = <1>; | |
523 | clock-output-names = "b"; | |
524 | }; | |
525 | p_clk: p_clk { | |
526 | compatible = "fixed-factor-clock"; | |
527 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
528 | #clock-cells = <0>; | |
529 | clock-div = <24>; | |
530 | clock-mult = <1>; | |
531 | clock-output-names = "p"; | |
532 | }; | |
533 | cl_clk: cl_clk { | |
534 | compatible = "fixed-factor-clock"; | |
535 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
536 | #clock-cells = <0>; | |
537 | clock-div = <48>; | |
538 | clock-mult = <1>; | |
539 | clock-output-names = "cl"; | |
540 | }; | |
541 | m2_clk: m2_clk { | |
542 | compatible = "fixed-factor-clock"; | |
543 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
544 | #clock-cells = <0>; | |
545 | clock-div = <8>; | |
546 | clock-mult = <1>; | |
547 | clock-output-names = "m2"; | |
548 | }; | |
549 | imp_clk: imp_clk { | |
550 | compatible = "fixed-factor-clock"; | |
551 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
552 | #clock-cells = <0>; | |
553 | clock-div = <4>; | |
554 | clock-mult = <1>; | |
555 | clock-output-names = "imp"; | |
556 | }; | |
557 | rclk_clk: rclk_clk { | |
558 | compatible = "fixed-factor-clock"; | |
559 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
560 | #clock-cells = <0>; | |
561 | clock-div = <(48 * 1024)>; | |
562 | clock-mult = <1>; | |
563 | clock-output-names = "rclk"; | |
564 | }; | |
565 | oscclk_clk: oscclk_clk { | |
566 | compatible = "fixed-factor-clock"; | |
567 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
568 | #clock-cells = <0>; | |
569 | clock-div = <(12 * 1024)>; | |
570 | clock-mult = <1>; | |
571 | clock-output-names = "oscclk"; | |
572 | }; | |
573 | zb3_clk: zb3_clk { | |
574 | compatible = "fixed-factor-clock"; | |
575 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; | |
576 | #clock-cells = <0>; | |
577 | clock-div = <4>; | |
578 | clock-mult = <1>; | |
579 | clock-output-names = "zb3"; | |
580 | }; | |
581 | zb3d2_clk: zb3d2_clk { | |
582 | compatible = "fixed-factor-clock"; | |
583 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; | |
584 | #clock-cells = <0>; | |
585 | clock-div = <8>; | |
586 | clock-mult = <1>; | |
587 | clock-output-names = "zb3d2"; | |
588 | }; | |
589 | ddr_clk: ddr_clk { | |
590 | compatible = "fixed-factor-clock"; | |
591 | clocks = <&cpg_clocks R8A7794_CLK_PLL3>; | |
592 | #clock-cells = <0>; | |
593 | clock-div = <8>; | |
594 | clock-mult = <1>; | |
595 | clock-output-names = "ddr"; | |
596 | }; | |
597 | mp_clk: mp_clk { | |
598 | compatible = "fixed-factor-clock"; | |
599 | clocks = <&pll1_div2_clk>; | |
600 | #clock-cells = <0>; | |
601 | clock-div = <15>; | |
602 | clock-mult = <1>; | |
603 | clock-output-names = "mp"; | |
604 | }; | |
605 | cp_clk: cp_clk { | |
606 | compatible = "fixed-factor-clock"; | |
607 | clocks = <&cpg_clocks R8A7794_CLK_PLL1>; | |
608 | #clock-cells = <0>; | |
609 | clock-div = <48>; | |
610 | clock-mult = <1>; | |
611 | clock-output-names = "cp"; | |
612 | }; | |
613 | ||
614 | acp_clk: acp_clk { | |
615 | compatible = "fixed-factor-clock"; | |
616 | clocks = <&extal_clk>; | |
617 | #clock-cells = <0>; | |
618 | clock-div = <2>; | |
619 | clock-mult = <1>; | |
620 | clock-output-names = "acp"; | |
621 | }; | |
622 | ||
623 | /* Gate clocks */ | |
624 | mstp0_clks: mstp0_clks@e6150130 { | |
625 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
626 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; | |
627 | clocks = <&mp_clk>; | |
628 | #clock-cells = <1>; | |
1045d065 | 629 | clock-indices = <R8A7794_CLK_MSIOF0>; |
0dce5454 UH |
630 | clock-output-names = "msiof0"; |
631 | }; | |
632 | mstp1_clks: mstp1_clks@e6150134 { | |
633 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
634 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
dc3cf93d YH |
635 | clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, |
636 | <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, | |
637 | <&zs_clk>, <&zs_clk>; | |
0dce5454 | 638 | #clock-cells = <1>; |
1045d065 | 639 | clock-indices = < |
dc3cf93d YH |
640 | R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 |
641 | R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 | |
642 | R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 | |
643 | R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S | |
0dce5454 UH |
644 | >; |
645 | clock-output-names = | |
dc3cf93d YH |
646 | "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", |
647 | "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; | |
0dce5454 UH |
648 | }; |
649 | mstp2_clks: mstp2_clks@e6150138 { | |
650 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
651 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
652 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
be16cd38 HY |
653 | <&mp_clk>, <&mp_clk>, <&mp_clk>, |
654 | <&zs_clk>, <&zs_clk>; | |
0dce5454 | 655 | #clock-cells = <1>; |
1045d065 | 656 | clock-indices = < |
0dce5454 UH |
657 | R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 |
658 | R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 | |
659 | R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 | |
be16cd38 | 660 | R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0 |
0dce5454 UH |
661 | >; |
662 | clock-output-names = | |
663 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", | |
be16cd38 HY |
664 | "scifb1", "msiof1", "scifb2", |
665 | "sys-dmac1", "sys-dmac0"; | |
0dce5454 UH |
666 | }; |
667 | mstp3_clks: mstp3_clks@e615013c { | |
668 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
669 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
5e7e1554 | 670 | clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, |
deac150c | 671 | <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; |
0dce5454 | 672 | #clock-cells = <1>; |
1045d065 | 673 | clock-indices = < |
8e181633 | 674 | R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 |
deac150c SU |
675 | R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1 |
676 | R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 | |
0dce5454 UH |
677 | >; |
678 | clock-output-names = | |
8e181633 | 679 | "sdhi2", "sdhi1", "sdhi0", |
deac150c | 680 | "mmcif0", "cmt1", "usbdmac0", "usbdmac1"; |
0dce5454 | 681 | }; |
1c5ca5db GU |
682 | mstp4_clks: mstp4_clks@e6150140 { |
683 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
684 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; | |
685 | clocks = <&cp_clk>; | |
686 | #clock-cells = <1>; | |
687 | clock-indices = <R8A7794_CLK_IRQC>; | |
688 | clock-output-names = "irqc"; | |
689 | }; | |
0dce5454 UH |
690 | mstp7_clks: mstp7_clks@e615014c { |
691 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
692 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
c7bab9f9 SU |
693 | clocks = <&mp_clk>, <&mp_clk>, |
694 | <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, | |
0dce5454 UH |
695 | <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; |
696 | #clock-cells = <1>; | |
1045d065 | 697 | clock-indices = < |
c7bab9f9 | 698 | R8A7794_CLK_EHCI R8A7794_CLK_HSUSB |
0dce5454 UH |
699 | R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 |
700 | R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 | |
701 | R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 | |
702 | R8A7794_CLK_SCIF0 | |
703 | >; | |
704 | clock-output-names = | |
c7bab9f9 | 705 | "ehci", "hsusb", |
0dce5454 UH |
706 | "hscif2", "scif5", "scif4", "hscif1", "hscif0", |
707 | "scif3", "scif2", "scif1", "scif0"; | |
708 | }; | |
709 | mstp8_clks: mstp8_clks@e6150990 { | |
710 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
711 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
148ebf47 | 712 | clocks = <&zg_clk>, <&zg_clk>, <&p_clk>; |
0dce5454 | 713 | #clock-cells = <1>; |
1045d065 | 714 | clock-indices = < |
148ebf47 | 715 | R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER |
0dce5454 UH |
716 | >; |
717 | clock-output-names = | |
148ebf47 | 718 | "vin1", "vin0", "ether"; |
0dce5454 | 719 | }; |
3281480b HN |
720 | mstp9_clks: mstp9_clks@e6150994 { |
721 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
722 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
c5d82c99 KM |
723 | clocks = <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>, |
724 | <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; | |
3281480b | 725 | #clock-cells = <1>; |
c5d82c99 KM |
726 | clock-indices = < |
727 | R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4 | |
728 | R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1 | |
729 | R8A7794_CLK_I2C0 | |
730 | >; | |
731 | clock-output-names = | |
732 | "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; | |
3281480b | 733 | }; |
0dce5454 UH |
734 | mstp11_clks: mstp11_clks@e615099c { |
735 | compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
736 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; | |
737 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; | |
738 | #clock-cells = <1>; | |
1045d065 | 739 | clock-indices = < |
0dce5454 UH |
740 | R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 |
741 | >; | |
742 | clock-output-names = "scifa3", "scifa4", "scifa5"; | |
743 | }; | |
744 | }; | |
1cb2794f LP |
745 | |
746 | ipmmu_sy0: mmu@e6280000 { | |
747 | compatible = "renesas,ipmmu-vmsa"; | |
748 | reg = <0 0xe6280000 0 0x1000>; | |
749 | interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, | |
750 | <0 224 IRQ_TYPE_LEVEL_HIGH>; | |
751 | #iommu-cells = <1>; | |
752 | status = "disabled"; | |
753 | }; | |
754 | ||
755 | ipmmu_sy1: mmu@e6290000 { | |
756 | compatible = "renesas,ipmmu-vmsa"; | |
757 | reg = <0 0xe6290000 0 0x1000>; | |
758 | interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; | |
759 | #iommu-cells = <1>; | |
760 | status = "disabled"; | |
761 | }; | |
762 | ||
763 | ipmmu_ds: mmu@e6740000 { | |
764 | compatible = "renesas,ipmmu-vmsa"; | |
765 | reg = <0 0xe6740000 0 0x1000>; | |
766 | interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, | |
767 | <0 199 IRQ_TYPE_LEVEL_HIGH>; | |
768 | #iommu-cells = <1>; | |
769 | }; | |
770 | ||
771 | ipmmu_mp: mmu@ec680000 { | |
772 | compatible = "renesas,ipmmu-vmsa"; | |
773 | reg = <0 0xec680000 0 0x1000>; | |
774 | interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; | |
775 | #iommu-cells = <1>; | |
776 | status = "disabled"; | |
777 | }; | |
778 | ||
779 | ipmmu_mx: mmu@fe951000 { | |
780 | compatible = "renesas,ipmmu-vmsa"; | |
781 | reg = <0 0xfe951000 0 0x1000>; | |
782 | interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, | |
783 | <0 221 IRQ_TYPE_LEVEL_HIGH>; | |
784 | #iommu-cells = <1>; | |
785 | }; | |
786 | ||
787 | ipmmu_gp: mmu@e62a0000 { | |
788 | compatible = "renesas,ipmmu-vmsa"; | |
789 | reg = <0 0xe62a0000 0 0x1000>; | |
790 | interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>, | |
791 | <0 261 IRQ_TYPE_LEVEL_HIGH>; | |
792 | #iommu-cells = <1>; | |
793 | status = "disabled"; | |
794 | }; | |
0dce5454 | 795 | }; |