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ARM: shmobile: kzm9g dts: Use adxl345-specific compatible property
[deliverable/linux.git] / arch / arm / boot / dts / r8a7794.dtsi
CommitLineData
0dce5454
UH		 1/*
2 * Device Tree Source for the r8a7794 SoC
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <dt-bindings/clock/r8a7794-clock.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
16/ {
17 compatible = "renesas,r8a7794";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
740b4a9f
SS		 22 aliases {
23 spi0 = &qspi;
24 };
25
0dce5454
UH		 26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu0: cpu@0 {
31 device_type = "cpu";
32 compatible = "arm,cortex-a7";
33 reg = <0>;
34 clock-frequency = <1000000000>;
35 };
36
37 cpu1: cpu@1 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a7";
40 reg = <1>;
41 clock-frequency = <1000000000>;
42 };
43 };
44
45 gic: interrupt-controller@f1001000 {
c73ddf42 46 compatible = "arm,gic-400";
0dce5454
UH		 47 #interrupt-cells = <3>;
48 #address-cells = <0>;
49 interrupt-controller;
50 reg = <0 0xf1001000 0 0x1000>,
51 <0 0xf1002000 0 0x1000>,
52 <0 0xf1004000 0 0x2000>,
53 <0 0xf1006000 0 0x2000>;
00add867 54 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0dce5454
UH		 55 };
56
e8f5de3b
SS		 57 gpio0: gpio@e6050000 {
58 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
59 reg = <0 0xe6050000 0 0x50>;
60 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
61 #gpio-cells = <2>;
62 gpio-controller;
63 gpio-ranges = <&pfc 0 0 32>;
64 #interrupt-cells = <2>;
65 interrupt-controller;
66 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
67 power-domains = <&cpg_clocks>;
68 };
69
70 gpio1: gpio@e6051000 {
71 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
72 reg = <0 0xe6051000 0 0x50>;
73 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
74 #gpio-cells = <2>;
75 gpio-controller;
76 gpio-ranges = <&pfc 0 32 26>;
77 #interrupt-cells = <2>;
78 interrupt-controller;
79 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
80 power-domains = <&cpg_clocks>;
81 };
82
83 gpio2: gpio@e6052000 {
84 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
85 reg = <0 0xe6052000 0 0x50>;
86 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
87 #gpio-cells = <2>;
88 gpio-controller;
89 gpio-ranges = <&pfc 0 64 32>;
90 #interrupt-cells = <2>;
91 interrupt-controller;
92 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
93 power-domains = <&cpg_clocks>;
94 };
95
96 gpio3: gpio@e6053000 {
97 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
98 reg = <0 0xe6053000 0 0x50>;
99 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
100 #gpio-cells = <2>;
101 gpio-controller;
102 gpio-ranges = <&pfc 0 96 32>;
103 #interrupt-cells = <2>;
104 interrupt-controller;
105 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
106 power-domains = <&cpg_clocks>;
107 };
108
109 gpio4: gpio@e6054000 {
110 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
111 reg = <0 0xe6054000 0 0x50>;
112 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
113 #gpio-cells = <2>;
114 gpio-controller;
115 gpio-ranges = <&pfc 0 128 32>;
116 #interrupt-cells = <2>;
117 interrupt-controller;
118 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
119 power-domains = <&cpg_clocks>;
120 };
121
122 gpio5: gpio@e6055000 {
123 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
124 reg = <0 0xe6055000 0 0x50>;
125 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
126 #gpio-cells = <2>;
127 gpio-controller;
128 gpio-ranges = <&pfc 0 160 28>;
129 #interrupt-cells = <2>;
130 interrupt-controller;
131 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
132 power-domains = <&cpg_clocks>;
133 };
134
135 gpio6: gpio@e6055400 {
136 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
137 reg = <0 0xe6055400 0 0x50>;
138 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
139 #gpio-cells = <2>;
140 gpio-controller;
141 gpio-ranges = <&pfc 0 192 26>;
142 #interrupt-cells = <2>;
143 interrupt-controller;
144 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
145 power-domains = <&cpg_clocks>;
146 };
147
0dce5454
UH		 148 cmt0: timer@ffca0000 {
149 compatible = "renesas,cmt-48-gen2";
150 reg = <0 0xffca0000 0 0x1004>;
151 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
152 <0 143 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
154 clock-names = "fck";
60c0745a 155 power-domains = <&cpg_clocks>;
0dce5454
UH		 156
157 renesas,channels-mask = <0x60>;
158
159 status = "disabled";
160 };
161
162 cmt1: timer@e6130000 {
163 compatible = "renesas,cmt-48-gen2";
164 reg = <0 0xe6130000 0 0x1004>;
165 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
166 <0 121 IRQ_TYPE_LEVEL_HIGH>,
167 <0 122 IRQ_TYPE_LEVEL_HIGH>,
168 <0 123 IRQ_TYPE_LEVEL_HIGH>,
169 <0 124 IRQ_TYPE_LEVEL_HIGH>,
170 <0 125 IRQ_TYPE_LEVEL_HIGH>,
171 <0 126 IRQ_TYPE_LEVEL_HIGH>,
172 <0 127 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
174 clock-names = "fck";
60c0745a 175 power-domains = <&cpg_clocks>;
0dce5454
UH		 176
177 renesas,channels-mask = <0xff>;
178
179 status = "disabled";
180 };
181
da33648c
HN		 182 timer {
183 compatible = "arm,armv7-timer";
00add867
GU		 184 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
185 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
186 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
187 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
da33648c
HN		 188 };
189
0dce5454
UH		 190 irqc0: interrupt-controller@e61c0000 {
191 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
192 #interrupt-cells = <2>;
193 interrupt-controller;
194 reg = <0 0xe61c0000 0 0x200>;
195 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
196 <0 1 IRQ_TYPE_LEVEL_HIGH>,
197 <0 2 IRQ_TYPE_LEVEL_HIGH>,
198 <0 3 IRQ_TYPE_LEVEL_HIGH>,
199 <0 12 IRQ_TYPE_LEVEL_HIGH>,
200 <0 13 IRQ_TYPE_LEVEL_HIGH>,
201 <0 14 IRQ_TYPE_LEVEL_HIGH>,
202 <0 15 IRQ_TYPE_LEVEL_HIGH>,
203 <0 16 IRQ_TYPE_LEVEL_HIGH>,
204 <0 17 IRQ_TYPE_LEVEL_HIGH>;
1c5ca5db 205 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
60c0745a 206 power-domains = <&cpg_clocks>;
0dce5454
UH		 207 };
208
fd1683c1
SS		 209 pfc: pin-controller@e6060000 {
210 compatible = "renesas,pfc-r8a7794";
211 reg = <0 0xe6060000 0 0x11c>;
212 #gpio-range-cells = <3>;
213 };
214
bd847485
LP		 215 dmac0: dma-controller@e6700000 {
216 compatible = "renesas,rcar-dmac";
217 reg = <0 0xe6700000 0 0x20000>;
218 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
219 0 200 IRQ_TYPE_LEVEL_HIGH
220 0 201 IRQ_TYPE_LEVEL_HIGH
221 0 202 IRQ_TYPE_LEVEL_HIGH
222 0 203 IRQ_TYPE_LEVEL_HIGH
223 0 204 IRQ_TYPE_LEVEL_HIGH
224 0 205 IRQ_TYPE_LEVEL_HIGH
225 0 206 IRQ_TYPE_LEVEL_HIGH
226 0 207 IRQ_TYPE_LEVEL_HIGH
227 0 208 IRQ_TYPE_LEVEL_HIGH
228 0 209 IRQ_TYPE_LEVEL_HIGH
229 0 210 IRQ_TYPE_LEVEL_HIGH
230 0 211 IRQ_TYPE_LEVEL_HIGH
231 0 212 IRQ_TYPE_LEVEL_HIGH
232 0 213 IRQ_TYPE_LEVEL_HIGH
233 0 214 IRQ_TYPE_LEVEL_HIGH>;
234 interrupt-names = "error",
235 "ch0", "ch1", "ch2", "ch3",
236 "ch4", "ch5", "ch6", "ch7",
237 "ch8", "ch9", "ch10", "ch11",
238 "ch12", "ch13", "ch14";
239 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
240 clock-names = "fck";
60c0745a 241 power-domains = <&cpg_clocks>;
bd847485
LP		 242 #dma-cells = <1>;
243 dma-channels = <15>;
244 };
245
246 dmac1: dma-controller@e6720000 {
247 compatible = "renesas,rcar-dmac";
248 reg = <0 0xe6720000 0 0x20000>;
249 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
250 0 216 IRQ_TYPE_LEVEL_HIGH
251 0 217 IRQ_TYPE_LEVEL_HIGH
252 0 218 IRQ_TYPE_LEVEL_HIGH
253 0 219 IRQ_TYPE_LEVEL_HIGH
254 0 308 IRQ_TYPE_LEVEL_HIGH
255 0 309 IRQ_TYPE_LEVEL_HIGH
256 0 310 IRQ_TYPE_LEVEL_HIGH
257 0 311 IRQ_TYPE_LEVEL_HIGH
258 0 312 IRQ_TYPE_LEVEL_HIGH
259 0 313 IRQ_TYPE_LEVEL_HIGH
260 0 314 IRQ_TYPE_LEVEL_HIGH
261 0 315 IRQ_TYPE_LEVEL_HIGH
262 0 316 IRQ_TYPE_LEVEL_HIGH
263 0 317 IRQ_TYPE_LEVEL_HIGH
264 0 318 IRQ_TYPE_LEVEL_HIGH>;
265 interrupt-names = "error",
266 "ch0", "ch1", "ch2", "ch3",
267 "ch4", "ch5", "ch6", "ch7",
268 "ch8", "ch9", "ch10", "ch11",
269 "ch12", "ch13", "ch14";
270 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
271 clock-names = "fck";
60c0745a 272 power-domains = <&cpg_clocks>;
bd847485
LP		 273 #dma-cells = <1>;
274 dma-channels = <15>;
275 };
276
0dce5454
UH		 277 scifa0: serial@e6c40000 {
278 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
279 reg = <0 0xe6c40000 0 64>;
280 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
282 clock-names = "sci_ick";
8233a0de
GU		 283 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
284 dma-names = "tx", "rx";
60c0745a 285 power-domains = <&cpg_clocks>;
0dce5454
UH		 286 status = "disabled";
287 };
288
289 scifa1: serial@e6c50000 {
290 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
291 reg = <0 0xe6c50000 0 64>;
292 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
294 clock-names = "sci_ick";
8233a0de
GU		 295 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
296 dma-names = "tx", "rx";
60c0745a 297 power-domains = <&cpg_clocks>;
0dce5454
UH		 298 status = "disabled";
299 };
300
301 scifa2: serial@e6c60000 {
302 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
303 reg = <0 0xe6c60000 0 64>;
304 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
306 clock-names = "sci_ick";
8233a0de
GU		 307 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
308 dma-names = "tx", "rx";
60c0745a 309 power-domains = <&cpg_clocks>;
0dce5454
UH		 310 status = "disabled";
311 };
312
313 scifa3: serial@e6c70000 {
314 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
315 reg = <0 0xe6c70000 0 64>;
316 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
318 clock-names = "sci_ick";
8233a0de
GU		 319 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
320 dma-names = "tx", "rx";
60c0745a 321 power-domains = <&cpg_clocks>;
0dce5454
UH		 322 status = "disabled";
323 };
324
325 scifa4: serial@e6c78000 {
326 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
327 reg = <0 0xe6c78000 0 64>;
328 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
330 clock-names = "sci_ick";
8233a0de
GU		 331 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
332 dma-names = "tx", "rx";
60c0745a 333 power-domains = <&cpg_clocks>;
0dce5454
UH		 334 status = "disabled";
335 };
336
337 scifa5: serial@e6c80000 {
338 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
339 reg = <0 0xe6c80000 0 64>;
340 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
342 clock-names = "sci_ick";
8233a0de
GU		 343 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
344 dma-names = "tx", "rx";
60c0745a 345 power-domains = <&cpg_clocks>;
0dce5454
UH		 346 status = "disabled";
347 };
348
349 scifb0: serial@e6c20000 {
350 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
351 reg = <0 0xe6c20000 0 64>;
352 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
354 clock-names = "sci_ick";
8233a0de
GU		 355 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
356 dma-names = "tx", "rx";
60c0745a 357 power-domains = <&cpg_clocks>;
0dce5454
UH		 358 status = "disabled";
359 };
360
361 scifb1: serial@e6c30000 {
362 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
363 reg = <0 0xe6c30000 0 64>;
364 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
366 clock-names = "sci_ick";
8233a0de
GU		 367 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
368 dma-names = "tx", "rx";
60c0745a 369 power-domains = <&cpg_clocks>;
0dce5454
UH		 370 status = "disabled";
371 };
372
373 scifb2: serial@e6ce0000 {
374 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
375 reg = <0 0xe6ce0000 0 64>;
376 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
378 clock-names = "sci_ick";
8233a0de
GU		 379 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
380 dma-names = "tx", "rx";
60c0745a 381 power-domains = <&cpg_clocks>;
0dce5454
UH		 382 status = "disabled";
383 };
384
385 scif0: serial@e6e60000 {
386 compatible = "renesas,scif-r8a7794", "renesas,scif";
387 reg = <0 0xe6e60000 0 64>;
388 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
390 clock-names = "sci_ick";
8233a0de
GU		 391 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
392 dma-names = "tx", "rx";
60c0745a 393 power-domains = <&cpg_clocks>;
0dce5454
UH		 394 status = "disabled";
395 };
396
397 scif1: serial@e6e68000 {
398 compatible = "renesas,scif-r8a7794", "renesas,scif";
399 reg = <0 0xe6e68000 0 64>;
400 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
402 clock-names = "sci_ick";
8233a0de
GU		 403 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
404 dma-names = "tx", "rx";
60c0745a 405 power-domains = <&cpg_clocks>;
0dce5454
UH		 406 status = "disabled";
407 };
408
409 scif2: serial@e6e58000 {
410 compatible = "renesas,scif-r8a7794", "renesas,scif";
411 reg = <0 0xe6e58000 0 64>;
412 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
414 clock-names = "sci_ick";
8233a0de
GU		 415 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
416 dma-names = "tx", "rx";
60c0745a 417 power-domains = <&cpg_clocks>;
0dce5454
UH		 418 status = "disabled";
419 };
420
421 scif3: serial@e6ea8000 {
422 compatible = "renesas,scif-r8a7794", "renesas,scif";
423 reg = <0 0xe6ea8000 0 64>;
424 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
426 clock-names = "sci_ick";
8233a0de
GU		 427 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
428 dma-names = "tx", "rx";
60c0745a 429 power-domains = <&cpg_clocks>;
0dce5454
UH		 430 status = "disabled";
431 };
432
433 scif4: serial@e6ee0000 {
434 compatible = "renesas,scif-r8a7794", "renesas,scif";
435 reg = <0 0xe6ee0000 0 64>;
436 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
438 clock-names = "sci_ick";
8233a0de
GU		 439 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
440 dma-names = "tx", "rx";
60c0745a 441 power-domains = <&cpg_clocks>;
0dce5454
UH		 442 status = "disabled";
443 };
444
445 scif5: serial@e6ee8000 {
446 compatible = "renesas,scif-r8a7794", "renesas,scif";
447 reg = <0 0xe6ee8000 0 64>;
448 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
450 clock-names = "sci_ick";
8233a0de
GU		 451 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
452 dma-names = "tx", "rx";
60c0745a 453 power-domains = <&cpg_clocks>;
0dce5454
UH		 454 status = "disabled";
455 };
456
457 hscif0: serial@e62c0000 {
458 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
459 reg = <0 0xe62c0000 0 96>;
460 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
462 clock-names = "sci_ick";
8233a0de
GU		 463 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
464 dma-names = "tx", "rx";
60c0745a 465 power-domains = <&cpg_clocks>;
0dce5454
UH		 466 status = "disabled";
467 };
468
469 hscif1: serial@e62c8000 {
470 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
471 reg = <0 0xe62c8000 0 96>;
472 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
474 clock-names = "sci_ick";
8233a0de
GU		 475 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
476 dma-names = "tx", "rx";
60c0745a 477 power-domains = <&cpg_clocks>;
0dce5454
UH		 478 status = "disabled";
479 };
480
481 hscif2: serial@e62d0000 {
482 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
483 reg = <0 0xe62d0000 0 96>;
484 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
486 clock-names = "sci_ick";
8233a0de
GU		 487 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
488 dma-names = "tx", "rx";
60c0745a 489 power-domains = <&cpg_clocks>;
0dce5454
UH		 490 status = "disabled";
491 };
492
82818d34
LP		 493 ether: ethernet@ee700000 {
494 compatible = "renesas,ether-r8a7794";
495 reg = <0 0xee700000 0 0x400>;
496 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
60c0745a 498 power-domains = <&cpg_clocks>;
82818d34
LP		 499 phy-mode = "rmii";
500 #address-cells = <1>;
501 #size-cells = <0>;
502 status = "disabled";
503 };
504
6cdf6ba1
SS		 505 mmcif0: mmc@ee200000 {
506 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
507 reg = <0 0xee200000 0 0x80>;
508 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
510 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
511 dma-names = "tx", "rx";
60c0745a 512 power-domains = <&cpg_clocks>;
6cdf6ba1
SS		 513 reg-io-width = <4>;
514 status = "disabled";
515 };
516
b8e8ea12
SS		 517 sdhi0: sd@ee100000 {
518 compatible = "renesas,sdhi-r8a7794";
519 reg = <0 0xee100000 0 0x200>;
520 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
60c0745a 522 power-domains = <&cpg_clocks>;
b8e8ea12
SS		 523 status = "disabled";
524 };
525
526 sdhi1: sd@ee140000 {
527 compatible = "renesas,sdhi-r8a7794";
528 reg = <0 0xee140000 0 0x100>;
529 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
60c0745a 531 power-domains = <&cpg_clocks>;
b8e8ea12
SS		 532 status = "disabled";
533 };
534
535 sdhi2: sd@ee160000 {
536 compatible = "renesas,sdhi-r8a7794";
537 reg = <0 0xee160000 0 0x100>;
538 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
60c0745a 540 power-domains = <&cpg_clocks>;
b8e8ea12
SS		 541 status = "disabled";
542 };
543
740b4a9f
SS		 544 qspi: spi@e6b10000 {
545 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
546 reg = <0 0xe6b10000 0 0x2c>;
547 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
549 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
550 dma-names = "tx", "rx";
551 power-domains = <&cpg_clocks>;
552 num-cs = <1>;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 status = "disabled";
556 };
557
0dce5454
UH		 558 clocks {
559 #address-cells = <2>;
560 #size-cells = <2>;
561 ranges;
562
563 /* External root clock */
564 extal_clk: extal_clk {
565 compatible = "fixed-clock";
566 #clock-cells = <0>;
567 /* This value must be overriden by the board. */
568 clock-frequency = <0>;
569 clock-output-names = "extal";
570 };
571
572 /* Special CPG clocks */
573 cpg_clocks: cpg_clocks@e6150000 {
574 compatible = "renesas,r8a7794-cpg-clocks",
575 "renesas,rcar-gen2-cpg-clocks";
576 reg = <0 0xe6150000 0 0x1000>;
577 clocks = <&extal_clk>;
578 #clock-cells = <1>;
579 clock-output-names = "main", "pll0", "pll1", "pll3",
580 "lb", "qspi", "sdh", "sd0", "z";
60c0745a 581 #power-domain-cells = <0>;
0dce5454 582 };
8e181633 583 /* Variable factor clocks */
5e7e1554 584 sd2_clk: sd2_clk@e6150078 {
8e181633
SU		 585 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
586 reg = <0 0xe6150078 0 4>;
587 clocks = <&pll1_div2_clk>;
588 #clock-cells = <0>;
5e7e1554 589 clock-output-names = "sd2";
8e181633 590 };
5e7e1554 591 sd3_clk: sd3_clk@e615026c {
8e181633 592 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
5e7e1554 593 reg = <0 0xe615026c 0 4>;
8e181633
SU		 594 clocks = <&pll1_div2_clk>;
595 #clock-cells = <0>;
5e7e1554 596 clock-output-names = "sd3";
8e181633 597 };
deac150c
SU		 598 mmc0_clk: mmc0_clk@e6150240 {
599 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
600 reg = <0 0xe6150240 0 4>;
601 clocks = <&pll1_div2_clk>;
602 #clock-cells = <0>;
603 clock-output-names = "mmc0";
604 };
0dce5454
UH		 605
606 /* Fixed factor clocks */
607 pll1_div2_clk: pll1_div2_clk {
608 compatible = "fixed-factor-clock";
609 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
610 #clock-cells = <0>;
611 clock-div = <2>;
612 clock-mult = <1>;
613 clock-output-names = "pll1_div2";
614 };
615 zg_clk: zg_clk {
616 compatible = "fixed-factor-clock";
617 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
618 #clock-cells = <0>;
619 clock-div = <6>;
620 clock-mult = <1>;
621 clock-output-names = "zg";
622 };
623 zx_clk: zx_clk {
624 compatible = "fixed-factor-clock";
625 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
626 #clock-cells = <0>;
627 clock-div = <3>;
628 clock-mult = <1>;
629 clock-output-names = "zx";
630 };
631 zs_clk: zs_clk {
632 compatible = "fixed-factor-clock";
633 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
634 #clock-cells = <0>;
635 clock-div = <6>;
636 clock-mult = <1>;
637 clock-output-names = "zs";
638 };
639 hp_clk: hp_clk {
640 compatible = "fixed-factor-clock";
641 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
642 #clock-cells = <0>;
643 clock-div = <12>;
644 clock-mult = <1>;
645 clock-output-names = "hp";
646 };
647 i_clk: i_clk {
648 compatible = "fixed-factor-clock";
649 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
650 #clock-cells = <0>;
651 clock-div = <2>;
652 clock-mult = <1>;
653 clock-output-names = "i";
654 };
655 b_clk: b_clk {
656 compatible = "fixed-factor-clock";
657 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
658 #clock-cells = <0>;
659 clock-div = <12>;
660 clock-mult = <1>;
661 clock-output-names = "b";
662 };
663 p_clk: p_clk {
664 compatible = "fixed-factor-clock";
665 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
666 #clock-cells = <0>;
667 clock-div = <24>;
668 clock-mult = <1>;
669 clock-output-names = "p";
670 };
671 cl_clk: cl_clk {
672 compatible = "fixed-factor-clock";
673 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
674 #clock-cells = <0>;
675 clock-div = <48>;
676 clock-mult = <1>;
677 clock-output-names = "cl";
678 };
679 m2_clk: m2_clk {
680 compatible = "fixed-factor-clock";
681 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
682 #clock-cells = <0>;
683 clock-div = <8>;
684 clock-mult = <1>;
685 clock-output-names = "m2";
686 };
687 imp_clk: imp_clk {
688 compatible = "fixed-factor-clock";
689 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
690 #clock-cells = <0>;
691 clock-div = <4>;
692 clock-mult = <1>;
693 clock-output-names = "imp";
694 };
695 rclk_clk: rclk_clk {
696 compatible = "fixed-factor-clock";
697 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
698 #clock-cells = <0>;
699 clock-div = <(48 * 1024)>;
700 clock-mult = <1>;
701 clock-output-names = "rclk";
702 };
703 oscclk_clk: oscclk_clk {
704 compatible = "fixed-factor-clock";
705 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
706 #clock-cells = <0>;
707 clock-div = <(12 * 1024)>;
708 clock-mult = <1>;
709 clock-output-names = "oscclk";
710 };
711 zb3_clk: zb3_clk {
712 compatible = "fixed-factor-clock";
713 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
714 #clock-cells = <0>;
715 clock-div = <4>;
716 clock-mult = <1>;
717 clock-output-names = "zb3";
718 };
719 zb3d2_clk: zb3d2_clk {
720 compatible = "fixed-factor-clock";
721 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
722 #clock-cells = <0>;
723 clock-div = <8>;
724 clock-mult = <1>;
725 clock-output-names = "zb3d2";
726 };
727 ddr_clk: ddr_clk {
728 compatible = "fixed-factor-clock";
729 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
730 #clock-cells = <0>;
731 clock-div = <8>;
732 clock-mult = <1>;
733 clock-output-names = "ddr";
734 };
735 mp_clk: mp_clk {
736 compatible = "fixed-factor-clock";
737 clocks = <&pll1_div2_clk>;
738 #clock-cells = <0>;
739 clock-div = <15>;
740 clock-mult = <1>;
741 clock-output-names = "mp";
742 };
743 cp_clk: cp_clk {
744 compatible = "fixed-factor-clock";
745 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
746 #clock-cells = <0>;
747 clock-div = <48>;
748 clock-mult = <1>;
749 clock-output-names = "cp";
750 };
751
752 acp_clk: acp_clk {
753 compatible = "fixed-factor-clock";
754 clocks = <&extal_clk>;
755 #clock-cells = <0>;
756 clock-div = <2>;
757 clock-mult = <1>;
758 clock-output-names = "acp";
759 };
760
761 /* Gate clocks */
762 mstp0_clks: mstp0_clks@e6150130 {
763 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
764 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
765 clocks = <&mp_clk>;
766 #clock-cells = <1>;
1045d065 767 clock-indices = <R8A7794_CLK_MSIOF0>;
0dce5454
UH		 768 clock-output-names = "msiof0";
769 };
770 mstp1_clks: mstp1_clks@e6150134 {
771 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
772 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
dc3cf93d
YH		 773 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
774 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
775 <&zs_clk>, <&zs_clk>;
0dce5454 776 #clock-cells = <1>;
1045d065 777 clock-indices = <
dc3cf93d
YH		 778 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
779 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
780 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
781 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
0dce5454
UH		 782 >;
783 clock-output-names =
dc3cf93d
YH		 784 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
785 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
0dce5454
UH		 786 };
787 mstp2_clks: mstp2_clks@e6150138 {
788 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
789 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
790 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
be16cd38
HY		 791 <&mp_clk>, <&mp_clk>, <&mp_clk>,
792 <&zs_clk>, <&zs_clk>;
0dce5454 793 #clock-cells = <1>;
1045d065 794 clock-indices = <
0dce5454
UH		 795 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
796 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
797 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
be16cd38 798 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
0dce5454
UH		 799 >;
800 clock-output-names =
801 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
be16cd38
HY		 802 "scifb1", "msiof1", "scifb2",
803 "sys-dmac1", "sys-dmac0";
0dce5454
UH		 804 };
805 mstp3_clks: mstp3_clks@e615013c {
806 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
807 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
5e7e1554 808 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
deac150c 809 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
0dce5454 810 #clock-cells = <1>;
1045d065 811 clock-indices = <
8e181633 812 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
deac150c
SU		 813 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
814 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
0dce5454
UH		 815 >;
816 clock-output-names =
8e181633 817 "sdhi2", "sdhi1", "sdhi0",
deac150c 818 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
0dce5454 819 };
1c5ca5db
GU		 820 mstp4_clks: mstp4_clks@e6150140 {
821 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
822 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
823 clocks = <&cp_clk>;
824 #clock-cells = <1>;
825 clock-indices = <R8A7794_CLK_IRQC>;
826 clock-output-names = "irqc";
827 };
0dce5454
UH		 828 mstp7_clks: mstp7_clks@e615014c {
829 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
830 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
c7bab9f9
SU		 831 clocks = <&mp_clk>, <&mp_clk>,
832 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
0dce5454
UH		 833 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
834 #clock-cells = <1>;
1045d065 835 clock-indices = <
c7bab9f9 836 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
0dce5454
UH		 837 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
838 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
839 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
840 R8A7794_CLK_SCIF0
841 >;
842 clock-output-names =
c7bab9f9 843 "ehci", "hsusb",
0dce5454
UH		 844 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
845 "scif3", "scif2", "scif1", "scif0";
846 };
847 mstp8_clks: mstp8_clks@e6150990 {
848 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
849 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
148ebf47 850 clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
0dce5454 851 #clock-cells = <1>;
1045d065 852 clock-indices = <
148ebf47 853 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
0dce5454
UH		 854 >;
855 clock-output-names =
148ebf47 856 "vin1", "vin0", "ether";
0dce5454 857 };
3281480b
HN		 858 mstp9_clks: mstp9_clks@e6150994 {
859 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
860 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
3f37e018
SS		 861 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
862 <&cp_clk>, <&cp_clk>, <&cp_clk>,
863 <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
864 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
3281480b 865 #clock-cells = <1>;
3f37e018
SS		 866 clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
867 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
868 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
869 R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD
870 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
871 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
872 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
c5d82c99 873 clock-output-names =
3f37e018
SS		 874 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
875 "gpio1", "gpio0", "qspi_mod",
876 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
3281480b 877 };
0dce5454
UH		 878 mstp11_clks: mstp11_clks@e615099c {
879 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
880 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
881 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
882 #clock-cells = <1>;
1045d065 883 clock-indices = <
0dce5454
UH		 884 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
885 >;
886 clock-output-names = "scifa3", "scifa4", "scifa5";
887 };
888 };
1cb2794f
LP		 889
890 ipmmu_sy0: mmu@e6280000 {
891 compatible = "renesas,ipmmu-vmsa";
892 reg = <0 0xe6280000 0 0x1000>;
893 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
894 <0 224 IRQ_TYPE_LEVEL_HIGH>;
895 #iommu-cells = <1>;
896 status = "disabled";
897 };
898
899 ipmmu_sy1: mmu@e6290000 {
900 compatible = "renesas,ipmmu-vmsa";
901 reg = <0 0xe6290000 0 0x1000>;
902 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
903 #iommu-cells = <1>;
904 status = "disabled";
905 };
906
907 ipmmu_ds: mmu@e6740000 {
908 compatible = "renesas,ipmmu-vmsa";
909 reg = <0 0xe6740000 0 0x1000>;
910 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
911 <0 199 IRQ_TYPE_LEVEL_HIGH>;
912 #iommu-cells = <1>;
913 };
914
915 ipmmu_mp: mmu@ec680000 {
916 compatible = "renesas,ipmmu-vmsa";
917 reg = <0 0xec680000 0 0x1000>;
918 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
919 #iommu-cells = <1>;
920 status = "disabled";
921 };
922
923 ipmmu_mx: mmu@fe951000 {
924 compatible = "renesas,ipmmu-vmsa";
925 reg = <0 0xfe951000 0 0x1000>;
926 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
927 <0 221 IRQ_TYPE_LEVEL_HIGH>;
928 #iommu-cells = <1>;
929 };
930
931 ipmmu_gp: mmu@e62a0000 {
932 compatible = "renesas,ipmmu-vmsa";
933 reg = <0 0xe62a0000 0 0x1000>;
934 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
935 <0 261 IRQ_TYPE_LEVEL_HIGH>;
936 #iommu-cells = <1>;
937 status = "disabled";
938 };
0dce5454 939};
Linux kernel - Deliverables
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