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faea098e XZ |
1 | /* |
2 | * This file is dual-licensed: you can use it either under the terms | |
3 | * of the GPL or the X11 license, at your option. Note that this dual | |
4 | * licensing only applies to this file, and not this project as a | |
5 | * whole. | |
6 | * | |
7 | * a) This file is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of the | |
10 | * License, or (at your option) any later version. | |
11 | * | |
12 | * This file is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * Or, alternatively, | |
18 | * | |
19 | * b) Permission is hereby granted, free of charge, to any person | |
20 | * obtaining a copy of this software and associated documentation | |
21 | * files (the "Software"), to deal in the Software without | |
22 | * restriction, including without limitation the rights to use, | |
23 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
24 | * sell copies of the Software, and to permit persons to whom the | |
25 | * Software is furnished to do so, subject to the following | |
26 | * conditions: | |
27 | * | |
28 | * The above copyright notice and this permission notice shall be | |
29 | * included in all copies or substantial portions of the Software. | |
30 | * | |
31 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
32 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
33 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
34 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
35 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
36 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
37 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
38 | * OTHER DEALINGS IN THE SOFTWARE. | |
39 | */ | |
40 | ||
41 | #include <dt-bindings/gpio/gpio.h> | |
42 | #include <dt-bindings/interrupt-controller/irq.h> | |
43 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
44 | #include <dt-bindings/pinctrl/rockchip.h> | |
45 | #include <dt-bindings/clock/rk3036-cru.h> | |
46 | #include "skeleton.dtsi" | |
47 | ||
48 | / { | |
49 | compatible = "rockchip,rk3036"; | |
50 | ||
51 | interrupt-parent = <&gic>; | |
52 | ||
53 | aliases { | |
54 | i2c0 = &i2c0; | |
55 | i2c1 = &i2c1; | |
56 | i2c2 = &i2c2; | |
57 | mshc0 = &emmc; | |
187d7967 CW |
58 | mshc1 = &sdmmc; |
59 | mshc2 = &sdio; | |
faea098e XZ |
60 | serial0 = &uart0; |
61 | serial1 = &uart1; | |
62 | serial2 = &uart2; | |
f629fcfa | 63 | spi = &spi; |
faea098e XZ |
64 | }; |
65 | ||
faea098e XZ |
66 | cpus { |
67 | #address-cells = <1>; | |
68 | #size-cells = <0>; | |
69 | enable-method = "rockchip,rk3036-smp"; | |
70 | ||
71 | cpu0: cpu@f00 { | |
72 | device_type = "cpu"; | |
73 | compatible = "arm,cortex-a7"; | |
74 | reg = <0xf00>; | |
75 | resets = <&cru SRST_CORE0>; | |
76 | operating-points = < | |
77 | /* KHz uV */ | |
78 | 816000 1000000 | |
79 | >; | |
80 | clock-latency = <40000>; | |
81 | clocks = <&cru ARMCLK>; | |
82 | }; | |
83 | ||
84 | cpu1: cpu@f01 { | |
85 | device_type = "cpu"; | |
86 | compatible = "arm,cortex-a7"; | |
87 | reg = <0xf01>; | |
88 | resets = <&cru SRST_CORE1>; | |
89 | }; | |
90 | }; | |
91 | ||
92 | amba { | |
2ef7d5f3 | 93 | compatible = "simple-bus"; |
faea098e XZ |
94 | #address-cells = <1>; |
95 | #size-cells = <1>; | |
96 | ranges; | |
97 | ||
98 | pdma: pdma@20078000 { | |
99 | compatible = "arm,pl330", "arm,primecell"; | |
100 | reg = <0x20078000 0x4000>; | |
101 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
102 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
103 | #dma-cells = <1>; | |
29f12bba | 104 | arm,pl330-broken-no-flushp; |
faea098e XZ |
105 | clocks = <&cru ACLK_DMAC2>; |
106 | clock-names = "apb_pclk"; | |
107 | }; | |
108 | }; | |
109 | ||
110 | arm-pmu { | |
111 | compatible = "arm,cortex-a7-pmu"; | |
112 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, | |
113 | <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
114 | interrupt-affinity = <&cpu0>, <&cpu1>; | |
115 | }; | |
116 | ||
d9abae3c CW |
117 | display-subsystem { |
118 | compatible = "rockchip,display-subsystem"; | |
119 | ports = <&vop_out>; | |
120 | }; | |
121 | ||
faea098e XZ |
122 | timer { |
123 | compatible = "arm,armv7-timer"; | |
124 | arm,cpu-registers-not-fw-configured; | |
125 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, | |
126 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, | |
127 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, | |
128 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
129 | clock-frequency = <24000000>; | |
130 | }; | |
131 | ||
132 | xin24m: oscillator { | |
133 | compatible = "fixed-clock"; | |
134 | clock-frequency = <24000000>; | |
135 | clock-output-names = "xin24m"; | |
136 | #clock-cells = <0>; | |
137 | }; | |
138 | ||
139 | bus_intmem@10080000 { | |
140 | compatible = "mmio-sram"; | |
141 | reg = <0x10080000 0x2000>; | |
142 | #address-cells = <1>; | |
143 | #size-cells = <1>; | |
144 | ranges = <0 0x10080000 0x2000>; | |
145 | ||
146 | smp-sram@0 { | |
147 | compatible = "rockchip,rk3066-smp-sram"; | |
148 | reg = <0x00 0x10>; | |
149 | }; | |
150 | }; | |
151 | ||
d9abae3c CW |
152 | vop: vop@10118000 { |
153 | compatible = "rockchip,rk3036-vop"; | |
154 | reg = <0x10118000 0x19c>; | |
155 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
156 | clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; | |
157 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
158 | resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; | |
159 | reset-names = "axi", "ahb", "dclk"; | |
160 | iommus = <&vop_mmu>; | |
161 | status = "disabled"; | |
162 | ||
163 | vop_out: port { | |
164 | #address-cells = <1>; | |
165 | #size-cells = <0>; | |
b7217cf1 CW |
166 | vop_out_hdmi: endpoint@0 { |
167 | reg = <0>; | |
168 | remote-endpoint = <&hdmi_in_vop>; | |
169 | }; | |
d9abae3c CW |
170 | }; |
171 | }; | |
172 | ||
173 | vop_mmu: iommu@10118300 { | |
174 | compatible = "rockchip,iommu"; | |
175 | reg = <0x10118300 0x100>; | |
176 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
177 | interrupt-names = "vop_mmu"; | |
178 | #iommu-cells = <0>; | |
179 | status = "disabled"; | |
180 | }; | |
181 | ||
faea098e XZ |
182 | gic: interrupt-controller@10139000 { |
183 | compatible = "arm,gic-400"; | |
184 | interrupt-controller; | |
185 | #interrupt-cells = <3>; | |
186 | #address-cells = <0>; | |
187 | ||
188 | reg = <0x10139000 0x1000>, | |
189 | <0x1013a000 0x1000>, | |
190 | <0x1013c000 0x2000>, | |
191 | <0x1013e000 0x2000>; | |
192 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
193 | }; | |
194 | ||
195 | usb_otg: usb@10180000 { | |
0082180c | 196 | compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", |
faea098e XZ |
197 | "snps,dwc2"; |
198 | reg = <0x10180000 0x40000>; | |
199 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
200 | clocks = <&cru HCLK_OTG0>; | |
201 | clock-names = "otg"; | |
202 | dr_mode = "otg"; | |
203 | g-np-tx-fifo-size = <16>; | |
204 | g-rx-fifo-size = <275>; | |
205 | g-tx-fifo-size = <256 128 128 64 64 32>; | |
206 | g-use-dma; | |
207 | status = "disabled"; | |
208 | }; | |
209 | ||
210 | usb_host: usb@101c0000 { | |
0082180c | 211 | compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", |
faea098e XZ |
212 | "snps,dwc2"; |
213 | reg = <0x101c0000 0x40000>; | |
214 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
215 | clocks = <&cru HCLK_OTG1>; | |
216 | clock-names = "otg"; | |
217 | dr_mode = "host"; | |
218 | status = "disabled"; | |
219 | }; | |
220 | ||
af671e7b XZ |
221 | emac: ethernet@10200000 { |
222 | compatible = "rockchip,rk3036-emac", "snps,arc-emac"; | |
223 | reg = <0x10200000 0x4000>; | |
224 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
225 | #address-cells = <1>; | |
226 | #size-cells = <0>; | |
227 | rockchip,grf = <&grf>; | |
228 | clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; | |
229 | clock-names = "hclk", "macref", "macclk"; | |
230 | /* | |
231 | * Fix the emac parent clock is DPLL instead of APLL. | |
232 | * since that will cause some unstable things if the cpufreq | |
233 | * is working. (e.g: the accurate 50MHz what mac_ref need) | |
234 | */ | |
235 | assigned-clocks = <&cru SCLK_MACPLL>; | |
236 | assigned-clock-parents = <&cru PLL_DPLL>; | |
237 | max-speed = <100>; | |
238 | phy-mode = "rmii"; | |
239 | status = "disabled"; | |
240 | }; | |
241 | ||
187d7967 CW |
242 | sdmmc: dwmmc@10214000 { |
243 | compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; | |
244 | reg = <0x10214000 0x4000>; | |
245 | clock-frequency = <37500000>; | |
246 | clock-freq-min-max = <400000 37500000>; | |
247 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; | |
248 | clock-names = "biu", "ciu"; | |
249 | fifo-depth = <0x100>; | |
250 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
251 | status = "disabled"; | |
252 | }; | |
253 | ||
254 | sdio: dwmmc@10218000 { | |
255 | compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; | |
256 | reg = <0x10218000 0x4000>; | |
257 | clock-freq-min-max = <400000 37500000>; | |
258 | clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, | |
259 | <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; | |
260 | clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; | |
261 | fifo-depth = <0x100>; | |
262 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
263 | status = "disabled"; | |
264 | }; | |
265 | ||
faea098e | 266 | emmc: dwmmc@1021c000 { |
0082180c | 267 | compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; |
faea098e XZ |
268 | reg = <0x1021c000 0x4000>; |
269 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
faea098e XZ |
270 | bus-width = <8>; |
271 | cap-mmc-highspeed; | |
272 | clock-frequency = <37500000>; | |
273 | clock-freq-min-max = <400000 37500000>; | |
274 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, | |
275 | <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; | |
276 | clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; | |
277 | default-sample-phase = <158>; | |
278 | disable-wp; | |
279 | dmas = <&pdma 12>; | |
280 | dma-names = "rx-tx"; | |
281 | fifo-depth = <0x100>; | |
282 | mmc-ddr-1_8v; | |
283 | non-removable; | |
284 | num-slots = <1>; | |
285 | pinctrl-names = "default"; | |
286 | pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; | |
287 | status = "disabled"; | |
288 | }; | |
289 | ||
290 | i2s: i2s@10220000 { | |
291 | compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; | |
292 | reg = <0x10220000 0x4000>; | |
293 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
294 | #address-cells = <1>; | |
295 | #size-cells = <0>; | |
3860aa1c HS |
296 | clock-names = "i2s_clk", "i2s_hclk"; |
297 | clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; | |
faea098e XZ |
298 | dmas = <&pdma 0>, <&pdma 1>; |
299 | dma-names = "tx", "rx"; | |
300 | pinctrl-names = "default"; | |
301 | pinctrl-0 = <&i2s_bus>; | |
302 | status = "disabled"; | |
303 | }; | |
304 | ||
305 | cru: clock-controller@20000000 { | |
306 | compatible = "rockchip,rk3036-cru"; | |
307 | reg = <0x20000000 0x1000>; | |
308 | rockchip,grf = <&grf>; | |
309 | #clock-cells = <1>; | |
310 | #reset-cells = <1>; | |
311 | assigned-clocks = <&cru PLL_GPLL>; | |
312 | assigned-clock-rates = <594000000>; | |
313 | }; | |
314 | ||
315 | grf: syscon@20008000 { | |
316 | compatible = "rockchip,rk3036-grf", "syscon"; | |
317 | reg = <0x20008000 0x1000>; | |
318 | }; | |
319 | ||
320 | acodec: acodec-ana@20030000 { | |
321 | compatible = "rk3036-codec"; | |
322 | reg = <0x20030000 0x4000>; | |
323 | rockchip,grf = <&grf>; | |
324 | clock-names = "acodec_pclk"; | |
325 | clocks = <&cru PCLK_ACODEC>; | |
326 | status = "disabled"; | |
327 | }; | |
328 | ||
b7217cf1 CW |
329 | hdmi: hdmi@20034000 { |
330 | compatible = "rockchip,rk3036-inno-hdmi"; | |
331 | reg = <0x20034000 0x4000>; | |
332 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
333 | clocks = <&cru PCLK_HDMI>; | |
334 | clock-names = "pclk"; | |
335 | rockchip,grf = <&grf>; | |
336 | pinctrl-names = "default"; | |
337 | pinctrl-0 = <&hdmi_ctl>; | |
338 | status = "disabled"; | |
339 | ||
340 | hdmi_in: port { | |
341 | #address-cells = <1>; | |
342 | #size-cells = <0>; | |
343 | hdmi_in_vop: endpoint@0 { | |
344 | reg = <0>; | |
345 | remote-endpoint = <&vop_out_hdmi>; | |
346 | }; | |
347 | }; | |
348 | }; | |
349 | ||
faea098e XZ |
350 | timer: timer@20044000 { |
351 | compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; | |
352 | reg = <0x20044000 0x20>; | |
353 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
354 | clocks = <&xin24m>, <&cru PCLK_TIMER>; | |
355 | clock-names = "timer", "pclk"; | |
356 | }; | |
357 | ||
358 | pwm0: pwm@20050000 { | |
359 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
360 | reg = <0x20050000 0x10>; | |
361 | #pwm-cells = <3>; | |
362 | clocks = <&cru PCLK_PWM>; | |
363 | clock-names = "pwm"; | |
364 | pinctrl-names = "default"; | |
365 | pinctrl-0 = <&pwm0_pin>; | |
366 | status = "disabled"; | |
367 | }; | |
368 | ||
369 | pwm1: pwm@20050010 { | |
370 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
371 | reg = <0x20050010 0x10>; | |
372 | #pwm-cells = <3>; | |
373 | clocks = <&cru PCLK_PWM>; | |
374 | clock-names = "pwm"; | |
375 | pinctrl-names = "default"; | |
376 | pinctrl-0 = <&pwm1_pin>; | |
377 | status = "disabled"; | |
378 | }; | |
379 | ||
380 | pwm2: pwm@20050020 { | |
381 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
382 | reg = <0x20050020 0x10>; | |
383 | #pwm-cells = <3>; | |
384 | clocks = <&cru PCLK_PWM>; | |
385 | clock-names = "pwm"; | |
386 | pinctrl-names = "default"; | |
387 | pinctrl-0 = <&pwm2_pin>; | |
388 | status = "disabled"; | |
389 | }; | |
390 | ||
391 | pwm3: pwm@20050030 { | |
392 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
393 | reg = <0x20050030 0x10>; | |
394 | #pwm-cells = <2>; | |
395 | clocks = <&cru PCLK_PWM>; | |
396 | clock-names = "pwm"; | |
397 | pinctrl-names = "default"; | |
398 | pinctrl-0 = <&pwm3_pin>; | |
399 | status = "disabled"; | |
400 | }; | |
401 | ||
402 | i2c1: i2c@20056000 { | |
0082180c | 403 | compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; |
faea098e XZ |
404 | reg = <0x20056000 0x1000>; |
405 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
406 | #address-cells = <1>; | |
407 | #size-cells = <0>; | |
408 | clock-names = "i2c"; | |
409 | clocks = <&cru PCLK_I2C1>; | |
410 | pinctrl-names = "default"; | |
411 | pinctrl-0 = <&i2c1_xfer>; | |
412 | status = "disabled"; | |
413 | }; | |
414 | ||
415 | i2c2: i2c@2005a000 { | |
0082180c | 416 | compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; |
faea098e XZ |
417 | reg = <0x2005a000 0x1000>; |
418 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
419 | #address-cells = <1>; | |
420 | #size-cells = <0>; | |
421 | clock-names = "i2c"; | |
422 | clocks = <&cru PCLK_I2C2>; | |
423 | pinctrl-names = "default"; | |
424 | pinctrl-0 = <&i2c2_xfer>; | |
425 | status = "disabled"; | |
426 | }; | |
427 | ||
428 | uart0: serial@20060000 { | |
429 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; | |
430 | reg = <0x20060000 0x100>; | |
431 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
432 | reg-shift = <2>; | |
433 | reg-io-width = <4>; | |
434 | clock-frequency = <24000000>; | |
435 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
436 | clock-names = "baudclk", "apb_pclk"; | |
437 | pinctrl-names = "default"; | |
438 | pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; | |
439 | status = "disabled"; | |
440 | }; | |
441 | ||
442 | uart1: serial@20064000 { | |
443 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; | |
444 | reg = <0x20064000 0x100>; | |
445 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
446 | reg-shift = <2>; | |
447 | reg-io-width = <4>; | |
448 | clock-frequency = <24000000>; | |
449 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
450 | clock-names = "baudclk", "apb_pclk"; | |
451 | pinctrl-names = "default"; | |
452 | pinctrl-0 = <&uart1_xfer>; | |
453 | status = "disabled"; | |
454 | }; | |
455 | ||
456 | uart2: serial@20068000 { | |
457 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; | |
458 | reg = <0x20068000 0x100>; | |
459 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
460 | reg-shift = <2>; | |
461 | reg-io-width = <4>; | |
462 | clock-frequency = <24000000>; | |
463 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
464 | clock-names = "baudclk", "apb_pclk"; | |
465 | pinctrl-names = "default"; | |
466 | pinctrl-0 = <&uart2_xfer>; | |
467 | status = "disabled"; | |
468 | }; | |
469 | ||
470 | i2c0: i2c@20072000 { | |
0082180c | 471 | compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; |
faea098e XZ |
472 | reg = <0x20072000 0x1000>; |
473 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
474 | #address-cells = <1>; | |
475 | #size-cells = <0>; | |
476 | clock-names = "i2c"; | |
477 | clocks = <&cru PCLK_I2C0>; | |
478 | pinctrl-names = "default"; | |
479 | pinctrl-0 = <&i2c0_xfer>; | |
480 | status = "disabled"; | |
481 | }; | |
482 | ||
f629fcfa CW |
483 | spi: spi@20074000 { |
484 | compatible = "rockchip,rockchip-spi"; | |
485 | reg = <0x20074000 0x1000>; | |
486 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
487 | clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>; | |
488 | clock-names = "apb-pclk","spi_pclk"; | |
489 | dmas = <&pdma 8>, <&pdma 9>; | |
490 | dma-names = "tx", "rx"; | |
491 | pinctrl-names = "default"; | |
492 | pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; | |
493 | #address-cells = <1>; | |
494 | #size-cells = <0>; | |
495 | status = "disabled"; | |
496 | }; | |
497 | ||
faea098e XZ |
498 | pinctrl: pinctrl { |
499 | compatible = "rockchip,rk3036-pinctrl"; | |
500 | rockchip,grf = <&grf>; | |
501 | #address-cells = <1>; | |
502 | #size-cells = <1>; | |
503 | ranges; | |
504 | ||
505 | gpio0: gpio0@2007c000 { | |
506 | compatible = "rockchip,gpio-bank"; | |
507 | reg = <0x2007c000 0x100>; | |
508 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
509 | clocks = <&cru PCLK_GPIO0>; | |
510 | ||
511 | gpio-controller; | |
512 | #gpio-cells = <2>; | |
513 | ||
514 | interrupt-controller; | |
515 | #interrupt-cells = <2>; | |
516 | }; | |
517 | ||
518 | gpio1: gpio1@20080000 { | |
519 | compatible = "rockchip,gpio-bank"; | |
520 | reg = <0x20080000 0x100>; | |
521 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
522 | clocks = <&cru PCLK_GPIO1>; | |
523 | ||
524 | gpio-controller; | |
525 | #gpio-cells = <2>; | |
526 | ||
527 | interrupt-controller; | |
528 | #interrupt-cells = <2>; | |
529 | }; | |
530 | ||
531 | gpio2: gpio2@20084000 { | |
532 | compatible = "rockchip,gpio-bank"; | |
533 | reg = <0x20084000 0x100>; | |
534 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
535 | clocks = <&cru PCLK_GPIO2>; | |
536 | ||
537 | gpio-controller; | |
538 | #gpio-cells = <2>; | |
539 | ||
540 | interrupt-controller; | |
541 | #interrupt-cells = <2>; | |
542 | }; | |
543 | ||
68556dd7 XZ |
544 | pcfg_pull_default: pcfg_pull_default { |
545 | bias-pull-pin-default; | |
faea098e XZ |
546 | }; |
547 | ||
548 | pcfg_pull_none: pcfg-pull-none { | |
549 | bias-disable; | |
550 | }; | |
551 | ||
552 | pwm0 { | |
553 | pwm0_pin: pwm0-pin { | |
554 | rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; | |
555 | }; | |
556 | }; | |
557 | ||
558 | pwm1 { | |
559 | pwm1_pin: pwm1-pin { | |
560 | rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; | |
561 | }; | |
562 | }; | |
563 | ||
564 | pwm2 { | |
565 | pwm2_pin: pwm2-pin { | |
566 | rockchip,pins = <0 1 2 &pcfg_pull_none>; | |
567 | }; | |
568 | }; | |
569 | ||
570 | pwm3 { | |
571 | pwm3_pin: pwm3-pin { | |
572 | rockchip,pins = <0 27 1 &pcfg_pull_none>; | |
573 | }; | |
574 | }; | |
575 | ||
187d7967 CW |
576 | sdmmc { |
577 | sdmmc_clk: sdmmc-clk { | |
578 | rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>; | |
579 | }; | |
580 | ||
581 | sdmmc_cmd: sdmmc-cmd { | |
582 | rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>; | |
583 | }; | |
584 | ||
585 | sdmmc_cd: sdmcc-cd { | |
586 | rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>; | |
587 | }; | |
588 | ||
589 | sdmmc_bus1: sdmmc-bus1 { | |
590 | rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>; | |
591 | }; | |
592 | ||
593 | sdmmc_bus4: sdmmc-bus4 { | |
594 | rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>, | |
595 | <1 19 RK_FUNC_1 &pcfg_pull_default>, | |
596 | <1 20 RK_FUNC_1 &pcfg_pull_default>, | |
597 | <1 21 RK_FUNC_1 &pcfg_pull_default>; | |
598 | }; | |
599 | }; | |
600 | ||
601 | sdio { | |
602 | sdio_bus1: sdio-bus1 { | |
603 | rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>; | |
604 | }; | |
605 | ||
606 | sdio_bus4: sdio-bus4 { | |
607 | rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>, | |
608 | <0 12 RK_FUNC_1 &pcfg_pull_default>, | |
609 | <0 13 RK_FUNC_1 &pcfg_pull_default>, | |
610 | <0 14 RK_FUNC_1 &pcfg_pull_default>; | |
611 | }; | |
612 | ||
613 | sdio_cmd: sdio-cmd { | |
614 | rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>; | |
615 | }; | |
616 | ||
617 | sdio_clk: sdio-clk { | |
618 | rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>; | |
619 | }; | |
620 | }; | |
621 | ||
faea098e XZ |
622 | emmc { |
623 | /* | |
624 | * We run eMMC at max speed; bump up drive strength. | |
625 | * We also have external pulls, so disable the internal ones. | |
626 | */ | |
627 | emmc_clk: emmc-clk { | |
628 | rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; | |
629 | }; | |
630 | ||
631 | emmc_cmd: emmc-cmd { | |
68556dd7 | 632 | rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>; |
faea098e XZ |
633 | }; |
634 | ||
635 | emmc_bus8: emmc-bus8 { | |
68556dd7 XZ |
636 | rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>, |
637 | <1 25 RK_FUNC_2 &pcfg_pull_default>, | |
638 | <1 26 RK_FUNC_2 &pcfg_pull_default>, | |
639 | <1 27 RK_FUNC_2 &pcfg_pull_default>, | |
640 | <1 28 RK_FUNC_2 &pcfg_pull_default>, | |
641 | <1 29 RK_FUNC_2 &pcfg_pull_default>, | |
642 | <1 30 RK_FUNC_2 &pcfg_pull_default>, | |
643 | <1 31 RK_FUNC_2 &pcfg_pull_default>; | |
faea098e XZ |
644 | }; |
645 | }; | |
646 | ||
af671e7b XZ |
647 | emac { |
648 | emac_xfer: emac-xfer { | |
649 | rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */ | |
650 | <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */ | |
651 | <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */ | |
652 | <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */ | |
653 | <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */ | |
654 | <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */ | |
655 | <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */ | |
656 | <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */ | |
657 | }; | |
658 | ||
659 | emac_mdio: emac-mdio { | |
660 | rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */ | |
661 | <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */ | |
662 | }; | |
663 | }; | |
664 | ||
faea098e XZ |
665 | i2c0 { |
666 | i2c0_xfer: i2c0-xfer { | |
667 | rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, | |
668 | <0 1 RK_FUNC_1 &pcfg_pull_none>; | |
669 | }; | |
670 | }; | |
671 | ||
672 | i2c1 { | |
673 | i2c1_xfer: i2c1-xfer { | |
674 | rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, | |
675 | <0 3 RK_FUNC_1 &pcfg_pull_none>; | |
676 | }; | |
677 | }; | |
678 | ||
679 | i2c2 { | |
680 | i2c2_xfer: i2c2-xfer { | |
681 | rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, | |
682 | <2 21 RK_FUNC_1 &pcfg_pull_none>; | |
683 | }; | |
684 | }; | |
685 | ||
686 | i2s { | |
687 | i2s_bus: i2s-bus { | |
f4755332 CW |
688 | rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>, |
689 | <1 1 RK_FUNC_1 &pcfg_pull_default>, | |
690 | <1 2 RK_FUNC_1 &pcfg_pull_default>, | |
691 | <1 3 RK_FUNC_1 &pcfg_pull_default>, | |
692 | <1 4 RK_FUNC_1 &pcfg_pull_default>, | |
693 | <1 5 RK_FUNC_1 &pcfg_pull_default>; | |
faea098e XZ |
694 | }; |
695 | }; | |
696 | ||
b7217cf1 CW |
697 | hdmi { |
698 | hdmi_ctl: hdmi-ctl { | |
699 | rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>, | |
700 | <1 9 RK_FUNC_1 &pcfg_pull_none>, | |
701 | <1 10 RK_FUNC_1 &pcfg_pull_none>, | |
702 | <1 11 RK_FUNC_1 &pcfg_pull_none>; | |
703 | }; | |
704 | }; | |
705 | ||
faea098e XZ |
706 | uart0 { |
707 | uart0_xfer: uart0-xfer { | |
68556dd7 | 708 | rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>, |
faea098e XZ |
709 | <0 17 RK_FUNC_1 &pcfg_pull_none>; |
710 | }; | |
711 | ||
712 | uart0_cts: uart0-cts { | |
68556dd7 | 713 | rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>; |
faea098e XZ |
714 | }; |
715 | ||
716 | uart0_rts: uart0-rts { | |
717 | rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; | |
718 | }; | |
719 | }; | |
720 | ||
721 | uart1 { | |
722 | uart1_xfer: uart1-xfer { | |
68556dd7 | 723 | rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>, |
faea098e XZ |
724 | <2 23 RK_FUNC_1 &pcfg_pull_none>; |
725 | }; | |
726 | /* no rts / cts for uart1 */ | |
727 | }; | |
728 | ||
729 | uart2 { | |
730 | uart2_xfer: uart2-xfer { | |
68556dd7 | 731 | rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>, |
faea098e XZ |
732 | <1 19 RK_FUNC_2 &pcfg_pull_none>; |
733 | }; | |
734 | /* no rts / cts for uart2 */ | |
735 | }; | |
f629fcfa CW |
736 | |
737 | spi { | |
738 | spi_txd:spi-txd { | |
739 | rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>; | |
740 | }; | |
741 | ||
742 | spi_rxd:spi-rxd { | |
743 | rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>; | |
744 | }; | |
745 | ||
746 | spi_clk:spi-clk { | |
747 | rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>; | |
748 | }; | |
749 | ||
750 | spi_cs0:spi-cs0 { | |
751 | rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>; | |
752 | ||
753 | }; | |
754 | ||
755 | spi_cs1:spi-cs1 { | |
756 | rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>; | |
757 | ||
758 | }; | |
759 | }; | |
faea098e XZ |
760 | }; |
761 | }; |