projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 6bcf60f8 HS |
1 | /* |
| 2 | * Copyright (c) 2013 MundoReader S.L. | |
| 3 | * Author: Heiko Stuebner <heiko@sntech.de> | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License as published by | |
| 7 | * the Free Software Foundation; either version 2 of the License, or | |
| 8 | * (at your option) any later version. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, | |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | */ | |
| 15 | ||
| 16 | #include <dt-bindings/gpio/gpio.h> | |
| 17 | #include <dt-bindings/pinctrl/rockchip.h> | |
| 18 | #include "rk3xxx.dtsi" | |
| 19 | #include "rk3188-clocks.dtsi" | |
| 20 | ||
| 21 | / { | |
| 22 | compatible = "rockchip,rk3188"; | |
| 23 | ||
| 24 | cpus { | |
| 25 | #address-cells = <1>; | |
| 26 | #size-cells = <0>; | |
| 27 | ||
| 28 | cpu@0 { | |
| 29 | device_type = "cpu"; | |
| 30 | compatible = "arm,cortex-a9"; | |
| 31 | next-level-cache = <&L2>; | |
| 32 | reg = <0x0>; | |
| 33 | }; | |
| 34 | cpu@1 { | |
| 35 | device_type = "cpu"; | |
| 36 | compatible = "arm,cortex-a9"; | |
| 37 | next-level-cache = <&L2>; | |
| 38 | reg = <0x1>; | |
| 39 | }; | |
| 40 | cpu@2 { | |
| 41 | device_type = "cpu"; | |
| 42 | compatible = "arm,cortex-a9"; | |
| 43 | next-level-cache = <&L2>; | |
| 44 | reg = <0x2>; | |
| 45 | }; | |
| 46 | cpu@3 { | |
| 47 | device_type = "cpu"; | |
| 48 | compatible = "arm,cortex-a9"; | |
| 49 | next-level-cache = <&L2>; | |
| 50 | reg = <0x3>; | |
| 51 | }; | |
| 52 | }; | |
| 53 | ||
| 54 | soc { | |
| 55 | global-timer@1013c200 { | |
| 56 | interrupts = <GIC_PPI 11 0xf04>; | |
| 57 | }; | |
| 58 | ||
| 59 | local-timer@1013c600 { | |
| 60 | interrupts = <GIC_PPI 13 0xf04>; | |
| 61 | }; | |
| 62 | ||
| 63 | pinctrl@20008000 { | |
| 64 | compatible = "rockchip,rk3188-pinctrl"; | |
| 65 | reg = <0x20008000 0xa0>, | |
| 66 | <0x20008164 0x1a0>; | |
| 67 | reg-names = "base", "pull"; | |
| 68 | #address-cells = <1>; | |
| 69 | #size-cells = <1>; | |
| 70 | ranges; | |
| 71 | ||
| 72 | gpio0: gpio0@0x2000a000 { | |
| 73 | compatible = "rockchip,rk3188-gpio-bank0"; | |
| 74 | reg = <0x2000a000 0x100>, | |
| 75 | <0x20004064 0x8>; | |
| 76 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
| 77 | clocks = <&clk_gates8 9>; | |
| 78 | ||
| 79 | gpio-controller; | |
| 80 | #gpio-cells = <2>; | |
| 81 | ||
| 82 | interrupt-controller; | |
| 83 | #interrupt-cells = <2>; | |
| 84 | }; | |
| 85 | ||
| 86 | gpio1: gpio1@0x2003c000 { | |
| 87 | compatible = "rockchip,gpio-bank"; | |
| 88 | reg = <0x2003c000 0x100>; | |
| 89 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
| 90 | clocks = <&clk_gates8 10>; | |
| 91 | ||
| 92 | gpio-controller; | |
| 93 | #gpio-cells = <2>; | |
| 94 | ||
| 95 | interrupt-controller; | |
| 96 | #interrupt-cells = <2>; | |
| 97 | }; | |
| 98 | ||
| 99 | gpio2: gpio2@2003e000 { | |
| 100 | compatible = "rockchip,gpio-bank"; | |
| 101 | reg = <0x2003e000 0x100>; | |
| 102 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
| 103 | clocks = <&clk_gates8 11>; | |
| 104 | ||
| 105 | gpio-controller; | |
| 106 | #gpio-cells = <2>; | |
| 107 | ||
| 108 | interrupt-controller; | |
| 109 | #interrupt-cells = <2>; | |
| 110 | }; | |
| 111 | ||
| 112 | gpio3: gpio3@20080000 { | |
| 113 | compatible = "rockchip,gpio-bank"; | |
| 114 | reg = <0x20080000 0x100>; | |
| 115 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
| 116 | clocks = <&clk_gates8 12>; | |
| 117 | ||
| 118 | gpio-controller; | |
| 119 | #gpio-cells = <2>; | |
| 120 | ||
| 121 | interrupt-controller; | |
| 122 | #interrupt-cells = <2>; | |
| 123 | }; | |
| 124 | ||
| 125 | pcfg_pull_up: pcfg_pull_up { | |
| 126 | bias-pull-up; | |
| 127 | }; | |
| 128 | ||
| 129 | pcfg_pull_down: pcfg_pull_down { | |
| 130 | bias-pull-down; | |
| 131 | }; | |
| 132 | ||
| 133 | pcfg_pull_none: pcfg_pull_none { | |
| 134 | bias-disable; | |
| 135 | }; | |
| 136 | ||
| 137 | uart0 { | |
| 138 | uart0_xfer: uart0-xfer { | |
| 139 | rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>, | |
| 140 | <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>; | |
| 141 | }; | |
| 142 | ||
| 143 | uart0_cts: uart0-cts { | |
| 144 | rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>; | |
| 145 | }; | |
| 146 | ||
| 147 | uart0_rts: uart0-rts { | |
| 148 | rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>; | |
| 149 | }; | |
| 150 | }; | |
| 151 | ||
| 152 | uart1 { | |
| 153 | uart1_xfer: uart1-xfer { | |
| 154 | rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>, | |
| 155 | <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>; | |
| 156 | }; | |
| 157 | ||
| 158 | uart1_cts: uart1-cts { | |
| 159 | rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>; | |
| 160 | }; | |
| 161 | ||
| 162 | uart1_rts: uart1-rts { | |
| 163 | rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>; | |
| 164 | }; | |
| 165 | }; | |
| 166 | ||
| 167 | uart2 { | |
| 168 | uart2_xfer: uart2-xfer { | |
| 169 | rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>, | |
| 170 | <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>; | |
| 171 | }; | |
| 172 | /* no rts / cts for uart2 */ | |
| 173 | }; | |
| 174 | ||
| 175 | uart3 { | |
| 176 | uart3_xfer: uart3-xfer { | |
| 177 | rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>, | |
| 178 | <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>; | |
| 179 | }; | |
| 180 | ||
| 181 | uart3_cts: uart3-cts { | |
| 182 | rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>; | |
| 183 | }; | |
| 184 | ||
| 185 | uart3_rts: uart3-rts { | |
| 186 | rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>; | |
| 187 | }; | |
| 188 | }; | |
| 189 | ||
| 190 | sd0 { | |
| 191 | sd0_clk: sd0-clk { | |
| 192 | rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>; | |
| 193 | }; | |
| 194 | ||
| 195 | sd0_cmd: sd0-cmd { | |
| 196 | rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>; | |
| 197 | }; | |
| 198 | ||
| 199 | sd0_cd: sd0-cd { | |
| 200 | rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>; | |
| 201 | }; | |
| 202 | ||
| 203 | sd0_wp: sd0-wp { | |
| 204 | rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>; | |
| 205 | }; | |
| 206 | ||
| 207 | sd0_pwr: sd0-pwr { | |
| 208 | rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>; | |
| 209 | }; | |
| 210 | ||
| 211 | sd0_bus1: sd0-bus-width1 { | |
| 212 | rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>; | |
| 213 | }; | |
| 214 | ||
| 215 | sd0_bus4: sd0-bus-width4 { | |
| 216 | rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>, | |
| 217 | <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>, | |
| 218 | <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>, | |
| 219 | <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>; | |
| 220 | }; | |
| 221 | }; | |
| 222 | ||
| 223 | sd1 { | |
| 224 | sd1_clk: sd1-clk { | |
| 225 | rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>; | |
| 226 | }; | |
| 227 | ||
| 228 | sd1_cmd: sd1-cmd { | |
| 229 | rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>; | |
| 230 | }; | |
| 231 | ||
| 232 | sd1_cd: sd1-cd { | |
| 233 | rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>; | |
| 234 | }; | |
| 235 | ||
| 236 | sd1_wp: sd1-wp { | |
| 237 | rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>; | |
| 238 | }; | |
| 239 | ||
| 240 | sd1_bus1: sd1-bus-width1 { | |
| 241 | rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>; | |
| 242 | }; | |
| 243 | ||
| 244 | sd1_bus4: sd1-bus-width4 { | |
| 245 | rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>, | |
| 246 | <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>, | |
| 247 | <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>, | |
| 248 | <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>; | |
| 249 | }; | |
| 250 | }; | |
| 251 | }; | |
| 252 | }; | |
| 253 | }; |