[deliverable/linux.git] / arch / arm / boot / dts / rk3188.dtsi

/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3188-cru.h>
#include "rk3xxx.dtsi"

/ {
	compatible = "rockchip,rk3188";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "rockchip,rk3066-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
			operating-points = <
				/* kHz    uV */
				1608000 1350000
				1416000 1250000
				1200000 1150000
				1008000 1075000
				 816000  975000
				 600000  950000
				 504000  925000
				 312000  875000
			>;
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x3>;
		};
	};

	sram: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x8000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x8000>;

		smp-sram@0 {
			compatible = "rockchip,rk3066-smp-sram";
			reg = <0x0 0x50>;
		};
	};

	i2s0: i2s@1011a000 {
		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
		reg = <0x1011a000 0x2000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s0_bus>;
		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
		status = "disabled";
	};

	spdif: sound@1011e000 {
		compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
		reg = <0x1011e000 0x2000>;
		#sound-dai-cells = <0>;
		clock-names = "hclk", "mclk";
		clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
		dmas = <&dmac1_s 8>;
		dma-names = "tx";
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&spdif_tx>;
		status = "disabled";
	};

	cru: clock-controller@20000000 {
		compatible = "rockchip,rk3188-cru";
		reg = <0x20000000 0x1000>;
		rockchip,grf = <&grf>;

		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	usbphy: phy {
		compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		usbphy0: usb-phy0 {
			#phy-cells = <0>;
			reg = <0x10c>;
			clocks = <&cru SCLK_OTGPHY0>;
			clock-names = "phyclk";
		};

		usbphy1: usb-phy1 {
			#phy-cells = <0>;
			reg = <0x11c>;
			clocks = <&cru SCLK_OTGPHY1>;
			clock-names = "phyclk";
		};
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3188-pinctrl";
		rockchip,grf = <&grf>;
		rockchip,pmu = <&pmu>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio0@2000a000 {
			compatible = "rockchip,rk3188-gpio-bank0";
			reg = <0x2000a000 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@2003c000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003c000 0x100>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@2003e000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003e000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@20080000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20080000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_up: pcfg_pull_up {
			bias-pull-up;
		};

		pcfg_pull_down: pcfg_pull_down {
			bias-pull-down;
		};

		pcfg_pull_none: pcfg_pull_none {
			bias-disable;
		};

		emmc {
			emmc_clk: emmc-clk {
				rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
			};

			emmc_rst: emmc-rst {
				rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
			};

			/*
			 * The data pins are shared between nandc and emmc and
			 * not accessible through pinctrl. Also they should've
			 * been already set correctly by firmware, as
			 * flash/emmc is the boot-device.
			 */
		};

		emac {
			emac_xfer: emac-xfer {
				rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
						<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
						<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
						<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
						<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
						<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
						<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
						<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
			};

			emac_mdio: emac-mdio {
				rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
						<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c2 {
			i2c2_xfer: i2c2-xfer {
				rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
						<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c4 {
			i2c4_xfer: i2c4-xfer {
				rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_out: pwm0-out {
				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_out: pwm1-out {
				rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_out: pwm2-out {
				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_out: pwm3-out {
				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		spi0 {
			spi0_clk: spi0-clk {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_cs0: spi0-cs0 {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_tx: spi0-tx {
				rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_rx: spi0-rx {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_cs1: spi0-cs1 {
				rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
			};
		};

		spi1 {
			spi1_clk: spi1-clk {
				rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_cs0: spi1-cs0 {
				rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_rx: spi1-rx {
				rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_tx: spi1-tx {
				rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_cs1: spi1-cs1 {
				rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart1_cts: uart1-cts {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart1_rts: uart1-rts {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart2 {
			uart2_xfer: uart2-xfer {
				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
			};
			/* no rts / cts for uart2 */
		};

		uart3 {
			uart3_xfer: uart3-xfer {
				rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart3_cts: uart3-cts {
				rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart3_rts: uart3-rts {
				rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		sd0 {
			sd0_clk: sd0-clk {
				rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_cmd: sd0-cmd {
				rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_cd: sd0-cd {
				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_wp: sd0-wp {
				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_pwr: sd0-pwr {
				rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_bus1: sd0-bus-width1 {
				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_bus4: sd0-bus-width4 {
				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		sd1 {
			sd1_clk: sd1-clk {
				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_cmd: sd1-cmd {
				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_cd: sd1-cd {
				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_wp: sd1-wp {
				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_bus1: sd1-bus-width1 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_bus4: sd1-bus-width4 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2s0 {
			i2s0_bus: i2s0-bus {
				rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		spdif {
			spdif_tx: spdif-tx {
				rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
			};
		};
	};
};

&emac {
	compatible = "rockchip,rk3188-emac";
};

&global_timer {
	interrupts = <GIC_PPI 11 0xf04>;
};

&local_timer {
	interrupts = <GIC_PPI 13 0xf04>;
};

&i2c0 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
};

&i2c1 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
};

&i2c2 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
};

&i2c3 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
};

&i2c4 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer>;
};

&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_out>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_out>;
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_out>;
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_out>;
};

&spi0 {
	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
};

&spi1 {
	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
};

&wdt {
	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
};
Commit	Line	Data
6bcf60f8 HS	1	/*
	2	* Copyright (c) 2013 MundoReader S.L.
	3	* Author: Heiko Stuebner <heiko@sntech.de>
	4	*
0892fed7 HS	5	* This file is dual-licensed: you can use it either under the terms
	6	* of the GPL or the X11 license, at your option. Note that this dual
	7	* licensing only applies to this file, and not this project as a
	8	* whole.
6bcf60f8	9	*
0892fed7 HS	10	* a) This file is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of the
	13	* License, or (at your option) any later version.
	14	*
	15	* This file is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* Or, alternatively,
	21	*
	22	* b) Permission is hereby granted, free of charge, to any person
	23	* obtaining a copy of this software and associated documentation
	24	* files (the "Software"), to deal in the Software without
	25	* restriction, including without limitation the rights to use,
	26	* copy, modify, merge, publish, distribute, sublicense, and/or
	27	* sell copies of the Software, and to permit persons to whom the
	28	* Software is furnished to do so, subject to the following
	29	* conditions:
	30	*
	31	* The above copyright notice and this permission notice shall be
	32	* included in all copies or substantial portions of the Software.
	33	*
	34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	35	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	36	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	37	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	38	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	39	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	40	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	41	* OTHER DEALINGS IN THE SOFTWARE.
6bcf60f8 HS	42	*/
	43
	44	#include <dt-bindings/gpio/gpio.h>
	45	#include <dt-bindings/pinctrl/rockchip.h>
b13d2a7b	46	#include <dt-bindings/clock/rk3188-cru.h>
6bcf60f8	47	#include "rk3xxx.dtsi"
6bcf60f8 HS	48
	49	/ {
	50	compatible = "rockchip,rk3188";
	51
	52	cpus {
	53	#address-cells = <1>;
	54	#size-cells = <0>;
26ab69cb	55	enable-method = "rockchip,rk3066-smp";
6bcf60f8	56
be8a77c5	57	cpu0: cpu@0 {
6bcf60f8 HS	58	device_type = "cpu";
	59	compatible = "arm,cortex-a9";
	60	next-level-cache = <&L2>;
	61	reg = <0x0>;
be8a77c5 HS	62	operating-points = <
	63	/* kHz uV */
	64	1608000 1350000
	65	1416000 1250000
	66	1200000 1150000
	67	1008000 1075000
	68	816000 975000
	69	600000 950000
	70	504000 925000
	71	312000 875000
	72	>;
	73	clock-latency = <40000>;
	74	clocks = <&cru ARMCLK>;
6bcf60f8 HS	75	};
	76	cpu@1 {
	77	device_type = "cpu";
	78	compatible = "arm,cortex-a9";
	79	next-level-cache = <&L2>;
	80	reg = <0x1>;
	81	};
	82	cpu@2 {
	83	device_type = "cpu";
	84	compatible = "arm,cortex-a9";
	85	next-level-cache = <&L2>;
	86	reg = <0x2>;
	87	};
	88	cpu@3 {
	89	device_type = "cpu";
	90	compatible = "arm,cortex-a9";
	91	next-level-cache = <&L2>;
	92	reg = <0x3>;
	93	};
	94	};
	95
c3030d30 HS	96	sram: sram@10080000 {
	97	compatible = "mmio-sram";
	98	reg = <0x10080000 0x8000>;
	99	#address-cells = <1>;
	100	#size-cells = <1>;
	101	ranges = <0 0x10080000 0x8000>;
	102
	103	smp-sram@0 {
	104	compatible = "rockchip,rk3066-smp-sram";
	105	reg = <0x0 0x50>;
6bcf60f8	106	};
c3030d30 HS	107	};
c3030d30 HS	108
5fe62b83 JC	109	i2s0: i2s@1011a000 {
	110	compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
	111	reg = <0x1011a000 0x2000>;
	112	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	113	#address-cells = <1>;
	114	#size-cells = <0>;
	115	pinctrl-names = "default";
	116	pinctrl-0 = <&i2s0_bus>;
	117	dmas = <&dmac1_s 6>, <&dmac1_s 7>;
	118	dma-names = "tx", "rx";
	119	clock-names = "i2s_hclk", "i2s_clk";
	120	clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
	121	status = "disabled";
	122	};
	123
39b37ce2 SS	124	spdif: sound@1011e000 {
	125	compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
	126	reg = <0x1011e000 0x2000>;
	127	#sound-dai-cells = <0>;
	128	clock-names = "hclk", "mclk";
	129	clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
	130	dmas = <&dmac1_s 8>;
	131	dma-names = "tx";
	132	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	133	pinctrl-names = "default";
	134	pinctrl-0 = <&spdif_tx>;
	135	status = "disabled";
	136	};
	137
c3030d30 HS	138	cru: clock-controller@20000000 {
	139	compatible = "rockchip,rk3188-cru";
	140	reg = <0x20000000 0x1000>;
	141	rockchip,grf = <&grf>;
	142
	143	#clock-cells = <1>;
	144	#reset-cells = <1>;
	145	};
6bcf60f8	146
760bb977 HS	147	usbphy: phy {
	148	compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
	149	rockchip,grf = <&grf>;
	150	#address-cells = <1>;
	151	#size-cells = <0>;
	152	status = "disabled";
	153
	154	usbphy0: usb-phy0 {
	155	#phy-cells = <0>;
	156	reg = <0x10c>;
	157	clocks = <&cru SCLK_OTGPHY0>;
	158	clock-names = "phyclk";
	159	};
	160
	161	usbphy1: usb-phy1 {
	162	#phy-cells = <0>;
	163	reg = <0x11c>;
	164	clocks = <&cru SCLK_OTGPHY1>;
	165	clock-names = "phyclk";
	166	};
	167	};
	168
6e4b3b4b	169	pinctrl: pinctrl {
c3030d30 HS	170	compatible = "rockchip,rk3188-pinctrl";
	171	rockchip,grf = <&grf>;
	172	rockchip,pmu = <&pmu>;
	173
	174	#address-cells = <1>;
	175	#size-cells = <1>;
	176	ranges;
	177
6df127f3	178	gpio0: gpio0@2000a000 {
c3030d30 HS	179	compatible = "rockchip,rk3188-gpio-bank0";
	180	reg = <0x2000a000 0x100>;
	181	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	182	clocks = <&cru PCLK_GPIO0>;
	183
	184	gpio-controller;
	185	#gpio-cells = <2>;
	186
	187	interrupt-controller;
	188	#interrupt-cells = <2>;
6bcf60f8 HS	189	};
6bcf60f8 HS	190
6df127f3	191	gpio1: gpio1@2003c000 {
c3030d30 HS	192	compatible = "rockchip,gpio-bank";
	193	reg = <0x2003c000 0x100>;
	194	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	195	clocks = <&cru PCLK_GPIO1>;
de18e014	196
c3030d30 HS	197	gpio-controller;
	198	#gpio-cells = <2>;
	199
	200	interrupt-controller;
	201	#interrupt-cells = <2>;
de18e014 HS	202	};
de18e014 HS	203
c3030d30 HS	204	gpio2: gpio2@2003e000 {
	205	compatible = "rockchip,gpio-bank";
	206	reg = <0x2003e000 0x100>;
	207	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	208	clocks = <&cru PCLK_GPIO2>;
	209
	210	gpio-controller;
	211	#gpio-cells = <2>;
b13d2a7b	212
c3030d30 HS	213	interrupt-controller;
c3030d30 HS	214	#interrupt-cells = <2>;
b13d2a7b HS	215	};
b13d2a7b HS	216
c3030d30 HS	217	gpio3: gpio3@20080000 {
	218	compatible = "rockchip,gpio-bank";
	219	reg = <0x20080000 0x100>;
	220	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	221	clocks = <&cru PCLK_GPIO3>;
56f2b894	222
c3030d30 HS	223	gpio-controller;
c3030d30 HS	224	#gpio-cells = <2>;
6bcf60f8	225
c3030d30 HS	226	interrupt-controller;
	227	#interrupt-cells = <2>;
	228	};
6bcf60f8	229
c3030d30 HS	230	pcfg_pull_up: pcfg_pull_up {
	231	bias-pull-up;
	232	};
6bcf60f8	233
c3030d30 HS	234	pcfg_pull_down: pcfg_pull_down {
	235	bias-pull-down;
	236	};
6bcf60f8	237
c3030d30 HS	238	pcfg_pull_none: pcfg_pull_none {
	239	bias-disable;
	240	};
6bcf60f8	241
4ff4ae12 HS	242	emmc {
4ff4ae12 HS	243	emmc_clk: emmc-clk {
bee1cef6	244	rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
4ff4ae12 HS	245	};
	246
	247	emmc_cmd: emmc-cmd {
bee1cef6	248	rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
4ff4ae12 HS	249	};
	250
	251	emmc_rst: emmc-rst {
bee1cef6	252	rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
4ff4ae12 HS	253	};
	254
	255	/*
	256	* The data pins are shared between nandc and emmc and
	257	* not accessible through pinctrl. Also they should've
	258	* been already set correctly by firmware, as
	259	* flash/emmc is the boot-device.
	260	*/
	261	};
	262
18ec91e1 RP	263	emac {
	264	emac_xfer: emac-xfer {
	265	rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
	266	<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
	267	<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
	268	<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
	269	<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
	270	<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
	271	<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
	272	<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
	273	};
	274
	275	emac_mdio: emac-mdio {
	276	rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
	277	<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
	278	};
	279	};
	280
9cdffd8c HS	281	i2c0 {
	282	i2c0_xfer: i2c0-xfer {
	283	rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
	284	<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
	285	};
	286	};
	287
	288	i2c1 {
	289	i2c1_xfer: i2c1-xfer {
	290	rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
	291	<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
	292	};
	293	};
	294
	295	i2c2 {
	296	i2c2_xfer: i2c2-xfer {
	297	rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
	298	<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
	299	};
	300	};
	301
	302	i2c3 {
	303	i2c3_xfer: i2c3-xfer {
	304	rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
	305	<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
	306	};
	307	};
	308
	309	i2c4 {
	310	i2c4_xfer: i2c4-xfer {
	311	rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
	312	<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
	313	};
	314	};
	315
550c7f4e BG	316	pwm0 {
	317	pwm0_out: pwm0-out {
	318	rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
	319	};
	320	};
	321
	322	pwm1 {
	323	pwm1_out: pwm1-out {
	324	rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
	325	};
	326	};
	327
	328	pwm2 {
	329	pwm2_out: pwm2-out {
	330	rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
	331	};
	332	};
	333
	334	pwm3 {
	335	pwm3_out: pwm3-out {
	336	rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
	337	};
	338	};
	339
39c2bd78 HS	340	spi0 {
	341	spi0_clk: spi0-clk {
	342	rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
	343	};
	344	spi0_cs0: spi0-cs0 {
	345	rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
	346	};
	347	spi0_tx: spi0-tx {
	348	rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
	349	};
	350	spi0_rx: spi0-rx {
	351	rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
	352	};
	353	spi0_cs1: spi0-cs1 {
	354	rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
	355	};
	356	};
	357
	358	spi1 {
	359	spi1_clk: spi1-clk {
	360	rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
	361	};
	362	spi1_cs0: spi1-cs0 {
	363	rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
	364	};
	365	spi1_rx: spi1-rx {
	366	rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
	367	};
	368	spi1_tx: spi1-tx {
	369	rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
	370	};
	371	spi1_cs1: spi1-cs1 {
	372	rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
	373	};
	374	};
	375
c3030d30 HS	376	uart0 {
	377	uart0_xfer: uart0-xfer {
	378	rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
	379	<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
	380	};
6bcf60f8	381
c3030d30 HS	382	uart0_cts: uart0-cts {
c3030d30 HS	383	rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	384	};
6bcf60f8 HS	385
c3030d30 HS	386	uart0_rts: uart0-rts {
	387	rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
	388	};
	389	};
6bcf60f8	390
c3030d30 HS	391	uart1 {
	392	uart1_xfer: uart1-xfer {
	393	rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
	394	<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
	395	};
6bcf60f8	396
c3030d30 HS	397	uart1_cts: uart1-cts {
c3030d30 HS	398	rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	399	};
6bcf60f8 HS	400
c3030d30 HS	401	uart1_rts: uart1-rts {
	402	rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
	403	};
	404	};
6bcf60f8	405
c3030d30 HS	406	uart2 {
	407	uart2_xfer: uart2-xfer {
	408	rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
	409	<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
	410	};
	411	/* no rts / cts for uart2 */
	412	};
6bcf60f8	413
c3030d30 HS	414	uart3 {
	415	uart3_xfer: uart3-xfer {
	416	rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
	417	<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	418	};
6bcf60f8 HS	419
c3030d30 HS	420	uart3_cts: uart3-cts {
c3030d30 HS	421	rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	422	};
6bcf60f8 HS	423
c3030d30 HS	424	uart3_rts: uart3-rts {
c3030d30 HS	425	rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8	426	};
c3030d30	427	};
6bcf60f8	428
c3030d30 HS	429	sd0 {
	430	sd0_clk: sd0-clk {
	431	rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	432	};
6bcf60f8 HS	433
c3030d30 HS	434	sd0_cmd: sd0-cmd {
	435	rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
	436	};
6bcf60f8	437
c3030d30 HS	438	sd0_cd: sd0-cd {
	439	rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
	440	};
6bcf60f8	441
c3030d30 HS	442	sd0_wp: sd0-wp {
c3030d30 HS	443	rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	444	};
6bcf60f8 HS	445
c3030d30 HS	446	sd0_pwr: sd0-pwr {
	447	rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
	448	};
6bcf60f8	449
c3030d30 HS	450	sd0_bus1: sd0-bus-width1 {
	451	rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
	452	};
6bcf60f8	453
c3030d30 HS	454	sd0_bus4: sd0-bus-width4 {
	455	rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
	456	<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
	457	<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
	458	<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8	459	};
c3030d30	460	};
6bcf60f8	461
c3030d30 HS	462	sd1 {
	463	sd1_clk: sd1-clk {
	464	rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	465	};
6bcf60f8 HS	466
c3030d30 HS	467	sd1_cmd: sd1-cmd {
	468	rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
	469	};
6bcf60f8	470
c3030d30 HS	471	sd1_cd: sd1-cd {
	472	rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
	473	};
6bcf60f8	474
c3030d30 HS	475	sd1_wp: sd1-wp {
c3030d30 HS	476	rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	477	};
6bcf60f8 HS	478
c3030d30 HS	479	sd1_bus1: sd1-bus-width1 {
c3030d30 HS	480	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	481	};
6bcf60f8 HS	482
c3030d30 HS	483	sd1_bus4: sd1-bus-width4 {
	484	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
	485	<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
	486	<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
	487	<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	488	};
6bcf60f8 HS	489	};
5fe62b83 JC	490
	491	i2s0 {
	492	i2s0_bus: i2s0-bus {
	493	rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
	494	<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
	495	<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
	496	<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
	497	<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
	498	<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
	499	};
	500	};
39b37ce2 SS	501
	502	spdif {
	503	spdif_tx: spdif-tx {
	504	rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
	505	};
	506	};
6bcf60f8 HS	507	};
6bcf60f8 HS	508	};
fcbbf965	509
18ec91e1 RP	510	&emac {
	511	compatible = "rockchip,rk3188-emac";
	512	};
	513
fcbbf965 HS	514	&global_timer {
	515	interrupts = <GIC_PPI 11 0xf04>;
	516	};
	517
	518	&local_timer {
	519	interrupts = <GIC_PPI 13 0xf04>;
	520	};
	521
9cdffd8c HS	522	&i2c0 {
	523	compatible = "rockchip,rk3188-i2c";
	524	pinctrl-names = "default";
	525	pinctrl-0 = <&i2c0_xfer>;
	526	};
	527
	528	&i2c1 {
	529	compatible = "rockchip,rk3188-i2c";
	530	pinctrl-names = "default";
	531	pinctrl-0 = <&i2c1_xfer>;
	532	};
	533
	534	&i2c2 {
	535	compatible = "rockchip,rk3188-i2c";
	536	pinctrl-names = "default";
	537	pinctrl-0 = <&i2c2_xfer>;
	538	};
	539
	540	&i2c3 {
	541	compatible = "rockchip,rk3188-i2c";
	542	pinctrl-names = "default";
	543	pinctrl-0 = <&i2c3_xfer>;
	544	};
	545
	546	&i2c4 {
	547	compatible = "rockchip,rk3188-i2c";
	548	pinctrl-names = "default";
	549	pinctrl-0 = <&i2c4_xfer>;
	550	};
	551
550c7f4e BG	552	&pwm0 {
	553	pinctrl-names = "default";
	554	pinctrl-0 = <&pwm0_out>;
	555	};
	556
	557	&pwm1 {
	558	pinctrl-names = "default";
	559	pinctrl-0 = <&pwm1_out>;
	560	};
	561
	562	&pwm2 {
	563	pinctrl-names = "default";
	564	pinctrl-0 = <&pwm2_out>;
	565	};
	566
	567	&pwm3 {
	568	pinctrl-names = "default";
	569	pinctrl-0 = <&pwm3_out>;
	570	};
	571
39c2bd78 HS	572	&spi0 {
	573	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	574	pinctrl-names = "default";
	575	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
	576	};
	577
	578	&spi1 {
	579	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	580	pinctrl-names = "default";
	581	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
	582	};
	583
fcbbf965 HS	584	&uart0 {
	585	pinctrl-names = "default";
	586	pinctrl-0 = <&uart0_xfer>;
	587	};
	588
	589	&uart1 {
	590	pinctrl-names = "default";
	591	pinctrl-0 = <&uart1_xfer>;
	592	};
	593
	594	&uart2 {
	595	pinctrl-names = "default";
	596	pinctrl-0 = <&uart2_xfer>;
	597	};
	598
	599	&uart3 {
	600	pinctrl-names = "default";
	601	pinctrl-0 = <&uart3_xfer>;
	602	};
eb2b9d47 HS	603
	604	&wdt {
	605	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
	606	};