[deliverable/linux.git] / arch / arm / boot / dts / rk3188.dtsi

/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3188-cru.h>
#include "rk3xxx.dtsi"

/ {
	compatible = "rockchip,rk3188";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "rockchip,rk3066-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
			operating-points = <
				/* kHz    uV */
				1608000 1350000
				1416000 1250000
				1200000 1150000
				1008000 1075000
				 816000  975000
				 600000  950000
				 504000  925000
				 312000  875000
			>;
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x3>;
		};
	};

	sram: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x8000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x8000>;

		smp-sram@0 {
			compatible = "rockchip,rk3066-smp-sram";
			reg = <0x0 0x50>;
		};
	};

	i2s0: i2s@1011a000 {
		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
		reg = <0x1011a000 0x2000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s0_bus>;
		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
		rockchip,playback-channels = <2>;
		rockchip,capture-channels = <2>;
		status = "disabled";
	};

	spdif: sound@1011e000 {
		compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
		reg = <0x1011e000 0x2000>;
		#sound-dai-cells = <0>;
		clock-names = "hclk", "mclk";
		clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
		dmas = <&dmac1_s 8>;
		dma-names = "tx";
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&spdif_tx>;
		status = "disabled";
	};

	cru: clock-controller@20000000 {
		compatible = "rockchip,rk3188-cru";
		reg = <0x20000000 0x1000>;
		rockchip,grf = <&grf>;

		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	usbphy: phy {
		compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		usbphy0: usb-phy0 {
			#phy-cells = <0>;
			reg = <0x10c>;
			clocks = <&cru SCLK_OTGPHY0>;
			clock-names = "phyclk";
		};

		usbphy1: usb-phy1 {
			#phy-cells = <0>;
			reg = <0x11c>;
			clocks = <&cru SCLK_OTGPHY1>;
			clock-names = "phyclk";
		};
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3188-pinctrl";
		rockchip,grf = <&grf>;
		rockchip,pmu = <&pmu>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio0@2000a000 {
			compatible = "rockchip,rk3188-gpio-bank0";
			reg = <0x2000a000 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@2003c000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003c000 0x100>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@2003e000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003e000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@20080000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20080000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_up: pcfg_pull_up {
			bias-pull-up;
		};

		pcfg_pull_down: pcfg_pull_down {
			bias-pull-down;
		};

		pcfg_pull_none: pcfg_pull_none {
			bias-disable;
		};

		emmc {
			emmc_clk: emmc-clk {
				rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
			};

			emmc_rst: emmc-rst {
				rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
			};

			/*
			 * The data pins are shared between nandc and emmc and
			 * not accessible through pinctrl. Also they should've
			 * been already set correctly by firmware, as
			 * flash/emmc is the boot-device.
			 */
		};

		emac {
			emac_xfer: emac-xfer {
				rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
						<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
						<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
						<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
						<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
						<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
						<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
						<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
			};

			emac_mdio: emac-mdio {
				rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
						<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c2 {
			i2c2_xfer: i2c2-xfer {
				rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
						<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c4 {
			i2c4_xfer: i2c4-xfer {
				rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_out: pwm0-out {
				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_out: pwm1-out {
				rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_out: pwm2-out {
				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_out: pwm3-out {
				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		spi0 {
			spi0_clk: spi0-clk {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_cs0: spi0-cs0 {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_tx: spi0-tx {
				rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_rx: spi0-rx {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_cs1: spi0-cs1 {
				rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
			};
		};

		spi1 {
			spi1_clk: spi1-clk {
				rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_cs0: spi1-cs0 {
				rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_rx: spi1-rx {
				rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_tx: spi1-tx {
				rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi1_cs1: spi1-cs1 {
				rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart1_cts: uart1-cts {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart1_rts: uart1-rts {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart2 {
			uart2_xfer: uart2-xfer {
				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
			};
			/* no rts / cts for uart2 */
		};

		uart3 {
			uart3_xfer: uart3-xfer {
				rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
						<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart3_cts: uart3-cts {
				rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart3_rts: uart3-rts {
				rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		sd0 {
			sd0_clk: sd0-clk {
				rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_cmd: sd0-cmd {
				rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_cd: sd0-cd {
				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_wp: sd0-wp {
				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_pwr: sd0-pwr {
				rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_bus1: sd0-bus-width1 {
				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd0_bus4: sd0-bus-width4 {
				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		sd1 {
			sd1_clk: sd1-clk {
				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_cmd: sd1-cmd {
				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_cd: sd1-cd {
				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_wp: sd1-wp {
				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_bus1: sd1-bus-width1 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
			};

			sd1_bus4: sd1-bus-width4 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2s0 {
			i2s0_bus: i2s0-bus {
				rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		spdif {
			spdif_tx: spdif-tx {
				rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
			};
		};
	};
};

&emac {
	compatible = "rockchip,rk3188-emac";
};

&global_timer {
	interrupts = <GIC_PPI 11 0xf04>;
};

&local_timer {
	interrupts = <GIC_PPI 13 0xf04>;
};

&i2c0 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
};

&i2c1 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
};

&i2c2 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
};

&i2c3 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
};

&i2c4 {
	compatible = "rockchip,rk3188-i2c";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer>;
};

&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_out>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_out>;
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_out>;
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_out>;
};

&spi0 {
	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
};

&spi1 {
	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
};

&wdt {
	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
};
Commit	Line	Data
6bcf60f8 HS	1	/*
	2	* Copyright (c) 2013 MundoReader S.L.
	3	* Author: Heiko Stuebner <heiko@sntech.de>
	4	*
0892fed7 HS	5	* This file is dual-licensed: you can use it either under the terms
	6	* of the GPL or the X11 license, at your option. Note that this dual
	7	* licensing only applies to this file, and not this project as a
	8	* whole.
6bcf60f8	9	*
0892fed7 HS	10	* a) This file is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of the
	13	* License, or (at your option) any later version.
	14	*
	15	* This file is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* Or, alternatively,
	21	*
	22	* b) Permission is hereby granted, free of charge, to any person
	23	* obtaining a copy of this software and associated documentation
	24	* files (the "Software"), to deal in the Software without
	25	* restriction, including without limitation the rights to use,
	26	* copy, modify, merge, publish, distribute, sublicense, and/or
	27	* sell copies of the Software, and to permit persons to whom the
	28	* Software is furnished to do so, subject to the following
	29	* conditions:
	30	*
	31	* The above copyright notice and this permission notice shall be
	32	* included in all copies or substantial portions of the Software.
	33	*
	34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	35	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	36	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	37	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	38	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	39	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	40	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	41	* OTHER DEALINGS IN THE SOFTWARE.
6bcf60f8 HS	42	*/
	43
	44	#include <dt-bindings/gpio/gpio.h>
	45	#include <dt-bindings/pinctrl/rockchip.h>
b13d2a7b	46	#include <dt-bindings/clock/rk3188-cru.h>
6bcf60f8	47	#include "rk3xxx.dtsi"
6bcf60f8 HS	48
	49	/ {
	50	compatible = "rockchip,rk3188";
	51
	52	cpus {
	53	#address-cells = <1>;
	54	#size-cells = <0>;
26ab69cb	55	enable-method = "rockchip,rk3066-smp";
6bcf60f8	56
be8a77c5	57	cpu0: cpu@0 {
6bcf60f8 HS	58	device_type = "cpu";
	59	compatible = "arm,cortex-a9";
	60	next-level-cache = <&L2>;
	61	reg = <0x0>;
be8a77c5 HS	62	operating-points = <
	63	/* kHz uV */
	64	1608000 1350000
	65	1416000 1250000
	66	1200000 1150000
	67	1008000 1075000
	68	816000 975000
	69	600000 950000
	70	504000 925000
	71	312000 875000
	72	>;
	73	clock-latency = <40000>;
	74	clocks = <&cru ARMCLK>;
6bcf60f8 HS	75	};
	76	cpu@1 {
	77	device_type = "cpu";
	78	compatible = "arm,cortex-a9";
	79	next-level-cache = <&L2>;
	80	reg = <0x1>;
	81	};
	82	cpu@2 {
	83	device_type = "cpu";
	84	compatible = "arm,cortex-a9";
	85	next-level-cache = <&L2>;
	86	reg = <0x2>;
	87	};
	88	cpu@3 {
	89	device_type = "cpu";
	90	compatible = "arm,cortex-a9";
	91	next-level-cache = <&L2>;
	92	reg = <0x3>;
	93	};
	94	};
	95
c3030d30 HS	96	sram: sram@10080000 {
	97	compatible = "mmio-sram";
	98	reg = <0x10080000 0x8000>;
	99	#address-cells = <1>;
	100	#size-cells = <1>;
	101	ranges = <0 0x10080000 0x8000>;
	102
	103	smp-sram@0 {
	104	compatible = "rockchip,rk3066-smp-sram";
	105	reg = <0x0 0x50>;
6bcf60f8	106	};
c3030d30 HS	107	};
c3030d30 HS	108
5fe62b83 JC	109	i2s0: i2s@1011a000 {
	110	compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
	111	reg = <0x1011a000 0x2000>;
	112	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	113	#address-cells = <1>;
	114	#size-cells = <0>;
	115	pinctrl-names = "default";
	116	pinctrl-0 = <&i2s0_bus>;
	117	dmas = <&dmac1_s 6>, <&dmac1_s 7>;
	118	dma-names = "tx", "rx";
	119	clock-names = "i2s_hclk", "i2s_clk";
	120	clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
e241657d SZ	121	rockchip,playback-channels = <2>;
e241657d SZ	122	rockchip,capture-channels = <2>;
5fe62b83 JC	123	status = "disabled";
	124	};
	125
39b37ce2 SS	126	spdif: sound@1011e000 {
	127	compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
	128	reg = <0x1011e000 0x2000>;
	129	#sound-dai-cells = <0>;
	130	clock-names = "hclk", "mclk";
	131	clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
	132	dmas = <&dmac1_s 8>;
	133	dma-names = "tx";
	134	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	135	pinctrl-names = "default";
	136	pinctrl-0 = <&spdif_tx>;
	137	status = "disabled";
	138	};
	139
c3030d30 HS	140	cru: clock-controller@20000000 {
	141	compatible = "rockchip,rk3188-cru";
	142	reg = <0x20000000 0x1000>;
	143	rockchip,grf = <&grf>;
	144
	145	#clock-cells = <1>;
	146	#reset-cells = <1>;
	147	};
6bcf60f8	148
760bb977 HS	149	usbphy: phy {
	150	compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
	151	rockchip,grf = <&grf>;
	152	#address-cells = <1>;
	153	#size-cells = <0>;
	154	status = "disabled";
	155
	156	usbphy0: usb-phy0 {
	157	#phy-cells = <0>;
	158	reg = <0x10c>;
	159	clocks = <&cru SCLK_OTGPHY0>;
	160	clock-names = "phyclk";
	161	};
	162
	163	usbphy1: usb-phy1 {
	164	#phy-cells = <0>;
	165	reg = <0x11c>;
	166	clocks = <&cru SCLK_OTGPHY1>;
	167	clock-names = "phyclk";
	168	};
	169	};
	170
6e4b3b4b	171	pinctrl: pinctrl {
c3030d30 HS	172	compatible = "rockchip,rk3188-pinctrl";
	173	rockchip,grf = <&grf>;
	174	rockchip,pmu = <&pmu>;
	175
	176	#address-cells = <1>;
	177	#size-cells = <1>;
	178	ranges;
	179
6df127f3	180	gpio0: gpio0@2000a000 {
c3030d30 HS	181	compatible = "rockchip,rk3188-gpio-bank0";
	182	reg = <0x2000a000 0x100>;
	183	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	184	clocks = <&cru PCLK_GPIO0>;
	185
	186	gpio-controller;
	187	#gpio-cells = <2>;
	188
	189	interrupt-controller;
	190	#interrupt-cells = <2>;
6bcf60f8 HS	191	};
6bcf60f8 HS	192
6df127f3	193	gpio1: gpio1@2003c000 {
c3030d30 HS	194	compatible = "rockchip,gpio-bank";
	195	reg = <0x2003c000 0x100>;
	196	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	197	clocks = <&cru PCLK_GPIO1>;
de18e014	198
c3030d30 HS	199	gpio-controller;
	200	#gpio-cells = <2>;
	201
	202	interrupt-controller;
	203	#interrupt-cells = <2>;
de18e014 HS	204	};
de18e014 HS	205
c3030d30 HS	206	gpio2: gpio2@2003e000 {
	207	compatible = "rockchip,gpio-bank";
	208	reg = <0x2003e000 0x100>;
	209	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	210	clocks = <&cru PCLK_GPIO2>;
	211
	212	gpio-controller;
	213	#gpio-cells = <2>;
b13d2a7b	214
c3030d30 HS	215	interrupt-controller;
c3030d30 HS	216	#interrupt-cells = <2>;
b13d2a7b HS	217	};
b13d2a7b HS	218
c3030d30 HS	219	gpio3: gpio3@20080000 {
	220	compatible = "rockchip,gpio-bank";
	221	reg = <0x20080000 0x100>;
	222	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	223	clocks = <&cru PCLK_GPIO3>;
56f2b894	224
c3030d30 HS	225	gpio-controller;
c3030d30 HS	226	#gpio-cells = <2>;
6bcf60f8	227
c3030d30 HS	228	interrupt-controller;
	229	#interrupt-cells = <2>;
	230	};
6bcf60f8	231
c3030d30 HS	232	pcfg_pull_up: pcfg_pull_up {
	233	bias-pull-up;
	234	};
6bcf60f8	235
c3030d30 HS	236	pcfg_pull_down: pcfg_pull_down {
	237	bias-pull-down;
	238	};
6bcf60f8	239
c3030d30 HS	240	pcfg_pull_none: pcfg_pull_none {
	241	bias-disable;
	242	};
6bcf60f8	243
4ff4ae12 HS	244	emmc {
4ff4ae12 HS	245	emmc_clk: emmc-clk {
bee1cef6	246	rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
4ff4ae12 HS	247	};
	248
	249	emmc_cmd: emmc-cmd {
bee1cef6	250	rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
4ff4ae12 HS	251	};
	252
	253	emmc_rst: emmc-rst {
bee1cef6	254	rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
4ff4ae12 HS	255	};
	256
	257	/*
	258	* The data pins are shared between nandc and emmc and
	259	* not accessible through pinctrl. Also they should've
	260	* been already set correctly by firmware, as
	261	* flash/emmc is the boot-device.
	262	*/
	263	};
	264
18ec91e1 RP	265	emac {
	266	emac_xfer: emac-xfer {
	267	rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
	268	<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
	269	<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
	270	<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
	271	<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
	272	<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
	273	<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
	274	<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
	275	};
	276
	277	emac_mdio: emac-mdio {
	278	rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
	279	<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
	280	};
	281	};
	282
9cdffd8c HS	283	i2c0 {
	284	i2c0_xfer: i2c0-xfer {
	285	rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
	286	<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
	287	};
	288	};
	289
	290	i2c1 {
	291	i2c1_xfer: i2c1-xfer {
	292	rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
	293	<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
	294	};
	295	};
	296
	297	i2c2 {
	298	i2c2_xfer: i2c2-xfer {
	299	rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
	300	<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
	301	};
	302	};
	303
	304	i2c3 {
	305	i2c3_xfer: i2c3-xfer {
	306	rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
	307	<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
	308	};
	309	};
	310
	311	i2c4 {
	312	i2c4_xfer: i2c4-xfer {
	313	rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
	314	<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
	315	};
	316	};
	317
550c7f4e BG	318	pwm0 {
	319	pwm0_out: pwm0-out {
	320	rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
	321	};
	322	};
	323
	324	pwm1 {
	325	pwm1_out: pwm1-out {
	326	rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
	327	};
	328	};
	329
	330	pwm2 {
	331	pwm2_out: pwm2-out {
	332	rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
	333	};
	334	};
	335
	336	pwm3 {
	337	pwm3_out: pwm3-out {
	338	rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
	339	};
	340	};
	341
39c2bd78 HS	342	spi0 {
	343	spi0_clk: spi0-clk {
	344	rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
	345	};
	346	spi0_cs0: spi0-cs0 {
	347	rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
	348	};
	349	spi0_tx: spi0-tx {
	350	rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
	351	};
	352	spi0_rx: spi0-rx {
	353	rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
	354	};
	355	spi0_cs1: spi0-cs1 {
	356	rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
	357	};
	358	};
	359
	360	spi1 {
	361	spi1_clk: spi1-clk {
	362	rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
	363	};
	364	spi1_cs0: spi1-cs0 {
	365	rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
	366	};
	367	spi1_rx: spi1-rx {
	368	rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
	369	};
	370	spi1_tx: spi1-tx {
	371	rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
	372	};
	373	spi1_cs1: spi1-cs1 {
	374	rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
	375	};
	376	};
	377
c3030d30 HS	378	uart0 {
	379	uart0_xfer: uart0-xfer {
	380	rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
	381	<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
	382	};
6bcf60f8	383
c3030d30 HS	384	uart0_cts: uart0-cts {
c3030d30 HS	385	rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	386	};
6bcf60f8 HS	387
c3030d30 HS	388	uart0_rts: uart0-rts {
	389	rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
	390	};
	391	};
6bcf60f8	392
c3030d30 HS	393	uart1 {
	394	uart1_xfer: uart1-xfer {
	395	rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
	396	<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
	397	};
6bcf60f8	398
c3030d30 HS	399	uart1_cts: uart1-cts {
c3030d30 HS	400	rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	401	};
6bcf60f8 HS	402
c3030d30 HS	403	uart1_rts: uart1-rts {
	404	rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
	405	};
	406	};
6bcf60f8	407
c3030d30 HS	408	uart2 {
	409	uart2_xfer: uart2-xfer {
	410	rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
	411	<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
	412	};
	413	/* no rts / cts for uart2 */
	414	};
6bcf60f8	415
c3030d30 HS	416	uart3 {
	417	uart3_xfer: uart3-xfer {
	418	rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
	419	<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	420	};
6bcf60f8 HS	421
c3030d30 HS	422	uart3_cts: uart3-cts {
c3030d30 HS	423	rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	424	};
6bcf60f8 HS	425
c3030d30 HS	426	uart3_rts: uart3-rts {
c3030d30 HS	427	rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8	428	};
c3030d30	429	};
6bcf60f8	430
c3030d30 HS	431	sd0 {
	432	sd0_clk: sd0-clk {
	433	rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	434	};
6bcf60f8 HS	435
c3030d30 HS	436	sd0_cmd: sd0-cmd {
	437	rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
	438	};
6bcf60f8	439
c3030d30 HS	440	sd0_cd: sd0-cd {
	441	rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
	442	};
6bcf60f8	443
c3030d30 HS	444	sd0_wp: sd0-wp {
c3030d30 HS	445	rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	446	};
6bcf60f8 HS	447
c3030d30 HS	448	sd0_pwr: sd0-pwr {
	449	rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
	450	};
6bcf60f8	451
c3030d30 HS	452	sd0_bus1: sd0-bus-width1 {
	453	rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
	454	};
6bcf60f8	455
c3030d30 HS	456	sd0_bus4: sd0-bus-width4 {
	457	rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
	458	<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
	459	<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
	460	<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8	461	};
c3030d30	462	};
6bcf60f8	463
c3030d30 HS	464	sd1 {
	465	sd1_clk: sd1-clk {
	466	rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	467	};
6bcf60f8 HS	468
c3030d30 HS	469	sd1_cmd: sd1-cmd {
	470	rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
	471	};
6bcf60f8	472
c3030d30 HS	473	sd1_cd: sd1-cd {
	474	rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
	475	};
6bcf60f8	476
c3030d30 HS	477	sd1_wp: sd1-wp {
c3030d30 HS	478	rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	479	};
6bcf60f8 HS	480
c3030d30 HS	481	sd1_bus1: sd1-bus-width1 {
c3030d30 HS	482	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	483	};
6bcf60f8 HS	484
c3030d30 HS	485	sd1_bus4: sd1-bus-width4 {
	486	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
	487	<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
	488	<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
	489	<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
6bcf60f8 HS	490	};
6bcf60f8 HS	491	};
5fe62b83 JC	492
	493	i2s0 {
	494	i2s0_bus: i2s0-bus {
	495	rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
	496	<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
	497	<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
	498	<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
	499	<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
	500	<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
	501	};
	502	};
39b37ce2 SS	503
	504	spdif {
	505	spdif_tx: spdif-tx {
	506	rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
	507	};
	508	};
6bcf60f8 HS	509	};
6bcf60f8 HS	510	};
fcbbf965	511
18ec91e1 RP	512	&emac {
	513	compatible = "rockchip,rk3188-emac";
	514	};
	515
fcbbf965 HS	516	&global_timer {
	517	interrupts = <GIC_PPI 11 0xf04>;
	518	};
	519
	520	&local_timer {
	521	interrupts = <GIC_PPI 13 0xf04>;
	522	};
	523
9cdffd8c HS	524	&i2c0 {
	525	compatible = "rockchip,rk3188-i2c";
	526	pinctrl-names = "default";
	527	pinctrl-0 = <&i2c0_xfer>;
	528	};
	529
	530	&i2c1 {
	531	compatible = "rockchip,rk3188-i2c";
	532	pinctrl-names = "default";
	533	pinctrl-0 = <&i2c1_xfer>;
	534	};
	535
	536	&i2c2 {
	537	compatible = "rockchip,rk3188-i2c";
	538	pinctrl-names = "default";
	539	pinctrl-0 = <&i2c2_xfer>;
	540	};
	541
	542	&i2c3 {
	543	compatible = "rockchip,rk3188-i2c";
	544	pinctrl-names = "default";
	545	pinctrl-0 = <&i2c3_xfer>;
	546	};
	547
	548	&i2c4 {
	549	compatible = "rockchip,rk3188-i2c";
	550	pinctrl-names = "default";
	551	pinctrl-0 = <&i2c4_xfer>;
	552	};
	553
550c7f4e BG	554	&pwm0 {
	555	pinctrl-names = "default";
	556	pinctrl-0 = <&pwm0_out>;
	557	};
	558
	559	&pwm1 {
	560	pinctrl-names = "default";
	561	pinctrl-0 = <&pwm1_out>;
	562	};
	563
	564	&pwm2 {
	565	pinctrl-names = "default";
	566	pinctrl-0 = <&pwm2_out>;
	567	};
	568
	569	&pwm3 {
	570	pinctrl-names = "default";
	571	pinctrl-0 = <&pwm3_out>;
	572	};
	573
39c2bd78 HS	574	&spi0 {
	575	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	576	pinctrl-names = "default";
	577	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
	578	};
	579
	580	&spi1 {
	581	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
	582	pinctrl-names = "default";
	583	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
	584	};
	585
fcbbf965 HS	586	&uart0 {
	587	pinctrl-names = "default";
	588	pinctrl-0 = <&uart0_xfer>;
	589	};
	590
	591	&uart1 {
	592	pinctrl-names = "default";
	593	pinctrl-0 = <&uart1_xfer>;
	594	};
	595
	596	&uart2 {
	597	pinctrl-names = "default";
	598	pinctrl-0 = <&uart2_xfer>;
	599	};
	600
	601	&uart3 {
	602	pinctrl-names = "default";
	603	pinctrl-0 = <&uart3_xfer>;
	604	};
eb2b9d47 HS	605
	606	&wdt {
	607	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
	608	};