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e28ea9db AS |
1 | /* |
2 | * Google Veyron (and derivatives) board device tree source | |
3 | * | |
4 | * Copyright 2015 Google, Inc | |
5 | * | |
6 | * This file is dual-licensed: you can use it either under the terms | |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
10 | * | |
11 | * a) This file is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
16 | * This file is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * Or, alternatively, | |
22 | * | |
23 | * b) Permission is hereby granted, free of charge, to any person | |
24 | * obtaining a copy of this software and associated documentation | |
25 | * files (the "Software"), to deal in the Software without | |
26 | * restriction, including without limitation the rights to use, | |
27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
28 | * sell copies of the Software, and to permit persons to whom the | |
29 | * Software is furnished to do so, subject to the following | |
30 | * conditions: | |
31 | * | |
32 | * The above copyright notice and this permission notice shall be | |
33 | * included in all copies or substantial portions of the Software. | |
34 | * | |
35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
42 | * OTHER DEALINGS IN THE SOFTWARE. | |
43 | */ | |
44 | ||
45 | #include <dt-bindings/clock/rockchip,rk808.h> | |
46 | #include <dt-bindings/input/input.h> | |
47 | #include "rk3288.dtsi" | |
48 | ||
49 | / { | |
fb7beae5 | 50 | memory@0 { |
e28ea9db AS |
51 | device_type = "memory"; |
52 | reg = <0x0 0x80000000>; | |
53 | }; | |
54 | ||
55 | gpio_keys: gpio-keys { | |
56 | compatible = "gpio-keys"; | |
57 | #address-cells = <1>; | |
58 | #size-cells = <0>; | |
59 | ||
60 | pinctrl-names = "default"; | |
61 | pinctrl-0 = <&pwr_key_l>; | |
62 | power { | |
63 | label = "Power"; | |
64 | gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; | |
65 | linux,code = <KEY_POWER>; | |
66 | debounce-interval = <100>; | |
4f66f247 | 67 | wakeup-source; |
e28ea9db AS |
68 | }; |
69 | }; | |
70 | ||
71 | gpio-restart { | |
72 | compatible = "gpio-restart"; | |
73 | gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; | |
74 | pinctrl-names = "default"; | |
75 | pinctrl-0 = <&ap_warm_reset_h>; | |
76 | priority = <200>; | |
77 | }; | |
78 | ||
79 | emmc_pwrseq: emmc-pwrseq { | |
80 | compatible = "mmc-pwrseq-emmc"; | |
81 | pinctrl-0 = <&emmc_reset>; | |
82 | pinctrl-names = "default"; | |
83 | reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; | |
84 | }; | |
85 | ||
e28ea9db AS |
86 | sdio_pwrseq: sdio-pwrseq { |
87 | compatible = "mmc-pwrseq-simple"; | |
88 | clocks = <&rk808 RK808_CLKOUT1>; | |
89 | clock-names = "ext_clock"; | |
90 | pinctrl-names = "default"; | |
91 | pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>; | |
92 | ||
93 | /* | |
94 | * On the module itself this is one of these (depending | |
95 | * on the actual card populated): | |
96 | * - SDIO_RESET_L_WL_REG_ON | |
97 | * - PDN (power down when low) | |
98 | */ | |
99 | reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; | |
100 | }; | |
101 | ||
102 | vcc_5v: vcc-5v { | |
103 | compatible = "regulator-fixed"; | |
104 | regulator-name = "vcc_5v"; | |
105 | regulator-always-on; | |
106 | regulator-boot-on; | |
107 | regulator-min-microvolt = <5000000>; | |
108 | regulator-max-microvolt = <5000000>; | |
109 | }; | |
110 | ||
111 | vcc33_sys: vcc33-sys { | |
112 | compatible = "regulator-fixed"; | |
113 | regulator-name = "vcc33_sys"; | |
114 | regulator-always-on; | |
115 | regulator-boot-on; | |
116 | regulator-min-microvolt = <3300000>; | |
117 | regulator-max-microvolt = <3300000>; | |
118 | }; | |
119 | ||
120 | vcc50_hdmi: vcc50-hdmi { | |
121 | compatible = "regulator-fixed"; | |
122 | regulator-name = "vcc50_hdmi"; | |
123 | regulator-always-on; | |
124 | regulator-boot-on; | |
125 | vin-supply = <&vcc_5v>; | |
126 | }; | |
127 | }; | |
128 | ||
129 | &cpu0 { | |
130 | cpu0-supply = <&vdd_cpu>; | |
1ab0c304 HS |
131 | operating-points = < |
132 | /* KHz uV */ | |
133 | 1800000 1400000 | |
134 | 1704000 1350000 | |
135 | 1608000 1300000 | |
136 | 1512000 1250000 | |
137 | 1416000 1200000 | |
138 | 1200000 1100000 | |
139 | 1008000 1050000 | |
140 | 816000 1000000 | |
141 | 696000 950000 | |
142 | 600000 900000 | |
143 | 408000 900000 | |
144 | 216000 900000 | |
145 | 126000 900000 | |
146 | >; | |
e28ea9db AS |
147 | }; |
148 | ||
149 | &emmc { | |
150 | status = "okay"; | |
151 | ||
e28ea9db AS |
152 | bus-width = <8>; |
153 | cap-mmc-highspeed; | |
c41d31f7 | 154 | rockchip,default-sample-phase = <158>; |
e28ea9db | 155 | disable-wp; |
c41d31f7 | 156 | mmc-hs200-1_8v; |
e28ea9db AS |
157 | mmc-pwrseq = <&emmc_pwrseq>; |
158 | non-removable; | |
159 | num-slots = <1>; | |
160 | pinctrl-names = "default"; | |
161 | pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; | |
162 | }; | |
163 | ||
164 | &hdmi { | |
a797451b | 165 | ddc-i2c-bus = <&i2c5>; |
e28ea9db AS |
166 | status = "okay"; |
167 | }; | |
168 | ||
169 | &i2c0 { | |
170 | status = "okay"; | |
171 | ||
172 | clock-frequency = <400000>; | |
173 | i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ | |
174 | i2c-scl-rising-time-ns = <100>; /* 45ns measured */ | |
175 | ||
176 | rk808: pmic@1b { | |
177 | compatible = "rockchip,rk808"; | |
178 | reg = <0x1b>; | |
179 | clock-output-names = "xin32k", "wifibt_32kin"; | |
180 | interrupt-parent = <&gpio0>; | |
181 | interrupts = <4 IRQ_TYPE_LEVEL_LOW>; | |
182 | pinctrl-names = "default"; | |
183 | pinctrl-0 = <&pmic_int_l>; | |
184 | rockchip,system-power-controller; | |
185 | wakeup-source; | |
186 | #clock-cells = <1>; | |
187 | ||
188 | vcc1-supply = <&vcc33_sys>; | |
189 | vcc2-supply = <&vcc33_sys>; | |
190 | vcc3-supply = <&vcc33_sys>; | |
191 | vcc4-supply = <&vcc33_sys>; | |
192 | vcc6-supply = <&vcc_5v>; | |
193 | vcc7-supply = <&vcc33_sys>; | |
194 | vcc8-supply = <&vcc33_sys>; | |
195 | vcc12-supply = <&vcc_18>; | |
196 | vddio-supply = <&vcc33_io>; | |
197 | ||
198 | regulators { | |
199 | vdd_cpu: DCDC_REG1 { | |
200 | regulator-name = "vdd_arm"; | |
201 | regulator-always-on; | |
202 | regulator-boot-on; | |
203 | regulator-min-microvolt = <750000>; | |
204 | regulator-max-microvolt = <1450000>; | |
205 | regulator-ramp-delay = <6001>; | |
206 | regulator-state-mem { | |
207 | regulator-off-in-suspend; | |
208 | }; | |
209 | }; | |
210 | ||
211 | vdd_gpu: DCDC_REG2 { | |
212 | regulator-name = "vdd_gpu"; | |
213 | regulator-always-on; | |
214 | regulator-boot-on; | |
215 | regulator-min-microvolt = <800000>; | |
216 | regulator-max-microvolt = <1250000>; | |
217 | regulator-ramp-delay = <6001>; | |
218 | regulator-state-mem { | |
219 | regulator-on-in-suspend; | |
220 | regulator-suspend-microvolt = <1000000>; | |
221 | }; | |
222 | }; | |
223 | ||
224 | vcc135_ddr: DCDC_REG3 { | |
225 | regulator-name = "vcc135_ddr"; | |
226 | regulator-always-on; | |
227 | regulator-boot-on; | |
228 | regulator-state-mem { | |
229 | regulator-on-in-suspend; | |
230 | }; | |
231 | }; | |
232 | ||
233 | /* | |
234 | * vcc_18 has several aliases. (vcc18_flashio and | |
235 | * vcc18_wl). We'll add those aliases here just to | |
236 | * make it easier to follow the schematic. The signals | |
237 | * are actually hooked together and only separated for | |
238 | * power measurement purposes). | |
239 | */ | |
240 | vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 { | |
241 | regulator-name = "vcc_18"; | |
242 | regulator-always-on; | |
243 | regulator-boot-on; | |
244 | regulator-min-microvolt = <1800000>; | |
245 | regulator-max-microvolt = <1800000>; | |
246 | regulator-state-mem { | |
247 | regulator-on-in-suspend; | |
248 | regulator-suspend-microvolt = <1800000>; | |
249 | }; | |
250 | }; | |
251 | ||
252 | /* | |
253 | * Note that both vcc33_io and vcc33_pmuio are always | |
254 | * powered together. To simplify the logic in the dts | |
255 | * we just refer to vcc33_io every time something is | |
256 | * powered from vcc33_pmuio. In fact, on later boards | |
257 | * (such as danger) they're the same net. | |
258 | */ | |
259 | vcc33_io: LDO_REG1 { | |
260 | regulator-name = "vcc33_io"; | |
261 | regulator-always-on; | |
262 | regulator-boot-on; | |
263 | regulator-min-microvolt = <3300000>; | |
264 | regulator-max-microvolt = <3300000>; | |
265 | regulator-state-mem { | |
266 | regulator-on-in-suspend; | |
267 | regulator-suspend-microvolt = <3300000>; | |
268 | }; | |
269 | }; | |
270 | ||
271 | vdd_10: LDO_REG3 { | |
272 | regulator-name = "vdd_10"; | |
273 | regulator-always-on; | |
274 | regulator-boot-on; | |
275 | regulator-min-microvolt = <1000000>; | |
276 | regulator-max-microvolt = <1000000>; | |
277 | regulator-state-mem { | |
278 | regulator-on-in-suspend; | |
279 | regulator-suspend-microvolt = <1000000>; | |
280 | }; | |
281 | }; | |
282 | ||
283 | vdd10_lcd_pwren_h: LDO_REG7 { | |
284 | regulator-name = "vdd10_lcd_pwren_h"; | |
285 | regulator-always-on; | |
286 | regulator-boot-on; | |
287 | regulator-min-microvolt = <2500000>; | |
288 | regulator-max-microvolt = <2500000>; | |
289 | regulator-state-mem { | |
290 | regulator-off-in-suspend; | |
291 | }; | |
292 | }; | |
293 | ||
294 | vcc33_lcd: SWITCH_REG1 { | |
295 | regulator-name = "vcc33_lcd"; | |
296 | regulator-always-on; | |
297 | regulator-boot-on; | |
298 | regulator-state-mem { | |
299 | regulator-off-in-suspend; | |
300 | }; | |
301 | }; | |
302 | }; | |
303 | }; | |
304 | }; | |
305 | ||
306 | &i2c1 { | |
307 | status = "okay"; | |
308 | ||
309 | clock-frequency = <400000>; | |
310 | i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ | |
311 | i2c-scl-rising-time-ns = <100>; /* 40ns measured */ | |
312 | ||
313 | tpm: tpm@20 { | |
314 | compatible = "infineon,slb9645tt"; | |
315 | reg = <0x20>; | |
316 | powered-while-suspended; | |
317 | }; | |
318 | }; | |
319 | ||
320 | &i2c2 { | |
321 | status = "okay"; | |
322 | ||
323 | /* 100kHz since 4.7k resistors don't rise fast enough */ | |
324 | clock-frequency = <100000>; | |
325 | i2c-scl-falling-time-ns = <50>; /* 10ns measured */ | |
326 | i2c-scl-rising-time-ns = <800>; /* 600ns measured */ | |
327 | }; | |
328 | ||
329 | &i2c4 { | |
330 | status = "okay"; | |
331 | ||
332 | clock-frequency = <400000>; | |
333 | i2c-scl-falling-time-ns = <50>; /* 11ns measured */ | |
334 | i2c-scl-rising-time-ns = <300>; /* 225ns measured */ | |
335 | }; | |
336 | ||
337 | &i2c5 { | |
338 | status = "okay"; | |
339 | ||
340 | clock-frequency = <100000>; | |
341 | i2c-scl-falling-time-ns = <300>; | |
342 | i2c-scl-rising-time-ns = <1000>; | |
343 | }; | |
344 | ||
3445b2fa HS |
345 | &io_domains { |
346 | status = "okay"; | |
347 | ||
348 | bb-supply = <&vcc33_io>; | |
349 | dvp-supply = <&vcc_18>; | |
350 | flash0-supply = <&vcc18_flashio>; | |
351 | gpio1830-supply = <&vcc33_io>; | |
352 | gpio30-supply = <&vcc33_io>; | |
353 | lcdc-supply = <&vcc33_lcd>; | |
354 | wifi-supply = <&vcc18_wl>; | |
355 | }; | |
356 | ||
e28ea9db AS |
357 | &pwm1 { |
358 | status = "okay"; | |
359 | }; | |
360 | ||
361 | &sdio0 { | |
362 | status = "okay"; | |
363 | ||
e28ea9db AS |
364 | bus-width = <4>; |
365 | cap-sd-highspeed; | |
366 | cap-sdio-irq; | |
367 | keep-power-in-suspend; | |
368 | mmc-pwrseq = <&sdio_pwrseq>; | |
369 | non-removable; | |
370 | num-slots = <1>; | |
371 | pinctrl-names = "default"; | |
372 | pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; | |
c41d31f7 HS |
373 | sd-uhs-sdr12; |
374 | sd-uhs-sdr25; | |
375 | sd-uhs-sdr50; | |
376 | sd-uhs-sdr104; | |
e28ea9db AS |
377 | vmmc-supply = <&vcc33_sys>; |
378 | vqmmc-supply = <&vcc18_wl>; | |
379 | }; | |
380 | ||
381 | &spi2 { | |
382 | status = "okay"; | |
383 | ||
384 | rx-sample-delay-ns = <12>; | |
9a205e33 BN |
385 | |
386 | flash@0 { | |
387 | compatible = "jedec,spi-nor"; | |
388 | spi-max-frequency = <50000000>; | |
389 | reg = <0>; | |
390 | }; | |
e28ea9db AS |
391 | }; |
392 | ||
393 | &tsadc { | |
394 | status = "okay"; | |
395 | ||
117ccc11 RP |
396 | rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ |
397 | rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ | |
e28ea9db AS |
398 | }; |
399 | ||
400 | &uart0 { | |
401 | status = "okay"; | |
402 | ||
403 | /* We need to go faster than 24MHz, so adjust clock parents / rates */ | |
404 | assigned-clocks = <&cru SCLK_UART0>; | |
405 | assigned-clock-rates = <48000000>; | |
406 | ||
407 | /* Pins don't include flow control by default; add that in */ | |
408 | pinctrl-names = "default"; | |
409 | pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; | |
410 | }; | |
411 | ||
412 | &uart1 { | |
413 | status = "okay"; | |
414 | }; | |
415 | ||
416 | &uart2 { | |
417 | status = "okay"; | |
418 | }; | |
419 | ||
420 | &usbphy { | |
421 | status = "okay"; | |
422 | }; | |
423 | ||
424 | &usb_host0_ehci { | |
425 | status = "okay"; | |
426 | ||
427 | needs-reset-on-resume; | |
428 | }; | |
429 | ||
430 | &usb_host1 { | |
431 | status = "okay"; | |
432 | }; | |
433 | ||
434 | &usb_otg { | |
435 | status = "okay"; | |
436 | ||
437 | assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; | |
219a5859 | 438 | assigned-clock-parents = <&usbphy0>; |
e28ea9db AS |
439 | dr_mode = "host"; |
440 | }; | |
441 | ||
442 | &vopb { | |
443 | status = "okay"; | |
444 | }; | |
445 | ||
446 | &vopb_mmu { | |
447 | status = "okay"; | |
448 | }; | |
449 | ||
450 | &wdt { | |
451 | status = "okay"; | |
452 | }; | |
453 | ||
454 | &pinctrl { | |
455 | pinctrl-names = "default", "sleep"; | |
456 | pinctrl-0 = < | |
457 | /* Common for sleep and wake, but no owners */ | |
458 | &global_pwroff | |
459 | >; | |
460 | pinctrl-1 = < | |
461 | /* Common for sleep and wake, but no owners */ | |
462 | &global_pwroff | |
463 | >; | |
464 | ||
465 | pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { | |
466 | bias-disable; | |
467 | drive-strength = <8>; | |
468 | }; | |
469 | ||
470 | pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { | |
471 | bias-pull-up; | |
472 | drive-strength = <8>; | |
473 | }; | |
474 | ||
475 | pcfg_output_high: pcfg-output-high { | |
476 | output-high; | |
477 | }; | |
478 | ||
479 | pcfg_output_low: pcfg-output-low { | |
480 | output-low; | |
481 | }; | |
482 | ||
483 | buttons { | |
484 | pwr_key_l: pwr-key-l { | |
485 | rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; | |
486 | }; | |
487 | }; | |
488 | ||
489 | emmc { | |
490 | emmc_reset: emmc-reset { | |
491 | rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; | |
492 | }; | |
493 | ||
494 | /* | |
495 | * We run eMMC at max speed; bump up drive strength. | |
496 | * We also have external pulls, so disable the internal ones. | |
497 | */ | |
498 | emmc_clk: emmc-clk { | |
499 | rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; | |
500 | }; | |
501 | ||
502 | emmc_cmd: emmc-cmd { | |
503 | rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; | |
504 | }; | |
505 | ||
506 | emmc_bus8: emmc-bus8 { | |
507 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, | |
508 | <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, | |
509 | <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, | |
510 | <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, | |
511 | <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, | |
512 | <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, | |
513 | <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, | |
514 | <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; | |
515 | }; | |
516 | }; | |
517 | ||
518 | pmic { | |
519 | pmic_int_l: pmic-int-l { | |
520 | rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; | |
521 | }; | |
522 | }; | |
523 | ||
524 | reboot { | |
525 | ap_warm_reset_h: ap-warm-reset-h { | |
526 | rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>; | |
527 | }; | |
528 | }; | |
529 | ||
530 | recovery-switch { | |
531 | rec_mode_l: rec-mode-l { | |
532 | rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; | |
533 | }; | |
534 | }; | |
535 | ||
536 | sdio0 { | |
537 | wifi_enable_h: wifienable-h { | |
538 | rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; | |
539 | }; | |
540 | ||
541 | /* NOTE: mislabelled on schematic; should be bt_enable_h */ | |
542 | bt_enable_l: bt-enable-l { | |
543 | rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>; | |
544 | }; | |
545 | ||
546 | /* | |
547 | * We run sdio0 at max speed; bump up drive strength. | |
548 | * We also have external pulls, so disable the internal ones. | |
549 | */ | |
550 | sdio0_bus4: sdio0-bus4 { | |
551 | rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, | |
552 | <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, | |
553 | <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, | |
554 | <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; | |
555 | }; | |
556 | ||
557 | sdio0_cmd: sdio0-cmd { | |
558 | rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; | |
559 | }; | |
560 | ||
561 | sdio0_clk: sdio0-clk { | |
562 | rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; | |
563 | }; | |
564 | }; | |
565 | ||
566 | tpm { | |
567 | tpm_int_h: tpm-int-h { | |
568 | rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; | |
569 | }; | |
570 | }; | |
571 | ||
e28ea9db AS |
572 | write-protect { |
573 | fw_wp_ap: fw-wp-ap { | |
574 | rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>; | |
575 | }; | |
576 | }; | |
577 | }; |