Commit | Line | Data |
---|---|---|
2ab557b7 | 1 | /* |
b1772506 HS |
2 | * This file is dual-licensed: you can use it either under the terms |
3 | * of the GPL or the X11 license, at your option. Note that this dual | |
4 | * licensing only applies to this file, and not this project as a | |
5 | * whole. | |
2ab557b7 | 6 | * |
b1772506 HS |
7 | * a) This file is free software; you can redistribute it and/or |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of the | |
10 | * License, or (at your option) any later version. | |
11 | * | |
12 | * This file is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * Or, alternatively, | |
18 | * | |
19 | * b) Permission is hereby granted, free of charge, to any person | |
20 | * obtaining a copy of this software and associated documentation | |
21 | * files (the "Software"), to deal in the Software without | |
22 | * restriction, including without limitation the rights to use, | |
23 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
24 | * sell copies of the Software, and to permit persons to whom the | |
25 | * Software is furnished to do so, subject to the following | |
26 | * conditions: | |
27 | * | |
28 | * The above copyright notice and this permission notice shall be | |
29 | * included in all copies or substantial portions of the Software. | |
30 | * | |
31 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
32 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
33 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
34 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
35 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
36 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
37 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
38 | * OTHER DEALINGS IN THE SOFTWARE. | |
2ab557b7 HS |
39 | */ |
40 | ||
41 | #include <dt-bindings/gpio/gpio.h> | |
42 | #include <dt-bindings/interrupt-controller/irq.h> | |
43 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
44 | #include <dt-bindings/pinctrl/rockchip.h> | |
45 | #include <dt-bindings/clock/rk3288-cru.h> | |
b67d6bc3 | 46 | #include <dt-bindings/thermal/thermal.h> |
b63af764 | 47 | #include <dt-bindings/power/rk3288-power.h> |
2ab557b7 HS |
48 | #include "skeleton.dtsi" |
49 | ||
50 | / { | |
51 | compatible = "rockchip,rk3288"; | |
52 | ||
53 | interrupt-parent = <&gic>; | |
54 | ||
55 | aliases { | |
85ef8d61 | 56 | ethernet0 = &gmac; |
2ab557b7 HS |
57 | i2c0 = &i2c0; |
58 | i2c1 = &i2c1; | |
59 | i2c2 = &i2c2; | |
60 | i2c3 = &i2c3; | |
61 | i2c4 = &i2c4; | |
62 | i2c5 = &i2c5; | |
d7f9a388 DA |
63 | mshc0 = &emmc; |
64 | mshc1 = &sdmmc; | |
65 | mshc2 = &sdio0; | |
66 | mshc3 = &sdio1; | |
2ab557b7 HS |
67 | serial0 = &uart0; |
68 | serial1 = &uart1; | |
69 | serial2 = &uart2; | |
70 | serial3 = &uart3; | |
71 | serial4 = &uart4; | |
1f53170b | 72 | spi0 = &spi0; |
73 | spi1 = &spi1; | |
74 | spi2 = &spi2; | |
2ab557b7 HS |
75 | }; |
76 | ||
f1840780 SR |
77 | arm-pmu { |
78 | compatible = "arm,cortex-a12-pmu"; | |
79 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, | |
80 | <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, | |
81 | <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, | |
82 | <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
4863dcd3 | 83 | interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
f1840780 SR |
84 | }; |
85 | ||
2ab557b7 HS |
86 | cpus { |
87 | #address-cells = <1>; | |
88 | #size-cells = <0>; | |
08bcc754 | 89 | enable-method = "rockchip,rk3066-smp"; |
fbdbc732 | 90 | rockchip,pmu = <&pmu>; |
2ab557b7 | 91 | |
be8a77c5 | 92 | cpu0: cpu@500 { |
2ab557b7 HS |
93 | device_type = "cpu"; |
94 | compatible = "arm,cortex-a12"; | |
95 | reg = <0x500>; | |
044542af | 96 | resets = <&cru SRST_CORE0>; |
be8a77c5 HS |
97 | operating-points = < |
98 | /* KHz uV */ | |
99 | 1608000 1350000 | |
100 | 1512000 1300000 | |
101 | 1416000 1200000 | |
102 | 1200000 1100000 | |
103 | 1008000 1050000 | |
104 | 816000 1000000 | |
105 | 696000 950000 | |
106 | 600000 900000 | |
107 | 408000 900000 | |
108 | 312000 900000 | |
109 | 216000 900000 | |
110 | 126000 900000 | |
111 | >; | |
b67d6bc3 | 112 | #cooling-cells = <2>; /* min followed by max */ |
be8a77c5 HS |
113 | clock-latency = <40000>; |
114 | clocks = <&cru ARMCLK>; | |
2ab557b7 | 115 | }; |
4863dcd3 | 116 | cpu1: cpu@501 { |
2ab557b7 HS |
117 | device_type = "cpu"; |
118 | compatible = "arm,cortex-a12"; | |
119 | reg = <0x501>; | |
044542af | 120 | resets = <&cru SRST_CORE1>; |
2ab557b7 | 121 | }; |
4863dcd3 | 122 | cpu2: cpu@502 { |
2ab557b7 HS |
123 | device_type = "cpu"; |
124 | compatible = "arm,cortex-a12"; | |
125 | reg = <0x502>; | |
044542af | 126 | resets = <&cru SRST_CORE2>; |
2ab557b7 | 127 | }; |
4863dcd3 | 128 | cpu3: cpu@503 { |
2ab557b7 HS |
129 | device_type = "cpu"; |
130 | compatible = "arm,cortex-a12"; | |
131 | reg = <0x503>; | |
044542af | 132 | resets = <&cru SRST_CORE3>; |
2ab557b7 HS |
133 | }; |
134 | }; | |
135 | ||
982891c3 | 136 | amba { |
2ef7d5f3 | 137 | compatible = "simple-bus"; |
982891c3 HS |
138 | #address-cells = <1>; |
139 | #size-cells = <1>; | |
140 | ranges; | |
141 | ||
142 | dmac_peri: dma-controller@ff250000 { | |
143 | compatible = "arm,pl330", "arm,primecell"; | |
144 | reg = <0xff250000 0x4000>; | |
145 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
146 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
147 | #dma-cells = <1>; | |
e7d6c9b1 | 148 | arm,pl330-broken-no-flushp; |
982891c3 HS |
149 | clocks = <&cru ACLK_DMAC2>; |
150 | clock-names = "apb_pclk"; | |
151 | }; | |
152 | ||
153 | dmac_bus_ns: dma-controller@ff600000 { | |
154 | compatible = "arm,pl330", "arm,primecell"; | |
155 | reg = <0xff600000 0x4000>; | |
156 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
157 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
158 | #dma-cells = <1>; | |
e7d6c9b1 | 159 | arm,pl330-broken-no-flushp; |
982891c3 HS |
160 | clocks = <&cru ACLK_DMAC1>; |
161 | clock-names = "apb_pclk"; | |
162 | status = "disabled"; | |
163 | }; | |
164 | ||
165 | dmac_bus_s: dma-controller@ffb20000 { | |
166 | compatible = "arm,pl330", "arm,primecell"; | |
167 | reg = <0xffb20000 0x4000>; | |
168 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
169 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
170 | #dma-cells = <1>; | |
e7d6c9b1 | 171 | arm,pl330-broken-no-flushp; |
982891c3 HS |
172 | clocks = <&cru ACLK_DMAC1>; |
173 | clock-names = "apb_pclk"; | |
174 | }; | |
175 | }; | |
176 | ||
b21bcfc9 HS |
177 | reserved-memory { |
178 | #address-cells = <1>; | |
179 | #size-cells = <1>; | |
180 | ranges; | |
181 | ||
182 | /* | |
183 | * The rk3288 cannot use the memory area above 0xfe000000 | |
184 | * for dma operations for some reason. While there is | |
185 | * probably a better solution available somewhere, we | |
186 | * haven't found it yet and while devices with 2GB of ram | |
187 | * are not affected, this issue prevents 4GB from booting. | |
188 | * So to make these devices at least bootable, block | |
189 | * this area for the time being until the real solution | |
190 | * is found. | |
191 | */ | |
192 | dma-unusable@fe000000 { | |
193 | reg = <0xfe000000 0x1000000>; | |
194 | }; | |
195 | }; | |
196 | ||
2ab557b7 HS |
197 | xin24m: oscillator { |
198 | compatible = "fixed-clock"; | |
199 | clock-frequency = <24000000>; | |
200 | clock-output-names = "xin24m"; | |
201 | #clock-cells = <0>; | |
202 | }; | |
203 | ||
204 | timer { | |
205 | compatible = "arm,armv7-timer"; | |
e2405a59 | 206 | arm,cpu-registers-not-fw-configured; |
2ab557b7 HS |
207 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
208 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
209 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
210 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
211 | clock-frequency = <24000000>; | |
212 | }; | |
213 | ||
e48cc181 DL |
214 | timer: timer@ff810000 { |
215 | compatible = "rockchip,rk3288-timer"; | |
216 | reg = <0xff810000 0x20>; | |
217 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
218 | clocks = <&xin24m>, <&cru PCLK_TIMER>; | |
219 | clock-names = "timer", "pclk"; | |
220 | }; | |
221 | ||
a29cb8c4 DK |
222 | display-subsystem { |
223 | compatible = "rockchip,display-subsystem"; | |
224 | ports = <&vopl_out>, <&vopb_out>; | |
225 | }; | |
226 | ||
85095bf3 DA |
227 | sdmmc: dwmmc@ff0c0000 { |
228 | compatible = "rockchip,rk3288-dw-mshc"; | |
f74ba117 | 229 | clock-freq-min-max = <400000 150000000>; |
f71ddc58 AS |
230 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, |
231 | <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; | |
232 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
85095bf3 DA |
233 | fifo-depth = <0x100>; |
234 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
235 | reg = <0xff0c0000 0x4000>; | |
236 | status = "disabled"; | |
237 | }; | |
238 | ||
f1a07231 AK |
239 | sdio0: dwmmc@ff0d0000 { |
240 | compatible = "rockchip,rk3288-dw-mshc"; | |
f74ba117 | 241 | clock-freq-min-max = <400000 150000000>; |
f71ddc58 AS |
242 | clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, |
243 | <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; | |
244 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
f1a07231 AK |
245 | fifo-depth = <0x100>; |
246 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
247 | reg = <0xff0d0000 0x4000>; | |
248 | status = "disabled"; | |
249 | }; | |
250 | ||
251 | sdio1: dwmmc@ff0e0000 { | |
252 | compatible = "rockchip,rk3288-dw-mshc"; | |
f74ba117 | 253 | clock-freq-min-max = <400000 150000000>; |
f71ddc58 AS |
254 | clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, |
255 | <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; | |
256 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
f1a07231 AK |
257 | fifo-depth = <0x100>; |
258 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
259 | reg = <0xff0e0000 0x4000>; | |
260 | status = "disabled"; | |
261 | }; | |
262 | ||
85095bf3 DA |
263 | emmc: dwmmc@ff0f0000 { |
264 | compatible = "rockchip,rk3288-dw-mshc"; | |
f74ba117 | 265 | clock-freq-min-max = <400000 150000000>; |
f71ddc58 AS |
266 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, |
267 | <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; | |
268 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
85095bf3 DA |
269 | fifo-depth = <0x100>; |
270 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
271 | reg = <0xff0f0000 0x4000>; | |
272 | status = "disabled"; | |
273 | }; | |
274 | ||
f23a6179 HS |
275 | saradc: saradc@ff100000 { |
276 | compatible = "rockchip,saradc"; | |
277 | reg = <0xff100000 0x100>; | |
278 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
279 | #io-channel-cells = <1>; | |
280 | clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; | |
281 | clock-names = "saradc", "apb_pclk"; | |
282 | status = "disabled"; | |
283 | }; | |
284 | ||
1f53170b | 285 | spi0: spi@ff110000 { |
286 | compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; | |
287 | clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; | |
288 | clock-names = "spiclk", "apb_pclk"; | |
11bd57b8 DA |
289 | dmas = <&dmac_peri 11>, <&dmac_peri 12>; |
290 | dma-names = "tx", "rx"; | |
1f53170b | 291 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
292 | pinctrl-names = "default"; | |
293 | pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; | |
294 | reg = <0xff110000 0x1000>; | |
295 | #address-cells = <1>; | |
296 | #size-cells = <0>; | |
297 | status = "disabled"; | |
298 | }; | |
299 | ||
300 | spi1: spi@ff120000 { | |
301 | compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; | |
302 | clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; | |
303 | clock-names = "spiclk", "apb_pclk"; | |
11bd57b8 DA |
304 | dmas = <&dmac_peri 13>, <&dmac_peri 14>; |
305 | dma-names = "tx", "rx"; | |
1f53170b | 306 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
307 | pinctrl-names = "default"; | |
308 | pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; | |
309 | reg = <0xff120000 0x1000>; | |
310 | #address-cells = <1>; | |
311 | #size-cells = <0>; | |
312 | status = "disabled"; | |
313 | }; | |
314 | ||
315 | spi2: spi@ff130000 { | |
316 | compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; | |
317 | clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; | |
318 | clock-names = "spiclk", "apb_pclk"; | |
11bd57b8 DA |
319 | dmas = <&dmac_peri 15>, <&dmac_peri 16>; |
320 | dma-names = "tx", "rx"; | |
1f53170b | 321 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
322 | pinctrl-names = "default"; | |
323 | pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; | |
324 | reg = <0xff130000 0x1000>; | |
325 | #address-cells = <1>; | |
326 | #size-cells = <0>; | |
327 | status = "disabled"; | |
328 | }; | |
329 | ||
2ab557b7 HS |
330 | i2c1: i2c@ff140000 { |
331 | compatible = "rockchip,rk3288-i2c"; | |
332 | reg = <0xff140000 0x1000>; | |
333 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
334 | #address-cells = <1>; | |
335 | #size-cells = <0>; | |
336 | clock-names = "i2c"; | |
337 | clocks = <&cru PCLK_I2C1>; | |
338 | pinctrl-names = "default"; | |
339 | pinctrl-0 = <&i2c1_xfer>; | |
340 | status = "disabled"; | |
341 | }; | |
342 | ||
343 | i2c3: i2c@ff150000 { | |
344 | compatible = "rockchip,rk3288-i2c"; | |
345 | reg = <0xff150000 0x1000>; | |
346 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
347 | #address-cells = <1>; | |
348 | #size-cells = <0>; | |
349 | clock-names = "i2c"; | |
350 | clocks = <&cru PCLK_I2C3>; | |
351 | pinctrl-names = "default"; | |
352 | pinctrl-0 = <&i2c3_xfer>; | |
353 | status = "disabled"; | |
354 | }; | |
355 | ||
356 | i2c4: i2c@ff160000 { | |
357 | compatible = "rockchip,rk3288-i2c"; | |
358 | reg = <0xff160000 0x1000>; | |
359 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; | |
360 | #address-cells = <1>; | |
361 | #size-cells = <0>; | |
362 | clock-names = "i2c"; | |
363 | clocks = <&cru PCLK_I2C4>; | |
364 | pinctrl-names = "default"; | |
365 | pinctrl-0 = <&i2c4_xfer>; | |
366 | status = "disabled"; | |
367 | }; | |
368 | ||
369 | i2c5: i2c@ff170000 { | |
370 | compatible = "rockchip,rk3288-i2c"; | |
371 | reg = <0xff170000 0x1000>; | |
372 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
373 | #address-cells = <1>; | |
374 | #size-cells = <0>; | |
375 | clock-names = "i2c"; | |
376 | clocks = <&cru PCLK_I2C5>; | |
377 | pinctrl-names = "default"; | |
378 | pinctrl-0 = <&i2c5_xfer>; | |
379 | status = "disabled"; | |
380 | }; | |
381 | ||
382 | uart0: serial@ff180000 { | |
383 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
384 | reg = <0xff180000 0x100>; | |
385 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
386 | reg-shift = <2>; | |
387 | reg-io-width = <4>; | |
388 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
389 | clock-names = "baudclk", "apb_pclk"; | |
390 | pinctrl-names = "default"; | |
391 | pinctrl-0 = <&uart0_xfer>; | |
392 | status = "disabled"; | |
393 | }; | |
394 | ||
395 | uart1: serial@ff190000 { | |
396 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
397 | reg = <0xff190000 0x100>; | |
398 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
399 | reg-shift = <2>; | |
400 | reg-io-width = <4>; | |
401 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
402 | clock-names = "baudclk", "apb_pclk"; | |
403 | pinctrl-names = "default"; | |
404 | pinctrl-0 = <&uart1_xfer>; | |
405 | status = "disabled"; | |
406 | }; | |
407 | ||
408 | uart2: serial@ff690000 { | |
409 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
410 | reg = <0xff690000 0x100>; | |
411 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
412 | reg-shift = <2>; | |
413 | reg-io-width = <4>; | |
414 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
415 | clock-names = "baudclk", "apb_pclk"; | |
416 | pinctrl-names = "default"; | |
417 | pinctrl-0 = <&uart2_xfer>; | |
418 | status = "disabled"; | |
419 | }; | |
420 | ||
421 | uart3: serial@ff1b0000 { | |
422 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
423 | reg = <0xff1b0000 0x100>; | |
424 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; | |
425 | reg-shift = <2>; | |
426 | reg-io-width = <4>; | |
427 | clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; | |
428 | clock-names = "baudclk", "apb_pclk"; | |
429 | pinctrl-names = "default"; | |
430 | pinctrl-0 = <&uart3_xfer>; | |
431 | status = "disabled"; | |
432 | }; | |
433 | ||
434 | uart4: serial@ff1c0000 { | |
435 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
436 | reg = <0xff1c0000 0x100>; | |
437 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | |
438 | reg-shift = <2>; | |
439 | reg-io-width = <4>; | |
440 | clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; | |
441 | clock-names = "baudclk", "apb_pclk"; | |
442 | pinctrl-names = "default"; | |
443 | pinctrl-0 = <&uart4_xfer>; | |
444 | status = "disabled"; | |
445 | }; | |
446 | ||
b67d6bc3 | 447 | thermal-zones { |
f87305fa CW |
448 | reserve_thermal: reserve_thermal { |
449 | polling-delay-passive = <1000>; /* milliseconds */ | |
450 | polling-delay = <5000>; /* milliseconds */ | |
451 | ||
452 | thermal-sensors = <&tsadc 0>; | |
453 | }; | |
454 | ||
455 | cpu_thermal: cpu_thermal { | |
456 | polling-delay-passive = <100>; /* milliseconds */ | |
457 | polling-delay = <5000>; /* milliseconds */ | |
458 | ||
459 | thermal-sensors = <&tsadc 1>; | |
460 | ||
461 | trips { | |
462 | cpu_alert0: cpu_alert0 { | |
463 | temperature = <70000>; /* millicelsius */ | |
464 | hysteresis = <2000>; /* millicelsius */ | |
465 | type = "passive"; | |
466 | }; | |
467 | cpu_alert1: cpu_alert1 { | |
468 | temperature = <75000>; /* millicelsius */ | |
469 | hysteresis = <2000>; /* millicelsius */ | |
470 | type = "passive"; | |
471 | }; | |
472 | cpu_crit: cpu_crit { | |
473 | temperature = <90000>; /* millicelsius */ | |
474 | hysteresis = <2000>; /* millicelsius */ | |
475 | type = "critical"; | |
476 | }; | |
477 | }; | |
478 | ||
479 | cooling-maps { | |
480 | map0 { | |
481 | trip = <&cpu_alert0>; | |
482 | cooling-device = | |
483 | <&cpu0 THERMAL_NO_LIMIT 6>; | |
484 | }; | |
485 | map1 { | |
486 | trip = <&cpu_alert1>; | |
487 | cooling-device = | |
488 | <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
489 | }; | |
490 | }; | |
491 | }; | |
492 | ||
493 | gpu_thermal: gpu_thermal { | |
494 | polling-delay-passive = <100>; /* milliseconds */ | |
495 | polling-delay = <5000>; /* milliseconds */ | |
496 | ||
497 | thermal-sensors = <&tsadc 2>; | |
498 | ||
499 | trips { | |
500 | gpu_alert0: gpu_alert0 { | |
501 | temperature = <70000>; /* millicelsius */ | |
502 | hysteresis = <2000>; /* millicelsius */ | |
503 | type = "passive"; | |
504 | }; | |
505 | gpu_crit: gpu_crit { | |
506 | temperature = <90000>; /* millicelsius */ | |
507 | hysteresis = <2000>; /* millicelsius */ | |
508 | type = "critical"; | |
509 | }; | |
510 | }; | |
511 | ||
512 | cooling-maps { | |
513 | map0 { | |
514 | trip = <&gpu_alert0>; | |
515 | cooling-device = | |
516 | <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
517 | }; | |
518 | }; | |
519 | }; | |
b67d6bc3 CW |
520 | }; |
521 | ||
522 | tsadc: tsadc@ff280000 { | |
523 | compatible = "rockchip,rk3288-tsadc"; | |
524 | reg = <0xff280000 0x100>; | |
525 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
526 | clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; | |
527 | clock-names = "tsadc", "apb_pclk"; | |
528 | resets = <&cru SRST_TSADC>; | |
529 | reset-names = "tsadc-apb"; | |
784359b8 CW |
530 | pinctrl-names = "init", "default", "sleep"; |
531 | pinctrl-0 = <&otp_gpio>; | |
532 | pinctrl-1 = <&otp_out>; | |
533 | pinctrl-2 = <&otp_gpio>; | |
b67d6bc3 CW |
534 | #thermal-sensor-cells = <1>; |
535 | rockchip,hw-tshut-temp = <95000>; | |
536 | status = "disabled"; | |
537 | }; | |
538 | ||
3d3fb74a RC |
539 | gmac: ethernet@ff290000 { |
540 | compatible = "rockchip,rk3288-gmac"; | |
541 | reg = <0xff290000 0x10000>; | |
542 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
543 | interrupt-names = "macirq"; | |
544 | rockchip,grf = <&grf>; | |
545 | clocks = <&cru SCLK_MAC>, | |
546 | <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, | |
547 | <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, | |
548 | <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; | |
549 | clock-names = "stmmaceth", | |
550 | "mac_clk_rx", "mac_clk_tx", | |
551 | "clk_mac_ref", "clk_mac_refout", | |
552 | "aclk_mac", "pclk_mac"; | |
e6b54649 RP |
553 | resets = <&cru SRST_MAC>; |
554 | reset-names = "stmmaceth"; | |
54b0bc60 | 555 | status = "disabled"; |
3d3fb74a RC |
556 | }; |
557 | ||
c9c32c50 DA |
558 | usb_host0_ehci: usb@ff500000 { |
559 | compatible = "generic-ehci"; | |
560 | reg = <0xff500000 0x100>; | |
561 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
562 | clocks = <&cru HCLK_USBHOST0>; | |
563 | clock-names = "usbhost"; | |
f6db7029 YL |
564 | phys = <&usbphy1>; |
565 | phy-names = "usb"; | |
c9c32c50 DA |
566 | status = "disabled"; |
567 | }; | |
568 | ||
569 | /* NOTE: ohci@ff520000 doesn't actually work on hardware */ | |
570 | ||
12dd3653 KY |
571 | usb_host1: usb@ff540000 { |
572 | compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", | |
573 | "snps,dwc2"; | |
574 | reg = <0xff540000 0x40000>; | |
575 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
576 | clocks = <&cru HCLK_USBHOST1>; | |
577 | clock-names = "otg"; | |
cabd2ea2 | 578 | dr_mode = "host"; |
f6db7029 YL |
579 | phys = <&usbphy2>; |
580 | phy-names = "usb2-phy"; | |
12dd3653 KY |
581 | status = "disabled"; |
582 | }; | |
583 | ||
584 | usb_otg: usb@ff580000 { | |
585 | compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", | |
586 | "snps,dwc2"; | |
587 | reg = <0xff580000 0x40000>; | |
588 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
589 | clocks = <&cru HCLK_OTG0>; | |
590 | clock-names = "otg"; | |
cabd2ea2 YL |
591 | dr_mode = "otg"; |
592 | g-np-tx-fifo-size = <16>; | |
593 | g-rx-fifo-size = <275>; | |
594 | g-tx-fifo-size = <256 128 128 64 64 32>; | |
595 | g-use-dma; | |
f6db7029 YL |
596 | phys = <&usbphy0>; |
597 | phy-names = "usb2-phy"; | |
12dd3653 KY |
598 | status = "disabled"; |
599 | }; | |
600 | ||
c9c32c50 DA |
601 | usb_hsic: usb@ff5c0000 { |
602 | compatible = "generic-ehci"; | |
603 | reg = <0xff5c0000 0x100>; | |
604 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
605 | clocks = <&cru HCLK_HSIC>; | |
606 | clock-names = "usbhost"; | |
607 | status = "disabled"; | |
608 | }; | |
609 | ||
2ab557b7 HS |
610 | i2c0: i2c@ff650000 { |
611 | compatible = "rockchip,rk3288-i2c"; | |
612 | reg = <0xff650000 0x1000>; | |
613 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
614 | #address-cells = <1>; | |
615 | #size-cells = <0>; | |
616 | clock-names = "i2c"; | |
617 | clocks = <&cru PCLK_I2C0>; | |
618 | pinctrl-names = "default"; | |
619 | pinctrl-0 = <&i2c0_xfer>; | |
620 | status = "disabled"; | |
621 | }; | |
622 | ||
623 | i2c2: i2c@ff660000 { | |
624 | compatible = "rockchip,rk3288-i2c"; | |
625 | reg = <0xff660000 0x1000>; | |
626 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
627 | #address-cells = <1>; | |
628 | #size-cells = <0>; | |
629 | clock-names = "i2c"; | |
630 | clocks = <&cru PCLK_I2C2>; | |
631 | pinctrl-names = "default"; | |
632 | pinctrl-0 = <&i2c2_xfer>; | |
633 | status = "disabled"; | |
634 | }; | |
635 | ||
df542df3 DA |
636 | pwm0: pwm@ff680000 { |
637 | compatible = "rockchip,rk3288-pwm"; | |
638 | reg = <0xff680000 0x10>; | |
639 | #pwm-cells = <3>; | |
640 | pinctrl-names = "default"; | |
641 | pinctrl-0 = <&pwm0_pin>; | |
642 | clocks = <&cru PCLK_PWM>; | |
643 | clock-names = "pwm"; | |
644 | status = "disabled"; | |
645 | }; | |
646 | ||
647 | pwm1: pwm@ff680010 { | |
648 | compatible = "rockchip,rk3288-pwm"; | |
649 | reg = <0xff680010 0x10>; | |
650 | #pwm-cells = <3>; | |
651 | pinctrl-names = "default"; | |
652 | pinctrl-0 = <&pwm1_pin>; | |
653 | clocks = <&cru PCLK_PWM>; | |
654 | clock-names = "pwm"; | |
655 | status = "disabled"; | |
656 | }; | |
657 | ||
658 | pwm2: pwm@ff680020 { | |
659 | compatible = "rockchip,rk3288-pwm"; | |
660 | reg = <0xff680020 0x10>; | |
661 | #pwm-cells = <3>; | |
662 | pinctrl-names = "default"; | |
663 | pinctrl-0 = <&pwm2_pin>; | |
664 | clocks = <&cru PCLK_PWM>; | |
665 | clock-names = "pwm"; | |
666 | status = "disabled"; | |
667 | }; | |
668 | ||
669 | pwm3: pwm@ff680030 { | |
670 | compatible = "rockchip,rk3288-pwm"; | |
671 | reg = <0xff680030 0x10>; | |
672 | #pwm-cells = <2>; | |
673 | pinctrl-names = "default"; | |
674 | pinctrl-0 = <&pwm3_pin>; | |
675 | clocks = <&cru PCLK_PWM>; | |
676 | clock-names = "pwm"; | |
677 | status = "disabled"; | |
678 | }; | |
679 | ||
1123d412 KY |
680 | bus_intmem@ff700000 { |
681 | compatible = "mmio-sram"; | |
682 | reg = <0xff700000 0x18000>; | |
683 | #address-cells = <1>; | |
684 | #size-cells = <1>; | |
685 | ranges = <0 0xff700000 0x18000>; | |
686 | smp-sram@0 { | |
687 | compatible = "rockchip,rk3066-smp-sram"; | |
688 | reg = <0x00 0x10>; | |
689 | }; | |
690 | }; | |
691 | ||
eecfe981 CZ |
692 | sram@ff720000 { |
693 | compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; | |
694 | reg = <0xff720000 0x1000>; | |
695 | }; | |
696 | ||
2ab557b7 | 697 | pmu: power-management@ff730000 { |
b63af764 | 698 | compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; |
2ab557b7 | 699 | reg = <0xff730000 0x100>; |
b63af764 CW |
700 | |
701 | power: power-controller { | |
702 | compatible = "rockchip,rk3288-power-controller"; | |
703 | #power-domain-cells = <1>; | |
704 | #address-cells = <1>; | |
705 | #size-cells = <0>; | |
706 | ||
df5ea015 SS |
707 | assigned-clocks = <&cru SCLK_EDP_24M>; |
708 | assigned-clock-parents = <&xin24m>; | |
709 | ||
b63af764 CW |
710 | /* |
711 | * Note: Although SCLK_* are the working clocks | |
712 | * of device without including on the NOC, needed for | |
713 | * synchronous reset. | |
714 | * | |
715 | * The clocks on the which NOC: | |
716 | * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. | |
717 | * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. | |
718 | * ACLK_RGA is on ACLK_RGA_NIU. | |
719 | * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. | |
720 | * | |
721 | * Which clock are device clocks: | |
722 | * clocks devices | |
723 | * *_IEP IEP:Image Enhancement Processor | |
724 | * *_ISP ISP:Image Signal Processing | |
725 | * *_VIP VIP:Video Input Processor | |
726 | * *_VOP* VOP:Visual Output Processor | |
727 | * *_RGA RGA | |
728 | * *_EDP* EDP | |
729 | * *_LVDS_* LVDS | |
730 | * *_HDMI HDMI | |
731 | * *_MIPI_* MIPI | |
732 | */ | |
95cface9 | 733 | pd_vio@RK3288_PD_VIO { |
b63af764 CW |
734 | reg = <RK3288_PD_VIO>; |
735 | clocks = <&cru ACLK_IEP>, | |
736 | <&cru ACLK_ISP>, | |
737 | <&cru ACLK_RGA>, | |
738 | <&cru ACLK_VIP>, | |
739 | <&cru ACLK_VOP0>, | |
740 | <&cru ACLK_VOP1>, | |
741 | <&cru DCLK_VOP0>, | |
742 | <&cru DCLK_VOP1>, | |
743 | <&cru HCLK_IEP>, | |
744 | <&cru HCLK_ISP>, | |
745 | <&cru HCLK_RGA>, | |
746 | <&cru HCLK_VIP>, | |
747 | <&cru HCLK_VOP0>, | |
748 | <&cru HCLK_VOP1>, | |
749 | <&cru PCLK_EDP_CTRL>, | |
750 | <&cru PCLK_HDMI_CTRL>, | |
751 | <&cru PCLK_LVDS_PHY>, | |
752 | <&cru PCLK_MIPI_CSI>, | |
753 | <&cru PCLK_MIPI_DSI0>, | |
754 | <&cru PCLK_MIPI_DSI1>, | |
755 | <&cru SCLK_EDP_24M>, | |
756 | <&cru SCLK_EDP>, | |
757 | <&cru SCLK_ISP_JPE>, | |
758 | <&cru SCLK_ISP>, | |
759 | <&cru SCLK_RGA>; | |
760 | }; | |
761 | ||
762 | /* | |
763 | * Note: The following 3 are HEVC(H.265) clocks, | |
764 | * and on the ACLK_HEVC_NIU (NOC). | |
765 | */ | |
95cface9 | 766 | pd_hevc@RK3288_PD_HEVC { |
b63af764 CW |
767 | reg = <RK3288_PD_HEVC>; |
768 | clocks = <&cru ACLK_HEVC>, | |
769 | <&cru SCLK_HEVC_CABAC>, | |
770 | <&cru SCLK_HEVC_CORE>; | |
771 | }; | |
772 | ||
773 | /* | |
774 | * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC | |
775 | * (video endecoder & decoder) clocks that on the | |
776 | * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). | |
777 | */ | |
95cface9 | 778 | pd_video@RK3288_PD_VIDEO { |
b63af764 CW |
779 | reg = <RK3288_PD_VIDEO>; |
780 | clocks = <&cru ACLK_VCODEC>, | |
781 | <&cru HCLK_VCODEC>; | |
782 | }; | |
783 | ||
784 | /* | |
785 | * Note: ACLK_GPU is the GPU clock, | |
786 | * and on the ACLK_GPU_NIU (NOC). | |
787 | */ | |
95cface9 | 788 | pd_gpu@RK3288_PD_GPU { |
b63af764 CW |
789 | reg = <RK3288_PD_GPU>; |
790 | clocks = <&cru ACLK_GPU>; | |
791 | }; | |
792 | }; | |
2ab557b7 HS |
793 | }; |
794 | ||
795 | sgrf: syscon@ff740000 { | |
796 | compatible = "rockchip,rk3288-sgrf", "syscon"; | |
797 | reg = <0xff740000 0x1000>; | |
798 | }; | |
799 | ||
800 | cru: clock-controller@ff760000 { | |
801 | compatible = "rockchip,rk3288-cru"; | |
802 | reg = <0xff760000 0x1000>; | |
803 | rockchip,grf = <&grf>; | |
804 | #clock-cells = <1>; | |
805 | #reset-cells = <1>; | |
cd78d0cd KY |
806 | assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, |
807 | <&cru PLL_NPLL>, <&cru ACLK_CPU>, | |
808 | <&cru HCLK_CPU>, <&cru PCLK_CPU>, | |
809 | <&cru ACLK_PERI>, <&cru HCLK_PERI>, | |
810 | <&cru PCLK_PERI>; | |
811 | assigned-clock-rates = <594000000>, <400000000>, | |
812 | <500000000>, <300000000>, | |
813 | <150000000>, <75000000>, | |
814 | <300000000>, <150000000>, | |
815 | <75000000>; | |
2ab557b7 HS |
816 | }; |
817 | ||
818 | grf: syscon@ff770000 { | |
6e38e6b2 | 819 | compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; |
2ab557b7 | 820 | reg = <0xff770000 0x1000>; |
4b915450 HS |
821 | |
822 | edp_phy: edp-phy { | |
823 | compatible = "rockchip,rk3288-dp-phy"; | |
824 | clocks = <&cru SCLK_EDP_24M>; | |
825 | clock-names = "24m"; | |
826 | #phy-cells = <0>; | |
827 | status = "disabled"; | |
828 | }; | |
2ab557b7 HS |
829 | }; |
830 | ||
831 | wdt: watchdog@ff800000 { | |
832 | compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; | |
833 | reg = <0xff800000 0x100>; | |
39d05162 | 834 | clocks = <&cru PCLK_WDT>; |
1a1b698b | 835 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
2ab557b7 HS |
836 | status = "disabled"; |
837 | }; | |
838 | ||
874e568e SS |
839 | spdif: sound@ff88b0000 { |
840 | compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; | |
841 | reg = <0xff8b0000 0x10000>; | |
842 | #sound-dai-cells = <0>; | |
843 | clock-names = "hclk", "mclk"; | |
844 | clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; | |
845 | dmas = <&dmac_bus_s 3>; | |
846 | dma-names = "tx"; | |
57dcfa56 | 847 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
874e568e SS |
848 | pinctrl-names = "default"; |
849 | pinctrl-0 = <&spdif_tx>; | |
850 | rockchip,grf = <&grf>; | |
851 | status = "disabled"; | |
852 | }; | |
853 | ||
a0f95e35 J |
854 | i2s: i2s@ff890000 { |
855 | compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; | |
856 | reg = <0xff890000 0x10000>; | |
57dcfa56 | 857 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
a0f95e35 J |
858 | #address-cells = <1>; |
859 | #size-cells = <0>; | |
860 | dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; | |
861 | dma-names = "tx", "rx"; | |
862 | clock-names = "i2s_hclk", "i2s_clk"; | |
863 | clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; | |
864 | pinctrl-names = "default"; | |
865 | pinctrl-0 = <&i2s0_bus>; | |
e241657d SZ |
866 | rockchip,playback-channels = <8>; |
867 | rockchip,capture-channels = <2>; | |
a0f95e35 J |
868 | status = "disabled"; |
869 | }; | |
870 | ||
c2cb6161 ZW |
871 | crypto: cypto-controller@ff8a0000 { |
872 | compatible = "rockchip,rk3288-crypto"; | |
873 | reg = <0xff8a0000 0x4000>; | |
874 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | |
875 | clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, | |
876 | <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; | |
877 | clock-names = "aclk", "hclk", "sclk", "apb_pclk"; | |
878 | resets = <&cru SRST_CRYPTO>; | |
879 | reset-names = "crypto-rst"; | |
880 | status = "okay"; | |
881 | }; | |
882 | ||
a29cb8c4 DK |
883 | vopb: vop@ff930000 { |
884 | compatible = "rockchip,rk3288-vop"; | |
885 | reg = <0xff930000 0x19c>; | |
886 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
887 | clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; | |
888 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
b63af764 | 889 | power-domains = <&power RK3288_PD_VIO>; |
a29cb8c4 DK |
890 | resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; |
891 | reset-names = "axi", "ahb", "dclk"; | |
892 | iommus = <&vopb_mmu>; | |
893 | status = "disabled"; | |
894 | ||
895 | vopb_out: port { | |
896 | #address-cells = <1>; | |
897 | #size-cells = <0>; | |
d5a1df48 AY |
898 | |
899 | vopb_out_hdmi: endpoint@0 { | |
900 | reg = <0>; | |
901 | remote-endpoint = <&hdmi_in_vopb>; | |
902 | }; | |
6df7ec61 HS |
903 | |
904 | vopb_out_edp: endpoint@1 { | |
905 | reg = <1>; | |
906 | remote-endpoint = <&edp_in_vopb>; | |
907 | }; | |
908 | ||
cab6f070 CZ |
909 | vopb_out_mipi: endpoint@2 { |
910 | reg = <2>; | |
911 | remote-endpoint = <&mipi_in_vopb>; | |
912 | }; | |
a29cb8c4 DK |
913 | }; |
914 | }; | |
915 | ||
7cae068b DK |
916 | vopb_mmu: iommu@ff930300 { |
917 | compatible = "rockchip,iommu"; | |
918 | reg = <0xff930300 0x100>; | |
919 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
920 | interrupt-names = "vopb_mmu"; | |
b63af764 | 921 | power-domains = <&power RK3288_PD_VIO>; |
7cae068b DK |
922 | #iommu-cells = <0>; |
923 | status = "disabled"; | |
924 | }; | |
925 | ||
a29cb8c4 DK |
926 | vopl: vop@ff940000 { |
927 | compatible = "rockchip,rk3288-vop"; | |
928 | reg = <0xff940000 0x19c>; | |
929 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
930 | clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; | |
931 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
b63af764 | 932 | power-domains = <&power RK3288_PD_VIO>; |
a29cb8c4 DK |
933 | resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; |
934 | reset-names = "axi", "ahb", "dclk"; | |
935 | iommus = <&vopl_mmu>; | |
936 | status = "disabled"; | |
937 | ||
938 | vopl_out: port { | |
939 | #address-cells = <1>; | |
940 | #size-cells = <0>; | |
d5a1df48 AY |
941 | |
942 | vopl_out_hdmi: endpoint@0 { | |
943 | reg = <0>; | |
944 | remote-endpoint = <&hdmi_in_vopl>; | |
945 | }; | |
6df7ec61 HS |
946 | |
947 | vopl_out_edp: endpoint@1 { | |
948 | reg = <1>; | |
949 | remote-endpoint = <&edp_in_vopl>; | |
950 | }; | |
951 | ||
cab6f070 CZ |
952 | vopl_out_mipi: endpoint@2 { |
953 | reg = <2>; | |
954 | remote-endpoint = <&mipi_in_vopl>; | |
955 | }; | |
a29cb8c4 DK |
956 | }; |
957 | }; | |
958 | ||
7cae068b DK |
959 | vopl_mmu: iommu@ff940300 { |
960 | compatible = "rockchip,iommu"; | |
961 | reg = <0xff940300 0x100>; | |
962 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
963 | interrupt-names = "vopl_mmu"; | |
b63af764 | 964 | power-domains = <&power RK3288_PD_VIO>; |
7cae068b DK |
965 | #iommu-cells = <0>; |
966 | status = "disabled"; | |
967 | }; | |
968 | ||
cab6f070 CZ |
969 | mipi_dsi: mipi@ff960000 { |
970 | compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; | |
971 | reg = <0xff960000 0x4000>; | |
5415ba40 | 972 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
cab6f070 CZ |
973 | clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; |
974 | clock-names = "ref", "pclk"; | |
1946a201 | 975 | power-domains = <&power RK3288_PD_VIO>; |
cab6f070 CZ |
976 | rockchip,grf = <&grf>; |
977 | #address-cells = <1>; | |
978 | #size-cells = <0>; | |
979 | status = "disabled"; | |
980 | ||
981 | ports { | |
cab6f070 CZ |
982 | mipi_in: port { |
983 | #address-cells = <1>; | |
984 | #size-cells = <0>; | |
985 | mipi_in_vopb: endpoint@0 { | |
986 | reg = <0>; | |
987 | remote-endpoint = <&vopb_out_mipi>; | |
988 | }; | |
989 | mipi_in_vopl: endpoint@1 { | |
990 | reg = <1>; | |
991 | remote-endpoint = <&vopl_out_mipi>; | |
992 | }; | |
993 | }; | |
994 | }; | |
995 | }; | |
996 | ||
6df7ec61 HS |
997 | edp: dp@ff970000 { |
998 | compatible = "rockchip,rk3288-dp"; | |
999 | reg = <0xff970000 0x4000>; | |
1000 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
1001 | clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; | |
1002 | clock-names = "dp", "pclk"; | |
1003 | phys = <&edp_phy>; | |
1004 | phy-names = "dp"; | |
1005 | resets = <&cru SRST_EDP>; | |
1006 | reset-names = "dp"; | |
1007 | rockchip,grf = <&grf>; | |
1008 | status = "disabled"; | |
1009 | ||
1010 | ports { | |
1011 | #address-cells = <1>; | |
1012 | #size-cells = <0>; | |
1013 | edp_in: port@0 { | |
1014 | reg = <0>; | |
1015 | #address-cells = <1>; | |
1016 | #size-cells = <0>; | |
1017 | edp_in_vopb: endpoint@0 { | |
1018 | reg = <0>; | |
1019 | remote-endpoint = <&vopb_out_edp>; | |
1020 | }; | |
1021 | edp_in_vopl: endpoint@1 { | |
1022 | reg = <1>; | |
1023 | remote-endpoint = <&vopl_out_edp>; | |
1024 | }; | |
1025 | }; | |
1026 | }; | |
1027 | }; | |
1028 | ||
d5a1df48 AY |
1029 | hdmi: hdmi@ff980000 { |
1030 | compatible = "rockchip,rk3288-dw-hdmi"; | |
1031 | reg = <0xff980000 0x20000>; | |
1032 | reg-io-width = <4>; | |
d5a1df48 AY |
1033 | rockchip,grf = <&grf>; |
1034 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
1035 | clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; | |
1036 | clock-names = "iahb", "isfr"; | |
b63af764 | 1037 | power-domains = <&power RK3288_PD_VIO>; |
d5a1df48 AY |
1038 | status = "disabled"; |
1039 | ||
1040 | ports { | |
1041 | hdmi_in: port { | |
1042 | #address-cells = <1>; | |
1043 | #size-cells = <0>; | |
1044 | hdmi_in_vopb: endpoint@0 { | |
1045 | reg = <0>; | |
1046 | remote-endpoint = <&vopb_out_hdmi>; | |
1047 | }; | |
1048 | hdmi_in_vopl: endpoint@1 { | |
1049 | reg = <1>; | |
1050 | remote-endpoint = <&vopl_out_hdmi>; | |
1051 | }; | |
1052 | }; | |
1053 | }; | |
1054 | }; | |
1055 | ||
2ab557b7 HS |
1056 | gic: interrupt-controller@ffc01000 { |
1057 | compatible = "arm,gic-400"; | |
1058 | interrupt-controller; | |
1059 | #interrupt-cells = <3>; | |
1060 | #address-cells = <0>; | |
1061 | ||
1062 | reg = <0xffc01000 0x1000>, | |
1063 | <0xffc02000 0x1000>, | |
1064 | <0xffc04000 0x2000>, | |
1065 | <0xffc06000 0x2000>; | |
1066 | interrupts = <GIC_PPI 9 0xf04>; | |
1067 | }; | |
1068 | ||
88185559 Z |
1069 | efuse: efuse@ffb40000 { |
1070 | compatible = "rockchip,rockchip-efuse"; | |
1071 | reg = <0xffb40000 0x20>; | |
1072 | #address-cells = <1>; | |
1073 | #size-cells = <1>; | |
1074 | clocks = <&cru PCLK_EFUSE256>; | |
1075 | clock-names = "pclk_efuse"; | |
1076 | ||
1077 | cpu_leakage: cpu_leakage@17 { | |
1078 | reg = <0x17 0x1>; | |
1079 | }; | |
1080 | }; | |
1081 | ||
f6db7029 YL |
1082 | usbphy: phy { |
1083 | compatible = "rockchip,rk3288-usb-phy"; | |
1084 | rockchip,grf = <&grf>; | |
1085 | #address-cells = <1>; | |
1086 | #size-cells = <0>; | |
1087 | status = "disabled"; | |
1088 | ||
a8f0fa27 | 1089 | usbphy0: usb-phy@320 { |
f6db7029 YL |
1090 | #phy-cells = <0>; |
1091 | reg = <0x320>; | |
1092 | clocks = <&cru SCLK_OTGPHY0>; | |
1093 | clock-names = "phyclk"; | |
0ace8217 | 1094 | #clock-cells = <0>; |
f6db7029 YL |
1095 | }; |
1096 | ||
a8f0fa27 | 1097 | usbphy1: usb-phy@334 { |
f6db7029 YL |
1098 | #phy-cells = <0>; |
1099 | reg = <0x334>; | |
1100 | clocks = <&cru SCLK_OTGPHY1>; | |
1101 | clock-names = "phyclk"; | |
0ace8217 | 1102 | #clock-cells = <0>; |
f6db7029 YL |
1103 | }; |
1104 | ||
a8f0fa27 | 1105 | usbphy2: usb-phy@348 { |
f6db7029 YL |
1106 | #phy-cells = <0>; |
1107 | reg = <0x348>; | |
1108 | clocks = <&cru SCLK_OTGPHY2>; | |
1109 | clock-names = "phyclk"; | |
0ace8217 | 1110 | #clock-cells = <0>; |
f6db7029 YL |
1111 | }; |
1112 | }; | |
1113 | ||
2ab557b7 HS |
1114 | pinctrl: pinctrl { |
1115 | compatible = "rockchip,rk3288-pinctrl"; | |
1116 | rockchip,grf = <&grf>; | |
1117 | rockchip,pmu = <&pmu>; | |
1118 | #address-cells = <1>; | |
1119 | #size-cells = <1>; | |
1120 | ranges; | |
1121 | ||
1122 | gpio0: gpio0@ff750000 { | |
1123 | compatible = "rockchip,gpio-bank"; | |
1124 | reg = <0xff750000 0x100>; | |
1125 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
1126 | clocks = <&cru PCLK_GPIO0>; | |
1127 | ||
1128 | gpio-controller; | |
1129 | #gpio-cells = <2>; | |
1130 | ||
1131 | interrupt-controller; | |
1132 | #interrupt-cells = <2>; | |
1133 | }; | |
1134 | ||
1135 | gpio1: gpio1@ff780000 { | |
1136 | compatible = "rockchip,gpio-bank"; | |
1137 | reg = <0xff780000 0x100>; | |
1138 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
1139 | clocks = <&cru PCLK_GPIO1>; | |
1140 | ||
1141 | gpio-controller; | |
1142 | #gpio-cells = <2>; | |
1143 | ||
1144 | interrupt-controller; | |
1145 | #interrupt-cells = <2>; | |
1146 | }; | |
1147 | ||
1148 | gpio2: gpio2@ff790000 { | |
1149 | compatible = "rockchip,gpio-bank"; | |
1150 | reg = <0xff790000 0x100>; | |
1151 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
1152 | clocks = <&cru PCLK_GPIO2>; | |
1153 | ||
1154 | gpio-controller; | |
1155 | #gpio-cells = <2>; | |
1156 | ||
1157 | interrupt-controller; | |
1158 | #interrupt-cells = <2>; | |
1159 | }; | |
1160 | ||
1161 | gpio3: gpio3@ff7a0000 { | |
1162 | compatible = "rockchip,gpio-bank"; | |
1163 | reg = <0xff7a0000 0x100>; | |
1164 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
1165 | clocks = <&cru PCLK_GPIO3>; | |
1166 | ||
1167 | gpio-controller; | |
1168 | #gpio-cells = <2>; | |
1169 | ||
1170 | interrupt-controller; | |
1171 | #interrupt-cells = <2>; | |
1172 | }; | |
1173 | ||
1174 | gpio4: gpio4@ff7b0000 { | |
1175 | compatible = "rockchip,gpio-bank"; | |
1176 | reg = <0xff7b0000 0x100>; | |
1177 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
1178 | clocks = <&cru PCLK_GPIO4>; | |
1179 | ||
1180 | gpio-controller; | |
1181 | #gpio-cells = <2>; | |
1182 | ||
1183 | interrupt-controller; | |
1184 | #interrupt-cells = <2>; | |
1185 | }; | |
1186 | ||
1187 | gpio5: gpio5@ff7c0000 { | |
1188 | compatible = "rockchip,gpio-bank"; | |
1189 | reg = <0xff7c0000 0x100>; | |
1190 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
1191 | clocks = <&cru PCLK_GPIO5>; | |
1192 | ||
1193 | gpio-controller; | |
1194 | #gpio-cells = <2>; | |
1195 | ||
1196 | interrupt-controller; | |
1197 | #interrupt-cells = <2>; | |
1198 | }; | |
1199 | ||
1200 | gpio6: gpio6@ff7d0000 { | |
1201 | compatible = "rockchip,gpio-bank"; | |
1202 | reg = <0xff7d0000 0x100>; | |
1203 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
1204 | clocks = <&cru PCLK_GPIO6>; | |
1205 | ||
1206 | gpio-controller; | |
1207 | #gpio-cells = <2>; | |
1208 | ||
1209 | interrupt-controller; | |
1210 | #interrupt-cells = <2>; | |
1211 | }; | |
1212 | ||
1213 | gpio7: gpio7@ff7e0000 { | |
1214 | compatible = "rockchip,gpio-bank"; | |
1215 | reg = <0xff7e0000 0x100>; | |
1216 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
1217 | clocks = <&cru PCLK_GPIO7>; | |
1218 | ||
1219 | gpio-controller; | |
1220 | #gpio-cells = <2>; | |
1221 | ||
1222 | interrupt-controller; | |
1223 | #interrupt-cells = <2>; | |
1224 | }; | |
1225 | ||
1226 | gpio8: gpio8@ff7f0000 { | |
1227 | compatible = "rockchip,gpio-bank"; | |
1228 | reg = <0xff7f0000 0x100>; | |
1229 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
1230 | clocks = <&cru PCLK_GPIO8>; | |
1231 | ||
1232 | gpio-controller; | |
1233 | #gpio-cells = <2>; | |
1234 | ||
1235 | interrupt-controller; | |
1236 | #interrupt-cells = <2>; | |
1237 | }; | |
1238 | ||
e61ccb12 DA |
1239 | hdmi { |
1240 | hdmi_ddc: hdmi-ddc { | |
1241 | rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, | |
1242 | <7 20 RK_FUNC_2 &pcfg_pull_none>; | |
1243 | }; | |
1244 | }; | |
1245 | ||
2ab557b7 HS |
1246 | pcfg_pull_up: pcfg-pull-up { |
1247 | bias-pull-up; | |
1248 | }; | |
1249 | ||
1250 | pcfg_pull_down: pcfg-pull-down { | |
1251 | bias-pull-down; | |
1252 | }; | |
1253 | ||
1254 | pcfg_pull_none: pcfg-pull-none { | |
1255 | bias-disable; | |
1256 | }; | |
1257 | ||
3d3fb74a RC |
1258 | pcfg_pull_none_12ma: pcfg-pull-none-12ma { |
1259 | bias-disable; | |
1260 | drive-strength = <12>; | |
1261 | }; | |
1262 | ||
eecfe981 CZ |
1263 | sleep { |
1264 | global_pwroff: global-pwroff { | |
1265 | rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; | |
1266 | }; | |
1267 | ||
1268 | ddrio_pwroff: ddrio-pwroff { | |
1269 | rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; | |
1270 | }; | |
1271 | ||
1272 | ddr0_retention: ddr0-retention { | |
1273 | rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; | |
1274 | }; | |
1275 | ||
1276 | ddr1_retention: ddr1-retention { | |
1277 | rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; | |
1278 | }; | |
1279 | }; | |
1280 | ||
a4e00345 HS |
1281 | edp { |
1282 | edp_hpd: edp-hpd { | |
1283 | rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; | |
1284 | }; | |
1285 | }; | |
1286 | ||
2ab557b7 HS |
1287 | i2c0 { |
1288 | i2c0_xfer: i2c0-xfer { | |
1289 | rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, | |
1290 | <0 16 RK_FUNC_1 &pcfg_pull_none>; | |
1291 | }; | |
1292 | }; | |
1293 | ||
1294 | i2c1 { | |
1295 | i2c1_xfer: i2c1-xfer { | |
1296 | rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, | |
1297 | <8 5 RK_FUNC_1 &pcfg_pull_none>; | |
1298 | }; | |
1299 | }; | |
1300 | ||
1301 | i2c2 { | |
1302 | i2c2_xfer: i2c2-xfer { | |
1303 | rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, | |
1304 | <6 10 RK_FUNC_1 &pcfg_pull_none>; | |
1305 | }; | |
1306 | }; | |
1307 | ||
1308 | i2c3 { | |
1309 | i2c3_xfer: i2c3-xfer { | |
1310 | rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, | |
1311 | <2 17 RK_FUNC_1 &pcfg_pull_none>; | |
1312 | }; | |
1313 | }; | |
1314 | ||
1315 | i2c4 { | |
1316 | i2c4_xfer: i2c4-xfer { | |
1317 | rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, | |
1318 | <7 18 RK_FUNC_1 &pcfg_pull_none>; | |
1319 | }; | |
1320 | }; | |
1321 | ||
1322 | i2c5 { | |
1323 | i2c5_xfer: i2c5-xfer { | |
1324 | rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, | |
1325 | <7 20 RK_FUNC_1 &pcfg_pull_none>; | |
a0f95e35 J |
1326 | }; |
1327 | }; | |
1328 | ||
1329 | i2s0 { | |
1330 | i2s0_bus: i2s0-bus { | |
1331 | rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, | |
1332 | <6 1 RK_FUNC_1 &pcfg_pull_none>, | |
1333 | <6 2 RK_FUNC_1 &pcfg_pull_none>, | |
1334 | <6 3 RK_FUNC_1 &pcfg_pull_none>, | |
1335 | <6 4 RK_FUNC_1 &pcfg_pull_none>, | |
1336 | <6 8 RK_FUNC_1 &pcfg_pull_none>; | |
2ab557b7 HS |
1337 | }; |
1338 | }; | |
1339 | ||
1340 | sdmmc { | |
1341 | sdmmc_clk: sdmmc-clk { | |
1342 | rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; | |
1343 | }; | |
1344 | ||
1345 | sdmmc_cmd: sdmmc-cmd { | |
1346 | rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; | |
1347 | }; | |
1348 | ||
d59df5d1 | 1349 | sdmmc_cd: sdmmc-cd { |
2ab557b7 HS |
1350 | rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; |
1351 | }; | |
1352 | ||
1353 | sdmmc_bus1: sdmmc-bus1 { | |
1354 | rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; | |
1355 | }; | |
1356 | ||
1357 | sdmmc_bus4: sdmmc-bus4 { | |
1358 | rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, | |
1359 | <6 17 RK_FUNC_1 &pcfg_pull_up>, | |
1360 | <6 18 RK_FUNC_1 &pcfg_pull_up>, | |
1361 | <6 19 RK_FUNC_1 &pcfg_pull_up>; | |
1362 | }; | |
1363 | }; | |
1364 | ||
f1a07231 AK |
1365 | sdio0 { |
1366 | sdio0_bus1: sdio0-bus1 { | |
1367 | rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; | |
1368 | }; | |
1369 | ||
1370 | sdio0_bus4: sdio0-bus4 { | |
1371 | rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, | |
1372 | <4 21 RK_FUNC_1 &pcfg_pull_up>, | |
1373 | <4 22 RK_FUNC_1 &pcfg_pull_up>, | |
1374 | <4 23 RK_FUNC_1 &pcfg_pull_up>; | |
1375 | }; | |
1376 | ||
1377 | sdio0_cmd: sdio0-cmd { | |
1378 | rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; | |
1379 | }; | |
1380 | ||
1381 | sdio0_clk: sdio0-clk { | |
1382 | rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; | |
1383 | }; | |
1384 | ||
1385 | sdio0_cd: sdio0-cd { | |
1386 | rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; | |
1387 | }; | |
1388 | ||
1389 | sdio0_wp: sdio0-wp { | |
1390 | rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; | |
1391 | }; | |
1392 | ||
1393 | sdio0_pwr: sdio0-pwr { | |
1394 | rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; | |
1395 | }; | |
1396 | ||
1397 | sdio0_bkpwr: sdio0-bkpwr { | |
1398 | rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; | |
1399 | }; | |
1400 | ||
1401 | sdio0_int: sdio0-int { | |
1402 | rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; | |
1403 | }; | |
1404 | }; | |
1405 | ||
1406 | sdio1 { | |
1407 | sdio1_bus1: sdio1-bus1 { | |
1408 | rockchip,pins = <3 24 4 &pcfg_pull_up>; | |
1409 | }; | |
1410 | ||
1411 | sdio1_bus4: sdio1-bus4 { | |
1412 | rockchip,pins = <3 24 4 &pcfg_pull_up>, | |
1413 | <3 25 4 &pcfg_pull_up>, | |
1414 | <3 26 4 &pcfg_pull_up>, | |
1415 | <3 27 4 &pcfg_pull_up>; | |
1416 | }; | |
1417 | ||
1418 | sdio1_cd: sdio1-cd { | |
1419 | rockchip,pins = <3 28 4 &pcfg_pull_up>; | |
1420 | }; | |
1421 | ||
1422 | sdio1_wp: sdio1-wp { | |
1423 | rockchip,pins = <3 29 4 &pcfg_pull_up>; | |
1424 | }; | |
1425 | ||
1426 | sdio1_bkpwr: sdio1-bkpwr { | |
1427 | rockchip,pins = <3 30 4 &pcfg_pull_up>; | |
1428 | }; | |
1429 | ||
1430 | sdio1_int: sdio1-int { | |
1431 | rockchip,pins = <3 31 4 &pcfg_pull_up>; | |
1432 | }; | |
1433 | ||
1434 | sdio1_cmd: sdio1-cmd { | |
1435 | rockchip,pins = <4 6 4 &pcfg_pull_up>; | |
1436 | }; | |
1437 | ||
1438 | sdio1_clk: sdio1-clk { | |
1439 | rockchip,pins = <4 7 4 &pcfg_pull_none>; | |
1440 | }; | |
1441 | ||
1442 | sdio1_pwr: sdio1-pwr { | |
1443 | rockchip,pins = <4 9 4 &pcfg_pull_up>; | |
1444 | }; | |
1445 | }; | |
1446 | ||
2ab557b7 HS |
1447 | emmc { |
1448 | emmc_clk: emmc-clk { | |
1449 | rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; | |
1450 | }; | |
1451 | ||
1452 | emmc_cmd: emmc-cmd { | |
1453 | rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; | |
1454 | }; | |
1455 | ||
1456 | emmc_pwr: emmc-pwr { | |
1457 | rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; | |
1458 | }; | |
1459 | ||
1460 | emmc_bus1: emmc-bus1 { | |
1461 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; | |
1462 | }; | |
1463 | ||
1464 | emmc_bus4: emmc-bus4 { | |
1465 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, | |
1466 | <3 1 RK_FUNC_2 &pcfg_pull_up>, | |
1467 | <3 2 RK_FUNC_2 &pcfg_pull_up>, | |
1468 | <3 3 RK_FUNC_2 &pcfg_pull_up>; | |
1469 | }; | |
1470 | ||
1471 | emmc_bus8: emmc-bus8 { | |
1472 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, | |
1473 | <3 1 RK_FUNC_2 &pcfg_pull_up>, | |
1474 | <3 2 RK_FUNC_2 &pcfg_pull_up>, | |
1475 | <3 3 RK_FUNC_2 &pcfg_pull_up>, | |
1476 | <3 4 RK_FUNC_2 &pcfg_pull_up>, | |
1477 | <3 5 RK_FUNC_2 &pcfg_pull_up>, | |
1478 | <3 6 RK_FUNC_2 &pcfg_pull_up>, | |
1479 | <3 7 RK_FUNC_2 &pcfg_pull_up>; | |
1480 | }; | |
1481 | }; | |
1482 | ||
1f53170b | 1483 | spi0 { |
1484 | spi0_clk: spi0-clk { | |
1485 | rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; | |
1486 | }; | |
1487 | spi0_cs0: spi0-cs0 { | |
1488 | rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; | |
1489 | }; | |
1490 | spi0_tx: spi0-tx { | |
1491 | rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; | |
1492 | }; | |
1493 | spi0_rx: spi0-rx { | |
1494 | rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; | |
1495 | }; | |
1496 | spi0_cs1: spi0-cs1 { | |
1497 | rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; | |
1498 | }; | |
1499 | }; | |
1500 | spi1 { | |
1501 | spi1_clk: spi1-clk { | |
1502 | rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; | |
1503 | }; | |
1504 | spi1_cs0: spi1-cs0 { | |
1505 | rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; | |
1506 | }; | |
1507 | spi1_rx: spi1-rx { | |
1508 | rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; | |
1509 | }; | |
1510 | spi1_tx: spi1-tx { | |
1511 | rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; | |
1512 | }; | |
1513 | }; | |
1514 | ||
1515 | spi2 { | |
1516 | spi2_cs1: spi2-cs1 { | |
1517 | rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; | |
1518 | }; | |
1519 | spi2_clk: spi2-clk { | |
1520 | rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; | |
1521 | }; | |
1522 | spi2_cs0: spi2-cs0 { | |
1523 | rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; | |
1524 | }; | |
1525 | spi2_rx: spi2-rx { | |
1526 | rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; | |
1527 | }; | |
1528 | spi2_tx: spi2-tx { | |
1529 | rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; | |
1530 | }; | |
1531 | }; | |
1532 | ||
2ab557b7 HS |
1533 | uart0 { |
1534 | uart0_xfer: uart0-xfer { | |
1535 | rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, | |
1536 | <4 17 RK_FUNC_1 &pcfg_pull_none>; | |
1537 | }; | |
1538 | ||
1539 | uart0_cts: uart0-cts { | |
8915f364 | 1540 | rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>; |
2ab557b7 HS |
1541 | }; |
1542 | ||
1543 | uart0_rts: uart0-rts { | |
1544 | rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; | |
1545 | }; | |
1546 | }; | |
1547 | ||
1548 | uart1 { | |
1549 | uart1_xfer: uart1-xfer { | |
1550 | rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, | |
1551 | <5 9 RK_FUNC_1 &pcfg_pull_none>; | |
1552 | }; | |
1553 | ||
1554 | uart1_cts: uart1-cts { | |
8915f364 | 1555 | rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>; |
2ab557b7 HS |
1556 | }; |
1557 | ||
1558 | uart1_rts: uart1-rts { | |
1559 | rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; | |
1560 | }; | |
1561 | }; | |
1562 | ||
1563 | uart2 { | |
1564 | uart2_xfer: uart2-xfer { | |
1565 | rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, | |
1566 | <7 23 RK_FUNC_1 &pcfg_pull_none>; | |
1567 | }; | |
1568 | /* no rts / cts for uart2 */ | |
1569 | }; | |
1570 | ||
1571 | uart3 { | |
1572 | uart3_xfer: uart3-xfer { | |
1573 | rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, | |
1574 | <7 8 RK_FUNC_1 &pcfg_pull_none>; | |
1575 | }; | |
1576 | ||
1577 | uart3_cts: uart3-cts { | |
8915f364 | 1578 | rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>; |
2ab557b7 HS |
1579 | }; |
1580 | ||
1581 | uart3_rts: uart3-rts { | |
1582 | rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; | |
1583 | }; | |
1584 | }; | |
1585 | ||
1586 | uart4 { | |
1587 | uart4_xfer: uart4-xfer { | |
1588 | rockchip,pins = <5 12 3 &pcfg_pull_up>, | |
1589 | <5 13 3 &pcfg_pull_none>; | |
1590 | }; | |
1591 | ||
1592 | uart4_cts: uart4-cts { | |
8915f364 | 1593 | rockchip,pins = <5 14 3 &pcfg_pull_up>; |
2ab557b7 HS |
1594 | }; |
1595 | ||
1596 | uart4_rts: uart4-rts { | |
1597 | rockchip,pins = <5 15 3 &pcfg_pull_none>; | |
1598 | }; | |
1599 | }; | |
df542df3 | 1600 | |
b67d6bc3 | 1601 | tsadc { |
784359b8 CW |
1602 | otp_gpio: otp-gpio { |
1603 | rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; | |
1604 | }; | |
1605 | ||
b67d6bc3 CW |
1606 | otp_out: otp-out { |
1607 | rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; | |
1608 | }; | |
1609 | }; | |
1610 | ||
df542df3 DA |
1611 | pwm0 { |
1612 | pwm0_pin: pwm0-pin { | |
1613 | rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; | |
1614 | }; | |
1615 | }; | |
1616 | ||
1617 | pwm1 { | |
1618 | pwm1_pin: pwm1-pin { | |
1619 | rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; | |
1620 | }; | |
1621 | }; | |
1622 | ||
1623 | pwm2 { | |
1624 | pwm2_pin: pwm2-pin { | |
1625 | rockchip,pins = <7 22 3 &pcfg_pull_none>; | |
1626 | }; | |
1627 | }; | |
1628 | ||
1629 | pwm3 { | |
1630 | pwm3_pin: pwm3-pin { | |
1631 | rockchip,pins = <7 23 3 &pcfg_pull_none>; | |
1632 | }; | |
1633 | }; | |
3d3fb74a RC |
1634 | |
1635 | gmac { | |
1636 | rgmii_pins: rgmii-pins { | |
1637 | rockchip,pins = <3 30 3 &pcfg_pull_none>, | |
1638 | <3 31 3 &pcfg_pull_none>, | |
1639 | <3 26 3 &pcfg_pull_none>, | |
1640 | <3 27 3 &pcfg_pull_none>, | |
1641 | <3 28 3 &pcfg_pull_none_12ma>, | |
1642 | <3 29 3 &pcfg_pull_none_12ma>, | |
1643 | <3 24 3 &pcfg_pull_none_12ma>, | |
1644 | <3 25 3 &pcfg_pull_none_12ma>, | |
1645 | <4 0 3 &pcfg_pull_none>, | |
1646 | <4 5 3 &pcfg_pull_none>, | |
1647 | <4 6 3 &pcfg_pull_none>, | |
1648 | <4 9 3 &pcfg_pull_none_12ma>, | |
1649 | <4 4 3 &pcfg_pull_none_12ma>, | |
1650 | <4 1 3 &pcfg_pull_none>, | |
1651 | <4 3 3 &pcfg_pull_none>; | |
1652 | }; | |
1653 | ||
1654 | rmii_pins: rmii-pins { | |
1655 | rockchip,pins = <3 30 3 &pcfg_pull_none>, | |
1656 | <3 31 3 &pcfg_pull_none>, | |
1657 | <3 28 3 &pcfg_pull_none>, | |
1658 | <3 29 3 &pcfg_pull_none>, | |
1659 | <4 0 3 &pcfg_pull_none>, | |
1660 | <4 5 3 &pcfg_pull_none>, | |
1661 | <4 4 3 &pcfg_pull_none>, | |
1662 | <4 1 3 &pcfg_pull_none>, | |
1663 | <4 2 3 &pcfg_pull_none>, | |
1664 | <4 3 3 &pcfg_pull_none>; | |
1665 | }; | |
1666 | }; | |
874e568e SS |
1667 | |
1668 | spdif { | |
1669 | spdif_tx: spdif-tx { | |
1670 | rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>; | |
1671 | }; | |
1672 | }; | |
2ab557b7 HS |
1673 | }; |
1674 | }; |