Commit | Line | Data |
---|---|---|
2ab557b7 | 1 | /* |
b1772506 HS |
2 | * This file is dual-licensed: you can use it either under the terms |
3 | * of the GPL or the X11 license, at your option. Note that this dual | |
4 | * licensing only applies to this file, and not this project as a | |
5 | * whole. | |
2ab557b7 | 6 | * |
b1772506 HS |
7 | * a) This file is free software; you can redistribute it and/or |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of the | |
10 | * License, or (at your option) any later version. | |
11 | * | |
12 | * This file is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * Or, alternatively, | |
18 | * | |
19 | * b) Permission is hereby granted, free of charge, to any person | |
20 | * obtaining a copy of this software and associated documentation | |
21 | * files (the "Software"), to deal in the Software without | |
22 | * restriction, including without limitation the rights to use, | |
23 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
24 | * sell copies of the Software, and to permit persons to whom the | |
25 | * Software is furnished to do so, subject to the following | |
26 | * conditions: | |
27 | * | |
28 | * The above copyright notice and this permission notice shall be | |
29 | * included in all copies or substantial portions of the Software. | |
30 | * | |
31 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
32 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
33 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
34 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
35 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
36 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
37 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
38 | * OTHER DEALINGS IN THE SOFTWARE. | |
2ab557b7 HS |
39 | */ |
40 | ||
41 | #include <dt-bindings/gpio/gpio.h> | |
42 | #include <dt-bindings/interrupt-controller/irq.h> | |
43 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
44 | #include <dt-bindings/pinctrl/rockchip.h> | |
45 | #include <dt-bindings/clock/rk3288-cru.h> | |
b67d6bc3 | 46 | #include <dt-bindings/thermal/thermal.h> |
b63af764 | 47 | #include <dt-bindings/power/rk3288-power.h> |
2ab557b7 HS |
48 | #include "skeleton.dtsi" |
49 | ||
50 | / { | |
51 | compatible = "rockchip,rk3288"; | |
52 | ||
53 | interrupt-parent = <&gic>; | |
54 | ||
55 | aliases { | |
56 | i2c0 = &i2c0; | |
57 | i2c1 = &i2c1; | |
58 | i2c2 = &i2c2; | |
59 | i2c3 = &i2c3; | |
60 | i2c4 = &i2c4; | |
61 | i2c5 = &i2c5; | |
d7f9a388 DA |
62 | mshc0 = &emmc; |
63 | mshc1 = &sdmmc; | |
64 | mshc2 = &sdio0; | |
65 | mshc3 = &sdio1; | |
2ab557b7 HS |
66 | serial0 = &uart0; |
67 | serial1 = &uart1; | |
68 | serial2 = &uart2; | |
69 | serial3 = &uart3; | |
70 | serial4 = &uart4; | |
1f53170b | 71 | spi0 = &spi0; |
72 | spi1 = &spi1; | |
73 | spi2 = &spi2; | |
2ab557b7 HS |
74 | }; |
75 | ||
f1840780 SR |
76 | arm-pmu { |
77 | compatible = "arm,cortex-a12-pmu"; | |
78 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, | |
79 | <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, | |
80 | <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, | |
81 | <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
4863dcd3 | 82 | interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
f1840780 SR |
83 | }; |
84 | ||
2ab557b7 HS |
85 | cpus { |
86 | #address-cells = <1>; | |
87 | #size-cells = <0>; | |
08bcc754 | 88 | enable-method = "rockchip,rk3066-smp"; |
fbdbc732 | 89 | rockchip,pmu = <&pmu>; |
2ab557b7 | 90 | |
be8a77c5 | 91 | cpu0: cpu@500 { |
2ab557b7 HS |
92 | device_type = "cpu"; |
93 | compatible = "arm,cortex-a12"; | |
94 | reg = <0x500>; | |
044542af | 95 | resets = <&cru SRST_CORE0>; |
be8a77c5 HS |
96 | operating-points = < |
97 | /* KHz uV */ | |
98 | 1608000 1350000 | |
99 | 1512000 1300000 | |
100 | 1416000 1200000 | |
101 | 1200000 1100000 | |
102 | 1008000 1050000 | |
103 | 816000 1000000 | |
104 | 696000 950000 | |
105 | 600000 900000 | |
106 | 408000 900000 | |
107 | 312000 900000 | |
108 | 216000 900000 | |
109 | 126000 900000 | |
110 | >; | |
b67d6bc3 | 111 | #cooling-cells = <2>; /* min followed by max */ |
be8a77c5 HS |
112 | clock-latency = <40000>; |
113 | clocks = <&cru ARMCLK>; | |
2ab557b7 | 114 | }; |
4863dcd3 | 115 | cpu1: cpu@501 { |
2ab557b7 HS |
116 | device_type = "cpu"; |
117 | compatible = "arm,cortex-a12"; | |
118 | reg = <0x501>; | |
044542af | 119 | resets = <&cru SRST_CORE1>; |
2ab557b7 | 120 | }; |
4863dcd3 | 121 | cpu2: cpu@502 { |
2ab557b7 HS |
122 | device_type = "cpu"; |
123 | compatible = "arm,cortex-a12"; | |
124 | reg = <0x502>; | |
044542af | 125 | resets = <&cru SRST_CORE2>; |
2ab557b7 | 126 | }; |
4863dcd3 | 127 | cpu3: cpu@503 { |
2ab557b7 HS |
128 | device_type = "cpu"; |
129 | compatible = "arm,cortex-a12"; | |
130 | reg = <0x503>; | |
044542af | 131 | resets = <&cru SRST_CORE3>; |
2ab557b7 HS |
132 | }; |
133 | }; | |
134 | ||
982891c3 HS |
135 | amba { |
136 | compatible = "arm,amba-bus"; | |
137 | #address-cells = <1>; | |
138 | #size-cells = <1>; | |
139 | ranges; | |
140 | ||
141 | dmac_peri: dma-controller@ff250000 { | |
142 | compatible = "arm,pl330", "arm,primecell"; | |
143 | reg = <0xff250000 0x4000>; | |
144 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
145 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
146 | #dma-cells = <1>; | |
147 | clocks = <&cru ACLK_DMAC2>; | |
148 | clock-names = "apb_pclk"; | |
149 | }; | |
150 | ||
151 | dmac_bus_ns: dma-controller@ff600000 { | |
152 | compatible = "arm,pl330", "arm,primecell"; | |
153 | reg = <0xff600000 0x4000>; | |
154 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
155 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
156 | #dma-cells = <1>; | |
157 | clocks = <&cru ACLK_DMAC1>; | |
158 | clock-names = "apb_pclk"; | |
159 | status = "disabled"; | |
160 | }; | |
161 | ||
162 | dmac_bus_s: dma-controller@ffb20000 { | |
163 | compatible = "arm,pl330", "arm,primecell"; | |
164 | reg = <0xffb20000 0x4000>; | |
165 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
166 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
167 | #dma-cells = <1>; | |
168 | clocks = <&cru ACLK_DMAC1>; | |
169 | clock-names = "apb_pclk"; | |
170 | }; | |
171 | }; | |
172 | ||
b21bcfc9 HS |
173 | reserved-memory { |
174 | #address-cells = <1>; | |
175 | #size-cells = <1>; | |
176 | ranges; | |
177 | ||
178 | /* | |
179 | * The rk3288 cannot use the memory area above 0xfe000000 | |
180 | * for dma operations for some reason. While there is | |
181 | * probably a better solution available somewhere, we | |
182 | * haven't found it yet and while devices with 2GB of ram | |
183 | * are not affected, this issue prevents 4GB from booting. | |
184 | * So to make these devices at least bootable, block | |
185 | * this area for the time being until the real solution | |
186 | * is found. | |
187 | */ | |
188 | dma-unusable@fe000000 { | |
189 | reg = <0xfe000000 0x1000000>; | |
190 | }; | |
191 | }; | |
192 | ||
2ab557b7 HS |
193 | xin24m: oscillator { |
194 | compatible = "fixed-clock"; | |
195 | clock-frequency = <24000000>; | |
196 | clock-output-names = "xin24m"; | |
197 | #clock-cells = <0>; | |
198 | }; | |
199 | ||
200 | timer { | |
201 | compatible = "arm,armv7-timer"; | |
e2405a59 | 202 | arm,cpu-registers-not-fw-configured; |
2ab557b7 HS |
203 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
204 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
205 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
206 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
207 | clock-frequency = <24000000>; | |
208 | }; | |
209 | ||
e48cc181 DL |
210 | timer: timer@ff810000 { |
211 | compatible = "rockchip,rk3288-timer"; | |
212 | reg = <0xff810000 0x20>; | |
213 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
214 | clocks = <&xin24m>, <&cru PCLK_TIMER>; | |
215 | clock-names = "timer", "pclk"; | |
216 | }; | |
217 | ||
a29cb8c4 DK |
218 | display-subsystem { |
219 | compatible = "rockchip,display-subsystem"; | |
220 | ports = <&vopl_out>, <&vopb_out>; | |
221 | }; | |
222 | ||
85095bf3 DA |
223 | sdmmc: dwmmc@ff0c0000 { |
224 | compatible = "rockchip,rk3288-dw-mshc"; | |
f74ba117 | 225 | clock-freq-min-max = <400000 150000000>; |
f71ddc58 AS |
226 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, |
227 | <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; | |
228 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
85095bf3 DA |
229 | fifo-depth = <0x100>; |
230 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
231 | reg = <0xff0c0000 0x4000>; | |
232 | status = "disabled"; | |
233 | }; | |
234 | ||
f1a07231 AK |
235 | sdio0: dwmmc@ff0d0000 { |
236 | compatible = "rockchip,rk3288-dw-mshc"; | |
f74ba117 | 237 | clock-freq-min-max = <400000 150000000>; |
f71ddc58 AS |
238 | clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, |
239 | <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; | |
240 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
f1a07231 AK |
241 | fifo-depth = <0x100>; |
242 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
243 | reg = <0xff0d0000 0x4000>; | |
244 | status = "disabled"; | |
245 | }; | |
246 | ||
247 | sdio1: dwmmc@ff0e0000 { | |
248 | compatible = "rockchip,rk3288-dw-mshc"; | |
f74ba117 | 249 | clock-freq-min-max = <400000 150000000>; |
f71ddc58 AS |
250 | clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, |
251 | <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; | |
252 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
f1a07231 AK |
253 | fifo-depth = <0x100>; |
254 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
255 | reg = <0xff0e0000 0x4000>; | |
256 | status = "disabled"; | |
257 | }; | |
258 | ||
85095bf3 DA |
259 | emmc: dwmmc@ff0f0000 { |
260 | compatible = "rockchip,rk3288-dw-mshc"; | |
f74ba117 | 261 | clock-freq-min-max = <400000 150000000>; |
f71ddc58 AS |
262 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, |
263 | <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; | |
264 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
85095bf3 DA |
265 | fifo-depth = <0x100>; |
266 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
267 | reg = <0xff0f0000 0x4000>; | |
268 | status = "disabled"; | |
269 | }; | |
270 | ||
f23a6179 HS |
271 | saradc: saradc@ff100000 { |
272 | compatible = "rockchip,saradc"; | |
273 | reg = <0xff100000 0x100>; | |
274 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
275 | #io-channel-cells = <1>; | |
276 | clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; | |
277 | clock-names = "saradc", "apb_pclk"; | |
278 | status = "disabled"; | |
279 | }; | |
280 | ||
1f53170b | 281 | spi0: spi@ff110000 { |
282 | compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; | |
283 | clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; | |
284 | clock-names = "spiclk", "apb_pclk"; | |
11bd57b8 DA |
285 | dmas = <&dmac_peri 11>, <&dmac_peri 12>; |
286 | dma-names = "tx", "rx"; | |
1f53170b | 287 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
288 | pinctrl-names = "default"; | |
289 | pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; | |
290 | reg = <0xff110000 0x1000>; | |
291 | #address-cells = <1>; | |
292 | #size-cells = <0>; | |
293 | status = "disabled"; | |
294 | }; | |
295 | ||
296 | spi1: spi@ff120000 { | |
297 | compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; | |
298 | clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; | |
299 | clock-names = "spiclk", "apb_pclk"; | |
11bd57b8 DA |
300 | dmas = <&dmac_peri 13>, <&dmac_peri 14>; |
301 | dma-names = "tx", "rx"; | |
1f53170b | 302 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
303 | pinctrl-names = "default"; | |
304 | pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; | |
305 | reg = <0xff120000 0x1000>; | |
306 | #address-cells = <1>; | |
307 | #size-cells = <0>; | |
308 | status = "disabled"; | |
309 | }; | |
310 | ||
311 | spi2: spi@ff130000 { | |
312 | compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; | |
313 | clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; | |
314 | clock-names = "spiclk", "apb_pclk"; | |
11bd57b8 DA |
315 | dmas = <&dmac_peri 15>, <&dmac_peri 16>; |
316 | dma-names = "tx", "rx"; | |
1f53170b | 317 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
318 | pinctrl-names = "default"; | |
319 | pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; | |
320 | reg = <0xff130000 0x1000>; | |
321 | #address-cells = <1>; | |
322 | #size-cells = <0>; | |
323 | status = "disabled"; | |
324 | }; | |
325 | ||
2ab557b7 HS |
326 | i2c1: i2c@ff140000 { |
327 | compatible = "rockchip,rk3288-i2c"; | |
328 | reg = <0xff140000 0x1000>; | |
329 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
330 | #address-cells = <1>; | |
331 | #size-cells = <0>; | |
332 | clock-names = "i2c"; | |
333 | clocks = <&cru PCLK_I2C1>; | |
334 | pinctrl-names = "default"; | |
335 | pinctrl-0 = <&i2c1_xfer>; | |
336 | status = "disabled"; | |
337 | }; | |
338 | ||
339 | i2c3: i2c@ff150000 { | |
340 | compatible = "rockchip,rk3288-i2c"; | |
341 | reg = <0xff150000 0x1000>; | |
342 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
343 | #address-cells = <1>; | |
344 | #size-cells = <0>; | |
345 | clock-names = "i2c"; | |
346 | clocks = <&cru PCLK_I2C3>; | |
347 | pinctrl-names = "default"; | |
348 | pinctrl-0 = <&i2c3_xfer>; | |
349 | status = "disabled"; | |
350 | }; | |
351 | ||
352 | i2c4: i2c@ff160000 { | |
353 | compatible = "rockchip,rk3288-i2c"; | |
354 | reg = <0xff160000 0x1000>; | |
355 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; | |
356 | #address-cells = <1>; | |
357 | #size-cells = <0>; | |
358 | clock-names = "i2c"; | |
359 | clocks = <&cru PCLK_I2C4>; | |
360 | pinctrl-names = "default"; | |
361 | pinctrl-0 = <&i2c4_xfer>; | |
362 | status = "disabled"; | |
363 | }; | |
364 | ||
365 | i2c5: i2c@ff170000 { | |
366 | compatible = "rockchip,rk3288-i2c"; | |
367 | reg = <0xff170000 0x1000>; | |
368 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
369 | #address-cells = <1>; | |
370 | #size-cells = <0>; | |
371 | clock-names = "i2c"; | |
372 | clocks = <&cru PCLK_I2C5>; | |
373 | pinctrl-names = "default"; | |
374 | pinctrl-0 = <&i2c5_xfer>; | |
375 | status = "disabled"; | |
376 | }; | |
377 | ||
378 | uart0: serial@ff180000 { | |
379 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
380 | reg = <0xff180000 0x100>; | |
381 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
382 | reg-shift = <2>; | |
383 | reg-io-width = <4>; | |
384 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
385 | clock-names = "baudclk", "apb_pclk"; | |
386 | pinctrl-names = "default"; | |
387 | pinctrl-0 = <&uart0_xfer>; | |
388 | status = "disabled"; | |
389 | }; | |
390 | ||
391 | uart1: serial@ff190000 { | |
392 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
393 | reg = <0xff190000 0x100>; | |
394 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
395 | reg-shift = <2>; | |
396 | reg-io-width = <4>; | |
397 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
398 | clock-names = "baudclk", "apb_pclk"; | |
399 | pinctrl-names = "default"; | |
400 | pinctrl-0 = <&uart1_xfer>; | |
401 | status = "disabled"; | |
402 | }; | |
403 | ||
404 | uart2: serial@ff690000 { | |
405 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
406 | reg = <0xff690000 0x100>; | |
407 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
408 | reg-shift = <2>; | |
409 | reg-io-width = <4>; | |
410 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
411 | clock-names = "baudclk", "apb_pclk"; | |
412 | pinctrl-names = "default"; | |
413 | pinctrl-0 = <&uart2_xfer>; | |
414 | status = "disabled"; | |
415 | }; | |
416 | ||
417 | uart3: serial@ff1b0000 { | |
418 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
419 | reg = <0xff1b0000 0x100>; | |
420 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; | |
421 | reg-shift = <2>; | |
422 | reg-io-width = <4>; | |
423 | clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; | |
424 | clock-names = "baudclk", "apb_pclk"; | |
425 | pinctrl-names = "default"; | |
426 | pinctrl-0 = <&uart3_xfer>; | |
427 | status = "disabled"; | |
428 | }; | |
429 | ||
430 | uart4: serial@ff1c0000 { | |
431 | compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; | |
432 | reg = <0xff1c0000 0x100>; | |
433 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | |
434 | reg-shift = <2>; | |
435 | reg-io-width = <4>; | |
436 | clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; | |
437 | clock-names = "baudclk", "apb_pclk"; | |
438 | pinctrl-names = "default"; | |
439 | pinctrl-0 = <&uart4_xfer>; | |
440 | status = "disabled"; | |
441 | }; | |
442 | ||
b67d6bc3 CW |
443 | thermal-zones { |
444 | #include "rk3288-thermal.dtsi" | |
445 | }; | |
446 | ||
447 | tsadc: tsadc@ff280000 { | |
448 | compatible = "rockchip,rk3288-tsadc"; | |
449 | reg = <0xff280000 0x100>; | |
450 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
451 | clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; | |
452 | clock-names = "tsadc", "apb_pclk"; | |
453 | resets = <&cru SRST_TSADC>; | |
454 | reset-names = "tsadc-apb"; | |
455 | pinctrl-names = "default"; | |
456 | pinctrl-0 = <&otp_out>; | |
457 | #thermal-sensor-cells = <1>; | |
458 | rockchip,hw-tshut-temp = <95000>; | |
459 | status = "disabled"; | |
460 | }; | |
461 | ||
3d3fb74a RC |
462 | gmac: ethernet@ff290000 { |
463 | compatible = "rockchip,rk3288-gmac"; | |
464 | reg = <0xff290000 0x10000>; | |
465 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
466 | interrupt-names = "macirq"; | |
467 | rockchip,grf = <&grf>; | |
468 | clocks = <&cru SCLK_MAC>, | |
469 | <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, | |
470 | <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, | |
471 | <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; | |
472 | clock-names = "stmmaceth", | |
473 | "mac_clk_rx", "mac_clk_tx", | |
474 | "clk_mac_ref", "clk_mac_refout", | |
475 | "aclk_mac", "pclk_mac"; | |
e6b54649 RP |
476 | resets = <&cru SRST_MAC>; |
477 | reset-names = "stmmaceth"; | |
54b0bc60 | 478 | status = "disabled"; |
3d3fb74a RC |
479 | }; |
480 | ||
c9c32c50 DA |
481 | usb_host0_ehci: usb@ff500000 { |
482 | compatible = "generic-ehci"; | |
483 | reg = <0xff500000 0x100>; | |
484 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
485 | clocks = <&cru HCLK_USBHOST0>; | |
486 | clock-names = "usbhost"; | |
f6db7029 YL |
487 | phys = <&usbphy1>; |
488 | phy-names = "usb"; | |
c9c32c50 DA |
489 | status = "disabled"; |
490 | }; | |
491 | ||
492 | /* NOTE: ohci@ff520000 doesn't actually work on hardware */ | |
493 | ||
12dd3653 KY |
494 | usb_host1: usb@ff540000 { |
495 | compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", | |
496 | "snps,dwc2"; | |
497 | reg = <0xff540000 0x40000>; | |
498 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
499 | clocks = <&cru HCLK_USBHOST1>; | |
500 | clock-names = "otg"; | |
cabd2ea2 | 501 | dr_mode = "host"; |
f6db7029 YL |
502 | phys = <&usbphy2>; |
503 | phy-names = "usb2-phy"; | |
12dd3653 KY |
504 | status = "disabled"; |
505 | }; | |
506 | ||
507 | usb_otg: usb@ff580000 { | |
508 | compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", | |
509 | "snps,dwc2"; | |
510 | reg = <0xff580000 0x40000>; | |
511 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
512 | clocks = <&cru HCLK_OTG0>; | |
513 | clock-names = "otg"; | |
cabd2ea2 YL |
514 | dr_mode = "otg"; |
515 | g-np-tx-fifo-size = <16>; | |
516 | g-rx-fifo-size = <275>; | |
517 | g-tx-fifo-size = <256 128 128 64 64 32>; | |
518 | g-use-dma; | |
f6db7029 YL |
519 | phys = <&usbphy0>; |
520 | phy-names = "usb2-phy"; | |
12dd3653 KY |
521 | status = "disabled"; |
522 | }; | |
523 | ||
c9c32c50 DA |
524 | usb_hsic: usb@ff5c0000 { |
525 | compatible = "generic-ehci"; | |
526 | reg = <0xff5c0000 0x100>; | |
527 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
528 | clocks = <&cru HCLK_HSIC>; | |
529 | clock-names = "usbhost"; | |
530 | status = "disabled"; | |
531 | }; | |
532 | ||
2ab557b7 HS |
533 | i2c0: i2c@ff650000 { |
534 | compatible = "rockchip,rk3288-i2c"; | |
535 | reg = <0xff650000 0x1000>; | |
536 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
537 | #address-cells = <1>; | |
538 | #size-cells = <0>; | |
539 | clock-names = "i2c"; | |
540 | clocks = <&cru PCLK_I2C0>; | |
541 | pinctrl-names = "default"; | |
542 | pinctrl-0 = <&i2c0_xfer>; | |
543 | status = "disabled"; | |
544 | }; | |
545 | ||
546 | i2c2: i2c@ff660000 { | |
547 | compatible = "rockchip,rk3288-i2c"; | |
548 | reg = <0xff660000 0x1000>; | |
549 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
550 | #address-cells = <1>; | |
551 | #size-cells = <0>; | |
552 | clock-names = "i2c"; | |
553 | clocks = <&cru PCLK_I2C2>; | |
554 | pinctrl-names = "default"; | |
555 | pinctrl-0 = <&i2c2_xfer>; | |
556 | status = "disabled"; | |
557 | }; | |
558 | ||
df542df3 DA |
559 | pwm0: pwm@ff680000 { |
560 | compatible = "rockchip,rk3288-pwm"; | |
561 | reg = <0xff680000 0x10>; | |
562 | #pwm-cells = <3>; | |
563 | pinctrl-names = "default"; | |
564 | pinctrl-0 = <&pwm0_pin>; | |
565 | clocks = <&cru PCLK_PWM>; | |
566 | clock-names = "pwm"; | |
567 | status = "disabled"; | |
568 | }; | |
569 | ||
570 | pwm1: pwm@ff680010 { | |
571 | compatible = "rockchip,rk3288-pwm"; | |
572 | reg = <0xff680010 0x10>; | |
573 | #pwm-cells = <3>; | |
574 | pinctrl-names = "default"; | |
575 | pinctrl-0 = <&pwm1_pin>; | |
576 | clocks = <&cru PCLK_PWM>; | |
577 | clock-names = "pwm"; | |
578 | status = "disabled"; | |
579 | }; | |
580 | ||
581 | pwm2: pwm@ff680020 { | |
582 | compatible = "rockchip,rk3288-pwm"; | |
583 | reg = <0xff680020 0x10>; | |
584 | #pwm-cells = <3>; | |
585 | pinctrl-names = "default"; | |
586 | pinctrl-0 = <&pwm2_pin>; | |
587 | clocks = <&cru PCLK_PWM>; | |
588 | clock-names = "pwm"; | |
589 | status = "disabled"; | |
590 | }; | |
591 | ||
592 | pwm3: pwm@ff680030 { | |
593 | compatible = "rockchip,rk3288-pwm"; | |
594 | reg = <0xff680030 0x10>; | |
595 | #pwm-cells = <2>; | |
596 | pinctrl-names = "default"; | |
597 | pinctrl-0 = <&pwm3_pin>; | |
598 | clocks = <&cru PCLK_PWM>; | |
599 | clock-names = "pwm"; | |
600 | status = "disabled"; | |
601 | }; | |
602 | ||
1123d412 KY |
603 | bus_intmem@ff700000 { |
604 | compatible = "mmio-sram"; | |
605 | reg = <0xff700000 0x18000>; | |
606 | #address-cells = <1>; | |
607 | #size-cells = <1>; | |
608 | ranges = <0 0xff700000 0x18000>; | |
609 | smp-sram@0 { | |
610 | compatible = "rockchip,rk3066-smp-sram"; | |
611 | reg = <0x00 0x10>; | |
612 | }; | |
613 | }; | |
614 | ||
eecfe981 CZ |
615 | sram@ff720000 { |
616 | compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; | |
617 | reg = <0xff720000 0x1000>; | |
618 | }; | |
619 | ||
2ab557b7 | 620 | pmu: power-management@ff730000 { |
b63af764 | 621 | compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; |
2ab557b7 | 622 | reg = <0xff730000 0x100>; |
b63af764 CW |
623 | |
624 | power: power-controller { | |
625 | compatible = "rockchip,rk3288-power-controller"; | |
626 | #power-domain-cells = <1>; | |
627 | #address-cells = <1>; | |
628 | #size-cells = <0>; | |
629 | ||
630 | /* | |
631 | * Note: Although SCLK_* are the working clocks | |
632 | * of device without including on the NOC, needed for | |
633 | * synchronous reset. | |
634 | * | |
635 | * The clocks on the which NOC: | |
636 | * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. | |
637 | * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. | |
638 | * ACLK_RGA is on ACLK_RGA_NIU. | |
639 | * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. | |
640 | * | |
641 | * Which clock are device clocks: | |
642 | * clocks devices | |
643 | * *_IEP IEP:Image Enhancement Processor | |
644 | * *_ISP ISP:Image Signal Processing | |
645 | * *_VIP VIP:Video Input Processor | |
646 | * *_VOP* VOP:Visual Output Processor | |
647 | * *_RGA RGA | |
648 | * *_EDP* EDP | |
649 | * *_LVDS_* LVDS | |
650 | * *_HDMI HDMI | |
651 | * *_MIPI_* MIPI | |
652 | */ | |
653 | pd_vio { | |
654 | reg = <RK3288_PD_VIO>; | |
655 | clocks = <&cru ACLK_IEP>, | |
656 | <&cru ACLK_ISP>, | |
657 | <&cru ACLK_RGA>, | |
658 | <&cru ACLK_VIP>, | |
659 | <&cru ACLK_VOP0>, | |
660 | <&cru ACLK_VOP1>, | |
661 | <&cru DCLK_VOP0>, | |
662 | <&cru DCLK_VOP1>, | |
663 | <&cru HCLK_IEP>, | |
664 | <&cru HCLK_ISP>, | |
665 | <&cru HCLK_RGA>, | |
666 | <&cru HCLK_VIP>, | |
667 | <&cru HCLK_VOP0>, | |
668 | <&cru HCLK_VOP1>, | |
669 | <&cru PCLK_EDP_CTRL>, | |
670 | <&cru PCLK_HDMI_CTRL>, | |
671 | <&cru PCLK_LVDS_PHY>, | |
672 | <&cru PCLK_MIPI_CSI>, | |
673 | <&cru PCLK_MIPI_DSI0>, | |
674 | <&cru PCLK_MIPI_DSI1>, | |
675 | <&cru SCLK_EDP_24M>, | |
676 | <&cru SCLK_EDP>, | |
677 | <&cru SCLK_ISP_JPE>, | |
678 | <&cru SCLK_ISP>, | |
679 | <&cru SCLK_RGA>; | |
680 | }; | |
681 | ||
682 | /* | |
683 | * Note: The following 3 are HEVC(H.265) clocks, | |
684 | * and on the ACLK_HEVC_NIU (NOC). | |
685 | */ | |
686 | pd_hevc { | |
687 | reg = <RK3288_PD_HEVC>; | |
688 | clocks = <&cru ACLK_HEVC>, | |
689 | <&cru SCLK_HEVC_CABAC>, | |
690 | <&cru SCLK_HEVC_CORE>; | |
691 | }; | |
692 | ||
693 | /* | |
694 | * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC | |
695 | * (video endecoder & decoder) clocks that on the | |
696 | * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). | |
697 | */ | |
698 | pd_video { | |
699 | reg = <RK3288_PD_VIDEO>; | |
700 | clocks = <&cru ACLK_VCODEC>, | |
701 | <&cru HCLK_VCODEC>; | |
702 | }; | |
703 | ||
704 | /* | |
705 | * Note: ACLK_GPU is the GPU clock, | |
706 | * and on the ACLK_GPU_NIU (NOC). | |
707 | */ | |
708 | pd_gpu { | |
709 | reg = <RK3288_PD_GPU>; | |
710 | clocks = <&cru ACLK_GPU>; | |
711 | }; | |
712 | }; | |
2ab557b7 HS |
713 | }; |
714 | ||
715 | sgrf: syscon@ff740000 { | |
716 | compatible = "rockchip,rk3288-sgrf", "syscon"; | |
717 | reg = <0xff740000 0x1000>; | |
718 | }; | |
719 | ||
720 | cru: clock-controller@ff760000 { | |
721 | compatible = "rockchip,rk3288-cru"; | |
722 | reg = <0xff760000 0x1000>; | |
723 | rockchip,grf = <&grf>; | |
724 | #clock-cells = <1>; | |
725 | #reset-cells = <1>; | |
cd78d0cd KY |
726 | assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, |
727 | <&cru PLL_NPLL>, <&cru ACLK_CPU>, | |
728 | <&cru HCLK_CPU>, <&cru PCLK_CPU>, | |
729 | <&cru ACLK_PERI>, <&cru HCLK_PERI>, | |
730 | <&cru PCLK_PERI>; | |
731 | assigned-clock-rates = <594000000>, <400000000>, | |
732 | <500000000>, <300000000>, | |
733 | <150000000>, <75000000>, | |
734 | <300000000>, <150000000>, | |
735 | <75000000>; | |
2ab557b7 HS |
736 | }; |
737 | ||
738 | grf: syscon@ff770000 { | |
739 | compatible = "rockchip,rk3288-grf", "syscon"; | |
740 | reg = <0xff770000 0x1000>; | |
741 | }; | |
742 | ||
743 | wdt: watchdog@ff800000 { | |
744 | compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; | |
745 | reg = <0xff800000 0x100>; | |
39d05162 | 746 | clocks = <&cru PCLK_WDT>; |
1a1b698b | 747 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
2ab557b7 HS |
748 | status = "disabled"; |
749 | }; | |
750 | ||
874e568e SS |
751 | spdif: sound@ff88b0000 { |
752 | compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; | |
753 | reg = <0xff8b0000 0x10000>; | |
754 | #sound-dai-cells = <0>; | |
755 | clock-names = "hclk", "mclk"; | |
756 | clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; | |
757 | dmas = <&dmac_bus_s 3>; | |
758 | dma-names = "tx"; | |
759 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
760 | pinctrl-names = "default"; | |
761 | pinctrl-0 = <&spdif_tx>; | |
762 | rockchip,grf = <&grf>; | |
763 | status = "disabled"; | |
764 | }; | |
765 | ||
a0f95e35 J |
766 | i2s: i2s@ff890000 { |
767 | compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; | |
768 | reg = <0xff890000 0x10000>; | |
769 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
770 | #address-cells = <1>; | |
771 | #size-cells = <0>; | |
772 | dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; | |
773 | dma-names = "tx", "rx"; | |
774 | clock-names = "i2s_hclk", "i2s_clk"; | |
775 | clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; | |
776 | pinctrl-names = "default"; | |
777 | pinctrl-0 = <&i2s0_bus>; | |
778 | status = "disabled"; | |
779 | }; | |
780 | ||
a29cb8c4 DK |
781 | vopb: vop@ff930000 { |
782 | compatible = "rockchip,rk3288-vop"; | |
783 | reg = <0xff930000 0x19c>; | |
784 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
785 | clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; | |
786 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
b63af764 | 787 | power-domains = <&power RK3288_PD_VIO>; |
a29cb8c4 DK |
788 | resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; |
789 | reset-names = "axi", "ahb", "dclk"; | |
790 | iommus = <&vopb_mmu>; | |
791 | status = "disabled"; | |
792 | ||
793 | vopb_out: port { | |
794 | #address-cells = <1>; | |
795 | #size-cells = <0>; | |
d5a1df48 AY |
796 | |
797 | vopb_out_hdmi: endpoint@0 { | |
798 | reg = <0>; | |
799 | remote-endpoint = <&hdmi_in_vopb>; | |
800 | }; | |
a29cb8c4 DK |
801 | }; |
802 | }; | |
803 | ||
7cae068b DK |
804 | vopb_mmu: iommu@ff930300 { |
805 | compatible = "rockchip,iommu"; | |
806 | reg = <0xff930300 0x100>; | |
807 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
808 | interrupt-names = "vopb_mmu"; | |
b63af764 | 809 | power-domains = <&power RK3288_PD_VIO>; |
7cae068b DK |
810 | #iommu-cells = <0>; |
811 | status = "disabled"; | |
812 | }; | |
813 | ||
a29cb8c4 DK |
814 | vopl: vop@ff940000 { |
815 | compatible = "rockchip,rk3288-vop"; | |
816 | reg = <0xff940000 0x19c>; | |
817 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
818 | clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; | |
819 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
b63af764 | 820 | power-domains = <&power RK3288_PD_VIO>; |
a29cb8c4 DK |
821 | resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; |
822 | reset-names = "axi", "ahb", "dclk"; | |
823 | iommus = <&vopl_mmu>; | |
824 | status = "disabled"; | |
825 | ||
826 | vopl_out: port { | |
827 | #address-cells = <1>; | |
828 | #size-cells = <0>; | |
d5a1df48 AY |
829 | |
830 | vopl_out_hdmi: endpoint@0 { | |
831 | reg = <0>; | |
832 | remote-endpoint = <&hdmi_in_vopl>; | |
833 | }; | |
a29cb8c4 DK |
834 | }; |
835 | }; | |
836 | ||
7cae068b DK |
837 | vopl_mmu: iommu@ff940300 { |
838 | compatible = "rockchip,iommu"; | |
839 | reg = <0xff940300 0x100>; | |
840 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
841 | interrupt-names = "vopl_mmu"; | |
b63af764 | 842 | power-domains = <&power RK3288_PD_VIO>; |
7cae068b DK |
843 | #iommu-cells = <0>; |
844 | status = "disabled"; | |
845 | }; | |
846 | ||
d5a1df48 AY |
847 | hdmi: hdmi@ff980000 { |
848 | compatible = "rockchip,rk3288-dw-hdmi"; | |
849 | reg = <0xff980000 0x20000>; | |
850 | reg-io-width = <4>; | |
d5a1df48 AY |
851 | rockchip,grf = <&grf>; |
852 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
853 | clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; | |
854 | clock-names = "iahb", "isfr"; | |
b63af764 | 855 | power-domains = <&power RK3288_PD_VIO>; |
d5a1df48 AY |
856 | status = "disabled"; |
857 | ||
858 | ports { | |
859 | hdmi_in: port { | |
860 | #address-cells = <1>; | |
861 | #size-cells = <0>; | |
862 | hdmi_in_vopb: endpoint@0 { | |
863 | reg = <0>; | |
864 | remote-endpoint = <&vopb_out_hdmi>; | |
865 | }; | |
866 | hdmi_in_vopl: endpoint@1 { | |
867 | reg = <1>; | |
868 | remote-endpoint = <&vopl_out_hdmi>; | |
869 | }; | |
870 | }; | |
871 | }; | |
872 | }; | |
873 | ||
2ab557b7 HS |
874 | gic: interrupt-controller@ffc01000 { |
875 | compatible = "arm,gic-400"; | |
876 | interrupt-controller; | |
877 | #interrupt-cells = <3>; | |
878 | #address-cells = <0>; | |
879 | ||
880 | reg = <0xffc01000 0x1000>, | |
881 | <0xffc02000 0x1000>, | |
882 | <0xffc04000 0x2000>, | |
883 | <0xffc06000 0x2000>; | |
884 | interrupts = <GIC_PPI 9 0xf04>; | |
885 | }; | |
886 | ||
f6db7029 YL |
887 | usbphy: phy { |
888 | compatible = "rockchip,rk3288-usb-phy"; | |
889 | rockchip,grf = <&grf>; | |
890 | #address-cells = <1>; | |
891 | #size-cells = <0>; | |
892 | status = "disabled"; | |
893 | ||
894 | usbphy0: usb-phy0 { | |
895 | #phy-cells = <0>; | |
896 | reg = <0x320>; | |
897 | clocks = <&cru SCLK_OTGPHY0>; | |
898 | clock-names = "phyclk"; | |
899 | }; | |
900 | ||
901 | usbphy1: usb-phy1 { | |
902 | #phy-cells = <0>; | |
903 | reg = <0x334>; | |
904 | clocks = <&cru SCLK_OTGPHY1>; | |
905 | clock-names = "phyclk"; | |
906 | }; | |
907 | ||
908 | usbphy2: usb-phy2 { | |
909 | #phy-cells = <0>; | |
910 | reg = <0x348>; | |
911 | clocks = <&cru SCLK_OTGPHY2>; | |
912 | clock-names = "phyclk"; | |
913 | }; | |
914 | }; | |
915 | ||
2ab557b7 HS |
916 | pinctrl: pinctrl { |
917 | compatible = "rockchip,rk3288-pinctrl"; | |
918 | rockchip,grf = <&grf>; | |
919 | rockchip,pmu = <&pmu>; | |
920 | #address-cells = <1>; | |
921 | #size-cells = <1>; | |
922 | ranges; | |
923 | ||
924 | gpio0: gpio0@ff750000 { | |
925 | compatible = "rockchip,gpio-bank"; | |
926 | reg = <0xff750000 0x100>; | |
927 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
928 | clocks = <&cru PCLK_GPIO0>; | |
929 | ||
930 | gpio-controller; | |
931 | #gpio-cells = <2>; | |
932 | ||
933 | interrupt-controller; | |
934 | #interrupt-cells = <2>; | |
935 | }; | |
936 | ||
937 | gpio1: gpio1@ff780000 { | |
938 | compatible = "rockchip,gpio-bank"; | |
939 | reg = <0xff780000 0x100>; | |
940 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
941 | clocks = <&cru PCLK_GPIO1>; | |
942 | ||
943 | gpio-controller; | |
944 | #gpio-cells = <2>; | |
945 | ||
946 | interrupt-controller; | |
947 | #interrupt-cells = <2>; | |
948 | }; | |
949 | ||
950 | gpio2: gpio2@ff790000 { | |
951 | compatible = "rockchip,gpio-bank"; | |
952 | reg = <0xff790000 0x100>; | |
953 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
954 | clocks = <&cru PCLK_GPIO2>; | |
955 | ||
956 | gpio-controller; | |
957 | #gpio-cells = <2>; | |
958 | ||
959 | interrupt-controller; | |
960 | #interrupt-cells = <2>; | |
961 | }; | |
962 | ||
963 | gpio3: gpio3@ff7a0000 { | |
964 | compatible = "rockchip,gpio-bank"; | |
965 | reg = <0xff7a0000 0x100>; | |
966 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
967 | clocks = <&cru PCLK_GPIO3>; | |
968 | ||
969 | gpio-controller; | |
970 | #gpio-cells = <2>; | |
971 | ||
972 | interrupt-controller; | |
973 | #interrupt-cells = <2>; | |
974 | }; | |
975 | ||
976 | gpio4: gpio4@ff7b0000 { | |
977 | compatible = "rockchip,gpio-bank"; | |
978 | reg = <0xff7b0000 0x100>; | |
979 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
980 | clocks = <&cru PCLK_GPIO4>; | |
981 | ||
982 | gpio-controller; | |
983 | #gpio-cells = <2>; | |
984 | ||
985 | interrupt-controller; | |
986 | #interrupt-cells = <2>; | |
987 | }; | |
988 | ||
989 | gpio5: gpio5@ff7c0000 { | |
990 | compatible = "rockchip,gpio-bank"; | |
991 | reg = <0xff7c0000 0x100>; | |
992 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
993 | clocks = <&cru PCLK_GPIO5>; | |
994 | ||
995 | gpio-controller; | |
996 | #gpio-cells = <2>; | |
997 | ||
998 | interrupt-controller; | |
999 | #interrupt-cells = <2>; | |
1000 | }; | |
1001 | ||
1002 | gpio6: gpio6@ff7d0000 { | |
1003 | compatible = "rockchip,gpio-bank"; | |
1004 | reg = <0xff7d0000 0x100>; | |
1005 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
1006 | clocks = <&cru PCLK_GPIO6>; | |
1007 | ||
1008 | gpio-controller; | |
1009 | #gpio-cells = <2>; | |
1010 | ||
1011 | interrupt-controller; | |
1012 | #interrupt-cells = <2>; | |
1013 | }; | |
1014 | ||
1015 | gpio7: gpio7@ff7e0000 { | |
1016 | compatible = "rockchip,gpio-bank"; | |
1017 | reg = <0xff7e0000 0x100>; | |
1018 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
1019 | clocks = <&cru PCLK_GPIO7>; | |
1020 | ||
1021 | gpio-controller; | |
1022 | #gpio-cells = <2>; | |
1023 | ||
1024 | interrupt-controller; | |
1025 | #interrupt-cells = <2>; | |
1026 | }; | |
1027 | ||
1028 | gpio8: gpio8@ff7f0000 { | |
1029 | compatible = "rockchip,gpio-bank"; | |
1030 | reg = <0xff7f0000 0x100>; | |
1031 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
1032 | clocks = <&cru PCLK_GPIO8>; | |
1033 | ||
1034 | gpio-controller; | |
1035 | #gpio-cells = <2>; | |
1036 | ||
1037 | interrupt-controller; | |
1038 | #interrupt-cells = <2>; | |
1039 | }; | |
1040 | ||
e61ccb12 DA |
1041 | hdmi { |
1042 | hdmi_ddc: hdmi-ddc { | |
1043 | rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, | |
1044 | <7 20 RK_FUNC_2 &pcfg_pull_none>; | |
1045 | }; | |
1046 | }; | |
1047 | ||
2ab557b7 HS |
1048 | pcfg_pull_up: pcfg-pull-up { |
1049 | bias-pull-up; | |
1050 | }; | |
1051 | ||
1052 | pcfg_pull_down: pcfg-pull-down { | |
1053 | bias-pull-down; | |
1054 | }; | |
1055 | ||
1056 | pcfg_pull_none: pcfg-pull-none { | |
1057 | bias-disable; | |
1058 | }; | |
1059 | ||
3d3fb74a RC |
1060 | pcfg_pull_none_12ma: pcfg-pull-none-12ma { |
1061 | bias-disable; | |
1062 | drive-strength = <12>; | |
1063 | }; | |
1064 | ||
eecfe981 CZ |
1065 | sleep { |
1066 | global_pwroff: global-pwroff { | |
1067 | rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; | |
1068 | }; | |
1069 | ||
1070 | ddrio_pwroff: ddrio-pwroff { | |
1071 | rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; | |
1072 | }; | |
1073 | ||
1074 | ddr0_retention: ddr0-retention { | |
1075 | rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; | |
1076 | }; | |
1077 | ||
1078 | ddr1_retention: ddr1-retention { | |
1079 | rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; | |
1080 | }; | |
1081 | }; | |
1082 | ||
2ab557b7 HS |
1083 | i2c0 { |
1084 | i2c0_xfer: i2c0-xfer { | |
1085 | rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, | |
1086 | <0 16 RK_FUNC_1 &pcfg_pull_none>; | |
1087 | }; | |
1088 | }; | |
1089 | ||
1090 | i2c1 { | |
1091 | i2c1_xfer: i2c1-xfer { | |
1092 | rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, | |
1093 | <8 5 RK_FUNC_1 &pcfg_pull_none>; | |
1094 | }; | |
1095 | }; | |
1096 | ||
1097 | i2c2 { | |
1098 | i2c2_xfer: i2c2-xfer { | |
1099 | rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, | |
1100 | <6 10 RK_FUNC_1 &pcfg_pull_none>; | |
1101 | }; | |
1102 | }; | |
1103 | ||
1104 | i2c3 { | |
1105 | i2c3_xfer: i2c3-xfer { | |
1106 | rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, | |
1107 | <2 17 RK_FUNC_1 &pcfg_pull_none>; | |
1108 | }; | |
1109 | }; | |
1110 | ||
1111 | i2c4 { | |
1112 | i2c4_xfer: i2c4-xfer { | |
1113 | rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, | |
1114 | <7 18 RK_FUNC_1 &pcfg_pull_none>; | |
1115 | }; | |
1116 | }; | |
1117 | ||
1118 | i2c5 { | |
1119 | i2c5_xfer: i2c5-xfer { | |
1120 | rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, | |
1121 | <7 20 RK_FUNC_1 &pcfg_pull_none>; | |
a0f95e35 J |
1122 | }; |
1123 | }; | |
1124 | ||
1125 | i2s0 { | |
1126 | i2s0_bus: i2s0-bus { | |
1127 | rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, | |
1128 | <6 1 RK_FUNC_1 &pcfg_pull_none>, | |
1129 | <6 2 RK_FUNC_1 &pcfg_pull_none>, | |
1130 | <6 3 RK_FUNC_1 &pcfg_pull_none>, | |
1131 | <6 4 RK_FUNC_1 &pcfg_pull_none>, | |
1132 | <6 8 RK_FUNC_1 &pcfg_pull_none>; | |
2ab557b7 HS |
1133 | }; |
1134 | }; | |
1135 | ||
1136 | sdmmc { | |
1137 | sdmmc_clk: sdmmc-clk { | |
1138 | rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; | |
1139 | }; | |
1140 | ||
1141 | sdmmc_cmd: sdmmc-cmd { | |
1142 | rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; | |
1143 | }; | |
1144 | ||
1145 | sdmmc_cd: sdmcc-cd { | |
1146 | rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; | |
1147 | }; | |
1148 | ||
1149 | sdmmc_bus1: sdmmc-bus1 { | |
1150 | rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; | |
1151 | }; | |
1152 | ||
1153 | sdmmc_bus4: sdmmc-bus4 { | |
1154 | rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, | |
1155 | <6 17 RK_FUNC_1 &pcfg_pull_up>, | |
1156 | <6 18 RK_FUNC_1 &pcfg_pull_up>, | |
1157 | <6 19 RK_FUNC_1 &pcfg_pull_up>; | |
1158 | }; | |
1159 | }; | |
1160 | ||
f1a07231 AK |
1161 | sdio0 { |
1162 | sdio0_bus1: sdio0-bus1 { | |
1163 | rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; | |
1164 | }; | |
1165 | ||
1166 | sdio0_bus4: sdio0-bus4 { | |
1167 | rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, | |
1168 | <4 21 RK_FUNC_1 &pcfg_pull_up>, | |
1169 | <4 22 RK_FUNC_1 &pcfg_pull_up>, | |
1170 | <4 23 RK_FUNC_1 &pcfg_pull_up>; | |
1171 | }; | |
1172 | ||
1173 | sdio0_cmd: sdio0-cmd { | |
1174 | rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; | |
1175 | }; | |
1176 | ||
1177 | sdio0_clk: sdio0-clk { | |
1178 | rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; | |
1179 | }; | |
1180 | ||
1181 | sdio0_cd: sdio0-cd { | |
1182 | rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; | |
1183 | }; | |
1184 | ||
1185 | sdio0_wp: sdio0-wp { | |
1186 | rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; | |
1187 | }; | |
1188 | ||
1189 | sdio0_pwr: sdio0-pwr { | |
1190 | rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; | |
1191 | }; | |
1192 | ||
1193 | sdio0_bkpwr: sdio0-bkpwr { | |
1194 | rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; | |
1195 | }; | |
1196 | ||
1197 | sdio0_int: sdio0-int { | |
1198 | rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; | |
1199 | }; | |
1200 | }; | |
1201 | ||
1202 | sdio1 { | |
1203 | sdio1_bus1: sdio1-bus1 { | |
1204 | rockchip,pins = <3 24 4 &pcfg_pull_up>; | |
1205 | }; | |
1206 | ||
1207 | sdio1_bus4: sdio1-bus4 { | |
1208 | rockchip,pins = <3 24 4 &pcfg_pull_up>, | |
1209 | <3 25 4 &pcfg_pull_up>, | |
1210 | <3 26 4 &pcfg_pull_up>, | |
1211 | <3 27 4 &pcfg_pull_up>; | |
1212 | }; | |
1213 | ||
1214 | sdio1_cd: sdio1-cd { | |
1215 | rockchip,pins = <3 28 4 &pcfg_pull_up>; | |
1216 | }; | |
1217 | ||
1218 | sdio1_wp: sdio1-wp { | |
1219 | rockchip,pins = <3 29 4 &pcfg_pull_up>; | |
1220 | }; | |
1221 | ||
1222 | sdio1_bkpwr: sdio1-bkpwr { | |
1223 | rockchip,pins = <3 30 4 &pcfg_pull_up>; | |
1224 | }; | |
1225 | ||
1226 | sdio1_int: sdio1-int { | |
1227 | rockchip,pins = <3 31 4 &pcfg_pull_up>; | |
1228 | }; | |
1229 | ||
1230 | sdio1_cmd: sdio1-cmd { | |
1231 | rockchip,pins = <4 6 4 &pcfg_pull_up>; | |
1232 | }; | |
1233 | ||
1234 | sdio1_clk: sdio1-clk { | |
1235 | rockchip,pins = <4 7 4 &pcfg_pull_none>; | |
1236 | }; | |
1237 | ||
1238 | sdio1_pwr: sdio1-pwr { | |
1239 | rockchip,pins = <4 9 4 &pcfg_pull_up>; | |
1240 | }; | |
1241 | }; | |
1242 | ||
2ab557b7 HS |
1243 | emmc { |
1244 | emmc_clk: emmc-clk { | |
1245 | rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; | |
1246 | }; | |
1247 | ||
1248 | emmc_cmd: emmc-cmd { | |
1249 | rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; | |
1250 | }; | |
1251 | ||
1252 | emmc_pwr: emmc-pwr { | |
1253 | rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; | |
1254 | }; | |
1255 | ||
1256 | emmc_bus1: emmc-bus1 { | |
1257 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; | |
1258 | }; | |
1259 | ||
1260 | emmc_bus4: emmc-bus4 { | |
1261 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, | |
1262 | <3 1 RK_FUNC_2 &pcfg_pull_up>, | |
1263 | <3 2 RK_FUNC_2 &pcfg_pull_up>, | |
1264 | <3 3 RK_FUNC_2 &pcfg_pull_up>; | |
1265 | }; | |
1266 | ||
1267 | emmc_bus8: emmc-bus8 { | |
1268 | rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, | |
1269 | <3 1 RK_FUNC_2 &pcfg_pull_up>, | |
1270 | <3 2 RK_FUNC_2 &pcfg_pull_up>, | |
1271 | <3 3 RK_FUNC_2 &pcfg_pull_up>, | |
1272 | <3 4 RK_FUNC_2 &pcfg_pull_up>, | |
1273 | <3 5 RK_FUNC_2 &pcfg_pull_up>, | |
1274 | <3 6 RK_FUNC_2 &pcfg_pull_up>, | |
1275 | <3 7 RK_FUNC_2 &pcfg_pull_up>; | |
1276 | }; | |
1277 | }; | |
1278 | ||
1f53170b | 1279 | spi0 { |
1280 | spi0_clk: spi0-clk { | |
1281 | rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; | |
1282 | }; | |
1283 | spi0_cs0: spi0-cs0 { | |
1284 | rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; | |
1285 | }; | |
1286 | spi0_tx: spi0-tx { | |
1287 | rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; | |
1288 | }; | |
1289 | spi0_rx: spi0-rx { | |
1290 | rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; | |
1291 | }; | |
1292 | spi0_cs1: spi0-cs1 { | |
1293 | rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; | |
1294 | }; | |
1295 | }; | |
1296 | spi1 { | |
1297 | spi1_clk: spi1-clk { | |
1298 | rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; | |
1299 | }; | |
1300 | spi1_cs0: spi1-cs0 { | |
1301 | rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; | |
1302 | }; | |
1303 | spi1_rx: spi1-rx { | |
1304 | rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; | |
1305 | }; | |
1306 | spi1_tx: spi1-tx { | |
1307 | rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; | |
1308 | }; | |
1309 | }; | |
1310 | ||
1311 | spi2 { | |
1312 | spi2_cs1: spi2-cs1 { | |
1313 | rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; | |
1314 | }; | |
1315 | spi2_clk: spi2-clk { | |
1316 | rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; | |
1317 | }; | |
1318 | spi2_cs0: spi2-cs0 { | |
1319 | rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; | |
1320 | }; | |
1321 | spi2_rx: spi2-rx { | |
1322 | rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; | |
1323 | }; | |
1324 | spi2_tx: spi2-tx { | |
1325 | rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; | |
1326 | }; | |
1327 | }; | |
1328 | ||
2ab557b7 HS |
1329 | uart0 { |
1330 | uart0_xfer: uart0-xfer { | |
1331 | rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, | |
1332 | <4 17 RK_FUNC_1 &pcfg_pull_none>; | |
1333 | }; | |
1334 | ||
1335 | uart0_cts: uart0-cts { | |
8915f364 | 1336 | rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>; |
2ab557b7 HS |
1337 | }; |
1338 | ||
1339 | uart0_rts: uart0-rts { | |
1340 | rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; | |
1341 | }; | |
1342 | }; | |
1343 | ||
1344 | uart1 { | |
1345 | uart1_xfer: uart1-xfer { | |
1346 | rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, | |
1347 | <5 9 RK_FUNC_1 &pcfg_pull_none>; | |
1348 | }; | |
1349 | ||
1350 | uart1_cts: uart1-cts { | |
8915f364 | 1351 | rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>; |
2ab557b7 HS |
1352 | }; |
1353 | ||
1354 | uart1_rts: uart1-rts { | |
1355 | rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; | |
1356 | }; | |
1357 | }; | |
1358 | ||
1359 | uart2 { | |
1360 | uart2_xfer: uart2-xfer { | |
1361 | rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, | |
1362 | <7 23 RK_FUNC_1 &pcfg_pull_none>; | |
1363 | }; | |
1364 | /* no rts / cts for uart2 */ | |
1365 | }; | |
1366 | ||
1367 | uart3 { | |
1368 | uart3_xfer: uart3-xfer { | |
1369 | rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, | |
1370 | <7 8 RK_FUNC_1 &pcfg_pull_none>; | |
1371 | }; | |
1372 | ||
1373 | uart3_cts: uart3-cts { | |
8915f364 | 1374 | rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>; |
2ab557b7 HS |
1375 | }; |
1376 | ||
1377 | uart3_rts: uart3-rts { | |
1378 | rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; | |
1379 | }; | |
1380 | }; | |
1381 | ||
1382 | uart4 { | |
1383 | uart4_xfer: uart4-xfer { | |
1384 | rockchip,pins = <5 12 3 &pcfg_pull_up>, | |
1385 | <5 13 3 &pcfg_pull_none>; | |
1386 | }; | |
1387 | ||
1388 | uart4_cts: uart4-cts { | |
8915f364 | 1389 | rockchip,pins = <5 14 3 &pcfg_pull_up>; |
2ab557b7 HS |
1390 | }; |
1391 | ||
1392 | uart4_rts: uart4-rts { | |
1393 | rockchip,pins = <5 15 3 &pcfg_pull_none>; | |
1394 | }; | |
1395 | }; | |
df542df3 | 1396 | |
b67d6bc3 CW |
1397 | tsadc { |
1398 | otp_out: otp-out { | |
1399 | rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; | |
1400 | }; | |
1401 | }; | |
1402 | ||
df542df3 DA |
1403 | pwm0 { |
1404 | pwm0_pin: pwm0-pin { | |
1405 | rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; | |
1406 | }; | |
1407 | }; | |
1408 | ||
1409 | pwm1 { | |
1410 | pwm1_pin: pwm1-pin { | |
1411 | rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; | |
1412 | }; | |
1413 | }; | |
1414 | ||
1415 | pwm2 { | |
1416 | pwm2_pin: pwm2-pin { | |
1417 | rockchip,pins = <7 22 3 &pcfg_pull_none>; | |
1418 | }; | |
1419 | }; | |
1420 | ||
1421 | pwm3 { | |
1422 | pwm3_pin: pwm3-pin { | |
1423 | rockchip,pins = <7 23 3 &pcfg_pull_none>; | |
1424 | }; | |
1425 | }; | |
3d3fb74a RC |
1426 | |
1427 | gmac { | |
1428 | rgmii_pins: rgmii-pins { | |
1429 | rockchip,pins = <3 30 3 &pcfg_pull_none>, | |
1430 | <3 31 3 &pcfg_pull_none>, | |
1431 | <3 26 3 &pcfg_pull_none>, | |
1432 | <3 27 3 &pcfg_pull_none>, | |
1433 | <3 28 3 &pcfg_pull_none_12ma>, | |
1434 | <3 29 3 &pcfg_pull_none_12ma>, | |
1435 | <3 24 3 &pcfg_pull_none_12ma>, | |
1436 | <3 25 3 &pcfg_pull_none_12ma>, | |
1437 | <4 0 3 &pcfg_pull_none>, | |
1438 | <4 5 3 &pcfg_pull_none>, | |
1439 | <4 6 3 &pcfg_pull_none>, | |
1440 | <4 9 3 &pcfg_pull_none_12ma>, | |
1441 | <4 4 3 &pcfg_pull_none_12ma>, | |
1442 | <4 1 3 &pcfg_pull_none>, | |
1443 | <4 3 3 &pcfg_pull_none>; | |
1444 | }; | |
1445 | ||
1446 | rmii_pins: rmii-pins { | |
1447 | rockchip,pins = <3 30 3 &pcfg_pull_none>, | |
1448 | <3 31 3 &pcfg_pull_none>, | |
1449 | <3 28 3 &pcfg_pull_none>, | |
1450 | <3 29 3 &pcfg_pull_none>, | |
1451 | <4 0 3 &pcfg_pull_none>, | |
1452 | <4 5 3 &pcfg_pull_none>, | |
1453 | <4 4 3 &pcfg_pull_none>, | |
1454 | <4 1 3 &pcfg_pull_none>, | |
1455 | <4 2 3 &pcfg_pull_none>, | |
1456 | <4 3 3 &pcfg_pull_none>; | |
1457 | }; | |
1458 | }; | |
874e568e SS |
1459 | |
1460 | spdif { | |
1461 | spdif_tx: spdif-tx { | |
1462 | rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>; | |
1463 | }; | |
1464 | }; | |
2ab557b7 HS |
1465 | }; |
1466 | }; |