projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branches 'amba', 'fixes', 'misc' and 'tauros2' into for-next
[deliverable/linux.git] / arch / arm / boot / dts / rk3288.dtsi
CommitLineData
2ab557b7 1/*
b1772506
HS		 2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
2ab557b7 6 *
b1772506
HS		 7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
2ab557b7
HS		 39 */
40
41#include <dt-bindings/gpio/gpio.h>
42#include <dt-bindings/interrupt-controller/irq.h>
43#include <dt-bindings/interrupt-controller/arm-gic.h>
44#include <dt-bindings/pinctrl/rockchip.h>
45#include <dt-bindings/clock/rk3288-cru.h>
b67d6bc3 46#include <dt-bindings/thermal/thermal.h>
b63af764 47#include <dt-bindings/power/rk3288-power.h>
2ab557b7
HS		 48#include "skeleton.dtsi"
49
50/ {
51 compatible = "rockchip,rk3288";
52
53 interrupt-parent = <&gic>;
54
55 aliases {
85ef8d61 56 ethernet0 = &gmac;
2ab557b7
HS		 57 i2c0 = &i2c0;
58 i2c1 = &i2c1;
59 i2c2 = &i2c2;
60 i2c3 = &i2c3;
61 i2c4 = &i2c4;
62 i2c5 = &i2c5;
d7f9a388
DA		 63 mshc0 = &emmc;
64 mshc1 = &sdmmc;
65 mshc2 = &sdio0;
66 mshc3 = &sdio1;
2ab557b7
HS		 67 serial0 = &uart0;
68 serial1 = &uart1;
69 serial2 = &uart2;
70 serial3 = &uart3;
71 serial4 = &uart4;
1f53170b 72 spi0 = &spi0;
73 spi1 = &spi1;
74 spi2 = &spi2;
2ab557b7
HS		 75 };
76
f1840780
SR		 77 arm-pmu {
78 compatible = "arm,cortex-a12-pmu";
79 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
4863dcd3 83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
f1840780
SR		 84 };
85
2ab557b7
HS		 86 cpus {
87 #address-cells = <1>;
88 #size-cells = <0>;
08bcc754 89 enable-method = "rockchip,rk3066-smp";
fbdbc732 90 rockchip,pmu = <&pmu>;
2ab557b7 91
be8a77c5 92 cpu0: cpu@500 {
2ab557b7
HS		 93 device_type = "cpu";
94 compatible = "arm,cortex-a12";
95 reg = <0x500>;
044542af 96 resets = <&cru SRST_CORE0>;
be8a77c5
HS		 97 operating-points = <
98 /* KHz uV */
99 1608000 1350000
100 1512000 1300000
101 1416000 1200000
102 1200000 1100000
103 1008000 1050000
104 816000 1000000
105 696000 950000
106 600000 900000
107 408000 900000
108 312000 900000
109 216000 900000
110 126000 900000
111 >;
b67d6bc3 112 #cooling-cells = <2>; /* min followed by max */
be8a77c5
HS		 113 clock-latency = <40000>;
114 clocks = <&cru ARMCLK>;
2ab557b7 115 };
4863dcd3 116 cpu1: cpu@501 {
2ab557b7
HS		 117 device_type = "cpu";
118 compatible = "arm,cortex-a12";
119 reg = <0x501>;
044542af 120 resets = <&cru SRST_CORE1>;
2ab557b7 121 };
4863dcd3 122 cpu2: cpu@502 {
2ab557b7
HS		 123 device_type = "cpu";
124 compatible = "arm,cortex-a12";
125 reg = <0x502>;
044542af 126 resets = <&cru SRST_CORE2>;
2ab557b7 127 };
4863dcd3 128 cpu3: cpu@503 {
2ab557b7
HS		 129 device_type = "cpu";
130 compatible = "arm,cortex-a12";
131 reg = <0x503>;
044542af 132 resets = <&cru SRST_CORE3>;
2ab557b7
HS		 133 };
134 };
135
982891c3
HS		 136 amba {
137 compatible = "arm,amba-bus";
138 #address-cells = <1>;
139 #size-cells = <1>;
140 ranges;
141
142 dmac_peri: dma-controller@ff250000 {
143 compatible = "arm,pl330", "arm,primecell";
144 reg = <0xff250000 0x4000>;
145 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
147 #dma-cells = <1>;
148 clocks = <&cru ACLK_DMAC2>;
149 clock-names = "apb_pclk";
150 };
151
152 dmac_bus_ns: dma-controller@ff600000 {
153 compatible = "arm,pl330", "arm,primecell";
154 reg = <0xff600000 0x4000>;
155 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
157 #dma-cells = <1>;
158 clocks = <&cru ACLK_DMAC1>;
159 clock-names = "apb_pclk";
160 status = "disabled";
161 };
162
163 dmac_bus_s: dma-controller@ffb20000 {
164 compatible = "arm,pl330", "arm,primecell";
165 reg = <0xffb20000 0x4000>;
166 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
168 #dma-cells = <1>;
169 clocks = <&cru ACLK_DMAC1>;
170 clock-names = "apb_pclk";
171 };
172 };
173
b21bcfc9
HS		 174 reserved-memory {
175 #address-cells = <1>;
176 #size-cells = <1>;
177 ranges;
178
179 /*
180 * The rk3288 cannot use the memory area above 0xfe000000
181 * for dma operations for some reason. While there is
182 * probably a better solution available somewhere, we
183 * haven't found it yet and while devices with 2GB of ram
184 * are not affected, this issue prevents 4GB from booting.
185 * So to make these devices at least bootable, block
186 * this area for the time being until the real solution
187 * is found.
188 */
189 dma-unusable@fe000000 {
190 reg = <0xfe000000 0x1000000>;
191 };
192 };
193
2ab557b7
HS		 194 xin24m: oscillator {
195 compatible = "fixed-clock";
196 clock-frequency = <24000000>;
197 clock-output-names = "xin24m";
198 #clock-cells = <0>;
199 };
200
201 timer {
202 compatible = "arm,armv7-timer";
e2405a59 203 arm,cpu-registers-not-fw-configured;
2ab557b7
HS		 204 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
206 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
208 clock-frequency = <24000000>;
209 };
210
e48cc181
DL		 211 timer: timer@ff810000 {
212 compatible = "rockchip,rk3288-timer";
213 reg = <0xff810000 0x20>;
214 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&xin24m>, <&cru PCLK_TIMER>;
216 clock-names = "timer", "pclk";
217 };
218
a29cb8c4
DK		 219 display-subsystem {
220 compatible = "rockchip,display-subsystem";
221 ports = <&vopl_out>, <&vopb_out>;
222 };
223
85095bf3
DA		 224 sdmmc: dwmmc@ff0c0000 {
225 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 226 clock-freq-min-max = <400000 150000000>;
f71ddc58
AS		 227 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
228 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
229 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
85095bf3
DA		 230 fifo-depth = <0x100>;
231 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
232 reg = <0xff0c0000 0x4000>;
233 status = "disabled";
234 };
235
f1a07231
AK		 236 sdio0: dwmmc@ff0d0000 {
237 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 238 clock-freq-min-max = <400000 150000000>;
f71ddc58
AS		 239 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
240 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
241 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
f1a07231
AK		 242 fifo-depth = <0x100>;
243 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
244 reg = <0xff0d0000 0x4000>;
245 status = "disabled";
246 };
247
248 sdio1: dwmmc@ff0e0000 {
249 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 250 clock-freq-min-max = <400000 150000000>;
f71ddc58
AS		 251 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
252 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
253 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
f1a07231
AK		 254 fifo-depth = <0x100>;
255 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
256 reg = <0xff0e0000 0x4000>;
257 status = "disabled";
258 };
259
85095bf3
DA		 260 emmc: dwmmc@ff0f0000 {
261 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 262 clock-freq-min-max = <400000 150000000>;
f71ddc58
AS		 263 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
264 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
265 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
85095bf3
DA		 266 fifo-depth = <0x100>;
267 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
268 reg = <0xff0f0000 0x4000>;
269 status = "disabled";
270 };
271
f23a6179
HS		 272 saradc: saradc@ff100000 {
273 compatible = "rockchip,saradc";
274 reg = <0xff100000 0x100>;
275 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
276 #io-channel-cells = <1>;
277 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
278 clock-names = "saradc", "apb_pclk";
279 status = "disabled";
280 };
281
1f53170b 282 spi0: spi@ff110000 {
283 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
284 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
285 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 286 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
287 dma-names = "tx", "rx";
1f53170b 288 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
291 reg = <0xff110000 0x1000>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 status = "disabled";
295 };
296
297 spi1: spi@ff120000 {
298 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
299 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
300 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 301 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
302 dma-names = "tx", "rx";
1f53170b 303 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
306 reg = <0xff120000 0x1000>;
307 #address-cells = <1>;
308 #size-cells = <0>;
309 status = "disabled";
310 };
311
312 spi2: spi@ff130000 {
313 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
314 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
315 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 316 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
317 dma-names = "tx", "rx";
1f53170b 318 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
321 reg = <0xff130000 0x1000>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 status = "disabled";
325 };
326
2ab557b7
HS		 327 i2c1: i2c@ff140000 {
328 compatible = "rockchip,rk3288-i2c";
329 reg = <0xff140000 0x1000>;
330 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333 clock-names = "i2c";
334 clocks = <&cru PCLK_I2C1>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&i2c1_xfer>;
337 status = "disabled";
338 };
339
340 i2c3: i2c@ff150000 {
341 compatible = "rockchip,rk3288-i2c";
342 reg = <0xff150000 0x1000>;
343 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 clock-names = "i2c";
347 clocks = <&cru PCLK_I2C3>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c3_xfer>;
350 status = "disabled";
351 };
352
353 i2c4: i2c@ff160000 {
354 compatible = "rockchip,rk3288-i2c";
355 reg = <0xff160000 0x1000>;
356 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
357 #address-cells = <1>;
358 #size-cells = <0>;
359 clock-names = "i2c";
360 clocks = <&cru PCLK_I2C4>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&i2c4_xfer>;
363 status = "disabled";
364 };
365
366 i2c5: i2c@ff170000 {
367 compatible = "rockchip,rk3288-i2c";
368 reg = <0xff170000 0x1000>;
369 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 clock-names = "i2c";
373 clocks = <&cru PCLK_I2C5>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&i2c5_xfer>;
376 status = "disabled";
377 };
378
379 uart0: serial@ff180000 {
380 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
381 reg = <0xff180000 0x100>;
382 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
383 reg-shift = <2>;
384 reg-io-width = <4>;
385 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
386 clock-names = "baudclk", "apb_pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&uart0_xfer>;
389 status = "disabled";
390 };
391
392 uart1: serial@ff190000 {
393 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
394 reg = <0xff190000 0x100>;
395 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
396 reg-shift = <2>;
397 reg-io-width = <4>;
398 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
399 clock-names = "baudclk", "apb_pclk";
400 pinctrl-names = "default";
401 pinctrl-0 = <&uart1_xfer>;
402 status = "disabled";
403 };
404
405 uart2: serial@ff690000 {
406 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
407 reg = <0xff690000 0x100>;
408 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
409 reg-shift = <2>;
410 reg-io-width = <4>;
411 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
412 clock-names = "baudclk", "apb_pclk";
413 pinctrl-names = "default";
414 pinctrl-0 = <&uart2_xfer>;
415 status = "disabled";
416 };
417
418 uart3: serial@ff1b0000 {
419 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
420 reg = <0xff1b0000 0x100>;
421 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
422 reg-shift = <2>;
423 reg-io-width = <4>;
424 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
425 clock-names = "baudclk", "apb_pclk";
426 pinctrl-names = "default";
427 pinctrl-0 = <&uart3_xfer>;
428 status = "disabled";
429 };
430
431 uart4: serial@ff1c0000 {
432 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
433 reg = <0xff1c0000 0x100>;
434 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
435 reg-shift = <2>;
436 reg-io-width = <4>;
437 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
438 clock-names = "baudclk", "apb_pclk";
439 pinctrl-names = "default";
440 pinctrl-0 = <&uart4_xfer>;
441 status = "disabled";
442 };
443
b67d6bc3
CW		 444 thermal-zones {
445 #include "rk3288-thermal.dtsi"
446 };
447
448 tsadc: tsadc@ff280000 {
449 compatible = "rockchip,rk3288-tsadc";
450 reg = <0xff280000 0x100>;
451 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
453 clock-names = "tsadc", "apb_pclk";
454 resets = <&cru SRST_TSADC>;
455 reset-names = "tsadc-apb";
784359b8
CW		 456 pinctrl-names = "init", "default", "sleep";
457 pinctrl-0 = <&otp_gpio>;
458 pinctrl-1 = <&otp_out>;
459 pinctrl-2 = <&otp_gpio>;
b67d6bc3
CW		 460 #thermal-sensor-cells = <1>;
461 rockchip,hw-tshut-temp = <95000>;
462 status = "disabled";
463 };
464
3d3fb74a
RC		 465 gmac: ethernet@ff290000 {
466 compatible = "rockchip,rk3288-gmac";
467 reg = <0xff290000 0x10000>;
468 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
469 interrupt-names = "macirq";
470 rockchip,grf = <&grf>;
471 clocks = <&cru SCLK_MAC>,
472 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
473 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
474 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
475 clock-names = "stmmaceth",
476 "mac_clk_rx", "mac_clk_tx",
477 "clk_mac_ref", "clk_mac_refout",
478 "aclk_mac", "pclk_mac";
e6b54649
RP		 479 resets = <&cru SRST_MAC>;
480 reset-names = "stmmaceth";
54b0bc60 481 status = "disabled";
3d3fb74a
RC		 482 };
483
c9c32c50
DA		 484 usb_host0_ehci: usb@ff500000 {
485 compatible = "generic-ehci";
486 reg = <0xff500000 0x100>;
487 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&cru HCLK_USBHOST0>;
489 clock-names = "usbhost";
f6db7029
YL		 490 phys = <&usbphy1>;
491 phy-names = "usb";
c9c32c50
DA		 492 status = "disabled";
493 };
494
495 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
496
12dd3653
KY		 497 usb_host1: usb@ff540000 {
498 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
499 "snps,dwc2";
500 reg = <0xff540000 0x40000>;
501 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&cru HCLK_USBHOST1>;
503 clock-names = "otg";
cabd2ea2 504 dr_mode = "host";
f6db7029
YL		 505 phys = <&usbphy2>;
506 phy-names = "usb2-phy";
12dd3653
KY		 507 status = "disabled";
508 };
509
510 usb_otg: usb@ff580000 {
511 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
512 "snps,dwc2";
513 reg = <0xff580000 0x40000>;
514 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&cru HCLK_OTG0>;
516 clock-names = "otg";
cabd2ea2
YL		 517 dr_mode = "otg";
518 g-np-tx-fifo-size = <16>;
519 g-rx-fifo-size = <275>;
520 g-tx-fifo-size = <256 128 128 64 64 32>;
521 g-use-dma;
f6db7029
YL		 522 phys = <&usbphy0>;
523 phy-names = "usb2-phy";
12dd3653
KY		 524 status = "disabled";
525 };
526
c9c32c50
DA		 527 usb_hsic: usb@ff5c0000 {
528 compatible = "generic-ehci";
529 reg = <0xff5c0000 0x100>;
530 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&cru HCLK_HSIC>;
532 clock-names = "usbhost";
533 status = "disabled";
534 };
535
2ab557b7
HS		 536 i2c0: i2c@ff650000 {
537 compatible = "rockchip,rk3288-i2c";
538 reg = <0xff650000 0x1000>;
539 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
540 #address-cells = <1>;
541 #size-cells = <0>;
542 clock-names = "i2c";
543 clocks = <&cru PCLK_I2C0>;
544 pinctrl-names = "default";
545 pinctrl-0 = <&i2c0_xfer>;
546 status = "disabled";
547 };
548
549 i2c2: i2c@ff660000 {
550 compatible = "rockchip,rk3288-i2c";
551 reg = <0xff660000 0x1000>;
552 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 clock-names = "i2c";
556 clocks = <&cru PCLK_I2C2>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&i2c2_xfer>;
559 status = "disabled";
560 };
561
df542df3
DA		 562 pwm0: pwm@ff680000 {
563 compatible = "rockchip,rk3288-pwm";
564 reg = <0xff680000 0x10>;
565 #pwm-cells = <3>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&pwm0_pin>;
568 clocks = <&cru PCLK_PWM>;
569 clock-names = "pwm";
570 status = "disabled";
571 };
572
573 pwm1: pwm@ff680010 {
574 compatible = "rockchip,rk3288-pwm";
575 reg = <0xff680010 0x10>;
576 #pwm-cells = <3>;
577 pinctrl-names = "default";
578 pinctrl-0 = <&pwm1_pin>;
579 clocks = <&cru PCLK_PWM>;
580 clock-names = "pwm";
581 status = "disabled";
582 };
583
584 pwm2: pwm@ff680020 {
585 compatible = "rockchip,rk3288-pwm";
586 reg = <0xff680020 0x10>;
587 #pwm-cells = <3>;
588 pinctrl-names = "default";
589 pinctrl-0 = <&pwm2_pin>;
590 clocks = <&cru PCLK_PWM>;
591 clock-names = "pwm";
592 status = "disabled";
593 };
594
595 pwm3: pwm@ff680030 {
596 compatible = "rockchip,rk3288-pwm";
597 reg = <0xff680030 0x10>;
598 #pwm-cells = <2>;
599 pinctrl-names = "default";
600 pinctrl-0 = <&pwm3_pin>;
601 clocks = <&cru PCLK_PWM>;
602 clock-names = "pwm";
603 status = "disabled";
604 };
605
1123d412
KY		 606 bus_intmem@ff700000 {
607 compatible = "mmio-sram";
608 reg = <0xff700000 0x18000>;
609 #address-cells = <1>;
610 #size-cells = <1>;
611 ranges = <0 0xff700000 0x18000>;
612 smp-sram@0 {
613 compatible = "rockchip,rk3066-smp-sram";
614 reg = <0x00 0x10>;
615 };
616 };
617
eecfe981
CZ		 618 sram@ff720000 {
619 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
620 reg = <0xff720000 0x1000>;
621 };
622
2ab557b7 623 pmu: power-management@ff730000 {
b63af764 624 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
2ab557b7 625 reg = <0xff730000 0x100>;
b63af764
CW		 626
627 power: power-controller {
628 compatible = "rockchip,rk3288-power-controller";
629 #power-domain-cells = <1>;
630 #address-cells = <1>;
631 #size-cells = <0>;
632
633 /*
634 * Note: Although SCLK_* are the working clocks
635 * of device without including on the NOC, needed for
636 * synchronous reset.
637 *
638 * The clocks on the which NOC:
639 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
640 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
641 * ACLK_RGA is on ACLK_RGA_NIU.
642 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
643 *
644 * Which clock are device clocks:
645 * clocks devices
646 * *_IEP IEP:Image Enhancement Processor
647 * *_ISP ISP:Image Signal Processing
648 * *_VIP VIP:Video Input Processor
649 * *_VOP* VOP:Visual Output Processor
650 * *_RGA RGA
651 * *_EDP* EDP
652 * *_LVDS_* LVDS
653 * *_HDMI HDMI
654 * *_MIPI_* MIPI
655 */
656 pd_vio {
657 reg = <RK3288_PD_VIO>;
658 clocks = <&cru ACLK_IEP>,
659 <&cru ACLK_ISP>,
660 <&cru ACLK_RGA>,
661 <&cru ACLK_VIP>,
662 <&cru ACLK_VOP0>,
663 <&cru ACLK_VOP1>,
664 <&cru DCLK_VOP0>,
665 <&cru DCLK_VOP1>,
666 <&cru HCLK_IEP>,
667 <&cru HCLK_ISP>,
668 <&cru HCLK_RGA>,
669 <&cru HCLK_VIP>,
670 <&cru HCLK_VOP0>,
671 <&cru HCLK_VOP1>,
672 <&cru PCLK_EDP_CTRL>,
673 <&cru PCLK_HDMI_CTRL>,
674 <&cru PCLK_LVDS_PHY>,
675 <&cru PCLK_MIPI_CSI>,
676 <&cru PCLK_MIPI_DSI0>,
677 <&cru PCLK_MIPI_DSI1>,
678 <&cru SCLK_EDP_24M>,
679 <&cru SCLK_EDP>,
680 <&cru SCLK_ISP_JPE>,
681 <&cru SCLK_ISP>,
682 <&cru SCLK_RGA>;
683 };
684
685 /*
686 * Note: The following 3 are HEVC(H.265) clocks,
687 * and on the ACLK_HEVC_NIU (NOC).
688 */
689 pd_hevc {
690 reg = <RK3288_PD_HEVC>;
691 clocks = <&cru ACLK_HEVC>,
692 <&cru SCLK_HEVC_CABAC>,
693 <&cru SCLK_HEVC_CORE>;
694 };
695
696 /*
697 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
698 * (video endecoder & decoder) clocks that on the
699 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
700 */
701 pd_video {
702 reg = <RK3288_PD_VIDEO>;
703 clocks = <&cru ACLK_VCODEC>,
704 <&cru HCLK_VCODEC>;
705 };
706
707 /*
708 * Note: ACLK_GPU is the GPU clock,
709 * and on the ACLK_GPU_NIU (NOC).
710 */
711 pd_gpu {
712 reg = <RK3288_PD_GPU>;
713 clocks = <&cru ACLK_GPU>;
714 };
715 };
2ab557b7
HS		 716 };
717
718 sgrf: syscon@ff740000 {
719 compatible = "rockchip,rk3288-sgrf", "syscon";
720 reg = <0xff740000 0x1000>;
721 };
722
723 cru: clock-controller@ff760000 {
724 compatible = "rockchip,rk3288-cru";
725 reg = <0xff760000 0x1000>;
726 rockchip,grf = <&grf>;
727 #clock-cells = <1>;
728 #reset-cells = <1>;
cd78d0cd
KY		 729 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
730 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
731 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
732 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
733 <&cru PCLK_PERI>;
734 assigned-clock-rates = <594000000>, <400000000>,
735 <500000000>, <300000000>,
736 <150000000>, <75000000>,
737 <300000000>, <150000000>,
738 <75000000>;
2ab557b7
HS		 739 };
740
741 grf: syscon@ff770000 {
742 compatible = "rockchip,rk3288-grf", "syscon";
743 reg = <0xff770000 0x1000>;
744 };
745
746 wdt: watchdog@ff800000 {
747 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
748 reg = <0xff800000 0x100>;
39d05162 749 clocks = <&cru PCLK_WDT>;
1a1b698b 750 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
2ab557b7
HS		 751 status = "disabled";
752 };
753
874e568e
SS		 754 spdif: sound@ff88b0000 {
755 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
756 reg = <0xff8b0000 0x10000>;
757 #sound-dai-cells = <0>;
758 clock-names = "hclk", "mclk";
759 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
760 dmas = <&dmac_bus_s 3>;
761 dma-names = "tx";
762 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
763 pinctrl-names = "default";
764 pinctrl-0 = <&spdif_tx>;
765 rockchip,grf = <&grf>;
766 status = "disabled";
767 };
768
a0f95e35
J		 769 i2s: i2s@ff890000 {
770 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
771 reg = <0xff890000 0x10000>;
772 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
773 #address-cells = <1>;
774 #size-cells = <0>;
775 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
776 dma-names = "tx", "rx";
777 clock-names = "i2s_hclk", "i2s_clk";
778 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&i2s0_bus>;
e241657d
SZ		 781 rockchip,playback-channels = <8>;
782 rockchip,capture-channels = <2>;
a0f95e35
J		 783 status = "disabled";
784 };
785
c2cb6161
ZW		 786 crypto: cypto-controller@ff8a0000 {
787 compatible = "rockchip,rk3288-crypto";
788 reg = <0xff8a0000 0x4000>;
789 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
791 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
792 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
793 resets = <&cru SRST_CRYPTO>;
794 reset-names = "crypto-rst";
795 status = "okay";
796 };
797
a29cb8c4
DK		 798 vopb: vop@ff930000 {
799 compatible = "rockchip,rk3288-vop";
800 reg = <0xff930000 0x19c>;
801 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
803 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
b63af764 804 power-domains = <&power RK3288_PD_VIO>;
a29cb8c4
DK		 805 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
806 reset-names = "axi", "ahb", "dclk";
807 iommus = <&vopb_mmu>;
808 status = "disabled";
809
810 vopb_out: port {
811 #address-cells = <1>;
812 #size-cells = <0>;
d5a1df48
AY		 813
814 vopb_out_hdmi: endpoint@0 {
815 reg = <0>;
816 remote-endpoint = <&hdmi_in_vopb>;
817 };
a29cb8c4
DK		 818 };
819 };
820
7cae068b
DK		 821 vopb_mmu: iommu@ff930300 {
822 compatible = "rockchip,iommu";
823 reg = <0xff930300 0x100>;
824 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
825 interrupt-names = "vopb_mmu";
b63af764 826 power-domains = <&power RK3288_PD_VIO>;
7cae068b
DK		 827 #iommu-cells = <0>;
828 status = "disabled";
829 };
830
a29cb8c4
DK		 831 vopl: vop@ff940000 {
832 compatible = "rockchip,rk3288-vop";
833 reg = <0xff940000 0x19c>;
834 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
836 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
b63af764 837 power-domains = <&power RK3288_PD_VIO>;
a29cb8c4
DK		 838 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
839 reset-names = "axi", "ahb", "dclk";
840 iommus = <&vopl_mmu>;
841 status = "disabled";
842
843 vopl_out: port {
844 #address-cells = <1>;
845 #size-cells = <0>;
d5a1df48
AY		 846
847 vopl_out_hdmi: endpoint@0 {
848 reg = <0>;
849 remote-endpoint = <&hdmi_in_vopl>;
850 };
a29cb8c4
DK		 851 };
852 };
853
7cae068b
DK		 854 vopl_mmu: iommu@ff940300 {
855 compatible = "rockchip,iommu";
856 reg = <0xff940300 0x100>;
857 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
858 interrupt-names = "vopl_mmu";
b63af764 859 power-domains = <&power RK3288_PD_VIO>;
7cae068b
DK		 860 #iommu-cells = <0>;
861 status = "disabled";
862 };
863
d5a1df48
AY		 864 hdmi: hdmi@ff980000 {
865 compatible = "rockchip,rk3288-dw-hdmi";
866 reg = <0xff980000 0x20000>;
867 reg-io-width = <4>;
d5a1df48
AY		 868 rockchip,grf = <&grf>;
869 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
871 clock-names = "iahb", "isfr";
b63af764 872 power-domains = <&power RK3288_PD_VIO>;
d5a1df48
AY		 873 status = "disabled";
874
875 ports {
876 hdmi_in: port {
877 #address-cells = <1>;
878 #size-cells = <0>;
879 hdmi_in_vopb: endpoint@0 {
880 reg = <0>;
881 remote-endpoint = <&vopb_out_hdmi>;
882 };
883 hdmi_in_vopl: endpoint@1 {
884 reg = <1>;
885 remote-endpoint = <&vopl_out_hdmi>;
886 };
887 };
888 };
889 };
890
2ab557b7
HS		 891 gic: interrupt-controller@ffc01000 {
892 compatible = "arm,gic-400";
893 interrupt-controller;
894 #interrupt-cells = <3>;
895 #address-cells = <0>;
896
897 reg = <0xffc01000 0x1000>,
898 <0xffc02000 0x1000>,
899 <0xffc04000 0x2000>,
900 <0xffc06000 0x2000>;
901 interrupts = <GIC_PPI 9 0xf04>;
902 };
903
88185559
Z		 904 efuse: efuse@ffb40000 {
905 compatible = "rockchip,rockchip-efuse";
906 reg = <0xffb40000 0x20>;
907 #address-cells = <1>;
908 #size-cells = <1>;
909 clocks = <&cru PCLK_EFUSE256>;
910 clock-names = "pclk_efuse";
911
912 cpu_leakage: cpu_leakage@17 {
913 reg = <0x17 0x1>;
914 };
915 };
916
f6db7029
YL		 917 usbphy: phy {
918 compatible = "rockchip,rk3288-usb-phy";
919 rockchip,grf = <&grf>;
920 #address-cells = <1>;
921 #size-cells = <0>;
922 status = "disabled";
923
924 usbphy0: usb-phy0 {
925 #phy-cells = <0>;
926 reg = <0x320>;
927 clocks = <&cru SCLK_OTGPHY0>;
928 clock-names = "phyclk";
929 };
930
931 usbphy1: usb-phy1 {
932 #phy-cells = <0>;
933 reg = <0x334>;
934 clocks = <&cru SCLK_OTGPHY1>;
935 clock-names = "phyclk";
936 };
937
938 usbphy2: usb-phy2 {
939 #phy-cells = <0>;
940 reg = <0x348>;
941 clocks = <&cru SCLK_OTGPHY2>;
942 clock-names = "phyclk";
943 };
944 };
945
2ab557b7
HS		 946 pinctrl: pinctrl {
947 compatible = "rockchip,rk3288-pinctrl";
948 rockchip,grf = <&grf>;
949 rockchip,pmu = <&pmu>;
950 #address-cells = <1>;
951 #size-cells = <1>;
952 ranges;
953
954 gpio0: gpio0@ff750000 {
955 compatible = "rockchip,gpio-bank";
956 reg = <0xff750000 0x100>;
957 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&cru PCLK_GPIO0>;
959
960 gpio-controller;
961 #gpio-cells = <2>;
962
963 interrupt-controller;
964 #interrupt-cells = <2>;
965 };
966
967 gpio1: gpio1@ff780000 {
968 compatible = "rockchip,gpio-bank";
969 reg = <0xff780000 0x100>;
970 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&cru PCLK_GPIO1>;
972
973 gpio-controller;
974 #gpio-cells = <2>;
975
976 interrupt-controller;
977 #interrupt-cells = <2>;
978 };
979
980 gpio2: gpio2@ff790000 {
981 compatible = "rockchip,gpio-bank";
982 reg = <0xff790000 0x100>;
983 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&cru PCLK_GPIO2>;
985
986 gpio-controller;
987 #gpio-cells = <2>;
988
989 interrupt-controller;
990 #interrupt-cells = <2>;
991 };
992
993 gpio3: gpio3@ff7a0000 {
994 compatible = "rockchip,gpio-bank";
995 reg = <0xff7a0000 0x100>;
996 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&cru PCLK_GPIO3>;
998
999 gpio-controller;
1000 #gpio-cells = <2>;
1001
1002 interrupt-controller;
1003 #interrupt-cells = <2>;
1004 };
1005
1006 gpio4: gpio4@ff7b0000 {
1007 compatible = "rockchip,gpio-bank";
1008 reg = <0xff7b0000 0x100>;
1009 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&cru PCLK_GPIO4>;
1011
1012 gpio-controller;
1013 #gpio-cells = <2>;
1014
1015 interrupt-controller;
1016 #interrupt-cells = <2>;
1017 };
1018
1019 gpio5: gpio5@ff7c0000 {
1020 compatible = "rockchip,gpio-bank";
1021 reg = <0xff7c0000 0x100>;
1022 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&cru PCLK_GPIO5>;
1024
1025 gpio-controller;
1026 #gpio-cells = <2>;
1027
1028 interrupt-controller;
1029 #interrupt-cells = <2>;
1030 };
1031
1032 gpio6: gpio6@ff7d0000 {
1033 compatible = "rockchip,gpio-bank";
1034 reg = <0xff7d0000 0x100>;
1035 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&cru PCLK_GPIO6>;
1037
1038 gpio-controller;
1039 #gpio-cells = <2>;
1040
1041 interrupt-controller;
1042 #interrupt-cells = <2>;
1043 };
1044
1045 gpio7: gpio7@ff7e0000 {
1046 compatible = "rockchip,gpio-bank";
1047 reg = <0xff7e0000 0x100>;
1048 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&cru PCLK_GPIO7>;
1050
1051 gpio-controller;
1052 #gpio-cells = <2>;
1053
1054 interrupt-controller;
1055 #interrupt-cells = <2>;
1056 };
1057
1058 gpio8: gpio8@ff7f0000 {
1059 compatible = "rockchip,gpio-bank";
1060 reg = <0xff7f0000 0x100>;
1061 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1062 clocks = <&cru PCLK_GPIO8>;
1063
1064 gpio-controller;
1065 #gpio-cells = <2>;
1066
1067 interrupt-controller;
1068 #interrupt-cells = <2>;
1069 };
1070
e61ccb12
DA		 1071 hdmi {
1072 hdmi_ddc: hdmi-ddc {
1073 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1074 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1075 };
1076 };
1077
2ab557b7
HS		 1078 pcfg_pull_up: pcfg-pull-up {
1079 bias-pull-up;
1080 };
1081
1082 pcfg_pull_down: pcfg-pull-down {
1083 bias-pull-down;
1084 };
1085
1086 pcfg_pull_none: pcfg-pull-none {
1087 bias-disable;
1088 };
1089
3d3fb74a
RC		 1090 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1091 bias-disable;
1092 drive-strength = <12>;
1093 };
1094
eecfe981
CZ		 1095 sleep {
1096 global_pwroff: global-pwroff {
1097 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1098 };
1099
1100 ddrio_pwroff: ddrio-pwroff {
1101 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1102 };
1103
1104 ddr0_retention: ddr0-retention {
1105 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1106 };
1107
1108 ddr1_retention: ddr1-retention {
1109 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1110 };
1111 };
1112
2ab557b7
HS		 1113 i2c0 {
1114 i2c0_xfer: i2c0-xfer {
1115 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1116 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1117 };
1118 };
1119
1120 i2c1 {
1121 i2c1_xfer: i2c1-xfer {
1122 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1123 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1124 };
1125 };
1126
1127 i2c2 {
1128 i2c2_xfer: i2c2-xfer {
1129 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1130 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1131 };
1132 };
1133
1134 i2c3 {
1135 i2c3_xfer: i2c3-xfer {
1136 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1137 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1138 };
1139 };
1140
1141 i2c4 {
1142 i2c4_xfer: i2c4-xfer {
1143 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1144 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1145 };
1146 };
1147
1148 i2c5 {
1149 i2c5_xfer: i2c5-xfer {
1150 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1151 <7 20 RK_FUNC_1 &pcfg_pull_none>;
a0f95e35
J		 1152 };
1153 };
1154
1155 i2s0 {
1156 i2s0_bus: i2s0-bus {
1157 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1158 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1159 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1160 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1161 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1162 <6 8 RK_FUNC_1 &pcfg_pull_none>;
2ab557b7
HS		 1163 };
1164 };
1165
1166 sdmmc {
1167 sdmmc_clk: sdmmc-clk {
1168 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1169 };
1170
1171 sdmmc_cmd: sdmmc-cmd {
1172 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1173 };
1174
d59df5d1 1175 sdmmc_cd: sdmmc-cd {
2ab557b7
HS		 1176 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1177 };
1178
1179 sdmmc_bus1: sdmmc-bus1 {
1180 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1181 };
1182
1183 sdmmc_bus4: sdmmc-bus4 {
1184 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1185 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1186 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1187 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1188 };
1189 };
1190
f1a07231
AK		 1191 sdio0 {
1192 sdio0_bus1: sdio0-bus1 {
1193 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1194 };
1195
1196 sdio0_bus4: sdio0-bus4 {
1197 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1198 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1199 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1200 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1201 };
1202
1203 sdio0_cmd: sdio0-cmd {
1204 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1205 };
1206
1207 sdio0_clk: sdio0-clk {
1208 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1209 };
1210
1211 sdio0_cd: sdio0-cd {
1212 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1213 };
1214
1215 sdio0_wp: sdio0-wp {
1216 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1217 };
1218
1219 sdio0_pwr: sdio0-pwr {
1220 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1221 };
1222
1223 sdio0_bkpwr: sdio0-bkpwr {
1224 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1225 };
1226
1227 sdio0_int: sdio0-int {
1228 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1229 };
1230 };
1231
1232 sdio1 {
1233 sdio1_bus1: sdio1-bus1 {
1234 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1235 };
1236
1237 sdio1_bus4: sdio1-bus4 {
1238 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1239 <3 25 4 &pcfg_pull_up>,
1240 <3 26 4 &pcfg_pull_up>,
1241 <3 27 4 &pcfg_pull_up>;
1242 };
1243
1244 sdio1_cd: sdio1-cd {
1245 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1246 };
1247
1248 sdio1_wp: sdio1-wp {
1249 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1250 };
1251
1252 sdio1_bkpwr: sdio1-bkpwr {
1253 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1254 };
1255
1256 sdio1_int: sdio1-int {
1257 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1258 };
1259
1260 sdio1_cmd: sdio1-cmd {
1261 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1262 };
1263
1264 sdio1_clk: sdio1-clk {
1265 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1266 };
1267
1268 sdio1_pwr: sdio1-pwr {
1269 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1270 };
1271 };
1272
2ab557b7
HS		 1273 emmc {
1274 emmc_clk: emmc-clk {
1275 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1276 };
1277
1278 emmc_cmd: emmc-cmd {
1279 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1280 };
1281
1282 emmc_pwr: emmc-pwr {
1283 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1284 };
1285
1286 emmc_bus1: emmc-bus1 {
1287 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1288 };
1289
1290 emmc_bus4: emmc-bus4 {
1291 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1292 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1293 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1294 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1295 };
1296
1297 emmc_bus8: emmc-bus8 {
1298 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1299 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1300 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1301 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1302 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1303 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1304 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1305 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1306 };
1307 };
1308
1f53170b 1309 spi0 {
1310 spi0_clk: spi0-clk {
1311 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1312 };
1313 spi0_cs0: spi0-cs0 {
1314 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1315 };
1316 spi0_tx: spi0-tx {
1317 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1318 };
1319 spi0_rx: spi0-rx {
1320 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1321 };
1322 spi0_cs1: spi0-cs1 {
1323 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1324 };
1325 };
1326 spi1 {
1327 spi1_clk: spi1-clk {
1328 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1329 };
1330 spi1_cs0: spi1-cs0 {
1331 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1332 };
1333 spi1_rx: spi1-rx {
1334 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1335 };
1336 spi1_tx: spi1-tx {
1337 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1338 };
1339 };
1340
1341 spi2 {
1342 spi2_cs1: spi2-cs1 {
1343 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1344 };
1345 spi2_clk: spi2-clk {
1346 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1347 };
1348 spi2_cs0: spi2-cs0 {
1349 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1350 };
1351 spi2_rx: spi2-rx {
1352 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1353 };
1354 spi2_tx: spi2-tx {
1355 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1356 };
1357 };
1358
2ab557b7
HS		 1359 uart0 {
1360 uart0_xfer: uart0-xfer {
1361 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1362 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1363 };
1364
1365 uart0_cts: uart0-cts {
8915f364 1366 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
2ab557b7
HS		 1367 };
1368
1369 uart0_rts: uart0-rts {
1370 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1371 };
1372 };
1373
1374 uart1 {
1375 uart1_xfer: uart1-xfer {
1376 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1377 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1378 };
1379
1380 uart1_cts: uart1-cts {
8915f364 1381 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
2ab557b7
HS		 1382 };
1383
1384 uart1_rts: uart1-rts {
1385 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1386 };
1387 };
1388
1389 uart2 {
1390 uart2_xfer: uart2-xfer {
1391 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1392 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1393 };
1394 /* no rts / cts for uart2 */
1395 };
1396
1397 uart3 {
1398 uart3_xfer: uart3-xfer {
1399 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1400 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1401 };
1402
1403 uart3_cts: uart3-cts {
8915f364 1404 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
2ab557b7
HS		 1405 };
1406
1407 uart3_rts: uart3-rts {
1408 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1409 };
1410 };
1411
1412 uart4 {
1413 uart4_xfer: uart4-xfer {
1414 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1415 <5 13 3 &pcfg_pull_none>;
1416 };
1417
1418 uart4_cts: uart4-cts {
8915f364 1419 rockchip,pins = <5 14 3 &pcfg_pull_up>;
2ab557b7
HS		 1420 };
1421
1422 uart4_rts: uart4-rts {
1423 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1424 };
1425 };
df542df3 1426
b67d6bc3 1427 tsadc {
784359b8
CW		 1428 otp_gpio: otp-gpio {
1429 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1430 };
1431
b67d6bc3
CW		 1432 otp_out: otp-out {
1433 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1434 };
1435 };
1436
df542df3
DA		 1437 pwm0 {
1438 pwm0_pin: pwm0-pin {
1439 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1440 };
1441 };
1442
1443 pwm1 {
1444 pwm1_pin: pwm1-pin {
1445 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1446 };
1447 };
1448
1449 pwm2 {
1450 pwm2_pin: pwm2-pin {
1451 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1452 };
1453 };
1454
1455 pwm3 {
1456 pwm3_pin: pwm3-pin {
1457 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1458 };
1459 };
3d3fb74a
RC		 1460
1461 gmac {
1462 rgmii_pins: rgmii-pins {
1463 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1464 <3 31 3 &pcfg_pull_none>,
1465 <3 26 3 &pcfg_pull_none>,
1466 <3 27 3 &pcfg_pull_none>,
1467 <3 28 3 &pcfg_pull_none_12ma>,
1468 <3 29 3 &pcfg_pull_none_12ma>,
1469 <3 24 3 &pcfg_pull_none_12ma>,
1470 <3 25 3 &pcfg_pull_none_12ma>,
1471 <4 0 3 &pcfg_pull_none>,
1472 <4 5 3 &pcfg_pull_none>,
1473 <4 6 3 &pcfg_pull_none>,
1474 <4 9 3 &pcfg_pull_none_12ma>,
1475 <4 4 3 &pcfg_pull_none_12ma>,
1476 <4 1 3 &pcfg_pull_none>,
1477 <4 3 3 &pcfg_pull_none>;
1478 };
1479
1480 rmii_pins: rmii-pins {
1481 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1482 <3 31 3 &pcfg_pull_none>,
1483 <3 28 3 &pcfg_pull_none>,
1484 <3 29 3 &pcfg_pull_none>,
1485 <4 0 3 &pcfg_pull_none>,
1486 <4 5 3 &pcfg_pull_none>,
1487 <4 4 3 &pcfg_pull_none>,
1488 <4 1 3 &pcfg_pull_none>,
1489 <4 2 3 &pcfg_pull_none>,
1490 <4 3 3 &pcfg_pull_none>;
1491 };
1492 };
874e568e
SS		 1493
1494 spdif {
1495 spdif_tx: spdif-tx {
1496 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1497 };
1498 };
2ab557b7
HS		 1499 };
1500};
Linux kernel - Deliverables
This page took 0.301473 seconds and 5 git commands to generate.