projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux...
[deliverable/linux.git] / arch / arm / boot / dts / rk3288.dtsi
CommitLineData
2ab557b7
HS		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/pinctrl/rockchip.h>
17#include <dt-bindings/clock/rk3288-cru.h>
b67d6bc3 18#include <dt-bindings/thermal/thermal.h>
2ab557b7
HS		 19#include "skeleton.dtsi"
20
21/ {
22 compatible = "rockchip,rk3288";
23
24 interrupt-parent = <&gic>;
25
26 aliases {
27 i2c0 = &i2c0;
28 i2c1 = &i2c1;
29 i2c2 = &i2c2;
30 i2c3 = &i2c3;
31 i2c4 = &i2c4;
32 i2c5 = &i2c5;
d7f9a388
DA		 33 mshc0 = &emmc;
34 mshc1 = &sdmmc;
35 mshc2 = &sdio0;
36 mshc3 = &sdio1;
2ab557b7
HS		 37 serial0 = &uart0;
38 serial1 = &uart1;
39 serial2 = &uart2;
40 serial3 = &uart3;
41 serial4 = &uart4;
1f53170b 42 spi0 = &spi0;
43 spi1 = &spi1;
44 spi2 = &spi2;
2ab557b7
HS		 45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
08bcc754 50 enable-method = "rockchip,rk3066-smp";
fbdbc732 51 rockchip,pmu = <&pmu>;
2ab557b7 52
be8a77c5 53 cpu0: cpu@500 {
2ab557b7
HS		 54 device_type = "cpu";
55 compatible = "arm,cortex-a12";
56 reg = <0x500>;
044542af 57 resets = <&cru SRST_CORE0>;
be8a77c5
HS		 58 operating-points = <
59 /* KHz uV */
60 1608000 1350000
61 1512000 1300000
62 1416000 1200000
63 1200000 1100000
64 1008000 1050000
65 816000 1000000
66 696000 950000
67 600000 900000
68 408000 900000
69 312000 900000
70 216000 900000
71 126000 900000
72 >;
b67d6bc3 73 #cooling-cells = <2>; /* min followed by max */
be8a77c5
HS		 74 clock-latency = <40000>;
75 clocks = <&cru ARMCLK>;
2ab557b7
HS		 76 };
77 cpu@501 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a12";
80 reg = <0x501>;
044542af 81 resets = <&cru SRST_CORE1>;
2ab557b7
HS		 82 };
83 cpu@502 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a12";
86 reg = <0x502>;
044542af 87 resets = <&cru SRST_CORE2>;
2ab557b7
HS		 88 };
89 cpu@503 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a12";
92 reg = <0x503>;
044542af 93 resets = <&cru SRST_CORE3>;
2ab557b7
HS		 94 };
95 };
96
982891c3
HS		 97 amba {
98 compatible = "arm,amba-bus";
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges;
102
103 dmac_peri: dma-controller@ff250000 {
104 compatible = "arm,pl330", "arm,primecell";
105 reg = <0xff250000 0x4000>;
106 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
108 #dma-cells = <1>;
109 clocks = <&cru ACLK_DMAC2>;
110 clock-names = "apb_pclk";
111 };
112
113 dmac_bus_ns: dma-controller@ff600000 {
114 compatible = "arm,pl330", "arm,primecell";
115 reg = <0xff600000 0x4000>;
116 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
118 #dma-cells = <1>;
119 clocks = <&cru ACLK_DMAC1>;
120 clock-names = "apb_pclk";
121 status = "disabled";
122 };
123
124 dmac_bus_s: dma-controller@ffb20000 {
125 compatible = "arm,pl330", "arm,primecell";
126 reg = <0xffb20000 0x4000>;
127 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
129 #dma-cells = <1>;
130 clocks = <&cru ACLK_DMAC1>;
131 clock-names = "apb_pclk";
132 };
133 };
134
2ab557b7
HS		 135 xin24m: oscillator {
136 compatible = "fixed-clock";
137 clock-frequency = <24000000>;
138 clock-output-names = "xin24m";
139 #clock-cells = <0>;
140 };
141
142 timer {
143 compatible = "arm,armv7-timer";
e2405a59 144 arm,cpu-registers-not-fw-configured;
2ab557b7
HS		 145 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
149 clock-frequency = <24000000>;
150 };
151
e48cc181
DL		 152 timer: timer@ff810000 {
153 compatible = "rockchip,rk3288-timer";
154 reg = <0xff810000 0x20>;
155 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&xin24m>, <&cru PCLK_TIMER>;
157 clock-names = "timer", "pclk";
158 };
159
a29cb8c4
DK		 160 display-subsystem {
161 compatible = "rockchip,display-subsystem";
162 ports = <&vopl_out>, <&vopb_out>;
163 };
164
85095bf3
DA		 165 sdmmc: dwmmc@ff0c0000 {
166 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 167 clock-freq-min-max = <400000 150000000>;
85095bf3
DA		 168 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
169 clock-names = "biu", "ciu";
170 fifo-depth = <0x100>;
171 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
172 reg = <0xff0c0000 0x4000>;
173 status = "disabled";
174 };
175
f1a07231
AK		 176 sdio0: dwmmc@ff0d0000 {
177 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 178 clock-freq-min-max = <400000 150000000>;
f1a07231
AK		 179 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
180 clock-names = "biu", "ciu";
181 fifo-depth = <0x100>;
182 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
183 reg = <0xff0d0000 0x4000>;
184 status = "disabled";
185 };
186
187 sdio1: dwmmc@ff0e0000 {
188 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 189 clock-freq-min-max = <400000 150000000>;
f1a07231
AK		 190 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
191 clock-names = "biu", "ciu";
192 fifo-depth = <0x100>;
193 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
194 reg = <0xff0e0000 0x4000>;
195 status = "disabled";
196 };
197
85095bf3
DA		 198 emmc: dwmmc@ff0f0000 {
199 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 200 clock-freq-min-max = <400000 150000000>;
85095bf3
DA		 201 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
202 clock-names = "biu", "ciu";
203 fifo-depth = <0x100>;
204 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
205 reg = <0xff0f0000 0x4000>;
206 status = "disabled";
207 };
208
f23a6179
HS		 209 saradc: saradc@ff100000 {
210 compatible = "rockchip,saradc";
211 reg = <0xff100000 0x100>;
212 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
213 #io-channel-cells = <1>;
214 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
215 clock-names = "saradc", "apb_pclk";
216 status = "disabled";
217 };
218
1f53170b 219 spi0: spi@ff110000 {
220 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
221 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
222 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 223 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
224 dma-names = "tx", "rx";
1f53170b 225 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
228 reg = <0xff110000 0x1000>;
229 #address-cells = <1>;
230 #size-cells = <0>;
231 status = "disabled";
232 };
233
234 spi1: spi@ff120000 {
235 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
236 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
237 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 238 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
239 dma-names = "tx", "rx";
1f53170b 240 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
243 reg = <0xff120000 0x1000>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246 status = "disabled";
247 };
248
249 spi2: spi@ff130000 {
250 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
251 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
252 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 253 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
254 dma-names = "tx", "rx";
1f53170b 255 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
258 reg = <0xff130000 0x1000>;
259 #address-cells = <1>;
260 #size-cells = <0>;
261 status = "disabled";
262 };
263
2ab557b7
HS		 264 i2c1: i2c@ff140000 {
265 compatible = "rockchip,rk3288-i2c";
266 reg = <0xff140000 0x1000>;
267 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
268 #address-cells = <1>;
269 #size-cells = <0>;
270 clock-names = "i2c";
271 clocks = <&cru PCLK_I2C1>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&i2c1_xfer>;
274 status = "disabled";
275 };
276
277 i2c3: i2c@ff150000 {
278 compatible = "rockchip,rk3288-i2c";
279 reg = <0xff150000 0x1000>;
280 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 clock-names = "i2c";
284 clocks = <&cru PCLK_I2C3>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&i2c3_xfer>;
287 status = "disabled";
288 };
289
290 i2c4: i2c@ff160000 {
291 compatible = "rockchip,rk3288-i2c";
292 reg = <0xff160000 0x1000>;
293 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
294 #address-cells = <1>;
295 #size-cells = <0>;
296 clock-names = "i2c";
297 clocks = <&cru PCLK_I2C4>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&i2c4_xfer>;
300 status = "disabled";
301 };
302
303 i2c5: i2c@ff170000 {
304 compatible = "rockchip,rk3288-i2c";
305 reg = <0xff170000 0x1000>;
306 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
307 #address-cells = <1>;
308 #size-cells = <0>;
309 clock-names = "i2c";
310 clocks = <&cru PCLK_I2C5>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&i2c5_xfer>;
313 status = "disabled";
314 };
315
316 uart0: serial@ff180000 {
317 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
318 reg = <0xff180000 0x100>;
319 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
320 reg-shift = <2>;
321 reg-io-width = <4>;
322 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
323 clock-names = "baudclk", "apb_pclk";
324 pinctrl-names = "default";
325 pinctrl-0 = <&uart0_xfer>;
326 status = "disabled";
327 };
328
329 uart1: serial@ff190000 {
330 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
331 reg = <0xff190000 0x100>;
332 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
333 reg-shift = <2>;
334 reg-io-width = <4>;
335 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
336 clock-names = "baudclk", "apb_pclk";
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart1_xfer>;
339 status = "disabled";
340 };
341
342 uart2: serial@ff690000 {
343 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
344 reg = <0xff690000 0x100>;
345 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
346 reg-shift = <2>;
347 reg-io-width = <4>;
348 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
349 clock-names = "baudclk", "apb_pclk";
350 pinctrl-names = "default";
351 pinctrl-0 = <&uart2_xfer>;
352 status = "disabled";
353 };
354
355 uart3: serial@ff1b0000 {
356 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
357 reg = <0xff1b0000 0x100>;
358 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
359 reg-shift = <2>;
360 reg-io-width = <4>;
361 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
362 clock-names = "baudclk", "apb_pclk";
363 pinctrl-names = "default";
364 pinctrl-0 = <&uart3_xfer>;
365 status = "disabled";
366 };
367
368 uart4: serial@ff1c0000 {
369 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
370 reg = <0xff1c0000 0x100>;
371 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
372 reg-shift = <2>;
373 reg-io-width = <4>;
374 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
375 clock-names = "baudclk", "apb_pclk";
376 pinctrl-names = "default";
377 pinctrl-0 = <&uart4_xfer>;
378 status = "disabled";
379 };
380
b67d6bc3
CW		 381 thermal-zones {
382 #include "rk3288-thermal.dtsi"
383 };
384
385 tsadc: tsadc@ff280000 {
386 compatible = "rockchip,rk3288-tsadc";
387 reg = <0xff280000 0x100>;
388 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
390 clock-names = "tsadc", "apb_pclk";
391 resets = <&cru SRST_TSADC>;
392 reset-names = "tsadc-apb";
393 pinctrl-names = "default";
394 pinctrl-0 = <&otp_out>;
395 #thermal-sensor-cells = <1>;
396 rockchip,hw-tshut-temp = <95000>;
397 status = "disabled";
398 };
399
3d3fb74a
RC		 400 gmac: ethernet@ff290000 {
401 compatible = "rockchip,rk3288-gmac";
402 reg = <0xff290000 0x10000>;
403 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
404 interrupt-names = "macirq";
405 rockchip,grf = <&grf>;
406 clocks = <&cru SCLK_MAC>,
407 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
408 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
409 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
410 clock-names = "stmmaceth",
411 "mac_clk_rx", "mac_clk_tx",
412 "clk_mac_ref", "clk_mac_refout",
413 "aclk_mac", "pclk_mac";
54b0bc60 414 status = "disabled";
3d3fb74a
RC		 415 };
416
c9c32c50
DA		 417 usb_host0_ehci: usb@ff500000 {
418 compatible = "generic-ehci";
419 reg = <0xff500000 0x100>;
420 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&cru HCLK_USBHOST0>;
422 clock-names = "usbhost";
423 status = "disabled";
424 };
425
426 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
427
12dd3653
KY		 428 usb_host1: usb@ff540000 {
429 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
430 "snps,dwc2";
431 reg = <0xff540000 0x40000>;
432 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&cru HCLK_USBHOST1>;
434 clock-names = "otg";
435 status = "disabled";
436 };
437
438 usb_otg: usb@ff580000 {
439 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
440 "snps,dwc2";
441 reg = <0xff580000 0x40000>;
442 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&cru HCLK_OTG0>;
444 clock-names = "otg";
445 status = "disabled";
446 };
447
c9c32c50
DA		 448 usb_hsic: usb@ff5c0000 {
449 compatible = "generic-ehci";
450 reg = <0xff5c0000 0x100>;
451 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&cru HCLK_HSIC>;
453 clock-names = "usbhost";
454 status = "disabled";
455 };
456
2ab557b7
HS		 457 i2c0: i2c@ff650000 {
458 compatible = "rockchip,rk3288-i2c";
459 reg = <0xff650000 0x1000>;
460 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
461 #address-cells = <1>;
462 #size-cells = <0>;
463 clock-names = "i2c";
464 clocks = <&cru PCLK_I2C0>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&i2c0_xfer>;
467 status = "disabled";
468 };
469
470 i2c2: i2c@ff660000 {
471 compatible = "rockchip,rk3288-i2c";
472 reg = <0xff660000 0x1000>;
473 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 clock-names = "i2c";
477 clocks = <&cru PCLK_I2C2>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&i2c2_xfer>;
480 status = "disabled";
481 };
482
df542df3
DA		 483 pwm0: pwm@ff680000 {
484 compatible = "rockchip,rk3288-pwm";
485 reg = <0xff680000 0x10>;
486 #pwm-cells = <3>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&pwm0_pin>;
489 clocks = <&cru PCLK_PWM>;
490 clock-names = "pwm";
491 status = "disabled";
492 };
493
494 pwm1: pwm@ff680010 {
495 compatible = "rockchip,rk3288-pwm";
496 reg = <0xff680010 0x10>;
497 #pwm-cells = <3>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&pwm1_pin>;
500 clocks = <&cru PCLK_PWM>;
501 clock-names = "pwm";
502 status = "disabled";
503 };
504
505 pwm2: pwm@ff680020 {
506 compatible = "rockchip,rk3288-pwm";
507 reg = <0xff680020 0x10>;
508 #pwm-cells = <3>;
509 pinctrl-names = "default";
510 pinctrl-0 = <&pwm2_pin>;
511 clocks = <&cru PCLK_PWM>;
512 clock-names = "pwm";
513 status = "disabled";
514 };
515
516 pwm3: pwm@ff680030 {
517 compatible = "rockchip,rk3288-pwm";
518 reg = <0xff680030 0x10>;
519 #pwm-cells = <2>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&pwm3_pin>;
522 clocks = <&cru PCLK_PWM>;
523 clock-names = "pwm";
524 status = "disabled";
525 };
526
1123d412
KY		 527 bus_intmem@ff700000 {
528 compatible = "mmio-sram";
529 reg = <0xff700000 0x18000>;
530 #address-cells = <1>;
531 #size-cells = <1>;
532 ranges = <0 0xff700000 0x18000>;
533 smp-sram@0 {
534 compatible = "rockchip,rk3066-smp-sram";
535 reg = <0x00 0x10>;
536 };
537 };
538
eecfe981
CZ		 539 sram@ff720000 {
540 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
541 reg = <0xff720000 0x1000>;
542 };
543
2ab557b7
HS		 544 pmu: power-management@ff730000 {
545 compatible = "rockchip,rk3288-pmu", "syscon";
546 reg = <0xff730000 0x100>;
547 };
548
549 sgrf: syscon@ff740000 {
550 compatible = "rockchip,rk3288-sgrf", "syscon";
551 reg = <0xff740000 0x1000>;
552 };
553
554 cru: clock-controller@ff760000 {
555 compatible = "rockchip,rk3288-cru";
556 reg = <0xff760000 0x1000>;
557 rockchip,grf = <&grf>;
558 #clock-cells = <1>;
559 #reset-cells = <1>;
cd78d0cd
KY		 560 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
561 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
562 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
563 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
564 <&cru PCLK_PERI>;
565 assigned-clock-rates = <594000000>, <400000000>,
566 <500000000>, <300000000>,
567 <150000000>, <75000000>,
568 <300000000>, <150000000>,
569 <75000000>;
2ab557b7
HS		 570 };
571
572 grf: syscon@ff770000 {
573 compatible = "rockchip,rk3288-grf", "syscon";
574 reg = <0xff770000 0x1000>;
575 };
576
577 wdt: watchdog@ff800000 {
578 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
579 reg = <0xff800000 0x100>;
39d05162 580 clocks = <&cru PCLK_WDT>;
2ab557b7
HS		 581 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
582 status = "disabled";
583 };
584
a0f95e35
J		 585 i2s: i2s@ff890000 {
586 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
587 reg = <0xff890000 0x10000>;
588 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
589 #address-cells = <1>;
590 #size-cells = <0>;
591 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
592 dma-names = "tx", "rx";
593 clock-names = "i2s_hclk", "i2s_clk";
594 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&i2s0_bus>;
597 status = "disabled";
598 };
599
a29cb8c4
DK		 600 vopb: vop@ff930000 {
601 compatible = "rockchip,rk3288-vop";
602 reg = <0xff930000 0x19c>;
603 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
605 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
606 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
607 reset-names = "axi", "ahb", "dclk";
608 iommus = <&vopb_mmu>;
609 status = "disabled";
610
611 vopb_out: port {
612 #address-cells = <1>;
613 #size-cells = <0>;
d5a1df48
AY		 614
615 vopb_out_hdmi: endpoint@0 {
616 reg = <0>;
617 remote-endpoint = <&hdmi_in_vopb>;
618 };
a29cb8c4
DK		 619 };
620 };
621
7cae068b
DK		 622 vopb_mmu: iommu@ff930300 {
623 compatible = "rockchip,iommu";
624 reg = <0xff930300 0x100>;
625 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
626 interrupt-names = "vopb_mmu";
627 #iommu-cells = <0>;
628 status = "disabled";
629 };
630
a29cb8c4
DK		 631 vopl: vop@ff940000 {
632 compatible = "rockchip,rk3288-vop";
633 reg = <0xff940000 0x19c>;
634 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
636 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
637 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
638 reset-names = "axi", "ahb", "dclk";
639 iommus = <&vopl_mmu>;
640 status = "disabled";
641
642 vopl_out: port {
643 #address-cells = <1>;
644 #size-cells = <0>;
d5a1df48
AY		 645
646 vopl_out_hdmi: endpoint@0 {
647 reg = <0>;
648 remote-endpoint = <&hdmi_in_vopl>;
649 };
a29cb8c4
DK		 650 };
651 };
652
7cae068b
DK		 653 vopl_mmu: iommu@ff940300 {
654 compatible = "rockchip,iommu";
655 reg = <0xff940300 0x100>;
656 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
657 interrupt-names = "vopl_mmu";
658 #iommu-cells = <0>;
659 status = "disabled";
660 };
661
d5a1df48
AY		 662 hdmi: hdmi@ff980000 {
663 compatible = "rockchip,rk3288-dw-hdmi";
664 reg = <0xff980000 0x20000>;
665 reg-io-width = <4>;
d5a1df48
AY		 666 rockchip,grf = <&grf>;
667 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
669 clock-names = "iahb", "isfr";
670 status = "disabled";
671
672 ports {
673 hdmi_in: port {
674 #address-cells = <1>;
675 #size-cells = <0>;
676 hdmi_in_vopb: endpoint@0 {
677 reg = <0>;
678 remote-endpoint = <&vopb_out_hdmi>;
679 };
680 hdmi_in_vopl: endpoint@1 {
681 reg = <1>;
682 remote-endpoint = <&vopl_out_hdmi>;
683 };
684 };
685 };
686 };
687
2ab557b7
HS		 688 gic: interrupt-controller@ffc01000 {
689 compatible = "arm,gic-400";
690 interrupt-controller;
691 #interrupt-cells = <3>;
692 #address-cells = <0>;
693
694 reg = <0xffc01000 0x1000>,
695 <0xffc02000 0x1000>,
696 <0xffc04000 0x2000>,
697 <0xffc06000 0x2000>;
698 interrupts = <GIC_PPI 9 0xf04>;
699 };
700
701 pinctrl: pinctrl {
702 compatible = "rockchip,rk3288-pinctrl";
703 rockchip,grf = <&grf>;
704 rockchip,pmu = <&pmu>;
705 #address-cells = <1>;
706 #size-cells = <1>;
707 ranges;
708
709 gpio0: gpio0@ff750000 {
710 compatible = "rockchip,gpio-bank";
711 reg = <0xff750000 0x100>;
712 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&cru PCLK_GPIO0>;
714
715 gpio-controller;
716 #gpio-cells = <2>;
717
718 interrupt-controller;
719 #interrupt-cells = <2>;
720 };
721
722 gpio1: gpio1@ff780000 {
723 compatible = "rockchip,gpio-bank";
724 reg = <0xff780000 0x100>;
725 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&cru PCLK_GPIO1>;
727
728 gpio-controller;
729 #gpio-cells = <2>;
730
731 interrupt-controller;
732 #interrupt-cells = <2>;
733 };
734
735 gpio2: gpio2@ff790000 {
736 compatible = "rockchip,gpio-bank";
737 reg = <0xff790000 0x100>;
738 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&cru PCLK_GPIO2>;
740
741 gpio-controller;
742 #gpio-cells = <2>;
743
744 interrupt-controller;
745 #interrupt-cells = <2>;
746 };
747
748 gpio3: gpio3@ff7a0000 {
749 compatible = "rockchip,gpio-bank";
750 reg = <0xff7a0000 0x100>;
751 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&cru PCLK_GPIO3>;
753
754 gpio-controller;
755 #gpio-cells = <2>;
756
757 interrupt-controller;
758 #interrupt-cells = <2>;
759 };
760
761 gpio4: gpio4@ff7b0000 {
762 compatible = "rockchip,gpio-bank";
763 reg = <0xff7b0000 0x100>;
764 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&cru PCLK_GPIO4>;
766
767 gpio-controller;
768 #gpio-cells = <2>;
769
770 interrupt-controller;
771 #interrupt-cells = <2>;
772 };
773
774 gpio5: gpio5@ff7c0000 {
775 compatible = "rockchip,gpio-bank";
776 reg = <0xff7c0000 0x100>;
777 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&cru PCLK_GPIO5>;
779
780 gpio-controller;
781 #gpio-cells = <2>;
782
783 interrupt-controller;
784 #interrupt-cells = <2>;
785 };
786
787 gpio6: gpio6@ff7d0000 {
788 compatible = "rockchip,gpio-bank";
789 reg = <0xff7d0000 0x100>;
790 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&cru PCLK_GPIO6>;
792
793 gpio-controller;
794 #gpio-cells = <2>;
795
796 interrupt-controller;
797 #interrupt-cells = <2>;
798 };
799
800 gpio7: gpio7@ff7e0000 {
801 compatible = "rockchip,gpio-bank";
802 reg = <0xff7e0000 0x100>;
803 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&cru PCLK_GPIO7>;
805
806 gpio-controller;
807 #gpio-cells = <2>;
808
809 interrupt-controller;
810 #interrupt-cells = <2>;
811 };
812
813 gpio8: gpio8@ff7f0000 {
814 compatible = "rockchip,gpio-bank";
815 reg = <0xff7f0000 0x100>;
816 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&cru PCLK_GPIO8>;
818
819 gpio-controller;
820 #gpio-cells = <2>;
821
822 interrupt-controller;
823 #interrupt-cells = <2>;
824 };
825
826 pcfg_pull_up: pcfg-pull-up {
827 bias-pull-up;
828 };
829
830 pcfg_pull_down: pcfg-pull-down {
831 bias-pull-down;
832 };
833
834 pcfg_pull_none: pcfg-pull-none {
835 bias-disable;
836 };
837
3d3fb74a
RC		 838 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
839 bias-disable;
840 drive-strength = <12>;
841 };
842
eecfe981
CZ		 843 sleep {
844 global_pwroff: global-pwroff {
845 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
846 };
847
848 ddrio_pwroff: ddrio-pwroff {
849 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
850 };
851
852 ddr0_retention: ddr0-retention {
853 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
854 };
855
856 ddr1_retention: ddr1-retention {
857 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
858 };
859 };
860
2ab557b7
HS		 861 i2c0 {
862 i2c0_xfer: i2c0-xfer {
863 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
864 <0 16 RK_FUNC_1 &pcfg_pull_none>;
865 };
866 };
867
868 i2c1 {
869 i2c1_xfer: i2c1-xfer {
870 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
871 <8 5 RK_FUNC_1 &pcfg_pull_none>;
872 };
873 };
874
875 i2c2 {
876 i2c2_xfer: i2c2-xfer {
877 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
878 <6 10 RK_FUNC_1 &pcfg_pull_none>;
879 };
880 };
881
882 i2c3 {
883 i2c3_xfer: i2c3-xfer {
884 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
885 <2 17 RK_FUNC_1 &pcfg_pull_none>;
886 };
887 };
888
889 i2c4 {
890 i2c4_xfer: i2c4-xfer {
891 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
892 <7 18 RK_FUNC_1 &pcfg_pull_none>;
893 };
894 };
895
896 i2c5 {
897 i2c5_xfer: i2c5-xfer {
898 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
899 <7 20 RK_FUNC_1 &pcfg_pull_none>;
a0f95e35
J		 900 };
901 };
902
903 i2s0 {
904 i2s0_bus: i2s0-bus {
905 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
906 <6 1 RK_FUNC_1 &pcfg_pull_none>,
907 <6 2 RK_FUNC_1 &pcfg_pull_none>,
908 <6 3 RK_FUNC_1 &pcfg_pull_none>,
909 <6 4 RK_FUNC_1 &pcfg_pull_none>,
910 <6 8 RK_FUNC_1 &pcfg_pull_none>;
2ab557b7
HS		 911 };
912 };
913
914 sdmmc {
915 sdmmc_clk: sdmmc-clk {
916 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
917 };
918
919 sdmmc_cmd: sdmmc-cmd {
920 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
921 };
922
923 sdmmc_cd: sdmcc-cd {
924 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
925 };
926
927 sdmmc_bus1: sdmmc-bus1 {
928 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
929 };
930
931 sdmmc_bus4: sdmmc-bus4 {
932 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
933 <6 17 RK_FUNC_1 &pcfg_pull_up>,
934 <6 18 RK_FUNC_1 &pcfg_pull_up>,
935 <6 19 RK_FUNC_1 &pcfg_pull_up>;
936 };
937 };
938
f1a07231
AK		 939 sdio0 {
940 sdio0_bus1: sdio0-bus1 {
941 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
942 };
943
944 sdio0_bus4: sdio0-bus4 {
945 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
946 <4 21 RK_FUNC_1 &pcfg_pull_up>,
947 <4 22 RK_FUNC_1 &pcfg_pull_up>,
948 <4 23 RK_FUNC_1 &pcfg_pull_up>;
949 };
950
951 sdio0_cmd: sdio0-cmd {
952 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
953 };
954
955 sdio0_clk: sdio0-clk {
956 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
957 };
958
959 sdio0_cd: sdio0-cd {
960 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
961 };
962
963 sdio0_wp: sdio0-wp {
964 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
965 };
966
967 sdio0_pwr: sdio0-pwr {
968 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
969 };
970
971 sdio0_bkpwr: sdio0-bkpwr {
972 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
973 };
974
975 sdio0_int: sdio0-int {
976 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
977 };
978 };
979
980 sdio1 {
981 sdio1_bus1: sdio1-bus1 {
982 rockchip,pins = <3 24 4 &pcfg_pull_up>;
983 };
984
985 sdio1_bus4: sdio1-bus4 {
986 rockchip,pins = <3 24 4 &pcfg_pull_up>,
987 <3 25 4 &pcfg_pull_up>,
988 <3 26 4 &pcfg_pull_up>,
989 <3 27 4 &pcfg_pull_up>;
990 };
991
992 sdio1_cd: sdio1-cd {
993 rockchip,pins = <3 28 4 &pcfg_pull_up>;
994 };
995
996 sdio1_wp: sdio1-wp {
997 rockchip,pins = <3 29 4 &pcfg_pull_up>;
998 };
999
1000 sdio1_bkpwr: sdio1-bkpwr {
1001 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1002 };
1003
1004 sdio1_int: sdio1-int {
1005 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1006 };
1007
1008 sdio1_cmd: sdio1-cmd {
1009 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1010 };
1011
1012 sdio1_clk: sdio1-clk {
1013 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1014 };
1015
1016 sdio1_pwr: sdio1-pwr {
1017 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1018 };
1019 };
1020
2ab557b7
HS		 1021 emmc {
1022 emmc_clk: emmc-clk {
1023 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1024 };
1025
1026 emmc_cmd: emmc-cmd {
1027 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1028 };
1029
1030 emmc_pwr: emmc-pwr {
1031 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1032 };
1033
1034 emmc_bus1: emmc-bus1 {
1035 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1036 };
1037
1038 emmc_bus4: emmc-bus4 {
1039 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1040 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1041 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1042 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1043 };
1044
1045 emmc_bus8: emmc-bus8 {
1046 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1047 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1048 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1049 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1050 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1051 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1052 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1053 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1054 };
1055 };
1056
1f53170b 1057 spi0 {
1058 spi0_clk: spi0-clk {
1059 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1060 };
1061 spi0_cs0: spi0-cs0 {
1062 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1063 };
1064 spi0_tx: spi0-tx {
1065 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1066 };
1067 spi0_rx: spi0-rx {
1068 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1069 };
1070 spi0_cs1: spi0-cs1 {
1071 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1072 };
1073 };
1074 spi1 {
1075 spi1_clk: spi1-clk {
1076 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1077 };
1078 spi1_cs0: spi1-cs0 {
1079 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1080 };
1081 spi1_rx: spi1-rx {
1082 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1083 };
1084 spi1_tx: spi1-tx {
1085 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1086 };
1087 };
1088
1089 spi2 {
1090 spi2_cs1: spi2-cs1 {
1091 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1092 };
1093 spi2_clk: spi2-clk {
1094 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1095 };
1096 spi2_cs0: spi2-cs0 {
1097 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1098 };
1099 spi2_rx: spi2-rx {
1100 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1101 };
1102 spi2_tx: spi2-tx {
1103 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1104 };
1105 };
1106
2ab557b7
HS		 1107 uart0 {
1108 uart0_xfer: uart0-xfer {
1109 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1110 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1111 };
1112
1113 uart0_cts: uart0-cts {
1114 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1115 };
1116
1117 uart0_rts: uart0-rts {
1118 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1119 };
1120 };
1121
1122 uart1 {
1123 uart1_xfer: uart1-xfer {
1124 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1125 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1126 };
1127
1128 uart1_cts: uart1-cts {
1129 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1130 };
1131
1132 uart1_rts: uart1-rts {
1133 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1134 };
1135 };
1136
1137 uart2 {
1138 uart2_xfer: uart2-xfer {
1139 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1140 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1141 };
1142 /* no rts / cts for uart2 */
1143 };
1144
1145 uart3 {
1146 uart3_xfer: uart3-xfer {
1147 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1148 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1149 };
1150
1151 uart3_cts: uart3-cts {
1152 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1153 };
1154
1155 uart3_rts: uart3-rts {
1156 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1157 };
1158 };
1159
1160 uart4 {
1161 uart4_xfer: uart4-xfer {
1162 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1163 <5 13 3 &pcfg_pull_none>;
1164 };
1165
1166 uart4_cts: uart4-cts {
1167 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1168 };
1169
1170 uart4_rts: uart4-rts {
1171 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1172 };
1173 };
df542df3 1174
b67d6bc3
CW		 1175 tsadc {
1176 otp_out: otp-out {
1177 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1178 };
1179 };
1180
df542df3
DA		 1181 pwm0 {
1182 pwm0_pin: pwm0-pin {
1183 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1184 };
1185 };
1186
1187 pwm1 {
1188 pwm1_pin: pwm1-pin {
1189 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1190 };
1191 };
1192
1193 pwm2 {
1194 pwm2_pin: pwm2-pin {
1195 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1196 };
1197 };
1198
1199 pwm3 {
1200 pwm3_pin: pwm3-pin {
1201 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1202 };
1203 };
3d3fb74a
RC		 1204
1205 gmac {
1206 rgmii_pins: rgmii-pins {
1207 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1208 <3 31 3 &pcfg_pull_none>,
1209 <3 26 3 &pcfg_pull_none>,
1210 <3 27 3 &pcfg_pull_none>,
1211 <3 28 3 &pcfg_pull_none_12ma>,
1212 <3 29 3 &pcfg_pull_none_12ma>,
1213 <3 24 3 &pcfg_pull_none_12ma>,
1214 <3 25 3 &pcfg_pull_none_12ma>,
1215 <4 0 3 &pcfg_pull_none>,
1216 <4 5 3 &pcfg_pull_none>,
1217 <4 6 3 &pcfg_pull_none>,
1218 <4 9 3 &pcfg_pull_none_12ma>,
1219 <4 4 3 &pcfg_pull_none_12ma>,
1220 <4 1 3 &pcfg_pull_none>,
1221 <4 3 3 &pcfg_pull_none>;
1222 };
1223
1224 rmii_pins: rmii-pins {
1225 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1226 <3 31 3 &pcfg_pull_none>,
1227 <3 28 3 &pcfg_pull_none>,
1228 <3 29 3 &pcfg_pull_none>,
1229 <4 0 3 &pcfg_pull_none>,
1230 <4 5 3 &pcfg_pull_none>,
1231 <4 4 3 &pcfg_pull_none>,
1232 <4 1 3 &pcfg_pull_none>,
1233 <4 2 3 &pcfg_pull_none>,
1234 <4 3 3 &pcfg_pull_none>;
1235 };
1236 };
2ab557b7
HS		 1237 };
1238};
Linux kernel - Deliverables
This page took 0.149888 seconds and 5 git commands to generate.