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ARM: dts: rockchip: add suspend settings for rk3288-evb-rk808
[deliverable/linux.git] / arch / arm / boot / dts / rk3288.dtsi
CommitLineData
2ab557b7
HS		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/pinctrl/rockchip.h>
17#include <dt-bindings/clock/rk3288-cru.h>
b67d6bc3 18#include <dt-bindings/thermal/thermal.h>
2ab557b7
HS		 19#include "skeleton.dtsi"
20
21/ {
22 compatible = "rockchip,rk3288";
23
24 interrupt-parent = <&gic>;
25
26 aliases {
27 i2c0 = &i2c0;
28 i2c1 = &i2c1;
29 i2c2 = &i2c2;
30 i2c3 = &i2c3;
31 i2c4 = &i2c4;
32 i2c5 = &i2c5;
d7f9a388
DA		 33 mshc0 = &emmc;
34 mshc1 = &sdmmc;
35 mshc2 = &sdio0;
36 mshc3 = &sdio1;
2ab557b7
HS		 37 serial0 = &uart0;
38 serial1 = &uart1;
39 serial2 = &uart2;
40 serial3 = &uart3;
41 serial4 = &uart4;
1f53170b 42 spi0 = &spi0;
43 spi1 = &spi1;
44 spi2 = &spi2;
2ab557b7
HS		 45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
08bcc754 50 enable-method = "rockchip,rk3066-smp";
fbdbc732 51 rockchip,pmu = <&pmu>;
2ab557b7 52
be8a77c5 53 cpu0: cpu@500 {
2ab557b7
HS		 54 device_type = "cpu";
55 compatible = "arm,cortex-a12";
56 reg = <0x500>;
044542af 57 resets = <&cru SRST_CORE0>;
be8a77c5
HS		 58 operating-points = <
59 /* KHz uV */
60 1608000 1350000
61 1512000 1300000
62 1416000 1200000
63 1200000 1100000
64 1008000 1050000
65 816000 1000000
66 696000 950000
67 600000 900000
68 408000 900000
69 312000 900000
70 216000 900000
71 126000 900000
72 >;
b67d6bc3 73 #cooling-cells = <2>; /* min followed by max */
be8a77c5
HS		 74 clock-latency = <40000>;
75 clocks = <&cru ARMCLK>;
2ab557b7
HS		 76 };
77 cpu@501 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a12";
80 reg = <0x501>;
044542af 81 resets = <&cru SRST_CORE1>;
2ab557b7
HS		 82 };
83 cpu@502 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a12";
86 reg = <0x502>;
044542af 87 resets = <&cru SRST_CORE2>;
2ab557b7
HS		 88 };
89 cpu@503 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a12";
92 reg = <0x503>;
044542af 93 resets = <&cru SRST_CORE3>;
2ab557b7
HS		 94 };
95 };
96
982891c3
HS		 97 amba {
98 compatible = "arm,amba-bus";
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges;
102
103 dmac_peri: dma-controller@ff250000 {
104 compatible = "arm,pl330", "arm,primecell";
105 reg = <0xff250000 0x4000>;
106 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
108 #dma-cells = <1>;
109 clocks = <&cru ACLK_DMAC2>;
110 clock-names = "apb_pclk";
111 };
112
113 dmac_bus_ns: dma-controller@ff600000 {
114 compatible = "arm,pl330", "arm,primecell";
115 reg = <0xff600000 0x4000>;
116 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
118 #dma-cells = <1>;
119 clocks = <&cru ACLK_DMAC1>;
120 clock-names = "apb_pclk";
121 status = "disabled";
122 };
123
124 dmac_bus_s: dma-controller@ffb20000 {
125 compatible = "arm,pl330", "arm,primecell";
126 reg = <0xffb20000 0x4000>;
127 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
129 #dma-cells = <1>;
130 clocks = <&cru ACLK_DMAC1>;
131 clock-names = "apb_pclk";
132 };
133 };
134
2ab557b7
HS		 135 xin24m: oscillator {
136 compatible = "fixed-clock";
137 clock-frequency = <24000000>;
138 clock-output-names = "xin24m";
139 #clock-cells = <0>;
140 };
141
142 timer {
143 compatible = "arm,armv7-timer";
e2405a59 144 arm,cpu-registers-not-fw-configured;
2ab557b7
HS		 145 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
149 clock-frequency = <24000000>;
150 };
151
85095bf3
DA		 152 sdmmc: dwmmc@ff0c0000 {
153 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 154 clock-freq-min-max = <400000 150000000>;
85095bf3
DA		 155 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
156 clock-names = "biu", "ciu";
157 fifo-depth = <0x100>;
158 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
159 reg = <0xff0c0000 0x4000>;
160 status = "disabled";
161 };
162
f1a07231
AK		 163 sdio0: dwmmc@ff0d0000 {
164 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 165 clock-freq-min-max = <400000 150000000>;
f1a07231
AK		 166 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
167 clock-names = "biu", "ciu";
168 fifo-depth = <0x100>;
169 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
170 reg = <0xff0d0000 0x4000>;
171 status = "disabled";
172 };
173
174 sdio1: dwmmc@ff0e0000 {
175 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 176 clock-freq-min-max = <400000 150000000>;
f1a07231
AK		 177 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
178 clock-names = "biu", "ciu";
179 fifo-depth = <0x100>;
180 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
181 reg = <0xff0e0000 0x4000>;
182 status = "disabled";
183 };
184
85095bf3
DA		 185 emmc: dwmmc@ff0f0000 {
186 compatible = "rockchip,rk3288-dw-mshc";
f74ba117 187 clock-freq-min-max = <400000 150000000>;
85095bf3
DA		 188 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
189 clock-names = "biu", "ciu";
190 fifo-depth = <0x100>;
191 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
192 reg = <0xff0f0000 0x4000>;
193 status = "disabled";
194 };
195
f23a6179
HS		 196 saradc: saradc@ff100000 {
197 compatible = "rockchip,saradc";
198 reg = <0xff100000 0x100>;
199 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
200 #io-channel-cells = <1>;
201 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
202 clock-names = "saradc", "apb_pclk";
203 status = "disabled";
204 };
205
1f53170b 206 spi0: spi@ff110000 {
207 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
208 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
209 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 210 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
211 dma-names = "tx", "rx";
1f53170b 212 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
215 reg = <0xff110000 0x1000>;
216 #address-cells = <1>;
217 #size-cells = <0>;
218 status = "disabled";
219 };
220
221 spi1: spi@ff120000 {
222 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
223 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
224 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 225 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
226 dma-names = "tx", "rx";
1f53170b 227 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
228 pinctrl-names = "default";
229 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
230 reg = <0xff120000 0x1000>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 status = "disabled";
234 };
235
236 spi2: spi@ff130000 {
237 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
238 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
239 clock-names = "spiclk", "apb_pclk";
11bd57b8
DA		 240 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
241 dma-names = "tx", "rx";
1f53170b 242 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
245 reg = <0xff130000 0x1000>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 status = "disabled";
249 };
250
2ab557b7
HS		 251 i2c1: i2c@ff140000 {
252 compatible = "rockchip,rk3288-i2c";
253 reg = <0xff140000 0x1000>;
254 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
255 #address-cells = <1>;
256 #size-cells = <0>;
257 clock-names = "i2c";
258 clocks = <&cru PCLK_I2C1>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&i2c1_xfer>;
261 status = "disabled";
262 };
263
264 i2c3: i2c@ff150000 {
265 compatible = "rockchip,rk3288-i2c";
266 reg = <0xff150000 0x1000>;
267 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
268 #address-cells = <1>;
269 #size-cells = <0>;
270 clock-names = "i2c";
271 clocks = <&cru PCLK_I2C3>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&i2c3_xfer>;
274 status = "disabled";
275 };
276
277 i2c4: i2c@ff160000 {
278 compatible = "rockchip,rk3288-i2c";
279 reg = <0xff160000 0x1000>;
280 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 clock-names = "i2c";
284 clocks = <&cru PCLK_I2C4>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&i2c4_xfer>;
287 status = "disabled";
288 };
289
290 i2c5: i2c@ff170000 {
291 compatible = "rockchip,rk3288-i2c";
292 reg = <0xff170000 0x1000>;
293 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
294 #address-cells = <1>;
295 #size-cells = <0>;
296 clock-names = "i2c";
297 clocks = <&cru PCLK_I2C5>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&i2c5_xfer>;
300 status = "disabled";
301 };
302
303 uart0: serial@ff180000 {
304 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
305 reg = <0xff180000 0x100>;
306 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
307 reg-shift = <2>;
308 reg-io-width = <4>;
309 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
310 clock-names = "baudclk", "apb_pclk";
311 pinctrl-names = "default";
312 pinctrl-0 = <&uart0_xfer>;
313 status = "disabled";
314 };
315
316 uart1: serial@ff190000 {
317 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
318 reg = <0xff190000 0x100>;
319 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
320 reg-shift = <2>;
321 reg-io-width = <4>;
322 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
323 clock-names = "baudclk", "apb_pclk";
324 pinctrl-names = "default";
325 pinctrl-0 = <&uart1_xfer>;
326 status = "disabled";
327 };
328
329 uart2: serial@ff690000 {
330 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
331 reg = <0xff690000 0x100>;
332 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
333 reg-shift = <2>;
334 reg-io-width = <4>;
335 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
336 clock-names = "baudclk", "apb_pclk";
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart2_xfer>;
339 status = "disabled";
340 };
341
342 uart3: serial@ff1b0000 {
343 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
344 reg = <0xff1b0000 0x100>;
345 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
346 reg-shift = <2>;
347 reg-io-width = <4>;
348 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
349 clock-names = "baudclk", "apb_pclk";
350 pinctrl-names = "default";
351 pinctrl-0 = <&uart3_xfer>;
352 status = "disabled";
353 };
354
355 uart4: serial@ff1c0000 {
356 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
357 reg = <0xff1c0000 0x100>;
358 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
359 reg-shift = <2>;
360 reg-io-width = <4>;
361 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
362 clock-names = "baudclk", "apb_pclk";
363 pinctrl-names = "default";
364 pinctrl-0 = <&uart4_xfer>;
365 status = "disabled";
366 };
367
b67d6bc3
CW		 368 thermal-zones {
369 #include "rk3288-thermal.dtsi"
370 };
371
372 tsadc: tsadc@ff280000 {
373 compatible = "rockchip,rk3288-tsadc";
374 reg = <0xff280000 0x100>;
375 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
377 clock-names = "tsadc", "apb_pclk";
378 resets = <&cru SRST_TSADC>;
379 reset-names = "tsadc-apb";
380 pinctrl-names = "default";
381 pinctrl-0 = <&otp_out>;
382 #thermal-sensor-cells = <1>;
383 rockchip,hw-tshut-temp = <95000>;
384 status = "disabled";
385 };
386
c9c32c50
DA		 387 usb_host0_ehci: usb@ff500000 {
388 compatible = "generic-ehci";
389 reg = <0xff500000 0x100>;
390 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&cru HCLK_USBHOST0>;
392 clock-names = "usbhost";
393 status = "disabled";
394 };
395
396 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
397
12dd3653
KY		 398 usb_host1: usb@ff540000 {
399 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
400 "snps,dwc2";
401 reg = <0xff540000 0x40000>;
402 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&cru HCLK_USBHOST1>;
404 clock-names = "otg";
405 status = "disabled";
406 };
407
408 usb_otg: usb@ff580000 {
409 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
410 "snps,dwc2";
411 reg = <0xff580000 0x40000>;
412 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&cru HCLK_OTG0>;
414 clock-names = "otg";
415 status = "disabled";
416 };
417
c9c32c50
DA		 418 usb_hsic: usb@ff5c0000 {
419 compatible = "generic-ehci";
420 reg = <0xff5c0000 0x100>;
421 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&cru HCLK_HSIC>;
423 clock-names = "usbhost";
424 status = "disabled";
425 };
426
2ab557b7
HS		 427 i2c0: i2c@ff650000 {
428 compatible = "rockchip,rk3288-i2c";
429 reg = <0xff650000 0x1000>;
430 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
432 #size-cells = <0>;
433 clock-names = "i2c";
434 clocks = <&cru PCLK_I2C0>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&i2c0_xfer>;
437 status = "disabled";
438 };
439
440 i2c2: i2c@ff660000 {
441 compatible = "rockchip,rk3288-i2c";
442 reg = <0xff660000 0x1000>;
443 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
444 #address-cells = <1>;
445 #size-cells = <0>;
446 clock-names = "i2c";
447 clocks = <&cru PCLK_I2C2>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&i2c2_xfer>;
450 status = "disabled";
451 };
452
df542df3
DA		 453 pwm0: pwm@ff680000 {
454 compatible = "rockchip,rk3288-pwm";
455 reg = <0xff680000 0x10>;
456 #pwm-cells = <3>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&pwm0_pin>;
459 clocks = <&cru PCLK_PWM>;
460 clock-names = "pwm";
461 status = "disabled";
462 };
463
464 pwm1: pwm@ff680010 {
465 compatible = "rockchip,rk3288-pwm";
466 reg = <0xff680010 0x10>;
467 #pwm-cells = <3>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&pwm1_pin>;
470 clocks = <&cru PCLK_PWM>;
471 clock-names = "pwm";
472 status = "disabled";
473 };
474
475 pwm2: pwm@ff680020 {
476 compatible = "rockchip,rk3288-pwm";
477 reg = <0xff680020 0x10>;
478 #pwm-cells = <3>;
479 pinctrl-names = "default";
480 pinctrl-0 = <&pwm2_pin>;
481 clocks = <&cru PCLK_PWM>;
482 clock-names = "pwm";
483 status = "disabled";
484 };
485
486 pwm3: pwm@ff680030 {
487 compatible = "rockchip,rk3288-pwm";
488 reg = <0xff680030 0x10>;
489 #pwm-cells = <2>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&pwm3_pin>;
492 clocks = <&cru PCLK_PWM>;
493 clock-names = "pwm";
494 status = "disabled";
495 };
496
1123d412
KY		 497 bus_intmem@ff700000 {
498 compatible = "mmio-sram";
499 reg = <0xff700000 0x18000>;
500 #address-cells = <1>;
501 #size-cells = <1>;
502 ranges = <0 0xff700000 0x18000>;
503 smp-sram@0 {
504 compatible = "rockchip,rk3066-smp-sram";
505 reg = <0x00 0x10>;
506 };
507 };
508
eecfe981
CZ		 509 sram@ff720000 {
510 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
511 reg = <0xff720000 0x1000>;
512 };
513
2ab557b7
HS		 514 pmu: power-management@ff730000 {
515 compatible = "rockchip,rk3288-pmu", "syscon";
516 reg = <0xff730000 0x100>;
517 };
518
519 sgrf: syscon@ff740000 {
520 compatible = "rockchip,rk3288-sgrf", "syscon";
521 reg = <0xff740000 0x1000>;
522 };
523
524 cru: clock-controller@ff760000 {
525 compatible = "rockchip,rk3288-cru";
526 reg = <0xff760000 0x1000>;
527 rockchip,grf = <&grf>;
528 #clock-cells = <1>;
529 #reset-cells = <1>;
cd78d0cd
KY		 530 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
531 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
532 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
533 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
534 <&cru PCLK_PERI>;
535 assigned-clock-rates = <594000000>, <400000000>,
536 <500000000>, <300000000>,
537 <150000000>, <75000000>,
538 <300000000>, <150000000>,
539 <75000000>;
2ab557b7
HS		 540 };
541
542 grf: syscon@ff770000 {
543 compatible = "rockchip,rk3288-grf", "syscon";
544 reg = <0xff770000 0x1000>;
545 };
546
547 wdt: watchdog@ff800000 {
548 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
549 reg = <0xff800000 0x100>;
550 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
551 status = "disabled";
552 };
553
a0f95e35
J		 554 i2s: i2s@ff890000 {
555 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
556 reg = <0xff890000 0x10000>;
557 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
561 dma-names = "tx", "rx";
562 clock-names = "i2s_hclk", "i2s_clk";
563 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&i2s0_bus>;
566 status = "disabled";
567 };
568
7cae068b
DK		 569 vopb_mmu: iommu@ff930300 {
570 compatible = "rockchip,iommu";
571 reg = <0xff930300 0x100>;
572 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
573 interrupt-names = "vopb_mmu";
574 #iommu-cells = <0>;
575 status = "disabled";
576 };
577
578 vopl_mmu: iommu@ff940300 {
579 compatible = "rockchip,iommu";
580 reg = <0xff940300 0x100>;
581 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
582 interrupt-names = "vopl_mmu";
583 #iommu-cells = <0>;
584 status = "disabled";
585 };
586
2ab557b7
HS		 587 gic: interrupt-controller@ffc01000 {
588 compatible = "arm,gic-400";
589 interrupt-controller;
590 #interrupt-cells = <3>;
591 #address-cells = <0>;
592
593 reg = <0xffc01000 0x1000>,
594 <0xffc02000 0x1000>,
595 <0xffc04000 0x2000>,
596 <0xffc06000 0x2000>;
597 interrupts = <GIC_PPI 9 0xf04>;
598 };
599
600 pinctrl: pinctrl {
601 compatible = "rockchip,rk3288-pinctrl";
602 rockchip,grf = <&grf>;
603 rockchip,pmu = <&pmu>;
604 #address-cells = <1>;
605 #size-cells = <1>;
606 ranges;
607
608 gpio0: gpio0@ff750000 {
609 compatible = "rockchip,gpio-bank";
610 reg = <0xff750000 0x100>;
611 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&cru PCLK_GPIO0>;
613
614 gpio-controller;
615 #gpio-cells = <2>;
616
617 interrupt-controller;
618 #interrupt-cells = <2>;
619 };
620
621 gpio1: gpio1@ff780000 {
622 compatible = "rockchip,gpio-bank";
623 reg = <0xff780000 0x100>;
624 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&cru PCLK_GPIO1>;
626
627 gpio-controller;
628 #gpio-cells = <2>;
629
630 interrupt-controller;
631 #interrupt-cells = <2>;
632 };
633
634 gpio2: gpio2@ff790000 {
635 compatible = "rockchip,gpio-bank";
636 reg = <0xff790000 0x100>;
637 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&cru PCLK_GPIO2>;
639
640 gpio-controller;
641 #gpio-cells = <2>;
642
643 interrupt-controller;
644 #interrupt-cells = <2>;
645 };
646
647 gpio3: gpio3@ff7a0000 {
648 compatible = "rockchip,gpio-bank";
649 reg = <0xff7a0000 0x100>;
650 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&cru PCLK_GPIO3>;
652
653 gpio-controller;
654 #gpio-cells = <2>;
655
656 interrupt-controller;
657 #interrupt-cells = <2>;
658 };
659
660 gpio4: gpio4@ff7b0000 {
661 compatible = "rockchip,gpio-bank";
662 reg = <0xff7b0000 0x100>;
663 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&cru PCLK_GPIO4>;
665
666 gpio-controller;
667 #gpio-cells = <2>;
668
669 interrupt-controller;
670 #interrupt-cells = <2>;
671 };
672
673 gpio5: gpio5@ff7c0000 {
674 compatible = "rockchip,gpio-bank";
675 reg = <0xff7c0000 0x100>;
676 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&cru PCLK_GPIO5>;
678
679 gpio-controller;
680 #gpio-cells = <2>;
681
682 interrupt-controller;
683 #interrupt-cells = <2>;
684 };
685
686 gpio6: gpio6@ff7d0000 {
687 compatible = "rockchip,gpio-bank";
688 reg = <0xff7d0000 0x100>;
689 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&cru PCLK_GPIO6>;
691
692 gpio-controller;
693 #gpio-cells = <2>;
694
695 interrupt-controller;
696 #interrupt-cells = <2>;
697 };
698
699 gpio7: gpio7@ff7e0000 {
700 compatible = "rockchip,gpio-bank";
701 reg = <0xff7e0000 0x100>;
702 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&cru PCLK_GPIO7>;
704
705 gpio-controller;
706 #gpio-cells = <2>;
707
708 interrupt-controller;
709 #interrupt-cells = <2>;
710 };
711
712 gpio8: gpio8@ff7f0000 {
713 compatible = "rockchip,gpio-bank";
714 reg = <0xff7f0000 0x100>;
715 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&cru PCLK_GPIO8>;
717
718 gpio-controller;
719 #gpio-cells = <2>;
720
721 interrupt-controller;
722 #interrupt-cells = <2>;
723 };
724
725 pcfg_pull_up: pcfg-pull-up {
726 bias-pull-up;
727 };
728
729 pcfg_pull_down: pcfg-pull-down {
730 bias-pull-down;
731 };
732
733 pcfg_pull_none: pcfg-pull-none {
734 bias-disable;
735 };
736
eecfe981
CZ		 737 sleep {
738 global_pwroff: global-pwroff {
739 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
740 };
741
742 ddrio_pwroff: ddrio-pwroff {
743 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
744 };
745
746 ddr0_retention: ddr0-retention {
747 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
748 };
749
750 ddr1_retention: ddr1-retention {
751 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
752 };
753 };
754
2ab557b7
HS		 755 i2c0 {
756 i2c0_xfer: i2c0-xfer {
757 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
758 <0 16 RK_FUNC_1 &pcfg_pull_none>;
759 };
760 };
761
762 i2c1 {
763 i2c1_xfer: i2c1-xfer {
764 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
765 <8 5 RK_FUNC_1 &pcfg_pull_none>;
766 };
767 };
768
769 i2c2 {
770 i2c2_xfer: i2c2-xfer {
771 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
772 <6 10 RK_FUNC_1 &pcfg_pull_none>;
773 };
774 };
775
776 i2c3 {
777 i2c3_xfer: i2c3-xfer {
778 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
779 <2 17 RK_FUNC_1 &pcfg_pull_none>;
780 };
781 };
782
783 i2c4 {
784 i2c4_xfer: i2c4-xfer {
785 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
786 <7 18 RK_FUNC_1 &pcfg_pull_none>;
787 };
788 };
789
790 i2c5 {
791 i2c5_xfer: i2c5-xfer {
792 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
793 <7 20 RK_FUNC_1 &pcfg_pull_none>;
a0f95e35
J		 794 };
795 };
796
797 i2s0 {
798 i2s0_bus: i2s0-bus {
799 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
800 <6 1 RK_FUNC_1 &pcfg_pull_none>,
801 <6 2 RK_FUNC_1 &pcfg_pull_none>,
802 <6 3 RK_FUNC_1 &pcfg_pull_none>,
803 <6 4 RK_FUNC_1 &pcfg_pull_none>,
804 <6 8 RK_FUNC_1 &pcfg_pull_none>;
2ab557b7
HS		 805 };
806 };
807
808 sdmmc {
809 sdmmc_clk: sdmmc-clk {
810 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
811 };
812
813 sdmmc_cmd: sdmmc-cmd {
814 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
815 };
816
817 sdmmc_cd: sdmcc-cd {
818 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
819 };
820
821 sdmmc_bus1: sdmmc-bus1 {
822 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
823 };
824
825 sdmmc_bus4: sdmmc-bus4 {
826 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
827 <6 17 RK_FUNC_1 &pcfg_pull_up>,
828 <6 18 RK_FUNC_1 &pcfg_pull_up>,
829 <6 19 RK_FUNC_1 &pcfg_pull_up>;
830 };
831 };
832
f1a07231
AK		 833 sdio0 {
834 sdio0_bus1: sdio0-bus1 {
835 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
836 };
837
838 sdio0_bus4: sdio0-bus4 {
839 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
840 <4 21 RK_FUNC_1 &pcfg_pull_up>,
841 <4 22 RK_FUNC_1 &pcfg_pull_up>,
842 <4 23 RK_FUNC_1 &pcfg_pull_up>;
843 };
844
845 sdio0_cmd: sdio0-cmd {
846 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
847 };
848
849 sdio0_clk: sdio0-clk {
850 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
851 };
852
853 sdio0_cd: sdio0-cd {
854 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
855 };
856
857 sdio0_wp: sdio0-wp {
858 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
859 };
860
861 sdio0_pwr: sdio0-pwr {
862 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
863 };
864
865 sdio0_bkpwr: sdio0-bkpwr {
866 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
867 };
868
869 sdio0_int: sdio0-int {
870 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
871 };
872 };
873
874 sdio1 {
875 sdio1_bus1: sdio1-bus1 {
876 rockchip,pins = <3 24 4 &pcfg_pull_up>;
877 };
878
879 sdio1_bus4: sdio1-bus4 {
880 rockchip,pins = <3 24 4 &pcfg_pull_up>,
881 <3 25 4 &pcfg_pull_up>,
882 <3 26 4 &pcfg_pull_up>,
883 <3 27 4 &pcfg_pull_up>;
884 };
885
886 sdio1_cd: sdio1-cd {
887 rockchip,pins = <3 28 4 &pcfg_pull_up>;
888 };
889
890 sdio1_wp: sdio1-wp {
891 rockchip,pins = <3 29 4 &pcfg_pull_up>;
892 };
893
894 sdio1_bkpwr: sdio1-bkpwr {
895 rockchip,pins = <3 30 4 &pcfg_pull_up>;
896 };
897
898 sdio1_int: sdio1-int {
899 rockchip,pins = <3 31 4 &pcfg_pull_up>;
900 };
901
902 sdio1_cmd: sdio1-cmd {
903 rockchip,pins = <4 6 4 &pcfg_pull_up>;
904 };
905
906 sdio1_clk: sdio1-clk {
907 rockchip,pins = <4 7 4 &pcfg_pull_none>;
908 };
909
910 sdio1_pwr: sdio1-pwr {
911 rockchip,pins = <4 9 4 &pcfg_pull_up>;
912 };
913 };
914
2ab557b7
HS		 915 emmc {
916 emmc_clk: emmc-clk {
917 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
918 };
919
920 emmc_cmd: emmc-cmd {
921 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
922 };
923
924 emmc_pwr: emmc-pwr {
925 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
926 };
927
928 emmc_bus1: emmc-bus1 {
929 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
930 };
931
932 emmc_bus4: emmc-bus4 {
933 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
934 <3 1 RK_FUNC_2 &pcfg_pull_up>,
935 <3 2 RK_FUNC_2 &pcfg_pull_up>,
936 <3 3 RK_FUNC_2 &pcfg_pull_up>;
937 };
938
939 emmc_bus8: emmc-bus8 {
940 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
941 <3 1 RK_FUNC_2 &pcfg_pull_up>,
942 <3 2 RK_FUNC_2 &pcfg_pull_up>,
943 <3 3 RK_FUNC_2 &pcfg_pull_up>,
944 <3 4 RK_FUNC_2 &pcfg_pull_up>,
945 <3 5 RK_FUNC_2 &pcfg_pull_up>,
946 <3 6 RK_FUNC_2 &pcfg_pull_up>,
947 <3 7 RK_FUNC_2 &pcfg_pull_up>;
948 };
949 };
950
1f53170b 951 spi0 {
952 spi0_clk: spi0-clk {
953 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
954 };
955 spi0_cs0: spi0-cs0 {
956 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
957 };
958 spi0_tx: spi0-tx {
959 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
960 };
961 spi0_rx: spi0-rx {
962 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
963 };
964 spi0_cs1: spi0-cs1 {
965 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
966 };
967 };
968 spi1 {
969 spi1_clk: spi1-clk {
970 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
971 };
972 spi1_cs0: spi1-cs0 {
973 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
974 };
975 spi1_rx: spi1-rx {
976 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
977 };
978 spi1_tx: spi1-tx {
979 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
980 };
981 };
982
983 spi2 {
984 spi2_cs1: spi2-cs1 {
985 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
986 };
987 spi2_clk: spi2-clk {
988 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
989 };
990 spi2_cs0: spi2-cs0 {
991 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
992 };
993 spi2_rx: spi2-rx {
994 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
995 };
996 spi2_tx: spi2-tx {
997 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
998 };
999 };
1000
2ab557b7
HS		 1001 uart0 {
1002 uart0_xfer: uart0-xfer {
1003 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1004 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1005 };
1006
1007 uart0_cts: uart0-cts {
1008 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1009 };
1010
1011 uart0_rts: uart0-rts {
1012 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1013 };
1014 };
1015
1016 uart1 {
1017 uart1_xfer: uart1-xfer {
1018 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1019 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1020 };
1021
1022 uart1_cts: uart1-cts {
1023 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1024 };
1025
1026 uart1_rts: uart1-rts {
1027 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1028 };
1029 };
1030
1031 uart2 {
1032 uart2_xfer: uart2-xfer {
1033 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1034 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1035 };
1036 /* no rts / cts for uart2 */
1037 };
1038
1039 uart3 {
1040 uart3_xfer: uart3-xfer {
1041 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1042 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1043 };
1044
1045 uart3_cts: uart3-cts {
1046 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1047 };
1048
1049 uart3_rts: uart3-rts {
1050 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1051 };
1052 };
1053
1054 uart4 {
1055 uart4_xfer: uart4-xfer {
1056 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1057 <5 13 3 &pcfg_pull_none>;
1058 };
1059
1060 uart4_cts: uart4-cts {
1061 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1062 };
1063
1064 uart4_rts: uart4-rts {
1065 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1066 };
1067 };
df542df3 1068
b67d6bc3
CW		 1069 tsadc {
1070 otp_out: otp-out {
1071 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1072 };
1073 };
1074
df542df3
DA		 1075 pwm0 {
1076 pwm0_pin: pwm0-pin {
1077 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1078 };
1079 };
1080
1081 pwm1 {
1082 pwm1_pin: pwm1-pin {
1083 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1084 };
1085 };
1086
1087 pwm2 {
1088 pwm2_pin: pwm2-pin {
1089 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1090 };
1091 };
1092
1093 pwm3 {
1094 pwm3_pin: pwm3-pin {
1095 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1096 };
1097 };
2ab557b7
HS		 1098 };
1099};
Linux kernel - Deliverables
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