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ARM: dts: rockchip: add saradc nodes
[deliverable/linux.git] / arch / arm / boot / dts / rk3288.dtsi
CommitLineData
2ab557b7
HS		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/pinctrl/rockchip.h>
17#include <dt-bindings/clock/rk3288-cru.h>
18#include "skeleton.dtsi"
19
20/ {
21 compatible = "rockchip,rk3288";
22
23 interrupt-parent = <&gic>;
24
25 aliases {
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 i2c2 = &i2c2;
29 i2c3 = &i2c3;
30 i2c4 = &i2c4;
31 i2c5 = &i2c5;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 };
38
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 cpu@500 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a12";
46 reg = <0x500>;
47 };
48 cpu@501 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a12";
51 reg = <0x501>;
52 };
53 cpu@502 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a12";
56 reg = <0x502>;
57 };
58 cpu@503 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a12";
61 reg = <0x503>;
62 };
63 };
64
65 xin24m: oscillator {
66 compatible = "fixed-clock";
67 clock-frequency = <24000000>;
68 clock-output-names = "xin24m";
69 #clock-cells = <0>;
70 };
71
72 timer {
73 compatible = "arm,armv7-timer";
74 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
77 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
78 clock-frequency = <24000000>;
79 };
80
85095bf3
DA		 81 sdmmc: dwmmc@ff0c0000 {
82 compatible = "rockchip,rk3288-dw-mshc";
83 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
84 clock-names = "biu", "ciu";
85 fifo-depth = <0x100>;
86 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
87 reg = <0xff0c0000 0x4000>;
88 status = "disabled";
89 };
90
91 emmc: dwmmc@ff0f0000 {
92 compatible = "rockchip,rk3288-dw-mshc";
93 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
94 clock-names = "biu", "ciu";
95 fifo-depth = <0x100>;
96 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
97 reg = <0xff0f0000 0x4000>;
98 status = "disabled";
99 };
100
f23a6179
HS		 101 saradc: saradc@ff100000 {
102 compatible = "rockchip,saradc";
103 reg = <0xff100000 0x100>;
104 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
105 #io-channel-cells = <1>;
106 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
107 clock-names = "saradc", "apb_pclk";
108 status = "disabled";
109 };
110
2ab557b7
HS		 111 i2c1: i2c@ff140000 {
112 compatible = "rockchip,rk3288-i2c";
113 reg = <0xff140000 0x1000>;
114 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
115 #address-cells = <1>;
116 #size-cells = <0>;
117 clock-names = "i2c";
118 clocks = <&cru PCLK_I2C1>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&i2c1_xfer>;
121 status = "disabled";
122 };
123
124 i2c3: i2c@ff150000 {
125 compatible = "rockchip,rk3288-i2c";
126 reg = <0xff150000 0x1000>;
127 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
128 #address-cells = <1>;
129 #size-cells = <0>;
130 clock-names = "i2c";
131 clocks = <&cru PCLK_I2C3>;
132 pinctrl-names = "default";
133 pinctrl-0 = <&i2c3_xfer>;
134 status = "disabled";
135 };
136
137 i2c4: i2c@ff160000 {
138 compatible = "rockchip,rk3288-i2c";
139 reg = <0xff160000 0x1000>;
140 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
141 #address-cells = <1>;
142 #size-cells = <0>;
143 clock-names = "i2c";
144 clocks = <&cru PCLK_I2C4>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&i2c4_xfer>;
147 status = "disabled";
148 };
149
150 i2c5: i2c@ff170000 {
151 compatible = "rockchip,rk3288-i2c";
152 reg = <0xff170000 0x1000>;
153 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
154 #address-cells = <1>;
155 #size-cells = <0>;
156 clock-names = "i2c";
157 clocks = <&cru PCLK_I2C5>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&i2c5_xfer>;
160 status = "disabled";
161 };
162
163 uart0: serial@ff180000 {
164 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
165 reg = <0xff180000 0x100>;
166 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
167 reg-shift = <2>;
168 reg-io-width = <4>;
169 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
170 clock-names = "baudclk", "apb_pclk";
171 pinctrl-names = "default";
172 pinctrl-0 = <&uart0_xfer>;
173 status = "disabled";
174 };
175
176 uart1: serial@ff190000 {
177 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
178 reg = <0xff190000 0x100>;
179 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
180 reg-shift = <2>;
181 reg-io-width = <4>;
182 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
183 clock-names = "baudclk", "apb_pclk";
184 pinctrl-names = "default";
185 pinctrl-0 = <&uart1_xfer>;
186 status = "disabled";
187 };
188
189 uart2: serial@ff690000 {
190 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
191 reg = <0xff690000 0x100>;
192 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
193 reg-shift = <2>;
194 reg-io-width = <4>;
195 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
196 clock-names = "baudclk", "apb_pclk";
197 pinctrl-names = "default";
198 pinctrl-0 = <&uart2_xfer>;
199 status = "disabled";
200 };
201
202 uart3: serial@ff1b0000 {
203 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
204 reg = <0xff1b0000 0x100>;
205 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
206 reg-shift = <2>;
207 reg-io-width = <4>;
208 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
209 clock-names = "baudclk", "apb_pclk";
210 pinctrl-names = "default";
211 pinctrl-0 = <&uart3_xfer>;
212 status = "disabled";
213 };
214
215 uart4: serial@ff1c0000 {
216 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
217 reg = <0xff1c0000 0x100>;
218 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
219 reg-shift = <2>;
220 reg-io-width = <4>;
221 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
222 clock-names = "baudclk", "apb_pclk";
223 pinctrl-names = "default";
224 pinctrl-0 = <&uart4_xfer>;
225 status = "disabled";
226 };
227
c9c32c50
DA		 228 usb_host0_ehci: usb@ff500000 {
229 compatible = "generic-ehci";
230 reg = <0xff500000 0x100>;
231 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&cru HCLK_USBHOST0>;
233 clock-names = "usbhost";
234 status = "disabled";
235 };
236
237 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
238
239 usb_hsic: usb@ff5c0000 {
240 compatible = "generic-ehci";
241 reg = <0xff5c0000 0x100>;
242 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&cru HCLK_HSIC>;
244 clock-names = "usbhost";
245 status = "disabled";
246 };
247
2ab557b7
HS		 248 i2c0: i2c@ff650000 {
249 compatible = "rockchip,rk3288-i2c";
250 reg = <0xff650000 0x1000>;
251 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
252 #address-cells = <1>;
253 #size-cells = <0>;
254 clock-names = "i2c";
255 clocks = <&cru PCLK_I2C0>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&i2c0_xfer>;
258 status = "disabled";
259 };
260
261 i2c2: i2c@ff660000 {
262 compatible = "rockchip,rk3288-i2c";
263 reg = <0xff660000 0x1000>;
264 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
265 #address-cells = <1>;
266 #size-cells = <0>;
267 clock-names = "i2c";
268 clocks = <&cru PCLK_I2C2>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&i2c2_xfer>;
271 status = "disabled";
272 };
273
df542df3
DA		 274 pwm0: pwm@ff680000 {
275 compatible = "rockchip,rk3288-pwm";
276 reg = <0xff680000 0x10>;
277 #pwm-cells = <3>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pwm0_pin>;
280 clocks = <&cru PCLK_PWM>;
281 clock-names = "pwm";
282 status = "disabled";
283 };
284
285 pwm1: pwm@ff680010 {
286 compatible = "rockchip,rk3288-pwm";
287 reg = <0xff680010 0x10>;
288 #pwm-cells = <3>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&pwm1_pin>;
291 clocks = <&cru PCLK_PWM>;
292 clock-names = "pwm";
293 status = "disabled";
294 };
295
296 pwm2: pwm@ff680020 {
297 compatible = "rockchip,rk3288-pwm";
298 reg = <0xff680020 0x10>;
299 #pwm-cells = <3>;
300 pinctrl-names = "default";
301 pinctrl-0 = <&pwm2_pin>;
302 clocks = <&cru PCLK_PWM>;
303 clock-names = "pwm";
304 status = "disabled";
305 };
306
307 pwm3: pwm@ff680030 {
308 compatible = "rockchip,rk3288-pwm";
309 reg = <0xff680030 0x10>;
310 #pwm-cells = <2>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&pwm3_pin>;
313 clocks = <&cru PCLK_PWM>;
314 clock-names = "pwm";
315 status = "disabled";
316 };
317
2ab557b7
HS		 318 pmu: power-management@ff730000 {
319 compatible = "rockchip,rk3288-pmu", "syscon";
320 reg = <0xff730000 0x100>;
321 };
322
323 sgrf: syscon@ff740000 {
324 compatible = "rockchip,rk3288-sgrf", "syscon";
325 reg = <0xff740000 0x1000>;
326 };
327
328 cru: clock-controller@ff760000 {
329 compatible = "rockchip,rk3288-cru";
330 reg = <0xff760000 0x1000>;
331 rockchip,grf = <&grf>;
332 #clock-cells = <1>;
333 #reset-cells = <1>;
334 };
335
336 grf: syscon@ff770000 {
337 compatible = "rockchip,rk3288-grf", "syscon";
338 reg = <0xff770000 0x1000>;
339 };
340
341 wdt: watchdog@ff800000 {
342 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
343 reg = <0xff800000 0x100>;
344 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
345 status = "disabled";
346 };
347
348 gic: interrupt-controller@ffc01000 {
349 compatible = "arm,gic-400";
350 interrupt-controller;
351 #interrupt-cells = <3>;
352 #address-cells = <0>;
353
354 reg = <0xffc01000 0x1000>,
355 <0xffc02000 0x1000>,
356 <0xffc04000 0x2000>,
357 <0xffc06000 0x2000>;
358 interrupts = <GIC_PPI 9 0xf04>;
359 };
360
361 pinctrl: pinctrl {
362 compatible = "rockchip,rk3288-pinctrl";
363 rockchip,grf = <&grf>;
364 rockchip,pmu = <&pmu>;
365 #address-cells = <1>;
366 #size-cells = <1>;
367 ranges;
368
369 gpio0: gpio0@ff750000 {
370 compatible = "rockchip,gpio-bank";
371 reg = <0xff750000 0x100>;
372 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&cru PCLK_GPIO0>;
374
375 gpio-controller;
376 #gpio-cells = <2>;
377
378 interrupt-controller;
379 #interrupt-cells = <2>;
380 };
381
382 gpio1: gpio1@ff780000 {
383 compatible = "rockchip,gpio-bank";
384 reg = <0xff780000 0x100>;
385 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&cru PCLK_GPIO1>;
387
388 gpio-controller;
389 #gpio-cells = <2>;
390
391 interrupt-controller;
392 #interrupt-cells = <2>;
393 };
394
395 gpio2: gpio2@ff790000 {
396 compatible = "rockchip,gpio-bank";
397 reg = <0xff790000 0x100>;
398 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&cru PCLK_GPIO2>;
400
401 gpio-controller;
402 #gpio-cells = <2>;
403
404 interrupt-controller;
405 #interrupt-cells = <2>;
406 };
407
408 gpio3: gpio3@ff7a0000 {
409 compatible = "rockchip,gpio-bank";
410 reg = <0xff7a0000 0x100>;
411 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&cru PCLK_GPIO3>;
413
414 gpio-controller;
415 #gpio-cells = <2>;
416
417 interrupt-controller;
418 #interrupt-cells = <2>;
419 };
420
421 gpio4: gpio4@ff7b0000 {
422 compatible = "rockchip,gpio-bank";
423 reg = <0xff7b0000 0x100>;
424 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&cru PCLK_GPIO4>;
426
427 gpio-controller;
428 #gpio-cells = <2>;
429
430 interrupt-controller;
431 #interrupt-cells = <2>;
432 };
433
434 gpio5: gpio5@ff7c0000 {
435 compatible = "rockchip,gpio-bank";
436 reg = <0xff7c0000 0x100>;
437 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&cru PCLK_GPIO5>;
439
440 gpio-controller;
441 #gpio-cells = <2>;
442
443 interrupt-controller;
444 #interrupt-cells = <2>;
445 };
446
447 gpio6: gpio6@ff7d0000 {
448 compatible = "rockchip,gpio-bank";
449 reg = <0xff7d0000 0x100>;
450 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&cru PCLK_GPIO6>;
452
453 gpio-controller;
454 #gpio-cells = <2>;
455
456 interrupt-controller;
457 #interrupt-cells = <2>;
458 };
459
460 gpio7: gpio7@ff7e0000 {
461 compatible = "rockchip,gpio-bank";
462 reg = <0xff7e0000 0x100>;
463 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&cru PCLK_GPIO7>;
465
466 gpio-controller;
467 #gpio-cells = <2>;
468
469 interrupt-controller;
470 #interrupt-cells = <2>;
471 };
472
473 gpio8: gpio8@ff7f0000 {
474 compatible = "rockchip,gpio-bank";
475 reg = <0xff7f0000 0x100>;
476 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cru PCLK_GPIO8>;
478
479 gpio-controller;
480 #gpio-cells = <2>;
481
482 interrupt-controller;
483 #interrupt-cells = <2>;
484 };
485
486 pcfg_pull_up: pcfg-pull-up {
487 bias-pull-up;
488 };
489
490 pcfg_pull_down: pcfg-pull-down {
491 bias-pull-down;
492 };
493
494 pcfg_pull_none: pcfg-pull-none {
495 bias-disable;
496 };
497
498 i2c0 {
499 i2c0_xfer: i2c0-xfer {
500 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
501 <0 16 RK_FUNC_1 &pcfg_pull_none>;
502 };
503 };
504
505 i2c1 {
506 i2c1_xfer: i2c1-xfer {
507 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
508 <8 5 RK_FUNC_1 &pcfg_pull_none>;
509 };
510 };
511
512 i2c2 {
513 i2c2_xfer: i2c2-xfer {
514 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
515 <6 10 RK_FUNC_1 &pcfg_pull_none>;
516 };
517 };
518
519 i2c3 {
520 i2c3_xfer: i2c3-xfer {
521 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
522 <2 17 RK_FUNC_1 &pcfg_pull_none>;
523 };
524 };
525
526 i2c4 {
527 i2c4_xfer: i2c4-xfer {
528 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
529 <7 18 RK_FUNC_1 &pcfg_pull_none>;
530 };
531 };
532
533 i2c5 {
534 i2c5_xfer: i2c5-xfer {
535 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
536 <7 20 RK_FUNC_1 &pcfg_pull_none>;
537 };
538 };
539
540 sdmmc {
541 sdmmc_clk: sdmmc-clk {
542 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
543 };
544
545 sdmmc_cmd: sdmmc-cmd {
546 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
547 };
548
549 sdmmc_cd: sdmcc-cd {
550 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
551 };
552
553 sdmmc_bus1: sdmmc-bus1 {
554 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
555 };
556
557 sdmmc_bus4: sdmmc-bus4 {
558 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
559 <6 17 RK_FUNC_1 &pcfg_pull_up>,
560 <6 18 RK_FUNC_1 &pcfg_pull_up>,
561 <6 19 RK_FUNC_1 &pcfg_pull_up>;
562 };
563 };
564
565 emmc {
566 emmc_clk: emmc-clk {
567 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
568 };
569
570 emmc_cmd: emmc-cmd {
571 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
572 };
573
574 emmc_pwr: emmc-pwr {
575 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
576 };
577
578 emmc_bus1: emmc-bus1 {
579 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
580 };
581
582 emmc_bus4: emmc-bus4 {
583 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
584 <3 1 RK_FUNC_2 &pcfg_pull_up>,
585 <3 2 RK_FUNC_2 &pcfg_pull_up>,
586 <3 3 RK_FUNC_2 &pcfg_pull_up>;
587 };
588
589 emmc_bus8: emmc-bus8 {
590 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
591 <3 1 RK_FUNC_2 &pcfg_pull_up>,
592 <3 2 RK_FUNC_2 &pcfg_pull_up>,
593 <3 3 RK_FUNC_2 &pcfg_pull_up>,
594 <3 4 RK_FUNC_2 &pcfg_pull_up>,
595 <3 5 RK_FUNC_2 &pcfg_pull_up>,
596 <3 6 RK_FUNC_2 &pcfg_pull_up>,
597 <3 7 RK_FUNC_2 &pcfg_pull_up>;
598 };
599 };
600
601 uart0 {
602 uart0_xfer: uart0-xfer {
603 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
604 <4 17 RK_FUNC_1 &pcfg_pull_none>;
605 };
606
607 uart0_cts: uart0-cts {
608 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
609 };
610
611 uart0_rts: uart0-rts {
612 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
613 };
614 };
615
616 uart1 {
617 uart1_xfer: uart1-xfer {
618 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
619 <5 9 RK_FUNC_1 &pcfg_pull_none>;
620 };
621
622 uart1_cts: uart1-cts {
623 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
624 };
625
626 uart1_rts: uart1-rts {
627 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
628 };
629 };
630
631 uart2 {
632 uart2_xfer: uart2-xfer {
633 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
634 <7 23 RK_FUNC_1 &pcfg_pull_none>;
635 };
636 /* no rts / cts for uart2 */
637 };
638
639 uart3 {
640 uart3_xfer: uart3-xfer {
641 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
642 <7 8 RK_FUNC_1 &pcfg_pull_none>;
643 };
644
645 uart3_cts: uart3-cts {
646 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
647 };
648
649 uart3_rts: uart3-rts {
650 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
651 };
652 };
653
654 uart4 {
655 uart4_xfer: uart4-xfer {
656 rockchip,pins = <5 12 3 &pcfg_pull_up>,
657 <5 13 3 &pcfg_pull_none>;
658 };
659
660 uart4_cts: uart4-cts {
661 rockchip,pins = <5 14 3 &pcfg_pull_none>;
662 };
663
664 uart4_rts: uart4-rts {
665 rockchip,pins = <5 15 3 &pcfg_pull_none>;
666 };
667 };
df542df3
DA		 668
669 pwm0 {
670 pwm0_pin: pwm0-pin {
671 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
672 };
673 };
674
675 pwm1 {
676 pwm1_pin: pwm1-pin {
677 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
678 };
679 };
680
681 pwm2 {
682 pwm2_pin: pwm2-pin {
683 rockchip,pins = <7 22 3 &pcfg_pull_none>;
684 };
685 };
686
687 pwm3 {
688 pwm3_pin: pwm3-pin {
689 rockchip,pins = <7 23 3 &pcfg_pull_none>;
690 };
691 };
2ab557b7
HS		 692 };
693};
Linux kernel - Deliverables
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