projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f75efdd7 HS |
1 | /* |
| 2 | * Copyright (c) 2013 MundoReader S.L. | |
| 3 | * Author: Heiko Stuebner <heiko@sntech.de> | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License as published by | |
| 7 | * the Free Software Foundation; either version 2 of the License, or | |
| 8 | * (at your option) any later version. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, | |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | */ | |
| 15 | ||
| 16 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 17 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 18 | #include "skeleton.dtsi" | |
| 19 | ||
| 20 | / { | |
| 21 | interrupt-parent = <&gic>; | |
| 22 | ||
| 560106c1 HS |
23 | xin24m: oscillator { |
| 24 | compatible = "fixed-clock"; | |
| 25 | clock-frequency = <24000000>; | |
| 26 | #clock-cells = <0>; | |
| 27 | clock-output-names = "xin24m"; | |
| 28 | }; | |
| 29 | ||
| c3030d30 HS |
30 | scu@1013c000 { |
| 31 | compatible = "arm,cortex-a9-scu"; | |
| 32 | reg = <0x1013c000 0x100>; | |
| 33 | }; | |
| 34 | ||
| 35 | pmu: pmu@20004000 { | |
| 36 | compatible = "rockchip,rk3066-pmu", "syscon"; | |
| 37 | reg = <0x20004000 0x100>; | |
| 38 | }; | |
| 39 | ||
| 40 | grf: grf@20008000 { | |
| 41 | compatible = "syscon"; | |
| 42 | reg = <0x20008000 0x200>; | |
| 43 | }; | |
| 44 | ||
| 45 | gic: interrupt-controller@1013d000 { | |
| 46 | compatible = "arm,cortex-a9-gic"; | |
| 47 | interrupt-controller; | |
| 48 | #interrupt-cells = <3>; | |
| 49 | reg = <0x1013d000 0x1000>, | |
| 50 | <0x1013c100 0x0100>; | |
| 51 | }; | |
| 52 | ||
| 53 | L2: l2-cache-controller@10138000 { | |
| 54 | compatible = "arm,pl310-cache"; | |
| 55 | reg = <0x10138000 0x1000>; | |
| 56 | cache-unified; | |
| 57 | cache-level = <2>; | |
| 58 | }; | |
| 59 | ||
| e40b43d6 | 60 | global_timer: global-timer@1013c200 { |
| c3030d30 HS |
61 | compatible = "arm,cortex-a9-global-timer"; |
| 62 | reg = <0x1013c200 0x20>; | |
| 63 | interrupts = <GIC_PPI 11 0x304>; | |
| 64 | clocks = <&cru CORE_PERI>; | |
| 65 | }; | |
| 66 | ||
| e40b43d6 | 67 | local_timer: local-timer@1013c600 { |
| c3030d30 HS |
68 | compatible = "arm,cortex-a9-twd-timer"; |
| 69 | reg = <0x1013c600 0x20>; | |
| 70 | interrupts = <GIC_PPI 13 0x304>; | |
| 71 | clocks = <&cru CORE_PERI>; | |
| 72 | }; | |
| 73 | ||
| 74 | uart0: serial@10124000 { | |
| 75 | compatible = "snps,dw-apb-uart"; | |
| 76 | reg = <0x10124000 0x400>; | |
| 77 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
| 78 | reg-shift = <2>; | |
| 79 | reg-io-width = <1>; | |
| 80 | clocks = <&cru SCLK_UART0>; | |
| 81 | status = "disabled"; | |
| 82 | }; | |
| 83 | ||
| 84 | uart1: serial@10126000 { | |
| 85 | compatible = "snps,dw-apb-uart"; | |
| 86 | reg = <0x10126000 0x400>; | |
| 87 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
| 88 | reg-shift = <2>; | |
| 89 | reg-io-width = <1>; | |
| 90 | clocks = <&cru SCLK_UART1>; | |
| 91 | status = "disabled"; | |
| 92 | }; | |
| 93 | ||
| 94 | uart2: serial@20064000 { | |
| 95 | compatible = "snps,dw-apb-uart"; | |
| 96 | reg = <0x20064000 0x400>; | |
| 97 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| 98 | reg-shift = <2>; | |
| 99 | reg-io-width = <1>; | |
| 100 | clocks = <&cru SCLK_UART2>; | |
| 101 | status = "disabled"; | |
| 102 | }; | |
| 103 | ||
| 104 | uart3: serial@20068000 { | |
| 105 | compatible = "snps,dw-apb-uart"; | |
| 106 | reg = <0x20068000 0x400>; | |
| 107 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
| 108 | reg-shift = <2>; | |
| 109 | reg-io-width = <1>; | |
| 110 | clocks = <&cru SCLK_UART3>; | |
| 111 | status = "disabled"; | |
| 112 | }; | |
| 113 | ||
| e40b43d6 | 114 | mmc0: dwmmc@10214000 { |
| c3030d30 HS |
115 | compatible = "rockchip,rk2928-dw-mshc"; |
| 116 | reg = <0x10214000 0x1000>; | |
| 117 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| f75efdd7 | 118 | #address-cells = <1>; |
| c3030d30 HS |
119 | #size-cells = <0>; |
| 120 | ||
| 121 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; | |
| 122 | clock-names = "biu", "ciu"; | |
| 123 | ||
| 124 | status = "disabled"; | |
| 125 | }; | |
| 126 | ||
| e40b43d6 | 127 | mmc1: dwmmc@10218000 { |
| c3030d30 HS |
128 | compatible = "rockchip,rk2928-dw-mshc"; |
| 129 | reg = <0x10218000 0x1000>; | |
| 130 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
| 131 | #address-cells = <1>; | |
| 132 | #size-cells = <0>; | |
| 133 | ||
| 134 | clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; | |
| 135 | clock-names = "biu", "ciu"; | |
| 136 | ||
| 137 | status = "disabled"; | |
| f75efdd7 HS |
138 | }; |
| 139 | }; |