[deliverable/linux.git] / arch / arm / boot / dts / rk3xxx.dtsi

/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"

/ {
	interrupt-parent = <&gic>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		mshc0 = &emmc;
		mshc1 = &mmc0;
		mshc2 = &mmc1;
		spi0 = &spi0;
		spi1 = &spi1;
	};

	amba {
		compatible = "arm,amba-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		dmac1_s: dma-controller@20018000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x20018000 0x4000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			clocks = <&cru ACLK_DMA1>;
			clock-names = "apb_pclk";
		};

		dmac1_ns: dma-controller@2001c000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x2001c000 0x4000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			clocks = <&cru ACLK_DMA1>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		dmac2: dma-controller@20078000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x20078000 0x4000>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			clocks = <&cru ACLK_DMA2>;
			clock-names = "apb_pclk";
		};
	};

	xin24m: oscillator {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		#clock-cells = <0>;
		clock-output-names = "xin24m";
	};

	L2: l2-cache-controller@10138000 {
		compatible = "arm,pl310-cache";
		reg = <0x10138000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

	scu@1013c000 {
		compatible = "arm,cortex-a9-scu";
		reg = <0x1013c000 0x100>;
	};

	global_timer: global-timer@1013c200 {
		compatible = "arm,cortex-a9-global-timer";
		reg = <0x1013c200 0x20>;
		interrupts = <GIC_PPI 11 0x304>;
		clocks = <&cru CORE_PERI>;
	};

	local_timer: local-timer@1013c600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x1013c600 0x20>;
		interrupts = <GIC_PPI 13 0x304>;
		clocks = <&cru CORE_PERI>;
	};

	gic: interrupt-controller@1013d000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x1013d000 0x1000>,
		      <0x1013c100 0x0100>;
	};

	uart0: serial@10124000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x10124000 0x400>;
		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <1>;
		clock-names = "baudclk", "apb_pclk";
		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
		status = "disabled";
	};

	uart1: serial@10126000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x10126000 0x400>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <1>;
		clock-names = "baudclk", "apb_pclk";
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		status = "disabled";
	};

	usb_otg: usb@10180000 {
		compatible = "rockchip,rk3066-usb", "snps,dwc2";
		reg = <0x10180000 0x40000>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_OTG0>;
		clock-names = "otg";
		status = "disabled";
	};

	usb_host: usb@101c0000 {
		compatible = "snps,dwc2";
		reg = <0x101c0000 0x40000>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_OTG1>;
		clock-names = "otg";
		status = "disabled";
	};

	emac: ethernet@10204000 {
		compatible = "snps,arc-emac";
		reg = <0x10204000 0x3c>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
		clock-names = "hclk", "macref";
		max-speed = <100>;
		phy-mode = "rmii";

		status = "disabled";
	};

	mmc0: dwmmc@10214000 {
		compatible = "rockchip,rk2928-dw-mshc";
		reg = <0x10214000 0x1000>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
		clock-names = "biu", "ciu";

		status = "disabled";
	};

	mmc1: dwmmc@10218000 {
		compatible = "rockchip,rk2928-dw-mshc";
		reg = <0x10218000 0x1000>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
		clock-names = "biu", "ciu";

		status = "disabled";
	};

	emmc: dwmmc@1021c000 {
		compatible = "rockchip,rk2928-dw-mshc";
		reg = <0x1021c000 0x1000>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
		clock-names = "biu", "ciu";

		status = "disabled";
	};

	pmu: pmu@20004000 {
		compatible = "rockchip,rk3066-pmu", "syscon";
		reg = <0x20004000 0x100>;
	};

	grf: grf@20008000 {
		compatible = "syscon";
		reg = <0x20008000 0x200>;
	};

	i2c0: i2c@2002d000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x2002d000 0x1000>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clock-names = "i2c";
		clocks = <&cru PCLK_I2C0>;

		status = "disabled";
	};

	i2c1: i2c@2002f000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x2002f000 0x1000>;
		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clocks = <&cru PCLK_I2C1>;
		clock-names = "i2c";

		status = "disabled";
	};

	pwm0: pwm@20030000 {
		compatible = "rockchip,rk2928-pwm";
		reg = <0x20030000 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM01>;
		status = "disabled";
	};

	pwm1: pwm@20030010 {
		compatible = "rockchip,rk2928-pwm";
		reg = <0x20030010 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM01>;
		status = "disabled";
	};

	wdt: watchdog@2004c000 {
		compatible = "snps,dw-wdt";
		reg = <0x2004c000 0x100>;
		clocks = <&cru PCLK_WDT>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	pwm2: pwm@20050020 {
		compatible = "rockchip,rk2928-pwm";
		reg = <0x20050020 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM23>;
		status = "disabled";
	};

	pwm3: pwm@20050030 {
		compatible = "rockchip,rk2928-pwm";
		reg = <0x20050030 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM23>;
		status = "disabled";
	};

	i2c2: i2c@20056000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x20056000 0x1000>;
		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clocks = <&cru PCLK_I2C2>;
		clock-names = "i2c";

		status = "disabled";
	};

	i2c3: i2c@2005a000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x2005a000 0x1000>;
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clocks = <&cru PCLK_I2C3>;
		clock-names = "i2c";

		status = "disabled";
	};

	i2c4: i2c@2005e000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x2005e000 0x1000>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clocks = <&cru PCLK_I2C4>;
		clock-names = "i2c";

		status = "disabled";
	};

	uart2: serial@20064000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x20064000 0x400>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <1>;
		clock-names = "baudclk", "apb_pclk";
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		status = "disabled";
	};

	uart3: serial@20068000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x20068000 0x400>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <1>;
		clock-names = "baudclk", "apb_pclk";
		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
		status = "disabled";
	};

	saradc: saradc@2006c000 {
		compatible = "rockchip,saradc";
		reg = <0x2006c000 0x100>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		#io-channel-cells = <1>;
		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
		clock-names = "saradc", "apb_pclk";
		status = "disabled";
	};

	spi0: spi@20070000 {
		compatible = "rockchip,rk3066-spi";
		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
		clock-names = "spiclk", "apb_pclk";
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x20070000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		dmas = <&dmac2 10>, <&dmac2 11>;
		dma-names = "tx", "rx";
		status = "disabled";
	};

	spi1: spi@20074000 {
		compatible = "rockchip,rk3066-spi";
		clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
		clock-names = "spiclk", "apb_pclk";
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x20074000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		dmas = <&dmac2 12>, <&dmac2 13>;
		dma-names = "tx", "rx";
		status = "disabled";
	};
};
Commit	Line	Data
f75efdd7 HS	1	/*
	2	* Copyright (c) 2013 MundoReader S.L.
	3	* Author: Heiko Stuebner <heiko@sntech.de>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <dt-bindings/interrupt-controller/irq.h>
	17	#include <dt-bindings/interrupt-controller/arm-gic.h>
	18	#include "skeleton.dtsi"
	19
	20	/ {
	21	interrupt-parent = <&gic>;
	22
9cdffd8c HS	23	aliases {
	24	i2c0 = &i2c0;
	25	i2c1 = &i2c1;
	26	i2c2 = &i2c2;
	27	i2c3 = &i2c3;
	28	i2c4 = &i2c4;
4ff4ae12 HS	29	mshc0 = &emmc;
	30	mshc1 = &mmc0;
	31	mshc2 = &mmc1;
39c2bd78 HS	32	spi0 = &spi0;
39c2bd78 HS	33	spi1 = &spi1;
9cdffd8c HS	34	};
9cdffd8c HS	35
ac42f481 HS	36	amba {
	37	compatible = "arm,amba-bus";
	38	#address-cells = <1>;
	39	#size-cells = <1>;
	40	ranges;
	41
	42	dmac1_s: dma-controller@20018000 {
	43	compatible = "arm,pl330", "arm,primecell";
	44	reg = <0x20018000 0x4000>;
	45	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	46	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	47	#dma-cells = <1>;
	48	clocks = <&cru ACLK_DMA1>;
	49	clock-names = "apb_pclk";
	50	};
	51
	52	dmac1_ns: dma-controller@2001c000 {
	53	compatible = "arm,pl330", "arm,primecell";
	54	reg = <0x2001c000 0x4000>;
	55	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	56	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	57	#dma-cells = <1>;
	58	clocks = <&cru ACLK_DMA1>;
	59	clock-names = "apb_pclk";
	60	status = "disabled";
	61	};
	62
	63	dmac2: dma-controller@20078000 {
	64	compatible = "arm,pl330", "arm,primecell";
	65	reg = <0x20078000 0x4000>;
	66	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	67	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	68	#dma-cells = <1>;
	69	clocks = <&cru ACLK_DMA2>;
	70	clock-names = "apb_pclk";
	71	};
	72	};
	73
560106c1 HS	74	xin24m: oscillator {
	75	compatible = "fixed-clock";
	76	clock-frequency = <24000000>;
	77	#clock-cells = <0>;
	78	clock-output-names = "xin24m";
	79	};
	80
c3030d30 HS	81	L2: l2-cache-controller@10138000 {
	82	compatible = "arm,pl310-cache";
	83	reg = <0x10138000 0x1000>;
	84	cache-unified;
	85	cache-level = <2>;
	86	};
	87
ff84b90e HS	88	scu@1013c000 {
	89	compatible = "arm,cortex-a9-scu";
	90	reg = <0x1013c000 0x100>;
	91	};
	92
e40b43d6	93	global_timer: global-timer@1013c200 {
c3030d30 HS	94	compatible = "arm,cortex-a9-global-timer";
	95	reg = <0x1013c200 0x20>;
	96	interrupts = <GIC_PPI 11 0x304>;
	97	clocks = <&cru CORE_PERI>;
	98	};
	99
e40b43d6	100	local_timer: local-timer@1013c600 {
c3030d30 HS	101	compatible = "arm,cortex-a9-twd-timer";
	102	reg = <0x1013c600 0x20>;
	103	interrupts = <GIC_PPI 13 0x304>;
	104	clocks = <&cru CORE_PERI>;
	105	};
	106
ff84b90e HS	107	gic: interrupt-controller@1013d000 {
	108	compatible = "arm,cortex-a9-gic";
	109	interrupt-controller;
	110	#interrupt-cells = <3>;
	111	reg = <0x1013d000 0x1000>,
	112	<0x1013c100 0x0100>;
	113	};
	114
c3030d30 HS	115	uart0: serial@10124000 {
	116	compatible = "snps,dw-apb-uart";
	117	reg = <0x10124000 0x400>;
	118	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	119	reg-shift = <2>;
	120	reg-io-width = <1>;
69667ca2 HS	121	clock-names = "baudclk", "apb_pclk";
69667ca2 HS	122	clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
c3030d30 HS	123	status = "disabled";
	124	};
	125
	126	uart1: serial@10126000 {
	127	compatible = "snps,dw-apb-uart";
	128	reg = <0x10126000 0x400>;
	129	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	130	reg-shift = <2>;
	131	reg-io-width = <1>;
69667ca2 HS	132	clock-names = "baudclk", "apb_pclk";
69667ca2 HS	133	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
c3030d30 HS	134	status = "disabled";
	135	};
	136
fd14e6f9 HS	137	usb_otg: usb@10180000 {
	138	compatible = "rockchip,rk3066-usb", "snps,dwc2";
	139	reg = <0x10180000 0x40000>;
	140	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	141	clocks = <&cru HCLK_OTG0>;
	142	clock-names = "otg";
	143	status = "disabled";
	144	};
	145
	146	usb_host: usb@101c0000 {
	147	compatible = "snps,dwc2";
	148	reg = <0x101c0000 0x40000>;
	149	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	150	clocks = <&cru HCLK_OTG1>;
	151	clock-names = "otg";
	152	status = "disabled";
	153	};
	154
18ec91e1 RP	155	emac: ethernet@10204000 {
	156	compatible = "snps,arc-emac";
	157	reg = <0x10204000 0x3c>;
	158	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	159	#address-cells = <1>;
	160	#size-cells = <0>;
	161
	162	rockchip,grf = <&grf>;
	163
	164	clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
	165	clock-names = "hclk", "macref";
	166	max-speed = <100>;
	167	phy-mode = "rmii";
	168
	169	status = "disabled";
	170	};
	171
e40b43d6	172	mmc0: dwmmc@10214000 {
c3030d30 HS	173	compatible = "rockchip,rk2928-dw-mshc";
	174	reg = <0x10214000 0x1000>;
	175	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
c3030d30 HS	176
	177	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
	178	clock-names = "biu", "ciu";
	179
	180	status = "disabled";
	181	};
	182
e40b43d6	183	mmc1: dwmmc@10218000 {
c3030d30 HS	184	compatible = "rockchip,rk2928-dw-mshc";
	185	reg = <0x10218000 0x1000>;
	186	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
c3030d30 HS	187
	188	clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
	189	clock-names = "biu", "ciu";
	190
	191	status = "disabled";
f75efdd7	192	};
ff84b90e	193
4ff4ae12 HS	194	emmc: dwmmc@1021c000 {
	195	compatible = "rockchip,rk2928-dw-mshc";
	196	reg = <0x1021c000 0x1000>;
	197	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	198
	199	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
	200	clock-names = "biu", "ciu";
	201
	202	status = "disabled";
	203	};
	204
ff84b90e HS	205	pmu: pmu@20004000 {
	206	compatible = "rockchip,rk3066-pmu", "syscon";
	207	reg = <0x20004000 0x100>;
	208	};
	209
	210	grf: grf@20008000 {
	211	compatible = "syscon";
	212	reg = <0x20008000 0x200>;
	213	};
	214
9cdffd8c HS	215	i2c0: i2c@2002d000 {
	216	compatible = "rockchip,rk3066-i2c";
	217	reg = <0x2002d000 0x1000>;
	218	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	219	#address-cells = <1>;
	220	#size-cells = <0>;
	221
	222	rockchip,grf = <&grf>;
9cdffd8c HS	223
	224	clock-names = "i2c";
	225	clocks = <&cru PCLK_I2C0>;
	226
	227	status = "disabled";
	228	};
	229
	230	i2c1: i2c@2002f000 {
	231	compatible = "rockchip,rk3066-i2c";
	232	reg = <0x2002f000 0x1000>;
	233	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	234	#address-cells = <1>;
	235	#size-cells = <0>;
	236
	237	rockchip,grf = <&grf>;
	238
	239	clocks = <&cru PCLK_I2C1>;
	240	clock-names = "i2c";
	241
	242	status = "disabled";
	243	};
	244
550c7f4e BG	245	pwm0: pwm@20030000 {
	246	compatible = "rockchip,rk2928-pwm";
	247	reg = <0x20030000 0x10>;
	248	#pwm-cells = <2>;
	249	clocks = <&cru PCLK_PWM01>;
	250	status = "disabled";
	251	};
	252
	253	pwm1: pwm@20030010 {
	254	compatible = "rockchip,rk2928-pwm";
	255	reg = <0x20030010 0x10>;
	256	#pwm-cells = <2>;
	257	clocks = <&cru PCLK_PWM01>;
	258	status = "disabled";
	259	};
	260
eb2b9d47 HS	261	wdt: watchdog@2004c000 {
	262	compatible = "snps,dw-wdt";
	263	reg = <0x2004c000 0x100>;
	264	clocks = <&cru PCLK_WDT>;
	265	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	266	status = "disabled";
	267	};
	268
550c7f4e BG	269	pwm2: pwm@20050020 {
	270	compatible = "rockchip,rk2928-pwm";
	271	reg = <0x20050020 0x10>;
	272	#pwm-cells = <2>;
	273	clocks = <&cru PCLK_PWM23>;
	274	status = "disabled";
	275	};
	276
	277	pwm3: pwm@20050030 {
	278	compatible = "rockchip,rk2928-pwm";
	279	reg = <0x20050030 0x10>;
	280	#pwm-cells = <2>;
	281	clocks = <&cru PCLK_PWM23>;
	282	status = "disabled";
	283	};
	284
9cdffd8c HS	285	i2c2: i2c@20056000 {
	286	compatible = "rockchip,rk3066-i2c";
	287	reg = <0x20056000 0x1000>;
	288	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	289	#address-cells = <1>;
	290	#size-cells = <0>;
	291
	292	rockchip,grf = <&grf>;
	293
	294	clocks = <&cru PCLK_I2C2>;
	295	clock-names = "i2c";
	296
	297	status = "disabled";
	298	};
	299
	300	i2c3: i2c@2005a000 {
	301	compatible = "rockchip,rk3066-i2c";
	302	reg = <0x2005a000 0x1000>;
	303	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	304	#address-cells = <1>;
	305	#size-cells = <0>;
	306
	307	rockchip,grf = <&grf>;
	308
	309	clocks = <&cru PCLK_I2C3>;
	310	clock-names = "i2c";
	311
	312	status = "disabled";
	313	};
	314
	315	i2c4: i2c@2005e000 {
	316	compatible = "rockchip,rk3066-i2c";
	317	reg = <0x2005e000 0x1000>;
	318	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	319	#address-cells = <1>;
	320	#size-cells = <0>;
	321
	322	rockchip,grf = <&grf>;
	323
	324	clocks = <&cru PCLK_I2C4>;
	325	clock-names = "i2c";
	326
	327	status = "disabled";
	328	};
	329
ff84b90e HS	330	uart2: serial@20064000 {
	331	compatible = "snps,dw-apb-uart";
	332	reg = <0x20064000 0x400>;
	333	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	334	reg-shift = <2>;
	335	reg-io-width = <1>;
69667ca2 HS	336	clock-names = "baudclk", "apb_pclk";
69667ca2 HS	337	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
ff84b90e HS	338	status = "disabled";
	339	};
	340
	341	uart3: serial@20068000 {
	342	compatible = "snps,dw-apb-uart";
	343	reg = <0x20068000 0x400>;
	344	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	345	reg-shift = <2>;
	346	reg-io-width = <1>;
69667ca2 HS	347	clock-names = "baudclk", "apb_pclk";
69667ca2 HS	348	clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
ff84b90e HS	349	status = "disabled";
ff84b90e HS	350	};
f23a6179 HS	351
	352	saradc: saradc@2006c000 {
	353	compatible = "rockchip,saradc";
	354	reg = <0x2006c000 0x100>;
	355	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	356	#io-channel-cells = <1>;
	357	clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
	358	clock-names = "saradc", "apb_pclk";
	359	status = "disabled";
	360	};
39c2bd78 HS	361
	362	spi0: spi@20070000 {
	363	compatible = "rockchip,rk3066-spi";
	364	clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
	365	clock-names = "spiclk", "apb_pclk";
	366	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	367	reg = <0x20070000 0x1000>;
	368	#address-cells = <1>;
	369	#size-cells = <0>;
b3e3a7b2 JC	370	dmas = <&dmac2 10>, <&dmac2 11>;
b3e3a7b2 JC	371	dma-names = "tx", "rx";
39c2bd78 HS	372	status = "disabled";
	373	};
	374
	375	spi1: spi@20074000 {
	376	compatible = "rockchip,rk3066-spi";
	377	clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
	378	clock-names = "spiclk", "apb_pclk";
	379	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	380	reg = <0x20074000 0x1000>;
	381	#address-cells = <1>;
	382	#size-cells = <0>;
b3e3a7b2 JC	383	dmas = <&dmac2 12>, <&dmac2 13>;
b3e3a7b2 JC	384	dma-names = "tx", "rx";
39c2bd78 HS	385	status = "disabled";
39c2bd78 HS	386	};
f75efdd7	387	};