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e30cf8d3 LD |
1 | /* |
2 | * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC | |
3 | * | |
4 | * Copyright (C) 2015 Atmel, | |
5 | * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> | |
6 | * | |
7 | * This file is dual-licensed: you can use it either under the terms | |
8 | * of the GPL or the X11 license, at your option. Note that this dual | |
9 | * licensing only applies to this file, and not this project as a | |
10 | * whole. | |
11 | * | |
12 | * a) This file is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of the | |
15 | * License, or (at your option) any later version. | |
16 | * | |
17 | * This file is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * Or, alternatively, | |
23 | * | |
24 | * b) Permission is hereby granted, free of charge, to any person | |
25 | * obtaining a copy of this software and associated documentation | |
26 | * files (the "Software"), to deal in the Software without | |
27 | * restriction, including without limitation the rights to use, | |
28 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
29 | * sell copies of the Software, and to permit persons to whom the | |
30 | * Software is furnished to do so, subject to the following | |
31 | * conditions: | |
32 | * | |
33 | * The above copyright notice and this permission notice shall be | |
34 | * included in all copies or substantial portions of the Software. | |
35 | * | |
36 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
37 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
38 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
39 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
40 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
41 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
42 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
43 | * OTHER DEALINGS IN THE SOFTWARE. | |
44 | */ | |
45 | ||
46 | #include "skeleton.dtsi" | |
47 | #include <dt-bindings/dma/at91.h> | |
48 | #include <dt-bindings/interrupt-controller/irq.h> | |
49 | #include <dt-bindings/clock/at91.h> | |
50 | ||
51 | / { | |
52 | model = "Atmel SAMA5D2 family SoC"; | |
53 | compatible = "atmel,sama5d2"; | |
54 | interrupt-parent = <&aic>; | |
55 | ||
56 | aliases { | |
57 | serial0 = &uart1; | |
58 | serial1 = &uart3; | |
59 | tcb0 = &tcb0; | |
60 | tcb1 = &tcb1; | |
61 | }; | |
62 | ||
63 | cpus { | |
64 | #address-cells = <1>; | |
65 | #size-cells = <0>; | |
66 | ||
67 | cpu@0 { | |
68 | device_type = "cpu"; | |
69 | compatible = "arm,cortex-a5"; | |
70 | reg = <0>; | |
71 | next-level-cache = <&L2>; | |
72 | }; | |
73 | }; | |
74 | ||
75 | memory { | |
76 | reg = <0x20000000 0x20000000>; | |
77 | }; | |
78 | ||
79 | clocks { | |
80 | slow_xtal: slow_xtal { | |
81 | compatible = "fixed-clock"; | |
82 | #clock-cells = <0>; | |
83 | clock-frequency = <0>; | |
84 | }; | |
85 | ||
86 | main_xtal: main_xtal { | |
87 | compatible = "fixed-clock"; | |
88 | #clock-cells = <0>; | |
89 | clock-frequency = <0>; | |
90 | }; | |
e30cf8d3 LD |
91 | }; |
92 | ||
93 | ns_sram: sram@00200000 { | |
94 | compatible = "mmio-sram"; | |
95 | reg = <0x00200000 0x20000>; | |
96 | }; | |
97 | ||
98 | ahb { | |
99 | compatible = "simple-bus"; | |
100 | #address-cells = <1>; | |
101 | #size-cells = <1>; | |
102 | ranges; | |
103 | ||
104 | usb0: gadget@00300000 { | |
105 | #address-cells = <1>; | |
106 | #size-cells = <0>; | |
107 | compatible = "atmel,sama5d3-udc"; | |
108 | reg = <0x00300000 0x100000 | |
109 | 0xfc02c000 0x400>; | |
110 | interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; | |
111 | clocks = <&udphs_clk>, <&utmi>; | |
112 | clock-names = "pclk", "hclk"; | |
113 | status = "disabled"; | |
114 | ||
115 | ep0 { | |
116 | reg = <0>; | |
117 | atmel,fifo-size = <64>; | |
118 | atmel,nb-banks = <1>; | |
119 | }; | |
120 | ||
121 | ep1 { | |
122 | reg = <1>; | |
123 | atmel,fifo-size = <1024>; | |
124 | atmel,nb-banks = <3>; | |
125 | atmel,can-dma; | |
126 | atmel,can-isoc; | |
127 | }; | |
128 | ||
129 | ep2 { | |
130 | reg = <2>; | |
131 | atmel,fifo-size = <1024>; | |
132 | atmel,nb-banks = <3>; | |
133 | atmel,can-dma; | |
134 | atmel,can-isoc; | |
135 | }; | |
136 | ||
137 | ep3 { | |
138 | reg = <3>; | |
139 | atmel,fifo-size = <1024>; | |
140 | atmel,nb-banks = <2>; | |
141 | atmel,can-dma; | |
142 | atmel,can-isoc; | |
143 | }; | |
144 | ||
145 | ep4 { | |
146 | reg = <4>; | |
147 | atmel,fifo-size = <1024>; | |
148 | atmel,nb-banks = <2>; | |
149 | atmel,can-dma; | |
150 | atmel,can-isoc; | |
151 | }; | |
152 | ||
153 | ep5 { | |
154 | reg = <5>; | |
155 | atmel,fifo-size = <1024>; | |
156 | atmel,nb-banks = <2>; | |
157 | atmel,can-dma; | |
158 | atmel,can-isoc; | |
159 | }; | |
160 | ||
161 | ep6 { | |
162 | reg = <6>; | |
163 | atmel,fifo-size = <1024>; | |
164 | atmel,nb-banks = <2>; | |
165 | atmel,can-dma; | |
166 | atmel,can-isoc; | |
167 | }; | |
168 | ||
169 | ep7 { | |
170 | reg = <7>; | |
171 | atmel,fifo-size = <1024>; | |
172 | atmel,nb-banks = <2>; | |
173 | atmel,can-dma; | |
174 | atmel,can-isoc; | |
175 | }; | |
176 | ||
177 | ep8 { | |
178 | reg = <8>; | |
179 | atmel,fifo-size = <1024>; | |
180 | atmel,nb-banks = <2>; | |
181 | atmel,can-isoc; | |
182 | }; | |
183 | ||
184 | ep9 { | |
185 | reg = <9>; | |
186 | atmel,fifo-size = <1024>; | |
187 | atmel,nb-banks = <2>; | |
188 | atmel,can-isoc; | |
189 | }; | |
190 | ||
191 | ep10 { | |
192 | reg = <10>; | |
193 | atmel,fifo-size = <1024>; | |
194 | atmel,nb-banks = <2>; | |
195 | atmel,can-isoc; | |
196 | }; | |
197 | ||
198 | ep11 { | |
199 | reg = <11>; | |
200 | atmel,fifo-size = <1024>; | |
201 | atmel,nb-banks = <2>; | |
202 | atmel,can-isoc; | |
203 | }; | |
204 | ||
205 | ep12 { | |
206 | reg = <12>; | |
207 | atmel,fifo-size = <1024>; | |
208 | atmel,nb-banks = <2>; | |
209 | atmel,can-isoc; | |
210 | }; | |
211 | ||
212 | ep13 { | |
213 | reg = <13>; | |
214 | atmel,fifo-size = <1024>; | |
215 | atmel,nb-banks = <2>; | |
216 | atmel,can-isoc; | |
217 | }; | |
218 | ||
219 | ep14 { | |
220 | reg = <14>; | |
221 | atmel,fifo-size = <1024>; | |
222 | atmel,nb-banks = <2>; | |
223 | atmel,can-isoc; | |
224 | }; | |
225 | ||
226 | ep15 { | |
227 | reg = <15>; | |
228 | atmel,fifo-size = <1024>; | |
229 | atmel,nb-banks = <2>; | |
230 | atmel,can-isoc; | |
231 | }; | |
232 | }; | |
233 | ||
234 | usb1: ohci@00400000 { | |
235 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
236 | reg = <0x00400000 0x100000>; | |
237 | interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; | |
238 | clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; | |
239 | clock-names = "ohci_clk", "hclk", "uhpck"; | |
240 | status = "disabled"; | |
241 | }; | |
242 | ||
243 | usb2: ehci@00500000 { | |
244 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
245 | reg = <0x00500000 0x100000>; | |
246 | interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; | |
247 | clocks = <&utmi>, <&uhphs_clk>; | |
248 | clock-names = "usb_clk", "ehci_clk"; | |
249 | status = "disabled"; | |
250 | }; | |
251 | ||
252 | L2: cache-controller@00a00000 { | |
253 | compatible = "arm,pl310-cache"; | |
254 | reg = <0x00a00000 0x1000>; | |
255 | interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; | |
256 | cache-unified; | |
257 | cache-level = <2>; | |
258 | }; | |
259 | ||
28fe8007 RI |
260 | nand0: nand@80000000 { |
261 | compatible = "atmel,sama5d2-nand"; | |
262 | #address-cells = <1>; | |
263 | #size-cells = <1>; | |
264 | ranges; | |
265 | reg = < /* EBI CS3 */ | |
266 | 0x80000000 0x08000000 | |
267 | /* SMC PMECC regs */ | |
268 | 0xf8014070 0x00000490 | |
269 | /* SMC PMECC Error Location regs */ | |
270 | 0xf8014500 0x00000200 | |
271 | /* ROM Galois tables */ | |
272 | 0x00040000 0x00018000 | |
273 | >; | |
274 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; | |
275 | atmel,nand-addr-offset = <21>; | |
276 | atmel,nand-cmd-offset = <22>; | |
277 | atmel,nand-has-dma; | |
278 | atmel,has-pmecc; | |
279 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; | |
280 | status = "disabled"; | |
281 | ||
282 | nfc@c0000000 { | |
283 | compatible = "atmel,sama5d4-nfc"; | |
284 | #address-cells = <1>; | |
285 | #size-cells = <1>; | |
286 | reg = < /* NFC Command Registers */ | |
287 | 0xc0000000 0x08000000 | |
288 | /* NFC HSMC regs */ | |
289 | 0xf8014000 0x00000070 | |
290 | /* NFC SRAM banks */ | |
291 | 0x00100000 0x00100000 | |
292 | >; | |
293 | clocks = <&hsmc_clk>; | |
294 | atmel,write-by-sram; | |
295 | }; | |
296 | }; | |
297 | ||
512fc048 LD |
298 | sdmmc0: sdio-host@a0000000 { |
299 | compatible = "atmel,sama5d2-sdhci"; | |
300 | reg = <0xa0000000 0x300>; | |
301 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; | |
302 | clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>; | |
303 | clock-names = "hclock", "multclk", "baseclk"; | |
304 | status = "disabled"; | |
305 | }; | |
306 | ||
307 | sdmmc1: sdio-host@b0000000 { | |
308 | compatible = "atmel,sama5d2-sdhci"; | |
309 | reg = <0xb0000000 0x300>; | |
310 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; | |
311 | clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>; | |
312 | clock-names = "hclock", "multclk", "baseclk"; | |
313 | status = "disabled"; | |
314 | }; | |
315 | ||
e30cf8d3 LD |
316 | apb { |
317 | compatible = "simple-bus"; | |
318 | #address-cells = <1>; | |
319 | #size-cells = <1>; | |
320 | ranges; | |
321 | ||
fd718627 NF |
322 | hlcdc: hlcdc@f0000000 { |
323 | compatible = "atmel,sama5d2-hlcdc"; | |
324 | reg = <0xf0000000 0x2000>; | |
325 | interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; | |
326 | clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; | |
327 | clock-names = "periph_clk","sys_clk", "slow_clk"; | |
328 | status = "disabled"; | |
329 | ||
330 | hlcdc-display-controller { | |
331 | compatible = "atmel,hlcdc-display-controller"; | |
332 | #address-cells = <1>; | |
333 | #size-cells = <0>; | |
334 | ||
335 | port@0 { | |
336 | #address-cells = <1>; | |
337 | #size-cells = <0>; | |
338 | reg = <0>; | |
339 | }; | |
340 | }; | |
341 | ||
342 | hlcdc_pwm: hlcdc-pwm { | |
343 | compatible = "atmel,hlcdc-pwm"; | |
344 | #pwm-cells = <3>; | |
345 | }; | |
346 | }; | |
347 | ||
e30cf8d3 LD |
348 | ramc0: ramc@f000c000 { |
349 | compatible = "atmel,sama5d3-ddramc"; | |
350 | reg = <0xf000c000 0x200>; | |
351 | clocks = <&ddrck>, <&mpddr_clk>; | |
352 | clock-names = "ddrck", "mpddr"; | |
353 | }; | |
354 | ||
355 | dma0: dma-controller@f0010000 { | |
356 | compatible = "atmel,sama5d4-dma"; | |
357 | reg = <0xf0010000 0x1000>; | |
358 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; | |
359 | #dma-cells = <1>; | |
360 | clocks = <&dma0_clk>; | |
361 | clock-names = "dma_clk"; | |
362 | }; | |
363 | ||
364 | pmc: pmc@f0014000 { | |
620f5033 | 365 | compatible = "atmel,sama5d2-pmc", "syscon"; |
e30cf8d3 LD |
366 | reg = <0xf0014000 0x160>; |
367 | interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; | |
368 | interrupt-controller; | |
369 | #address-cells = <1>; | |
370 | #size-cells = <0>; | |
371 | #interrupt-cells = <1>; | |
372 | ||
373 | main_rc_osc: main_rc_osc { | |
374 | compatible = "atmel,at91sam9x5-clk-main-rc-osc"; | |
375 | #clock-cells = <0>; | |
376 | interrupt-parent = <&pmc>; | |
377 | interrupts = <AT91_PMC_MOSCRCS>; | |
378 | clock-frequency = <12000000>; | |
379 | clock-accuracy = <100000000>; | |
380 | }; | |
381 | ||
382 | main_osc: main_osc { | |
383 | compatible = "atmel,at91rm9200-clk-main-osc"; | |
384 | #clock-cells = <0>; | |
385 | interrupt-parent = <&pmc>; | |
386 | interrupts = <AT91_PMC_MOSCS>; | |
387 | clocks = <&main_xtal>; | |
388 | }; | |
389 | ||
390 | main: mainck { | |
391 | compatible = "atmel,at91sam9x5-clk-main"; | |
392 | #clock-cells = <0>; | |
393 | interrupt-parent = <&pmc>; | |
394 | interrupts = <AT91_PMC_MOSCSELS>; | |
395 | clocks = <&main_rc_osc &main_osc>; | |
396 | }; | |
397 | ||
398 | plla: pllack { | |
399 | compatible = "atmel,sama5d3-clk-pll"; | |
400 | #clock-cells = <0>; | |
401 | interrupt-parent = <&pmc>; | |
402 | interrupts = <AT91_PMC_LOCKA>; | |
403 | clocks = <&main>; | |
404 | reg = <0>; | |
405 | atmel,clk-input-range = <12000000 12000000>; | |
406 | #atmel,pll-clk-output-range-cells = <4>; | |
407 | atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; | |
408 | }; | |
409 | ||
410 | plladiv: plladivck { | |
411 | compatible = "atmel,at91sam9x5-clk-plldiv"; | |
412 | #clock-cells = <0>; | |
413 | clocks = <&plla>; | |
414 | }; | |
415 | ||
416 | utmi: utmick { | |
417 | compatible = "atmel,at91sam9x5-clk-utmi"; | |
418 | #clock-cells = <0>; | |
419 | interrupt-parent = <&pmc>; | |
420 | interrupts = <AT91_PMC_LOCKU>; | |
421 | clocks = <&main>; | |
422 | }; | |
423 | ||
424 | mck: masterck { | |
425 | compatible = "atmel,at91sam9x5-clk-master"; | |
426 | #clock-cells = <0>; | |
427 | interrupt-parent = <&pmc>; | |
428 | interrupts = <AT91_PMC_MCKRDY>; | |
429 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; | |
430 | atmel,clk-output-range = <124000000 166000000>; | |
431 | atmel,clk-divisors = <1 2 4 3>; | |
432 | }; | |
433 | ||
434 | h32ck: h32mxck { | |
435 | #clock-cells = <0>; | |
436 | compatible = "atmel,sama5d4-clk-h32mx"; | |
437 | clocks = <&mck>; | |
438 | }; | |
439 | ||
440 | usb: usbck { | |
441 | compatible = "atmel,at91sam9x5-clk-usb"; | |
442 | #clock-cells = <0>; | |
443 | clocks = <&plladiv>, <&utmi>; | |
444 | }; | |
445 | ||
446 | prog: progck { | |
447 | compatible = "atmel,at91sam9x5-clk-programmable"; | |
448 | #address-cells = <1>; | |
449 | #size-cells = <0>; | |
450 | interrupt-parent = <&pmc>; | |
451 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; | |
452 | ||
453 | prog0: prog0 { | |
454 | #clock-cells = <0>; | |
455 | reg = <0>; | |
456 | interrupts = <AT91_PMC_PCKRDY(0)>; | |
457 | }; | |
458 | ||
459 | prog1: prog1 { | |
460 | #clock-cells = <0>; | |
461 | reg = <1>; | |
462 | interrupts = <AT91_PMC_PCKRDY(1)>; | |
463 | }; | |
464 | ||
465 | prog2: prog2 { | |
466 | #clock-cells = <0>; | |
467 | reg = <2>; | |
468 | interrupts = <AT91_PMC_PCKRDY(2)>; | |
469 | }; | |
470 | }; | |
471 | ||
472 | systemck { | |
473 | compatible = "atmel,at91rm9200-clk-system"; | |
474 | #address-cells = <1>; | |
475 | #size-cells = <0>; | |
476 | ||
477 | ddrck: ddrck { | |
478 | #clock-cells = <0>; | |
479 | reg = <2>; | |
480 | clocks = <&mck>; | |
481 | }; | |
482 | ||
483 | lcdck: lcdck { | |
484 | #clock-cells = <0>; | |
485 | reg = <3>; | |
486 | clocks = <&mck>; | |
487 | }; | |
488 | ||
489 | uhpck: uhpck { | |
490 | #clock-cells = <0>; | |
491 | reg = <6>; | |
492 | clocks = <&usb>; | |
493 | }; | |
494 | ||
495 | udpck: udpck { | |
496 | #clock-cells = <0>; | |
497 | reg = <7>; | |
498 | clocks = <&usb>; | |
499 | }; | |
500 | ||
501 | pck0: pck0 { | |
502 | #clock-cells = <0>; | |
503 | reg = <8>; | |
504 | clocks = <&prog0>; | |
505 | }; | |
506 | ||
507 | pck1: pck1 { | |
508 | #clock-cells = <0>; | |
509 | reg = <9>; | |
510 | clocks = <&prog1>; | |
511 | }; | |
512 | ||
513 | pck2: pck2 { | |
514 | #clock-cells = <0>; | |
515 | reg = <10>; | |
516 | clocks = <&prog2>; | |
517 | }; | |
518 | ||
519 | iscck: iscck { | |
520 | #clock-cells = <0>; | |
521 | reg = <18>; | |
522 | clocks = <&mck>; | |
523 | }; | |
524 | }; | |
525 | ||
526 | periph32ck { | |
527 | compatible = "atmel,at91sam9x5-clk-peripheral"; | |
528 | #address-cells = <1>; | |
529 | #size-cells = <0>; | |
530 | clocks = <&h32ck>; | |
531 | ||
532 | macb0_clk: macb0_clk { | |
533 | #clock-cells = <0>; | |
534 | reg = <5>; | |
535 | atmel,clk-output-range = <0 83000000>; | |
536 | }; | |
537 | ||
538 | tdes_clk: tdes_clk { | |
539 | #clock-cells = <0>; | |
540 | reg = <11>; | |
541 | atmel,clk-output-range = <0 83000000>; | |
542 | }; | |
543 | ||
544 | matrix1_clk: matrix1_clk { | |
545 | #clock-cells = <0>; | |
546 | reg = <14>; | |
547 | }; | |
548 | ||
549 | hsmc_clk: hsmc_clk { | |
550 | #clock-cells = <0>; | |
551 | reg = <17>; | |
552 | }; | |
553 | ||
554 | pioA_clk: pioA_clk { | |
555 | #clock-cells = <0>; | |
556 | reg = <18>; | |
557 | atmel,clk-output-range = <0 83000000>; | |
558 | }; | |
559 | ||
560 | flx0_clk: flx0_clk { | |
561 | #clock-cells = <0>; | |
562 | reg = <19>; | |
563 | atmel,clk-output-range = <0 83000000>; | |
564 | }; | |
565 | ||
566 | flx1_clk: flx1_clk { | |
567 | #clock-cells = <0>; | |
568 | reg = <20>; | |
569 | atmel,clk-output-range = <0 83000000>; | |
570 | }; | |
571 | ||
572 | flx2_clk: flx2_clk { | |
573 | #clock-cells = <0>; | |
574 | reg = <21>; | |
575 | atmel,clk-output-range = <0 83000000>; | |
576 | }; | |
577 | ||
578 | flx3_clk: flx3_clk { | |
579 | #clock-cells = <0>; | |
580 | reg = <22>; | |
581 | atmel,clk-output-range = <0 83000000>; | |
582 | }; | |
583 | ||
584 | flx4_clk: flx4_clk { | |
585 | #clock-cells = <0>; | |
586 | reg = <23>; | |
587 | atmel,clk-output-range = <0 83000000>; | |
588 | }; | |
589 | ||
590 | uart0_clk: uart0_clk { | |
591 | #clock-cells = <0>; | |
592 | reg = <24>; | |
593 | atmel,clk-output-range = <0 83000000>; | |
594 | }; | |
595 | ||
596 | uart1_clk: uart1_clk { | |
597 | #clock-cells = <0>; | |
598 | reg = <25>; | |
599 | atmel,clk-output-range = <0 83000000>; | |
600 | }; | |
601 | ||
602 | uart2_clk: uart2_clk { | |
603 | #clock-cells = <0>; | |
604 | reg = <26>; | |
605 | atmel,clk-output-range = <0 83000000>; | |
606 | }; | |
607 | ||
608 | uart3_clk: uart3_clk { | |
609 | #clock-cells = <0>; | |
610 | reg = <27>; | |
611 | atmel,clk-output-range = <0 83000000>; | |
612 | }; | |
613 | ||
614 | uart4_clk: uart4_clk { | |
615 | #clock-cells = <0>; | |
616 | reg = <28>; | |
617 | atmel,clk-output-range = <0 83000000>; | |
618 | }; | |
619 | ||
620 | twi0_clk: twi0_clk { | |
621 | reg = <29>; | |
622 | #clock-cells = <0>; | |
623 | atmel,clk-output-range = <0 83000000>; | |
624 | }; | |
625 | ||
626 | twi1_clk: twi1_clk { | |
627 | #clock-cells = <0>; | |
628 | reg = <30>; | |
629 | atmel,clk-output-range = <0 83000000>; | |
630 | }; | |
631 | ||
632 | spi0_clk: spi0_clk { | |
633 | #clock-cells = <0>; | |
634 | reg = <33>; | |
635 | atmel,clk-output-range = <0 83000000>; | |
636 | }; | |
637 | ||
638 | spi1_clk: spi1_clk { | |
639 | #clock-cells = <0>; | |
640 | reg = <34>; | |
641 | atmel,clk-output-range = <0 83000000>; | |
642 | }; | |
643 | ||
644 | tcb0_clk: tcb0_clk { | |
645 | #clock-cells = <0>; | |
646 | reg = <35>; | |
647 | atmel,clk-output-range = <0 83000000>; | |
648 | }; | |
649 | ||
650 | tcb1_clk: tcb1_clk { | |
651 | #clock-cells = <0>; | |
652 | reg = <36>; | |
653 | atmel,clk-output-range = <0 83000000>; | |
654 | }; | |
655 | ||
656 | pwm_clk: pwm_clk { | |
657 | #clock-cells = <0>; | |
658 | reg = <38>; | |
659 | atmel,clk-output-range = <0 83000000>; | |
660 | }; | |
661 | ||
662 | adc_clk: adc_clk { | |
663 | #clock-cells = <0>; | |
664 | reg = <40>; | |
665 | atmel,clk-output-range = <0 83000000>; | |
666 | }; | |
667 | ||
668 | uhphs_clk: uhphs_clk { | |
669 | #clock-cells = <0>; | |
670 | reg = <41>; | |
671 | atmel,clk-output-range = <0 83000000>; | |
672 | }; | |
673 | ||
674 | udphs_clk: udphs_clk { | |
675 | #clock-cells = <0>; | |
676 | reg = <42>; | |
677 | atmel,clk-output-range = <0 83000000>; | |
678 | }; | |
679 | ||
680 | ssc0_clk: ssc0_clk { | |
681 | #clock-cells = <0>; | |
682 | reg = <43>; | |
683 | atmel,clk-output-range = <0 83000000>; | |
684 | }; | |
685 | ||
686 | ssc1_clk: ssc1_clk { | |
687 | #clock-cells = <0>; | |
688 | reg = <44>; | |
689 | atmel,clk-output-range = <0 83000000>; | |
690 | }; | |
691 | ||
692 | trng_clk: trng_clk { | |
693 | #clock-cells = <0>; | |
694 | reg = <47>; | |
695 | atmel,clk-output-range = <0 83000000>; | |
696 | }; | |
697 | ||
70450d4d SW |
698 | pdmic_clk: pdmic_clk { |
699 | #clock-cells = <0>; | |
700 | reg = <48>; | |
701 | atmel,clk-output-range = <0 83000000>; | |
702 | }; | |
703 | ||
512fc048 LD |
704 | i2s0_clk: i2s0_clk { |
705 | #clock-cells = <0>; | |
706 | reg = <54>; | |
707 | atmel,clk-output-range = <0 83000000>; | |
708 | }; | |
709 | ||
710 | i2s1_clk: i2s1_clk { | |
711 | #clock-cells = <0>; | |
712 | reg = <55>; | |
713 | atmel,clk-output-range = <0 83000000>; | |
714 | }; | |
715 | ||
e30cf8d3 LD |
716 | classd_clk: classd_clk { |
717 | #clock-cells = <0>; | |
718 | reg = <59>; | |
719 | atmel,clk-output-range = <0 83000000>; | |
720 | }; | |
721 | }; | |
722 | ||
723 | periph64ck { | |
724 | compatible = "atmel,at91sam9x5-clk-peripheral"; | |
725 | #address-cells = <1>; | |
726 | #size-cells = <0>; | |
727 | clocks = <&mck>; | |
728 | ||
729 | dma0_clk: dma0_clk { | |
730 | #clock-cells = <0>; | |
731 | reg = <6>; | |
732 | }; | |
733 | ||
734 | dma1_clk: dma1_clk { | |
735 | #clock-cells = <0>; | |
736 | reg = <7>; | |
737 | }; | |
738 | ||
739 | aes_clk: aes_clk { | |
740 | #clock-cells = <0>; | |
741 | reg = <9>; | |
742 | }; | |
743 | ||
744 | aesb_clk: aesb_clk { | |
745 | #clock-cells = <0>; | |
746 | reg = <10>; | |
747 | }; | |
748 | ||
749 | sha_clk: sha_clk { | |
750 | #clock-cells = <0>; | |
751 | reg = <12>; | |
752 | }; | |
753 | ||
754 | mpddr_clk: mpddr_clk { | |
755 | #clock-cells = <0>; | |
756 | reg = <13>; | |
757 | }; | |
758 | ||
759 | matrix0_clk: matrix0_clk { | |
760 | #clock-cells = <0>; | |
761 | reg = <15>; | |
762 | }; | |
763 | ||
764 | sdmmc0_hclk: sdmmc0_hclk { | |
765 | #clock-cells = <0>; | |
766 | reg = <31>; | |
767 | }; | |
768 | ||
769 | sdmmc1_hclk: sdmmc1_hclk { | |
770 | #clock-cells = <0>; | |
771 | reg = <32>; | |
772 | }; | |
773 | ||
774 | lcdc_clk: lcdc_clk { | |
775 | #clock-cells = <0>; | |
776 | reg = <45>; | |
777 | }; | |
778 | ||
779 | isc_clk: isc_clk { | |
780 | #clock-cells = <0>; | |
781 | reg = <46>; | |
782 | }; | |
783 | ||
784 | qspi0_clk: qspi0_clk { | |
785 | #clock-cells = <0>; | |
786 | reg = <52>; | |
787 | }; | |
788 | ||
789 | qspi1_clk: qspi1_clk { | |
790 | #clock-cells = <0>; | |
791 | reg = <53>; | |
792 | }; | |
793 | }; | |
512fc048 LD |
794 | |
795 | gck { | |
796 | compatible = "atmel,sama5d2-clk-generated"; | |
797 | #address-cells = <1>; | |
798 | #size-cells = <0>; | |
799 | interrupt-parent = <&pmc>; | |
800 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; | |
801 | ||
802 | sdmmc0_gclk: sdmmc0_gclk { | |
803 | #clock-cells = <0>; | |
804 | reg = <31>; | |
805 | }; | |
806 | ||
807 | sdmmc1_gclk: sdmmc1_gclk { | |
808 | #clock-cells = <0>; | |
809 | reg = <32>; | |
810 | }; | |
811 | ||
812 | tcb0_gclk: tcb0_gclk { | |
813 | #clock-cells = <0>; | |
814 | reg = <35>; | |
815 | atmel,clk-output-range = <0 83000000>; | |
816 | }; | |
817 | ||
818 | tcb1_gclk: tcb1_gclk { | |
819 | #clock-cells = <0>; | |
820 | reg = <36>; | |
821 | atmel,clk-output-range = <0 83000000>; | |
822 | }; | |
823 | ||
824 | pwm_gclk: pwm_gclk { | |
825 | #clock-cells = <0>; | |
826 | reg = <38>; | |
827 | atmel,clk-output-range = <0 83000000>; | |
828 | }; | |
829 | ||
70450d4d SW |
830 | pdmic_gclk: pdmic_gclk { |
831 | #clock-cells = <0>; | |
832 | reg = <48>; | |
833 | }; | |
834 | ||
512fc048 LD |
835 | i2s0_gclk: i2s0_gclk { |
836 | #clock-cells = <0>; | |
837 | reg = <54>; | |
838 | }; | |
839 | ||
840 | i2s1_gclk: i2s1_gclk { | |
841 | #clock-cells = <0>; | |
842 | reg = <55>; | |
843 | }; | |
844 | }; | |
e30cf8d3 LD |
845 | }; |
846 | ||
847 | sha@f0028000 { | |
848 | compatible = "atmel,at91sam9g46-sha"; | |
849 | reg = <0xf0028000 0x100>; | |
850 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; | |
851 | dmas = <&dma0 | |
852 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
853 | AT91_XDMAC_DT_PERID(30))>; | |
854 | dma-names = "tx"; | |
855 | clocks = <&sha_clk>; | |
856 | clock-names = "sha_clk"; | |
512fc048 | 857 | status = "okay"; |
e30cf8d3 LD |
858 | }; |
859 | ||
860 | aes@f002c000 { | |
861 | compatible = "atmel,at91sam9g46-aes"; | |
862 | reg = <0xf002c000 0x100>; | |
863 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; | |
864 | dmas = <&dma0 | |
865 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
866 | AT91_XDMAC_DT_PERID(26))>, | |
867 | <&dma0 | |
868 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
869 | AT91_XDMAC_DT_PERID(27))>; | |
870 | dma-names = "tx", "rx"; | |
871 | clocks = <&aes_clk>; | |
872 | clock-names = "aes_clk"; | |
512fc048 | 873 | status = "okay"; |
e30cf8d3 LD |
874 | }; |
875 | ||
876 | spi0: spi@f8000000 { | |
877 | compatible = "atmel,at91rm9200-spi"; | |
878 | reg = <0xf8000000 0x100>; | |
879 | interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; | |
880 | dmas = <&dma0 | |
881 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
882 | AT91_XDMAC_DT_PERID(6))>, | |
883 | <&dma0 | |
884 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
885 | AT91_XDMAC_DT_PERID(7))>; | |
886 | dma-names = "tx", "rx"; | |
887 | clocks = <&spi0_clk>; | |
888 | clock-names = "spi_clk"; | |
889 | atmel,fifo-size = <16>; | |
890 | #address-cells = <1>; | |
891 | #size-cells = <0>; | |
892 | status = "disabled"; | |
893 | }; | |
894 | ||
895 | macb0: ethernet@f8008000 { | |
896 | compatible = "atmel,sama5d2-gem"; | |
897 | reg = <0xf8008000 0x1000>; | |
898 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ | |
899 | 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ | |
900 | 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ | |
901 | #address-cells = <1>; | |
902 | #size-cells = <0>; | |
903 | clocks = <&macb0_clk>, <&macb0_clk>; | |
904 | clock-names = "hclk", "pclk"; | |
905 | status = "disabled"; | |
906 | }; | |
907 | ||
908 | tcb0: timer@f800c000 { | |
909 | compatible = "atmel,at91sam9x5-tcb"; | |
910 | reg = <0xf800c000 0x100>; | |
911 | interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; | |
761c5867 AB |
912 | clocks = <&tcb0_clk>, <&clk32k>; |
913 | clock-names = "t0_clk", "slow_clk"; | |
e30cf8d3 LD |
914 | }; |
915 | ||
916 | tcb1: timer@f8010000 { | |
917 | compatible = "atmel,at91sam9x5-tcb"; | |
918 | reg = <0xf8010000 0x100>; | |
919 | interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; | |
761c5867 AB |
920 | clocks = <&tcb1_clk>, <&clk32k>; |
921 | clock-names = "t0_clk", "slow_clk"; | |
e30cf8d3 LD |
922 | }; |
923 | ||
70450d4d SW |
924 | pdmic: pdmic@f8018000 { |
925 | compatible = "atmel,sama5d2-pdmic"; | |
926 | reg = <0xf8018000 0x124>; | |
927 | interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; | |
928 | dmas = <&dma0 | |
929 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
930 | | AT91_XDMAC_DT_PERID(50))>; | |
931 | dma-names = "rx"; | |
932 | clocks = <&pdmic_clk>, <&pdmic_gclk>; | |
933 | clock-names = "pclk", "gclk"; | |
934 | status = "disabled"; | |
935 | }; | |
936 | ||
e30cf8d3 LD |
937 | uart0: serial@f801c000 { |
938 | compatible = "atmel,at91sam9260-usart"; | |
939 | reg = <0xf801c000 0x100>; | |
940 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; | |
b1708b72 NF |
941 | dmas = <&dma0 |
942 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
943 | AT91_XDMAC_DT_PERID(35))>, | |
944 | <&dma0 | |
945 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
946 | AT91_XDMAC_DT_PERID(36))>; | |
947 | dma-names = "tx", "rx"; | |
e30cf8d3 LD |
948 | clocks = <&uart0_clk>; |
949 | clock-names = "usart"; | |
950 | status = "disabled"; | |
951 | }; | |
952 | ||
953 | uart1: serial@f8020000 { | |
954 | compatible = "atmel,at91sam9260-usart"; | |
955 | reg = <0xf8020000 0x100>; | |
956 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; | |
b1708b72 NF |
957 | dmas = <&dma0 |
958 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
959 | AT91_XDMAC_DT_PERID(37))>, | |
960 | <&dma0 | |
961 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
962 | AT91_XDMAC_DT_PERID(38))>; | |
963 | dma-names = "tx", "rx"; | |
e30cf8d3 LD |
964 | clocks = <&uart1_clk>; |
965 | clock-names = "usart"; | |
966 | status = "disabled"; | |
967 | }; | |
968 | ||
969 | uart2: serial@f8024000 { | |
970 | compatible = "atmel,at91sam9260-usart"; | |
971 | reg = <0xf8024000 0x100>; | |
972 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; | |
b1708b72 NF |
973 | dmas = <&dma0 |
974 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
975 | AT91_XDMAC_DT_PERID(39))>, | |
976 | <&dma0 | |
977 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
978 | AT91_XDMAC_DT_PERID(40))>; | |
979 | dma-names = "tx", "rx"; | |
e30cf8d3 LD |
980 | clocks = <&uart2_clk>; |
981 | clock-names = "usart"; | |
982 | status = "disabled"; | |
983 | }; | |
984 | ||
985 | i2c0: i2c@f8028000 { | |
986 | compatible = "atmel,sama5d2-i2c"; | |
987 | reg = <0xf8028000 0x100>; | |
988 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; | |
989 | dmas = <&dma0 | |
990 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
991 | AT91_XDMAC_DT_PERID(0))>, | |
992 | <&dma0 | |
993 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
994 | AT91_XDMAC_DT_PERID(1))>; | |
995 | dma-names = "tx", "rx"; | |
996 | #address-cells = <1>; | |
997 | #size-cells = <0>; | |
998 | clocks = <&twi0_clk>; | |
999 | status = "disabled"; | |
1000 | }; | |
1001 | ||
c8f26c26 CP |
1002 | sfr: sfr@f8030000 { |
1003 | compatible = "atmel,sama5d2-sfr", "syscon"; | |
1004 | reg = <0xf8030000 0x98>; | |
1005 | }; | |
1006 | ||
512fc048 LD |
1007 | flx0: flexcom@f8034000 { |
1008 | compatible = "atmel,sama5d2-flexcom"; | |
1009 | reg = <0xf8034000 0x200>; | |
1010 | clocks = <&flx0_clk>; | |
1011 | #address-cells = <1>; | |
1012 | #size-cells = <1>; | |
1013 | ranges = <0x0 0xf8034000 0x800>; | |
1014 | status = "disabled"; | |
1015 | }; | |
1016 | ||
1017 | flx1: flexcom@f8038000 { | |
1018 | compatible = "atmel,sama5d2-flexcom"; | |
1019 | reg = <0xf8038000 0x200>; | |
1020 | clocks = <&flx1_clk>; | |
1021 | #address-cells = <1>; | |
1022 | #size-cells = <1>; | |
1023 | ranges = <0x0 0xf8038000 0x800>; | |
1024 | status = "disabled"; | |
1025 | }; | |
1026 | ||
1027 | rstc@f8048000 { | |
1028 | compatible = "atmel,sama5d3-rstc"; | |
1029 | reg = <0xf8048000 0x10>; | |
1030 | clocks = <&clk32k>; | |
1031 | }; | |
1032 | ||
e4b9a21b NF |
1033 | shdwc@f8048010 { |
1034 | compatible = "atmel,sama5d2-shdwc"; | |
1035 | reg = <0xf8048010 0x10>; | |
1036 | clocks = <&clk32k>; | |
1037 | #address-cells = <1>; | |
1038 | #size-cells = <0>; | |
1039 | atmel,wakeup-rtc-timer; | |
1040 | }; | |
1041 | ||
e30cf8d3 LD |
1042 | pit: timer@f8048030 { |
1043 | compatible = "atmel,at91sam9260-pit"; | |
1044 | reg = <0xf8048030 0x10>; | |
1045 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; | |
1046 | clocks = <&h32ck>; | |
1047 | }; | |
1048 | ||
92bd7aa4 WY |
1049 | watchdog@f8048040 { |
1050 | compatible = "atmel,sama5d4-wdt"; | |
1051 | reg = <0xf8048040 0x10>; | |
1052 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; | |
51755007 | 1053 | clocks = <&clk32k>; |
92bd7aa4 WY |
1054 | status = "disabled"; |
1055 | }; | |
1056 | ||
e30cf8d3 LD |
1057 | sckc@f8048050 { |
1058 | compatible = "atmel,at91sam9x5-sckc"; | |
1059 | reg = <0xf8048050 0x4>; | |
1060 | ||
1061 | slow_rc_osc: slow_rc_osc { | |
1062 | compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; | |
1063 | #clock-cells = <0>; | |
1064 | clock-frequency = <32768>; | |
1065 | clock-accuracy = <250000000>; | |
1066 | atmel,startup-time-usec = <75>; | |
1067 | }; | |
1068 | ||
1069 | slow_osc: slow_osc { | |
1070 | compatible = "atmel,at91sam9x5-clk-slow-osc"; | |
1071 | #clock-cells = <0>; | |
1072 | clocks = <&slow_xtal>; | |
1073 | atmel,startup-time-usec = <1200000>; | |
1074 | }; | |
1075 | ||
1076 | clk32k: slowck { | |
1077 | compatible = "atmel,at91sam9x5-clk-slow"; | |
1078 | #clock-cells = <0>; | |
1079 | clocks = <&slow_rc_osc &slow_osc>; | |
1080 | }; | |
1081 | }; | |
1082 | ||
1083 | rtc@f80480b0 { | |
1084 | compatible = "atmel,at91rm9200-rtc"; | |
1085 | reg = <0xf80480b0 0x30>; | |
1086 | interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; | |
761c5867 | 1087 | clocks = <&clk32k>; |
e30cf8d3 LD |
1088 | }; |
1089 | ||
1090 | spi1: spi@fc000000 { | |
1091 | compatible = "atmel,at91rm9200-spi"; | |
1092 | reg = <0xfc000000 0x100>; | |
1093 | interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; | |
1094 | dmas = <&dma0 | |
1095 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1096 | AT91_XDMAC_DT_PERID(8))>, | |
1097 | <&dma0 | |
1098 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1099 | AT91_XDMAC_DT_PERID(9))>; | |
1100 | dma-names = "tx", "rx"; | |
1101 | clocks = <&spi1_clk>; | |
1102 | clock-names = "spi_clk"; | |
1103 | atmel,fifo-size = <16>; | |
1104 | #address-cells = <1>; | |
1105 | #size-cells = <0>; | |
1106 | status = "disabled"; | |
1107 | }; | |
1108 | ||
1109 | uart3: serial@fc008000 { | |
1110 | compatible = "atmel,at91sam9260-usart"; | |
1111 | reg = <0xfc008000 0x100>; | |
1112 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; | |
b1708b72 NF |
1113 | dmas = <&dma0 |
1114 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1115 | AT91_XDMAC_DT_PERID(41))>, | |
1116 | <&dma0 | |
1117 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1118 | AT91_XDMAC_DT_PERID(42))>; | |
1119 | dma-names = "tx", "rx"; | |
e30cf8d3 LD |
1120 | clocks = <&uart3_clk>; |
1121 | clock-names = "usart"; | |
1122 | status = "disabled"; | |
1123 | }; | |
1124 | ||
1125 | uart4: serial@fc00c000 { | |
1126 | compatible = "atmel,at91sam9260-usart"; | |
1127 | reg = <0xfc00c000 0x100>; | |
b1708b72 NF |
1128 | dmas = <&dma0 |
1129 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1130 | AT91_XDMAC_DT_PERID(43))>, | |
1131 | <&dma0 | |
1132 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1133 | AT91_XDMAC_DT_PERID(44))>; | |
1134 | dma-names = "tx", "rx"; | |
e30cf8d3 LD |
1135 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; |
1136 | clocks = <&uart4_clk>; | |
1137 | clock-names = "usart"; | |
1138 | status = "disabled"; | |
1139 | }; | |
1140 | ||
512fc048 LD |
1141 | flx2: flexcom@fc010000 { |
1142 | compatible = "atmel,sama5d2-flexcom"; | |
1143 | reg = <0xfc010000 0x200>; | |
1144 | clocks = <&flx2_clk>; | |
1145 | #address-cells = <1>; | |
1146 | #size-cells = <1>; | |
1147 | ranges = <0x0 0xfc010000 0x800>; | |
1148 | status = "disabled"; | |
1149 | }; | |
1150 | ||
1151 | flx3: flexcom@fc014000 { | |
1152 | compatible = "atmel,sama5d2-flexcom"; | |
1153 | reg = <0xfc014000 0x200>; | |
1154 | clocks = <&flx3_clk>; | |
1155 | #address-cells = <1>; | |
1156 | #size-cells = <1>; | |
1157 | ranges = <0x0 0xfc014000 0x800>; | |
1158 | status = "disabled"; | |
1159 | }; | |
1160 | ||
1161 | flx4: flexcom@fc018000 { | |
1162 | compatible = "atmel,sama5d2-flexcom"; | |
1163 | reg = <0xfc018000 0x200>; | |
1164 | clocks = <&flx4_clk>; | |
1165 | #address-cells = <1>; | |
1166 | #size-cells = <1>; | |
1167 | ranges = <0x0 0xfc018000 0x800>; | |
1168 | status = "disabled"; | |
1169 | }; | |
1170 | ||
02eb8d68 MW |
1171 | trng@fc01c000 { |
1172 | compatible = "atmel,at91sam9g45-trng"; | |
1173 | reg = <0xfc01c000 0x100>; | |
1174 | interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; | |
1175 | clocks = <&trng_clk>; | |
1176 | }; | |
1177 | ||
e30cf8d3 LD |
1178 | aic: interrupt-controller@fc020000 { |
1179 | #interrupt-cells = <3>; | |
1180 | compatible = "atmel,sama5d2-aic"; | |
1181 | interrupt-controller; | |
1182 | reg = <0xfc020000 0x200>; | |
1183 | atmel,external-irqs = <49>; | |
1184 | }; | |
1185 | ||
1186 | i2c1: i2c@fc028000 { | |
1187 | compatible = "atmel,sama5d2-i2c"; | |
1188 | reg = <0xfc028000 0x100>; | |
1189 | interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; | |
1190 | dmas = <&dma0 | |
1191 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1192 | AT91_XDMAC_DT_PERID(2))>, | |
1193 | <&dma0 | |
1194 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1195 | AT91_XDMAC_DT_PERID(3))>; | |
1196 | dma-names = "tx", "rx"; | |
1197 | #address-cells = <1>; | |
1198 | #size-cells = <0>; | |
1199 | clocks = <&twi1_clk>; | |
1200 | status = "disabled"; | |
1201 | }; | |
f6c804b0 | 1202 | |
aea14e14 LD |
1203 | adc: adc@fc030000 { |
1204 | compatible = "atmel,sama5d2-adc"; | |
1205 | reg = <0xfc030000 0x100>; | |
1206 | interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; | |
1207 | clocks = <&adc_clk>; | |
1208 | clock-names = "adc_clk"; | |
1209 | atmel,min-sample-rate-hz = <200000>; | |
1210 | atmel,max-sample-rate-hz = <20000000>; | |
1211 | atmel,startup-time-ms = <4>; | |
1212 | status = "disabled"; | |
1213 | }; | |
1214 | ||
f6c804b0 LD |
1215 | pioA: pinctrl@fc038000 { |
1216 | compatible = "atmel,sama5d2-pinctrl"; | |
1217 | reg = <0xfc038000 0x600>; | |
1218 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, | |
1219 | <68 IRQ_TYPE_LEVEL_HIGH 7>, | |
1220 | <69 IRQ_TYPE_LEVEL_HIGH 7>, | |
1221 | <70 IRQ_TYPE_LEVEL_HIGH 7>; | |
1222 | interrupt-controller; | |
1223 | #interrupt-cells = <2>; | |
1224 | gpio-controller; | |
1225 | #gpio-cells = <2>; | |
1226 | clocks = <&pioA_clk>; | |
1227 | }; | |
c0d6fe2f | 1228 | |
512fc048 LD |
1229 | tdes@fc044000 { |
1230 | compatible = "atmel,at91sam9g46-tdes"; | |
1231 | reg = <0xfc044000 0x100>; | |
1232 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; | |
1233 | dmas = <&dma0 | |
1234 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1235 | AT91_XDMAC_DT_PERID(28))>, | |
1236 | <&dma0 | |
1237 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
1238 | AT91_XDMAC_DT_PERID(29))>; | |
1239 | dma-names = "tx", "rx"; | |
1240 | clocks = <&tdes_clk>; | |
1241 | clock-names = "tdes_clk"; | |
1242 | status = "okay"; | |
1243 | }; | |
d77c2387 LD |
1244 | |
1245 | chipid@fc069000 { | |
1246 | compatible = "atmel,sama5d2-chipid"; | |
1247 | reg = <0xfc069000 0x8>; | |
1248 | }; | |
e30cf8d3 LD |
1249 | }; |
1250 | }; | |
1251 | }; |