projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 655ff266 LD |
1 | /* |
| 2 | * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC | |
| 3 | * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC | |
| 4 | * | |
| 5 | * Copyright (C) 2013 Atmel, | |
| 6 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | |
| 7 | * | |
| 8 | * Licensed under GPLv2 or later. | |
| 9 | */ | |
| 10 | ||
| 6db64d29 | 11 | #include "skeleton.dtsi" |
| 92f8629b | 12 | #include <dt-bindings/gpio/gpio.h> |
| 655ff266 LD |
13 | |
| 14 | / { | |
| 15 | model = "Atmel SAMA5D3 family SoC"; | |
| 16 | compatible = "atmel,sama5d3", "atmel,sama5"; | |
| 17 | interrupt-parent = <&aic>; | |
| 18 | ||
| 19 | aliases { | |
| 20 | serial0 = &dbgu; | |
| 21 | serial1 = &usart0; | |
| 22 | serial2 = &usart1; | |
| 23 | serial3 = &usart2; | |
| 24 | serial4 = &usart3; | |
| 25 | gpio0 = &pioA; | |
| 26 | gpio1 = &pioB; | |
| 27 | gpio2 = &pioC; | |
| 28 | gpio3 = &pioD; | |
| 29 | gpio4 = &pioE; | |
| 30 | tcb0 = &tcb0; | |
| 31 | tcb1 = &tcb1; | |
| 32 | i2c0 = &i2c0; | |
| 33 | i2c1 = &i2c1; | |
| 34 | i2c2 = &i2c2; | |
| 35 | ssc0 = &ssc0; | |
| 36 | ssc1 = &ssc1; | |
| 37 | }; | |
| 38 | cpus { | |
| 39 | cpu@0 { | |
| 40 | compatible = "arm,cortex-a5"; | |
| 41 | }; | |
| 42 | }; | |
| 43 | ||
| 44 | memory { | |
| 45 | reg = <0x20000000 0x8000000>; | |
| 46 | }; | |
| 47 | ||
| 48 | ahb { | |
| 49 | compatible = "simple-bus"; | |
| 50 | #address-cells = <1>; | |
| 51 | #size-cells = <1>; | |
| 52 | ranges; | |
| 53 | ||
| 54 | apb { | |
| 55 | compatible = "simple-bus"; | |
| 56 | #address-cells = <1>; | |
| 57 | #size-cells = <1>; | |
| 58 | ranges; | |
| 59 | ||
| 60 | mmc0: mmc@f0000000 { | |
| 61 | compatible = "atmel,hsmci"; | |
| 62 | reg = <0xf0000000 0x600>; | |
| 63 | interrupts = <21 4 0>; | |
| 05c1bc97 LD |
64 | dmas = <&dma0 2 0>; |
| 65 | dma-names = "rxtx"; | |
| 655ff266 LD |
66 | pinctrl-names = "default"; |
| 67 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; | |
| 68 | status = "disabled"; | |
| 69 | #address-cells = <1>; | |
| 70 | #size-cells = <0>; | |
| 71 | }; | |
| 72 | ||
| 73 | spi0: spi@f0004000 { | |
| 74 | #address-cells = <1>; | |
| 75 | #size-cells = <0>; | |
| 76 | compatible = "atmel,at91sam9x5-spi"; | |
| 77 | reg = <0xf0004000 0x100>; | |
| 78 | interrupts = <24 4 3>; | |
| 79 | cs-gpios = <&pioD 13 0 | |
| 80 | &pioD 14 0 /* conflicts with SCK0 and CANRX0 */ | |
| 81 | &pioD 15 0 /* conflicts with CTS0 and CANTX0 */ | |
| 82 | &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */ | |
| 83 | >; | |
| 84 | pinctrl-names = "default"; | |
| 85 | pinctrl-0 = <&pinctrl_spi0>; | |
| 86 | status = "disabled"; | |
| 87 | }; | |
| 88 | ||
| 89 | ssc0: ssc@f0008000 { | |
| 90 | compatible = "atmel,at91sam9g45-ssc"; | |
| 91 | reg = <0xf0008000 0x4000>; | |
| 92 | interrupts = <38 4 4>; | |
| 93 | pinctrl-names = "default"; | |
| 94 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | |
| 95 | status = "disabled"; | |
| 96 | }; | |
| 97 | ||
| 98 | can0: can@f000c000 { | |
| 99 | compatible = "atmel,at91sam9x5-can"; | |
| 100 | reg = <0xf000c000 0x300>; | |
| 101 | interrupts = <40 4 3>; | |
| 102 | pinctrl-names = "default"; | |
| 103 | pinctrl-0 = <&pinctrl_can0_rx_tx>; | |
| 104 | status = "disabled"; | |
| 105 | }; | |
| 106 | ||
| 107 | tcb0: timer@f0010000 { | |
| 108 | compatible = "atmel,at91sam9x5-tcb"; | |
| 109 | reg = <0xf0010000 0x100>; | |
| 110 | interrupts = <26 4 0>; | |
| 111 | }; | |
| 112 | ||
| 113 | i2c0: i2c@f0014000 { | |
| 114 | compatible = "atmel,at91sam9x5-i2c"; | |
| 115 | reg = <0xf0014000 0x4000>; | |
| 116 | interrupts = <18 4 6>; | |
| d9a63a45 LD |
117 | dmas = <&dma0 2 7>, |
| 118 | <&dma0 2 8>; | |
| 119 | dma-names = "tx", "rx"; | |
| 655ff266 LD |
120 | pinctrl-names = "default"; |
| 121 | pinctrl-0 = <&pinctrl_i2c0>; | |
| 122 | #address-cells = <1>; | |
| 123 | #size-cells = <0>; | |
| 124 | status = "disabled"; | |
| 125 | }; | |
| 126 | ||
| 127 | i2c1: i2c@f0018000 { | |
| 128 | compatible = "atmel,at91sam9x5-i2c"; | |
| 129 | reg = <0xf0018000 0x4000>; | |
| 130 | interrupts = <19 4 6>; | |
| d9a63a45 LD |
131 | dmas = <&dma0 2 9>, |
| 132 | <&dma0 2 10>; | |
| 133 | dma-names = "tx", "rx"; | |
| 655ff266 LD |
134 | pinctrl-names = "default"; |
| 135 | pinctrl-0 = <&pinctrl_i2c1>; | |
| 136 | #address-cells = <1>; | |
| 137 | #size-cells = <0>; | |
| 138 | status = "disabled"; | |
| 139 | }; | |
| 140 | ||
| 141 | usart0: serial@f001c000 { | |
| 142 | compatible = "atmel,at91sam9260-usart"; | |
| 143 | reg = <0xf001c000 0x100>; | |
| 144 | interrupts = <12 4 5>; | |
| 145 | pinctrl-names = "default"; | |
| 146 | pinctrl-0 = <&pinctrl_usart0>; | |
| 147 | status = "disabled"; | |
| 148 | }; | |
| 149 | ||
| 150 | usart1: serial@f0020000 { | |
| 151 | compatible = "atmel,at91sam9260-usart"; | |
| 152 | reg = <0xf0020000 0x100>; | |
| 153 | interrupts = <13 4 5>; | |
| 154 | pinctrl-names = "default"; | |
| 155 | pinctrl-0 = <&pinctrl_usart1>; | |
| 156 | status = "disabled"; | |
| 157 | }; | |
| 158 | ||
| 159 | macb0: ethernet@f0028000 { | |
| 160 | compatible = "cnds,pc302-gem", "cdns,gem"; | |
| 161 | reg = <0xf0028000 0x100>; | |
| 162 | interrupts = <34 4 3>; | |
| 163 | pinctrl-names = "default"; | |
| 164 | pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; | |
| 165 | status = "disabled"; | |
| 166 | }; | |
| 167 | ||
| 168 | isi: isi@f0034000 { | |
| 169 | compatible = "atmel,at91sam9g45-isi"; | |
| 170 | reg = <0xf0034000 0x4000>; | |
| 171 | interrupts = <37 4 5>; | |
| 172 | status = "disabled"; | |
| 173 | }; | |
| 174 | ||
| 175 | mmc1: mmc@f8000000 { | |
| 176 | compatible = "atmel,hsmci"; | |
| 177 | reg = <0xf8000000 0x600>; | |
| 178 | interrupts = <22 4 0>; | |
| 05c1bc97 LD |
179 | dmas = <&dma1 2 0>; |
| 180 | dma-names = "rxtx"; | |
| 655ff266 LD |
181 | pinctrl-names = "default"; |
| 182 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; | |
| 183 | status = "disabled"; | |
| 184 | #address-cells = <1>; | |
| 185 | #size-cells = <0>; | |
| 186 | }; | |
| 187 | ||
| 188 | mmc2: mmc@f8004000 { | |
| 189 | compatible = "atmel,hsmci"; | |
| 190 | reg = <0xf8004000 0x600>; | |
| 191 | interrupts = <23 4 0>; | |
| 05c1bc97 LD |
192 | dmas = <&dma1 2 1>; |
| 193 | dma-names = "rxtx"; | |
| 655ff266 LD |
194 | pinctrl-names = "default"; |
| 195 | pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; | |
| 196 | status = "disabled"; | |
| 197 | #address-cells = <1>; | |
| 198 | #size-cells = <0>; | |
| 199 | }; | |
| 200 | ||
| 201 | spi1: spi@f8008000 { | |
| 202 | #address-cells = <1>; | |
| 203 | #size-cells = <0>; | |
| 204 | compatible = "atmel,at91sam9x5-spi"; | |
| 205 | reg = <0xf8008000 0x100>; | |
| 206 | interrupts = <25 4 3>; | |
| 207 | cs-gpios = <&pioC 25 0 | |
| 208 | &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */ | |
| 209 | &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */ | |
| 210 | &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */ | |
| 211 | >; | |
| 212 | pinctrl-names = "default"; | |
| 213 | pinctrl-0 = <&pinctrl_spi1>; | |
| 214 | status = "disabled"; | |
| 215 | }; | |
| 216 | ||
| 217 | ssc1: ssc@f800c000 { | |
| 218 | compatible = "atmel,at91sam9g45-ssc"; | |
| 219 | reg = <0xf800c000 0x4000>; | |
| 220 | interrupts = <39 4 4>; | |
| 221 | pinctrl-names = "default"; | |
| 222 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | |
| 223 | status = "disabled"; | |
| 224 | }; | |
| 225 | ||
| 226 | can1: can@f8010000 { | |
| 227 | compatible = "atmel,at91sam9x5-can"; | |
| 228 | reg = <0xf8010000 0x300>; | |
| 229 | interrupts = <41 4 3>; | |
| 230 | pinctrl-names = "default"; | |
| 231 | pinctrl-0 = <&pinctrl_can1_rx_tx>; | |
| 232 | }; | |
| 233 | ||
| 234 | tcb1: timer@f8014000 { | |
| 235 | compatible = "atmel,at91sam9x5-tcb"; | |
| 236 | reg = <0xf8014000 0x100>; | |
| 237 | interrupts = <27 4 0>; | |
| 238 | }; | |
| 239 | ||
| 240 | adc0: adc@f8018000 { | |
| 241 | compatible = "atmel,at91sam9260-adc"; | |
| 242 | reg = <0xf8018000 0x100>; | |
| 243 | interrupts = <29 4 5>; | |
| 244 | pinctrl-names = "default"; | |
| 245 | pinctrl-0 = < | |
| 246 | &pinctrl_adc0_adtrg | |
| 247 | &pinctrl_adc0_ad0 | |
| 248 | &pinctrl_adc0_ad1 | |
| 249 | &pinctrl_adc0_ad2 | |
| 250 | &pinctrl_adc0_ad3 | |
| 251 | &pinctrl_adc0_ad4 | |
| 252 | &pinctrl_adc0_ad5 | |
| 253 | &pinctrl_adc0_ad6 | |
| 254 | &pinctrl_adc0_ad7 | |
| 255 | &pinctrl_adc0_ad8 | |
| 256 | &pinctrl_adc0_ad9 | |
| 257 | &pinctrl_adc0_ad10 | |
| 258 | &pinctrl_adc0_ad11 | |
| 259 | >; | |
| 260 | atmel,adc-channel-base = <0x50>; | |
| 261 | atmel,adc-channels-used = <0xfff>; | |
| 262 | atmel,adc-drdy-mask = <0x1000000>; | |
| 263 | atmel,adc-num-channels = <12>; | |
| 264 | atmel,adc-startup-time = <40>; | |
| 265 | atmel,adc-status-register = <0x30>; | |
| 266 | atmel,adc-trigger-register = <0xc0>; | |
| 267 | atmel,adc-use-external; | |
| 268 | atmel,adc-vref = <3000>; | |
| 269 | atmel,adc-res = <10 12>; | |
| 270 | atmel,adc-res-names = "lowres", "highres"; | |
| 271 | status = "disabled"; | |
| 272 | ||
| 273 | trigger@0 { | |
| 274 | trigger-name = "external-rising"; | |
| 275 | trigger-value = <0x1>; | |
| 276 | trigger-external; | |
| 277 | }; | |
| 278 | trigger@1 { | |
| 279 | trigger-name = "external-falling"; | |
| 280 | trigger-value = <0x2>; | |
| 281 | trigger-external; | |
| 282 | }; | |
| 283 | trigger@2 { | |
| 284 | trigger-name = "external-any"; | |
| 285 | trigger-value = <0x3>; | |
| 286 | trigger-external; | |
| 287 | }; | |
| 288 | trigger@3 { | |
| 289 | trigger-name = "continuous"; | |
| 290 | trigger-value = <0x6>; | |
| 291 | }; | |
| 292 | }; | |
| 293 | ||
| 294 | tsadcc: tsadcc@f8018000 { | |
| 295 | compatible = "atmel,at91sam9x5-tsadcc"; | |
| 296 | reg = <0xf8018000 0x4000>; | |
| 297 | interrupts = <29 4 5>; | |
| 298 | atmel,tsadcc_clock = <300000>; | |
| 299 | atmel,filtering_average = <0x03>; | |
| 300 | atmel,pendet_debounce = <0x08>; | |
| 301 | atmel,pendet_sensitivity = <0x02>; | |
| 302 | atmel,ts_sample_hold_time = <0x0a>; | |
| 303 | status = "disabled"; | |
| 304 | }; | |
| 305 | ||
| 306 | i2c2: i2c@f801c000 { | |
| 307 | compatible = "atmel,at91sam9x5-i2c"; | |
| 308 | reg = <0xf801c000 0x4000>; | |
| 309 | interrupts = <20 4 6>; | |
| d9a63a45 LD |
310 | dmas = <&dma1 2 11>, |
| 311 | <&dma1 2 12>; | |
| 312 | dma-names = "tx", "rx"; | |
| 655ff266 LD |
313 | #address-cells = <1>; |
| 314 | #size-cells = <0>; | |
| 315 | status = "disabled"; | |
| 316 | }; | |
| 317 | ||
| 318 | usart2: serial@f8020000 { | |
| 319 | compatible = "atmel,at91sam9260-usart"; | |
| 320 | reg = <0xf8020000 0x100>; | |
| 321 | interrupts = <14 4 5>; | |
| 322 | pinctrl-names = "default"; | |
| 323 | pinctrl-0 = <&pinctrl_usart2>; | |
| 324 | status = "disabled"; | |
| 325 | }; | |
| 326 | ||
| 327 | usart3: serial@f8024000 { | |
| 328 | compatible = "atmel,at91sam9260-usart"; | |
| 329 | reg = <0xf8024000 0x100>; | |
| 330 | interrupts = <15 4 5>; | |
| 331 | pinctrl-names = "default"; | |
| 332 | pinctrl-0 = <&pinctrl_usart3>; | |
| 333 | status = "disabled"; | |
| 334 | }; | |
| 335 | ||
| 336 | macb1: ethernet@f802c000 { | |
| 337 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | |
| 338 | reg = <0xf802c000 0x100>; | |
| 339 | interrupts = <35 4 3>; | |
| 340 | pinctrl-names = "default"; | |
| 341 | pinctrl-0 = <&pinctrl_macb1_rmii>; | |
| 342 | status = "disabled"; | |
| 343 | }; | |
| 344 | ||
| 345 | sha@f8034000 { | |
| 346 | compatible = "atmel,sam9g46-sha"; | |
| 347 | reg = <0xf8034000 0x100>; | |
| 348 | interrupts = <42 4 0>; | |
| 349 | }; | |
| 350 | ||
| 351 | aes@f8038000 { | |
| 352 | compatible = "atmel,sam9g46-aes"; | |
| 353 | reg = <0xf8038000 0x100>; | |
| 354 | interrupts = <43 4 0>; | |
| 355 | }; | |
| 356 | ||
| 357 | tdes@f803c000 { | |
| 358 | compatible = "atmel,sam9g46-tdes"; | |
| 359 | reg = <0xf803c000 0x100>; | |
| 360 | interrupts = <44 4 0>; | |
| 361 | }; | |
| 362 | ||
| 363 | dma0: dma-controller@ffffe600 { | |
| 364 | compatible = "atmel,at91sam9g45-dma"; | |
| 365 | reg = <0xffffe600 0x200>; | |
| 366 | interrupts = <30 4 0>; | |
| 980ce7d9 | 367 | #dma-cells = <2>; |
| 655ff266 LD |
368 | }; |
| 369 | ||
| 370 | dma1: dma-controller@ffffe800 { | |
| 371 | compatible = "atmel,at91sam9g45-dma"; | |
| 372 | reg = <0xffffe800 0x200>; | |
| 373 | interrupts = <31 4 0>; | |
| 980ce7d9 | 374 | #dma-cells = <2>; |
| 655ff266 LD |
375 | }; |
| 376 | ||
| 377 | ramc0: ramc@ffffea00 { | |
| 378 | compatible = "atmel,at91sam9g45-ddramc"; | |
| 379 | reg = <0xffffea00 0x200>; | |
| 380 | }; | |
| 381 | ||
| 382 | dbgu: serial@ffffee00 { | |
| 383 | compatible = "atmel,at91sam9260-usart"; | |
| 384 | reg = <0xffffee00 0x200>; | |
| 385 | interrupts = <2 4 7>; | |
| 386 | pinctrl-names = "default"; | |
| 387 | pinctrl-0 = <&pinctrl_dbgu>; | |
| 388 | status = "disabled"; | |
| 389 | }; | |
| 390 | ||
| 391 | aic: interrupt-controller@fffff000 { | |
| 392 | #interrupt-cells = <3>; | |
| 393 | compatible = "atmel,sama5d3-aic"; | |
| 394 | interrupt-controller; | |
| 395 | reg = <0xfffff000 0x200>; | |
| 396 | atmel,external-irqs = <47>; | |
| 397 | }; | |
| 398 | ||
| 399 | pinctrl@fffff200 { | |
| 400 | #address-cells = <1>; | |
| 401 | #size-cells = <1>; | |
| 402 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; | |
| 403 | ranges = <0xfffff200 0xfffff200 0xa00>; | |
| 404 | atmel,mux-mask = < | |
| 405 | /* A B C */ | |
| 406 | 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ | |
| 407 | 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ | |
| 408 | 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ | |
| 409 | 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ | |
| 410 | 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ | |
| 411 | >; | |
| 412 | ||
| 413 | /* shared pinctrl settings */ | |
| 414 | adc0 { | |
| 415 | pinctrl_adc0_adtrg: adc0_adtrg { | |
| 416 | atmel,pins = | |
| 417 | <3 19 0x1 0x0>; /* PD19 periph A ADTRG */ | |
| 418 | }; | |
| 419 | pinctrl_adc0_ad0: adc0_ad0 { | |
| 420 | atmel,pins = | |
| 421 | <3 20 0x1 0x0>; /* PD20 periph A AD0 */ | |
| 422 | }; | |
| 423 | pinctrl_adc0_ad1: adc0_ad1 { | |
| 424 | atmel,pins = | |
| 425 | <3 21 0x1 0x0>; /* PD21 periph A AD1 */ | |
| 426 | }; | |
| 427 | pinctrl_adc0_ad2: adc0_ad2 { | |
| 428 | atmel,pins = | |
| 429 | <3 22 0x1 0x0>; /* PD22 periph A AD2 */ | |
| 430 | }; | |
| 431 | pinctrl_adc0_ad3: adc0_ad3 { | |
| 432 | atmel,pins = | |
| 433 | <3 23 0x1 0x0>; /* PD23 periph A AD3 */ | |
| 434 | }; | |
| 435 | pinctrl_adc0_ad4: adc0_ad4 { | |
| 436 | atmel,pins = | |
| 437 | <3 24 0x1 0x0>; /* PD24 periph A AD4 */ | |
| 438 | }; | |
| 439 | pinctrl_adc0_ad5: adc0_ad5 { | |
| 440 | atmel,pins = | |
| 441 | <3 25 0x1 0x0>; /* PD25 periph A AD5 */ | |
| 442 | }; | |
| 443 | pinctrl_adc0_ad6: adc0_ad6 { | |
| 444 | atmel,pins = | |
| 445 | <3 26 0x1 0x0>; /* PD26 periph A AD6 */ | |
| 446 | }; | |
| 447 | pinctrl_adc0_ad7: adc0_ad7 { | |
| 448 | atmel,pins = | |
| 449 | <3 27 0x1 0x0>; /* PD27 periph A AD7 */ | |
| 450 | }; | |
| 451 | pinctrl_adc0_ad8: adc0_ad8 { | |
| 452 | atmel,pins = | |
| 453 | <3 28 0x1 0x0>; /* PD28 periph A AD8 */ | |
| 454 | }; | |
| 455 | pinctrl_adc0_ad9: adc0_ad9 { | |
| 456 | atmel,pins = | |
| 457 | <3 29 0x1 0x0>; /* PD29 periph A AD9 */ | |
| 458 | }; | |
| 459 | pinctrl_adc0_ad10: adc0_ad10 { | |
| 460 | atmel,pins = | |
| 461 | <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */ | |
| 462 | }; | |
| 463 | pinctrl_adc0_ad11: adc0_ad11 { | |
| 464 | atmel,pins = | |
| 465 | <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */ | |
| 466 | }; | |
| 467 | }; | |
| 468 | ||
| 469 | can0 { | |
| 470 | pinctrl_can0_rx_tx: can0_rx_tx { | |
| 471 | atmel,pins = | |
| 472 | <3 14 0x3 0x0 /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ | |
| 473 | 3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ | |
| 474 | }; | |
| 475 | }; | |
| 476 | ||
| 477 | can1 { | |
| 478 | pinctrl_can1_rx_tx: can1_rx_tx { | |
| 479 | atmel,pins = | |
| 480 | <1 14 0x2 0x0 /* PB14 periph B RX, conflicts with GCRS */ | |
| 481 | 1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */ | |
| 482 | }; | |
| 483 | }; | |
| 484 | ||
| 485 | dbgu { | |
| 486 | pinctrl_dbgu: dbgu-0 { | |
| 487 | atmel,pins = | |
| 488 | <1 30 0x1 0x0 /* PB30 periph A */ | |
| 489 | 1 31 0x1 0x1>; /* PB31 periph A with pullup */ | |
| 490 | }; | |
| 491 | }; | |
| 492 | ||
| 493 | i2c0 { | |
| 494 | pinctrl_i2c0: i2c0-0 { | |
| 495 | atmel,pins = | |
| 496 | <0 30 0x1 0x0 /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ | |
| 497 | 0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ | |
| 498 | }; | |
| 499 | }; | |
| 500 | ||
| 501 | i2c1 { | |
| 502 | pinctrl_i2c1: i2c1-0 { | |
| 503 | atmel,pins = | |
| 504 | <2 26 0x2 0x0 /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ | |
| 505 | 2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ | |
| 506 | }; | |
| 507 | }; | |
| 508 | ||
| 509 | isi { | |
| 510 | pinctrl_isi: isi-0 { | |
| 511 | atmel,pins = | |
| 512 | <0 16 0x3 0x0 /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ | |
| 513 | 0 17 0x3 0x0 /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ | |
| 514 | 0 18 0x3 0x0 /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ | |
| 515 | 0 19 0x3 0x0 /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ | |
| 516 | 0 20 0x3 0x0 /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ | |
| 517 | 0 21 0x3 0x0 /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ | |
| 518 | 0 22 0x3 0x0 /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ | |
| 519 | 0 23 0x3 0x0 /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ | |
| 520 | 2 30 0x3 0x0 /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ | |
| 521 | 0 31 0x3 0x0 /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ | |
| 522 | 0 30 0x3 0x0 /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ | |
| 523 | 2 29 0x3 0x0 /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ | |
| 524 | 2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ | |
| 525 | }; | |
| 526 | pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { | |
| 527 | atmel,pins = | |
| 528 | <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */ | |
| 529 | }; | |
| 530 | }; | |
| 531 | ||
| 532 | lcd { | |
| 533 | pinctrl_lcd: lcd-0 { | |
| 534 | atmel,pins = | |
| 535 | <0 24 0x1 0x0 /* PA24 periph A LCDPWM */ | |
| 536 | 0 26 0x1 0x0 /* PA26 periph A LCDVSYNC */ | |
| 537 | 0 27 0x1 0x0 /* PA27 periph A LCDHSYNC */ | |
| 538 | 0 25 0x1 0x0 /* PA25 periph A LCDDISP */ | |
| 539 | 0 29 0x1 0x0 /* PA29 periph A LCDDEN */ | |
| 540 | 0 28 0x1 0x0 /* PA28 periph A LCDPCK */ | |
| 541 | 0 0 0x1 0x0 /* PA0 periph A LCDD0 pin */ | |
| 542 | 0 1 0x1 0x0 /* PA1 periph A LCDD1 pin */ | |
| 543 | 0 2 0x1 0x0 /* PA2 periph A LCDD2 pin */ | |
| 544 | 0 3 0x1 0x0 /* PA3 periph A LCDD3 pin */ | |
| 545 | 0 4 0x1 0x0 /* PA4 periph A LCDD4 pin */ | |
| 546 | 0 5 0x1 0x0 /* PA5 periph A LCDD5 pin */ | |
| 547 | 0 6 0x1 0x0 /* PA6 periph A LCDD6 pin */ | |
| 548 | 0 7 0x1 0x0 /* PA7 periph A LCDD7 pin */ | |
| 549 | 0 8 0x1 0x0 /* PA8 periph A LCDD8 pin */ | |
| 550 | 0 9 0x1 0x0 /* PA9 periph A LCDD9 pin */ | |
| 551 | 0 10 0x1 0x0 /* PA10 periph A LCDD10 pin */ | |
| 552 | 0 11 0x1 0x0 /* PA11 periph A LCDD11 pin */ | |
| 553 | 0 12 0x1 0x0 /* PA12 periph A LCDD12 pin */ | |
| 554 | 0 13 0x1 0x0 /* PA13 periph A LCDD13 pin */ | |
| 555 | 0 14 0x1 0x0 /* PA14 periph A LCDD14 pin */ | |
| 556 | 0 15 0x1 0x0 /* PA15 periph A LCDD15 pin */ | |
| 557 | 2 14 0x3 0x0 /* PC14 periph C LCDD16 pin */ | |
| 558 | 2 13 0x3 0x0 /* PC13 periph C LCDD17 pin */ | |
| 559 | 2 12 0x3 0x0 /* PC12 periph C LCDD18 pin */ | |
| 560 | 2 11 0x3 0x0 /* PC11 periph C LCDD19 pin */ | |
| 561 | 2 10 0x3 0x0 /* PC10 periph C LCDD20 pin */ | |
| 562 | 2 15 0x3 0x0 /* PC15 periph C LCDD21 pin */ | |
| 563 | 4 27 0x3 0x0 /* PE27 periph C LCDD22 pin */ | |
| 564 | 4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */ | |
| 565 | }; | |
| 566 | }; | |
| 567 | ||
| 568 | macb0 { | |
| 569 | pinctrl_macb0_data_rgmii: macb0_data_rgmii { | |
| 570 | atmel,pins = | |
| 571 | <1 0 0x1 0x0 /* PB0 periph A GTX0, conflicts with PWMH0 */ | |
| 572 | 1 1 0x1 0x0 /* PB1 periph A GTX1, conflicts with PWML0 */ | |
| 573 | 1 2 0x1 0x0 /* PB2 periph A GTX2, conflicts with TK1 */ | |
| 574 | 1 3 0x1 0x0 /* PB3 periph A GTX3, conflicts with TF1 */ | |
| 575 | 1 4 0x1 0x0 /* PB4 periph A GRX0, conflicts with PWMH1 */ | |
| 576 | 1 5 0x1 0x0 /* PB5 periph A GRX1, conflicts with PWML1 */ | |
| 577 | 1 6 0x1 0x0 /* PB6 periph A GRX2, conflicts with TD1 */ | |
| 578 | 1 7 0x1 0x0>; /* PB7 periph A GRX3, conflicts with RK1 */ | |
| 579 | }; | |
| 580 | pinctrl_macb0_data_gmii: macb0_data_gmii { | |
| 581 | atmel,pins = | |
| 582 | <1 19 0x2 0x0 /* PB19 periph B GTX4, conflicts with MCI1_CDA */ | |
| 583 | 1 20 0x2 0x0 /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ | |
| 584 | 1 21 0x2 0x0 /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ | |
| 585 | 1 22 0x2 0x0 /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ | |
| 586 | 1 23 0x2 0x0 /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ | |
| 587 | 1 24 0x2 0x0 /* PB24 periph B GRX5, conflicts with MCI1_CK */ | |
| 588 | 1 25 0x2 0x0 /* PB25 periph B GRX6, conflicts with SCK1 */ | |
| 589 | 1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */ | |
| 590 | }; | |
| 591 | pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { | |
| 592 | atmel,pins = | |
| 593 | <1 8 0x1 0x0 /* PB8 periph A GTXCK, conflicts with PWMH2 */ | |
| 594 | 1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ | |
| 595 | 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ | |
| 596 | 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ | |
| 597 | 1 16 0x1 0x0 /* PB16 periph A GMDC */ | |
| 598 | 1 17 0x1 0x0 /* PB17 periph A GMDIO */ | |
| 599 | 1 18 0x1 0x0>; /* PB18 periph A G125CK */ | |
| 600 | }; | |
| 601 | pinctrl_macb0_signal_gmii: macb0_signal_gmii { | |
| 602 | atmel,pins = | |
| 603 | <1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ | |
| 604 | 1 10 0x1 0x0 /* PB10 periph A GTXER, conflicts with RF1 */ | |
| 605 | 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ | |
| 606 | 1 12 0x1 0x0 /* PB12 periph A GRXDV, conflicts with PWMH3 */ | |
| 607 | 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ | |
| 608 | 1 14 0x1 0x0 /* PB14 periph A GCRS, conflicts with CANRX1 */ | |
| 609 | 1 15 0x1 0x0 /* PB15 periph A GCOL, conflicts with CANTX1 */ | |
| 610 | 1 16 0x1 0x0 /* PB16 periph A GMDC */ | |
| 611 | 1 17 0x1 0x0 /* PB17 periph A GMDIO */ | |
| 612 | 1 27 0x2 0x0>; /* PB27 periph B G125CKO */ | |
| 613 | }; | |
| 614 | ||
| 615 | }; | |
| 616 | ||
| 617 | macb1 { | |
| 618 | pinctrl_macb1_rmii: macb1_rmii-0 { | |
| 619 | atmel,pins = | |
| 620 | <2 0 0x1 0x0 /* PC0 periph A ETX0, conflicts with TIOA3 */ | |
| 621 | 2 1 0x1 0x0 /* PC1 periph A ETX1, conflicts with TIOB3 */ | |
| 622 | 2 2 0x1 0x0 /* PC2 periph A ERX0, conflicts with TCLK3 */ | |
| 623 | 2 3 0x1 0x0 /* PC3 periph A ERX1, conflicts with TIOA4 */ | |
| 624 | 2 4 0x1 0x0 /* PC4 periph A ETXEN, conflicts with TIOB4 */ | |
| 625 | 2 5 0x1 0x0 /* PC5 periph A ECRSDV,conflicts with TCLK4 */ | |
| 626 | 2 6 0x1 0x0 /* PC6 periph A ERXER, conflicts with TIOA5 */ | |
| 627 | 2 7 0x1 0x0 /* PC7 periph A EREFCK, conflicts with TIOB5 */ | |
| 628 | 2 8 0x1 0x0 /* PC8 periph A EMDC, conflicts with TCLK5 */ | |
| 629 | 2 9 0x1 0x0>; /* PC9 periph A EMDIO */ | |
| 630 | }; | |
| 631 | }; | |
| 632 | ||
| 633 | mmc0 { | |
| 634 | pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { | |
| 635 | atmel,pins = | |
| 636 | <3 9 0x1 0x0 /* PD9 periph A MCI0_CK */ | |
| 637 | 3 0 0x1 0x1 /* PD0 periph A MCI0_CDA with pullup */ | |
| 638 | 3 1 0x1 0x1>; /* PD1 periph A MCI0_DA0 with pullup */ | |
| 639 | }; | |
| 640 | pinctrl_mmc0_dat1_3: mmc0_dat1_3 { | |
| 641 | atmel,pins = | |
| 642 | <3 2 0x1 0x1 /* PD2 periph A MCI0_DA1 with pullup */ | |
| 643 | 3 3 0x1 0x1 /* PD3 periph A MCI0_DA2 with pullup */ | |
| 644 | 3 4 0x1 0x1>; /* PD4 periph A MCI0_DA3 with pullup */ | |
| 645 | }; | |
| 646 | pinctrl_mmc0_dat4_7: mmc0_dat4_7 { | |
| 647 | atmel,pins = | |
| 648 | <3 5 0x1 0x1 /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ | |
| 649 | 3 6 0x1 0x1 /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ | |
| 650 | 3 7 0x1 0x1 /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ | |
| 651 | 3 8 0x1 0x1>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ | |
| 652 | }; | |
| 653 | }; | |
| 654 | ||
| 655 | mmc1 { | |
| 656 | pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { | |
| 657 | atmel,pins = | |
| 658 | <1 24 0x1 0x0 /* PB24 periph A MCI1_CK, conflicts with GRX5 */ | |
| 659 | 1 19 0x1 0x1 /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ | |
| 660 | 1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ | |
| 661 | }; | |
| 662 | pinctrl_mmc1_dat1_3: mmc1_dat1_3 { | |
| 663 | atmel,pins = | |
| 664 | <1 21 0x1 0x1 /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ | |
| 665 | 1 22 0x1 0x1 /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ | |
| 666 | 1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ | |
| 667 | }; | |
| 668 | }; | |
| 669 | ||
| 670 | mmc2 { | |
| 671 | pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { | |
| 672 | atmel,pins = | |
| 673 | <2 15 0x1 0x0 /* PC15 periph A MCI2_CK, conflicts with PCK2 */ | |
| 674 | 2 10 0x1 0x1 /* PC10 periph A MCI2_CDA with pullup */ | |
| 675 | 2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */ | |
| 676 | }; | |
| 677 | pinctrl_mmc2_dat1_3: mmc2_dat1_3 { | |
| 678 | atmel,pins = | |
| 679 | <2 12 0x1 0x0 /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ | |
| 680 | 2 13 0x1 0x0 /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ | |
| 681 | 2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ | |
| 682 | }; | |
| 683 | }; | |
| 684 | ||
| 685 | nand0 { | |
| 686 | pinctrl_nand0_ale_cle: nand0_ale_cle-0 { | |
| 687 | atmel,pins = | |
| 688 | <4 21 0x1 0x1 /* PE21 periph A with pullup */ | |
| 689 | 4 22 0x1 0x1>; /* PE22 periph A with pullup */ | |
| 690 | }; | |
| 691 | }; | |
| 692 | ||
| 693 | pioA: gpio@fffff200 { | |
| 694 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 695 | reg = <0xfffff200 0x100>; | |
| 696 | interrupts = <6 4 1>; | |
| 697 | #gpio-cells = <2>; | |
| 698 | gpio-controller; | |
| 699 | interrupt-controller; | |
| 700 | #interrupt-cells = <2>; | |
| 701 | }; | |
| 702 | ||
| 703 | pioB: gpio@fffff400 { | |
| 704 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 705 | reg = <0xfffff400 0x100>; | |
| 706 | interrupts = <7 4 1>; | |
| 707 | #gpio-cells = <2>; | |
| 708 | gpio-controller; | |
| 709 | interrupt-controller; | |
| 710 | #interrupt-cells = <2>; | |
| 711 | }; | |
| 712 | ||
| 713 | pioC: gpio@fffff600 { | |
| 714 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 715 | reg = <0xfffff600 0x100>; | |
| 716 | interrupts = <8 4 1>; | |
| 717 | #gpio-cells = <2>; | |
| 718 | gpio-controller; | |
| 719 | interrupt-controller; | |
| 720 | #interrupt-cells = <2>; | |
| 721 | }; | |
| 722 | ||
| 723 | pioD: gpio@fffff800 { | |
| 724 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 725 | reg = <0xfffff800 0x100>; | |
| 726 | interrupts = <9 4 1>; | |
| 727 | #gpio-cells = <2>; | |
| 728 | gpio-controller; | |
| 729 | interrupt-controller; | |
| 730 | #interrupt-cells = <2>; | |
| 731 | }; | |
| 732 | ||
| 733 | pioE: gpio@fffffa00 { | |
| 734 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 735 | reg = <0xfffffa00 0x100>; | |
| 736 | interrupts = <10 4 1>; | |
| 737 | #gpio-cells = <2>; | |
| 738 | gpio-controller; | |
| 739 | interrupt-controller; | |
| 740 | #interrupt-cells = <2>; | |
| 741 | }; | |
| 742 | ||
| 743 | spi0 { | |
| 744 | pinctrl_spi0: spi0-0 { | |
| 745 | atmel,pins = | |
| 746 | <3 10 0x1 0x0 /* PD10 periph A SPI0_MISO pin */ | |
| 747 | 3 11 0x1 0x0 /* PD11 periph A SPI0_MOSI pin */ | |
| 748 | 3 12 0x1 0x0 /* PD12 periph A SPI0_SPCK pin */ | |
| 749 | 3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */ | |
| 750 | }; | |
| 751 | }; | |
| 752 | ||
| 753 | spi1 { | |
| 754 | pinctrl_spi1: spi1-0 { | |
| 755 | atmel,pins = | |
| 756 | <2 22 0x1 0x0 /* PC22 periph A SPI1_MISO pin */ | |
| 757 | 2 23 0x1 0x0 /* PC23 periph A SPI1_MOSI pin */ | |
| 758 | 2 24 0x1 0x0 /* PC24 periph A SPI1_SPCK pin */ | |
| 759 | 2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */ | |
| 760 | }; | |
| 761 | }; | |
| 762 | ||
| 763 | ssc0 { | |
| 764 | pinctrl_ssc0_tx: ssc0_tx { | |
| 765 | atmel,pins = | |
| 766 | <2 16 0x1 0x0 /* PC16 periph A TK0 */ | |
| 767 | 2 17 0x1 0x0 /* PC17 periph A TF0 */ | |
| 768 | 2 18 0x1 0x0>; /* PC18 periph A TD0 */ | |
| 769 | }; | |
| 770 | ||
| 771 | pinctrl_ssc0_rx: ssc0_rx { | |
| 772 | atmel,pins = | |
| 773 | <2 19 0x1 0x0 /* PC19 periph A RK0 */ | |
| 774 | 2 20 0x1 0x0 /* PC20 periph A RF0 */ | |
| 775 | 2 21 0x1 0x0>; /* PC21 periph A RD0 */ | |
| 776 | }; | |
| 777 | }; | |
| 778 | ||
| 779 | ssc1 { | |
| 780 | pinctrl_ssc1_tx: ssc1_tx { | |
| 781 | atmel,pins = | |
| 782 | <1 2 0x2 0x0 /* PB2 periph B TK1, conflicts with GTX2 */ | |
| 783 | 1 3 0x2 0x0 /* PB3 periph B TF1, conflicts with GTX3 */ | |
| 784 | 1 6 0x2 0x0>; /* PB6 periph B TD1, conflicts with TD1 */ | |
| 785 | }; | |
| 786 | ||
| 787 | pinctrl_ssc1_rx: ssc1_rx { | |
| 788 | atmel,pins = | |
| 789 | <1 7 0x2 0x0 /* PB7 periph B RK1, conflicts with EREFCK */ | |
| 790 | 1 10 0x2 0x0 /* PB10 periph B RF1, conflicts with GTXER */ | |
| 791 | 1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */ | |
| 792 | }; | |
| 793 | }; | |
| 794 | ||
| 795 | uart0 { | |
| 796 | pinctrl_uart0: uart0-0 { | |
| 797 | atmel,pins = | |
| 798 | <2 29 0x1 0x0 /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ | |
| 799 | 2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ | |
| 800 | }; | |
| 801 | }; | |
| 802 | ||
| 803 | uart1 { | |
| 804 | pinctrl_uart1: uart1-0 { | |
| 805 | atmel,pins = | |
| 806 | <0 30 0x2 0x0 /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ | |
| 807 | 0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ | |
| 808 | }; | |
| 809 | }; | |
| 810 | ||
| 811 | usart0 { | |
| 812 | pinctrl_usart0: usart0-0 { | |
| 813 | atmel,pins = | |
| 814 | <3 17 0x1 0x0 /* PD17 periph A */ | |
| 815 | 3 18 0x1 0x1>; /* PD18 periph A with pullup */ | |
| 816 | }; | |
| 817 | ||
| 818 | pinctrl_usart0_rts_cts: usart0_rts_cts-0 { | |
| 819 | atmel,pins = | |
| 820 | <3 15 0x1 0x0 /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ | |
| 821 | 3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ | |
| 822 | }; | |
| 823 | }; | |
| 824 | ||
| 825 | usart1 { | |
| 826 | pinctrl_usart1: usart1-0 { | |
| 827 | atmel,pins = | |
| 828 | <1 28 0x1 0x0 /* PB28 periph A */ | |
| 829 | 1 29 0x1 0x1>; /* PB29 periph A with pullup */ | |
| 830 | }; | |
| 831 | ||
| 832 | pinctrl_usart1_rts_cts: usart1_rts_cts-0 { | |
| 833 | atmel,pins = | |
| 834 | <1 26 0x1 0x0 /* PB26 periph A, conflicts with GRX7 */ | |
| 835 | 1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */ | |
| 836 | }; | |
| 837 | }; | |
| 838 | ||
| 839 | usart2 { | |
| 840 | pinctrl_usart2: usart2-0 { | |
| 841 | atmel,pins = | |
| 842 | <4 25 0x2 0x0 /* PE25 periph B, conflicts with A25 */ | |
| 843 | 4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */ | |
| 844 | }; | |
| 845 | ||
| 846 | pinctrl_usart2_rts_cts: usart2_rts_cts-0 { | |
| 847 | atmel,pins = | |
| 848 | <4 23 0x2 0x0 /* PE23 periph B, conflicts with A23 */ | |
| 849 | 4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */ | |
| 850 | }; | |
| 851 | }; | |
| 852 | ||
| 853 | usart3 { | |
| 854 | pinctrl_usart3: usart3-0 { | |
| 855 | atmel,pins = | |
| 856 | <4 18 0x2 0x0 /* PE18 periph B, conflicts with A18 */ | |
| 857 | 4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */ | |
| 858 | }; | |
| 859 | ||
| 860 | pinctrl_usart3_rts_cts: usart3_rts_cts-0 { | |
| 861 | atmel,pins = | |
| 862 | <4 16 0x2 0x0 /* PE16 periph B, conflicts with A16 */ | |
| 863 | 4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */ | |
| 864 | }; | |
| 865 | }; | |
| 866 | }; | |
| 867 | ||
| 868 | pmc: pmc@fffffc00 { | |
| 869 | compatible = "atmel,at91rm9200-pmc"; | |
| 870 | reg = <0xfffffc00 0x120>; | |
| 871 | }; | |
| 872 | ||
| 873 | rstc@fffffe00 { | |
| 874 | compatible = "atmel,at91sam9g45-rstc"; | |
| 875 | reg = <0xfffffe00 0x10>; | |
| 876 | }; | |
| 877 | ||
| 878 | pit: timer@fffffe30 { | |
| 879 | compatible = "atmel,at91sam9260-pit"; | |
| 880 | reg = <0xfffffe30 0xf>; | |
| 881 | interrupts = <3 4 5>; | |
| 882 | }; | |
| 883 | ||
| 884 | watchdog@fffffe40 { | |
| 885 | compatible = "atmel,at91sam9260-wdt"; | |
| 886 | reg = <0xfffffe40 0x10>; | |
| 887 | status = "disabled"; | |
| 888 | }; | |
| 889 | ||
| 890 | rtc@fffffeb0 { | |
| 891 | compatible = "atmel,at91rm9200-rtc"; | |
| 892 | reg = <0xfffffeb0 0x30>; | |
| 893 | interrupts = <1 4 7>; | |
| 894 | }; | |
| 895 | }; | |
| 896 | ||
| 897 | usb0: gadget@00500000 { | |
| 898 | #address-cells = <1>; | |
| 899 | #size-cells = <0>; | |
| 900 | compatible = "atmel,at91sam9rl-udc"; | |
| 901 | reg = <0x00500000 0x100000 | |
| 902 | 0xf8030000 0x4000>; | |
| 903 | interrupts = <33 4 2>; | |
| 904 | status = "disabled"; | |
| 905 | ||
| 906 | ep0 { | |
| 907 | reg = <0>; | |
| 908 | atmel,fifo-size = <64>; | |
| 909 | atmel,nb-banks = <1>; | |
| 910 | }; | |
| 911 | ||
| 912 | ep1 { | |
| 913 | reg = <1>; | |
| 914 | atmel,fifo-size = <1024>; | |
| 915 | atmel,nb-banks = <3>; | |
| 916 | atmel,can-dma; | |
| 917 | atmel,can-isoc; | |
| 918 | }; | |
| 919 | ||
| 920 | ep2 { | |
| 921 | reg = <2>; | |
| 922 | atmel,fifo-size = <1024>; | |
| 923 | atmel,nb-banks = <3>; | |
| 924 | atmel,can-dma; | |
| 925 | atmel,can-isoc; | |
| 926 | }; | |
| 927 | ||
| 928 | ep3 { | |
| 929 | reg = <3>; | |
| 930 | atmel,fifo-size = <1024>; | |
| 931 | atmel,nb-banks = <2>; | |
| 932 | atmel,can-dma; | |
| 933 | }; | |
| 934 | ||
| 935 | ep4 { | |
| 936 | reg = <4>; | |
| 937 | atmel,fifo-size = <1024>; | |
| 938 | atmel,nb-banks = <2>; | |
| 939 | atmel,can-dma; | |
| 940 | }; | |
| 941 | ||
| 942 | ep5 { | |
| 943 | reg = <5>; | |
| 944 | atmel,fifo-size = <1024>; | |
| 945 | atmel,nb-banks = <2>; | |
| 946 | atmel,can-dma; | |
| 947 | }; | |
| 948 | ||
| 949 | ep6 { | |
| 950 | reg = <6>; | |
| 951 | atmel,fifo-size = <1024>; | |
| 952 | atmel,nb-banks = <2>; | |
| 953 | atmel,can-dma; | |
| 954 | }; | |
| 955 | ||
| 956 | ep7 { | |
| 957 | reg = <7>; | |
| 958 | atmel,fifo-size = <1024>; | |
| 959 | atmel,nb-banks = <2>; | |
| 960 | atmel,can-dma; | |
| 961 | }; | |
| 962 | ||
| 963 | ep8 { | |
| 964 | reg = <8>; | |
| 965 | atmel,fifo-size = <1024>; | |
| 966 | atmel,nb-banks = <2>; | |
| 967 | }; | |
| 968 | ||
| 969 | ep9 { | |
| 970 | reg = <9>; | |
| 971 | atmel,fifo-size = <1024>; | |
| 972 | atmel,nb-banks = <2>; | |
| 973 | }; | |
| 974 | ||
| 975 | ep10 { | |
| 976 | reg = <10>; | |
| 977 | atmel,fifo-size = <1024>; | |
| 978 | atmel,nb-banks = <2>; | |
| 979 | }; | |
| 980 | ||
| 981 | ep11 { | |
| 982 | reg = <11>; | |
| 983 | atmel,fifo-size = <1024>; | |
| 984 | atmel,nb-banks = <2>; | |
| 985 | }; | |
| 986 | ||
| 987 | ep12 { | |
| 988 | reg = <12>; | |
| 989 | atmel,fifo-size = <1024>; | |
| 990 | atmel,nb-banks = <2>; | |
| 991 | }; | |
| 992 | ||
| 993 | ep13 { | |
| 994 | reg = <13>; | |
| 995 | atmel,fifo-size = <1024>; | |
| 996 | atmel,nb-banks = <2>; | |
| 997 | }; | |
| 998 | ||
| 999 | ep14 { | |
| 1000 | reg = <14>; | |
| 1001 | atmel,fifo-size = <1024>; | |
| 1002 | atmel,nb-banks = <2>; | |
| 1003 | }; | |
| 1004 | ||
| 1005 | ep15 { | |
| 1006 | reg = <15>; | |
| 1007 | atmel,fifo-size = <1024>; | |
| 1008 | atmel,nb-banks = <2>; | |
| 1009 | }; | |
| 1010 | }; | |
| 1011 | ||
| 1012 | usb1: ohci@00600000 { | |
| 1013 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
| 1014 | reg = <0x00600000 0x100000>; | |
| 1015 | interrupts = <32 4 2>; | |
| 1016 | status = "disabled"; | |
| 1017 | }; | |
| 1018 | ||
| 1019 | usb2: ehci@00700000 { | |
| 1020 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
| 1021 | reg = <0x00700000 0x100000>; | |
| 1022 | interrupts = <32 4 2>; | |
| 1023 | status = "disabled"; | |
| 1024 | }; | |
| 1025 | ||
| 1026 | nand0: nand@60000000 { | |
| 1027 | compatible = "atmel,at91rm9200-nand"; | |
| 1028 | #address-cells = <1>; | |
| 1029 | #size-cells = <1>; | |
| 1030 | reg = < 0x60000000 0x01000000 /* EBI CS3 */ | |
| 1031 | 0xffffc070 0x00000490 /* SMC PMECC regs */ | |
| 1032 | 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ | |
| 1033 | 0x00100000 0x00100000 /* ROM code */ | |
| 1034 | 0x70000000 0x10000000 /* NFC Command Registers */ | |
| 1035 | 0xffffc000 0x00000070 /* NFC HSMC regs */ | |
| 1036 | 0x00200000 0x00100000 /* NFC SRAM banks */ | |
| 1037 | >; | |
| 1038 | interrupts = <5 4 6>; | |
| 1039 | atmel,nand-addr-offset = <21>; | |
| 1040 | atmel,nand-cmd-offset = <22>; | |
| 1041 | pinctrl-names = "default"; | |
| 1042 | pinctrl-0 = <&pinctrl_nand0_ale_cle>; | |
| 1043 | atmel,pmecc-lookup-table-offset = <0x10000 0x18000>; | |
| 1044 | status = "disabled"; | |
| 1045 | }; | |
| 1046 | }; | |
| 1047 | }; |