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ARM: at91: Animeo IP: fix mtd partition table
[deliverable/linux.git] / arch / arm / boot / dts / sama5d3.dtsi
CommitLineData
655ff266
LD		 1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC
4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
6db64d29 11#include "skeleton.dtsi"
d4ae89c8 12#include <dt-bindings/dma/at91.h>
c9d0f317 13#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 14#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 15#include <dt-bindings/gpio/gpio.h>
d2e8190b 16#include <dt-bindings/clk/at91.h>
655ff266
LD		 17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 gpio4 = &pioE;
34 tcb0 = &tcb0;
655ff266
LD		 35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 ssc0 = &ssc0;
39 ssc1 = &ssc1;
40 };
41 cpus {
8b2efa89
AB		 42 #address-cells = <1>;
43 #size-cells = <0>;
655ff266 44 cpu@0 {
e757a6ee 45 device_type = "cpu";
655ff266 46 compatible = "arm,cortex-a5";
e757a6ee 47 reg = <0x0>;
655ff266
LD		 48 };
49 };
50
d9da9778
AB		 51 pmu {
52 compatible = "arm,cortex-a5-pmu";
53 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
54 };
55
655ff266
LD		 56 memory {
57 reg = <0x20000000 0x8000000>;
58 };
59
d2e8190b
BB		 60 clocks {
61 adc_op_clk: adc_op_clk{
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <20000000>;
65 };
66 };
67
655ff266
LD		 68 ahb {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges;
73
74 apb {
75 compatible = "simple-bus";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 ranges;
79
80 mmc0: mmc@f0000000 {
81 compatible = "atmel,hsmci";
82 reg = <0xf0000000 0x600>;
5e8b3bc3 83 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 84 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 85 dma-names = "rxtx";
655ff266
LD		 86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
88 status = "disabled";
89 #address-cells = <1>;
90 #size-cells = <0>;
d2e8190b
BB		 91 clocks = <&mci0_clk>;
92 clock-names = "mci_clk";
655ff266
LD		 93 };
94
95 spi0: spi@f0004000 {
96 #address-cells = <1>;
97 #size-cells = <0>;
b7ef678e 98 compatible = "atmel,at91rm9200-spi";
655ff266 99 reg = <0xf0004000 0x100>;
5e8b3bc3 100 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 101 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
102 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
103 dma-names = "tx", "rx";
655ff266
LD		 104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_spi0>;
d2e8190b
BB		 106 clocks = <&spi0_clk>;
107 clock-names = "spi_clk";
655ff266
LD		 108 status = "disabled";
109 };
110
111 ssc0: ssc@f0008000 {
112 compatible = "atmel,at91sam9g45-ssc";
113 reg = <0xf0008000 0x4000>;
5e8b3bc3 114 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
655ff266
LD		 115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
d2e8190b
BB		 117 clocks = <&ssc0_clk>;
118 clock-names = "pclk";
655ff266
LD		 119 status = "disabled";
120 };
121
655ff266
LD		 122 tcb0: timer@f0010000 {
123 compatible = "atmel,at91sam9x5-tcb";
124 reg = <0xf0010000 0x100>;
5e8b3bc3 125 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
d2e8190b
BB		 126 clocks = <&tcb0_clk>;
127 clock-names = "t0_clk";
655ff266
LD		 128 };
129
130 i2c0: i2c@f0014000 {
131 compatible = "atmel,at91sam9x5-i2c";
132 reg = <0xf0014000 0x4000>;
5e8b3bc3 133 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 134 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
135 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
d9a63a45 136 dma-names = "tx", "rx";
655ff266
LD		 137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_i2c0>;
139 #address-cells = <1>;
140 #size-cells = <0>;
d2e8190b 141 clocks = <&twi0_clk>;
655ff266
LD		 142 status = "disabled";
143 };
144
145 i2c1: i2c@f0018000 {
146 compatible = "atmel,at91sam9x5-i2c";
147 reg = <0xf0018000 0x4000>;
5e8b3bc3 148 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 149 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
150 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
d9a63a45 151 dma-names = "tx", "rx";
655ff266
LD		 152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_i2c1>;
154 #address-cells = <1>;
155 #size-cells = <0>;
d2e8190b 156 clocks = <&twi1_clk>;
655ff266
LD		 157 status = "disabled";
158 };
159
160 usart0: serial@f001c000 {
161 compatible = "atmel,at91sam9260-usart";
162 reg = <0xf001c000 0x100>;
5e8b3bc3 163 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_usart0>;
d2e8190b
BB		 166 clocks = <&usart0_clk>;
167 clock-names = "usart";
655ff266
LD		 168 status = "disabled";
169 };
170
171 usart1: serial@f0020000 {
172 compatible = "atmel,at91sam9260-usart";
173 reg = <0xf0020000 0x100>;
5e8b3bc3 174 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_usart1>;
d2e8190b
BB		 177 clocks = <&usart1_clk>;
178 clock-names = "usart";
655ff266
LD		 179 status = "disabled";
180 };
181
655ff266
LD		 182 isi: isi@f0034000 {
183 compatible = "atmel,at91sam9g45-isi";
184 reg = <0xf0034000 0x4000>;
5e8b3bc3 185 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 186 status = "disabled";
187 };
188
189 mmc1: mmc@f8000000 {
190 compatible = "atmel,hsmci";
191 reg = <0xf8000000 0x600>;
5e8b3bc3 192 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 193 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 194 dma-names = "rxtx";
655ff266
LD		 195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
197 status = "disabled";
198 #address-cells = <1>;
199 #size-cells = <0>;
d2e8190b
BB		 200 clocks = <&mci1_clk>;
201 clock-names = "mci_clk";
655ff266
LD		 202 };
203
655ff266
LD		 204 spi1: spi@f8008000 {
205 #address-cells = <1>;
206 #size-cells = <0>;
b7ef678e 207 compatible = "atmel,at91rm9200-spi";
655ff266 208 reg = <0xf8008000 0x100>;
5e8b3bc3 209 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 210 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
211 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
212 dma-names = "tx", "rx";
655ff266
LD		 213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_spi1>;
d2e8190b
BB		 215 clocks = <&spi1_clk>;
216 clock-names = "spi_clk";
655ff266
LD		 217 status = "disabled";
218 };
219
220 ssc1: ssc@f800c000 {
221 compatible = "atmel,at91sam9g45-ssc";
222 reg = <0xf800c000 0x4000>;
5e8b3bc3 223 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
655ff266
LD		 224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
d2e8190b
BB		 226 clocks = <&ssc1_clk>;
227 clock-names = "pclk";
655ff266
LD		 228 status = "disabled";
229 };
230
655ff266
LD		 231 adc0: adc@f8018000 {
232 compatible = "atmel,at91sam9260-adc";
233 reg = <0xf8018000 0x100>;
5e8b3bc3 234 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 235 pinctrl-names = "default";
236 pinctrl-0 = <
237 &pinctrl_adc0_adtrg
238 &pinctrl_adc0_ad0
239 &pinctrl_adc0_ad1
240 &pinctrl_adc0_ad2
241 &pinctrl_adc0_ad3
242 &pinctrl_adc0_ad4
243 &pinctrl_adc0_ad5
244 &pinctrl_adc0_ad6
245 &pinctrl_adc0_ad7
246 &pinctrl_adc0_ad8
247 &pinctrl_adc0_ad9
248 &pinctrl_adc0_ad10
249 &pinctrl_adc0_ad11
250 >;
d2e8190b
BB		 251 clocks = <&adc_clk>,
252 <&adc_op_clk>;
253 clock-names = "adc_clk", "adc_op_clk";
655ff266
LD		 254 atmel,adc-channel-base = <0x50>;
255 atmel,adc-channels-used = <0xfff>;
256 atmel,adc-drdy-mask = <0x1000000>;
257 atmel,adc-num-channels = <12>;
258 atmel,adc-startup-time = <40>;
259 atmel,adc-status-register = <0x30>;
260 atmel,adc-trigger-register = <0xc0>;
261 atmel,adc-use-external;
262 atmel,adc-vref = <3000>;
263 atmel,adc-res = <10 12>;
264 atmel,adc-res-names = "lowres", "highres";
265 status = "disabled";
266
267 trigger@0 {
268 trigger-name = "external-rising";
269 trigger-value = <0x1>;
270 trigger-external;
271 };
272 trigger@1 {
273 trigger-name = "external-falling";
274 trigger-value = <0x2>;
275 trigger-external;
276 };
277 trigger@2 {
278 trigger-name = "external-any";
279 trigger-value = <0x3>;
280 trigger-external;
281 };
282 trigger@3 {
283 trigger-name = "continuous";
284 trigger-value = <0x6>;
285 };
286 };
287
288 tsadcc: tsadcc@f8018000 {
289 compatible = "atmel,at91sam9x5-tsadcc";
290 reg = <0xf8018000 0x4000>;
5e8b3bc3 291 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 292 atmel,tsadcc_clock = <300000>;
293 atmel,filtering_average = <0x03>;
294 atmel,pendet_debounce = <0x08>;
295 atmel,pendet_sensitivity = <0x02>;
296 atmel,ts_sample_hold_time = <0x0a>;
297 status = "disabled";
298 };
299
300 i2c2: i2c@f801c000 {
301 compatible = "atmel,at91sam9x5-i2c";
302 reg = <0xf801c000 0x4000>;
5e8b3bc3 303 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 304 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
305 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
d9a63a45 306 dma-names = "tx", "rx";
655ff266
LD		 307 #address-cells = <1>;
308 #size-cells = <0>;
d2e8190b 309 clocks = <&twi2_clk>;
655ff266
LD		 310 status = "disabled";
311 };
312
313 usart2: serial@f8020000 {
314 compatible = "atmel,at91sam9260-usart";
315 reg = <0xf8020000 0x100>;
5e8b3bc3 316 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_usart2>;
d2e8190b
BB		 319 clocks = <&usart2_clk>;
320 clock-names = "usart";
655ff266
LD		 321 status = "disabled";
322 };
323
324 usart3: serial@f8024000 {
325 compatible = "atmel,at91sam9260-usart";
326 reg = <0xf8024000 0x100>;
5e8b3bc3 327 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_usart3>;
d2e8190b
BB		 330 clocks = <&usart3_clk>;
331 clock-names = "usart";
655ff266
LD		 332 status = "disabled";
333 };
334
655ff266 335 sha@f8034000 {
c76f266d 336 compatible = "atmel,at91sam9g46-sha";
655ff266 337 reg = <0xf8034000 0x100>;
5e8b3bc3 338 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 339 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
340 dma-names = "tx";
655ff266
LD		 341 };
342
343 aes@f8038000 {
c76f266d 344 compatible = "atmel,at91sam9g46-aes";
655ff266 345 reg = <0xf8038000 0x100>;
07f7d503 346 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 347 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
348 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
349 dma-names = "tx", "rx";
655ff266
LD		 350 };
351
352 tdes@f803c000 {
c76f266d 353 compatible = "atmel,at91sam9g46-tdes";
655ff266 354 reg = <0xf803c000 0x100>;
5e8b3bc3 355 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 356 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
357 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
358 dma-names = "tx", "rx";
655ff266
LD		 359 };
360
361 dma0: dma-controller@ffffe600 {
362 compatible = "atmel,at91sam9g45-dma";
363 reg = <0xffffe600 0x200>;
5e8b3bc3 364 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 365 #dma-cells = <2>;
d2e8190b
BB		 366 clocks = <&dma0_clk>;
367 clock-names = "dma_clk";
655ff266
LD		 368 };
369
370 dma1: dma-controller@ffffe800 {
371 compatible = "atmel,at91sam9g45-dma";
372 reg = <0xffffe800 0x200>;
5e8b3bc3 373 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 374 #dma-cells = <2>;
d2e8190b
BB		 375 clocks = <&dma1_clk>;
376 clock-names = "dma_clk";
655ff266
LD		 377 };
378
379 ramc0: ramc@ffffea00 {
380 compatible = "atmel,at91sam9g45-ddramc";
381 reg = <0xffffea00 0x200>;
382 };
383
384 dbgu: serial@ffffee00 {
385 compatible = "atmel,at91sam9260-usart";
386 reg = <0xffffee00 0x200>;
5e8b3bc3 387 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 388 pinctrl-names = "default";
389 pinctrl-0 = <&pinctrl_dbgu>;
d2e8190b
BB		 390 clocks = <&dbgu_clk>;
391 clock-names = "usart";
655ff266
LD		 392 status = "disabled";
393 };
394
395 aic: interrupt-controller@fffff000 {
396 #interrupt-cells = <3>;
397 compatible = "atmel,sama5d3-aic";
398 interrupt-controller;
399 reg = <0xfffff000 0x200>;
400 atmel,external-irqs = <47>;
401 };
402
403 pinctrl@fffff200 {
404 #address-cells = <1>;
405 #size-cells = <1>;
406 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
407 ranges = <0xfffff200 0xfffff200 0xa00>;
408 atmel,mux-mask = <
409 /* A B C */
410 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
411 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
412 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
413 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
414 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
415 >;
416
417 /* shared pinctrl settings */
418 adc0 {
419 pinctrl_adc0_adtrg: adc0_adtrg {
420 atmel,pins =
c9d0f317 421 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
655ff266
LD		 422 };
423 pinctrl_adc0_ad0: adc0_ad0 {
424 atmel,pins =
c9d0f317 425 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
655ff266
LD		 426 };
427 pinctrl_adc0_ad1: adc0_ad1 {
428 atmel,pins =
c9d0f317 429 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
655ff266
LD		 430 };
431 pinctrl_adc0_ad2: adc0_ad2 {
432 atmel,pins =
c9d0f317 433 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
655ff266
LD		 434 };
435 pinctrl_adc0_ad3: adc0_ad3 {
436 atmel,pins =
c9d0f317 437 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
655ff266
LD		 438 };
439 pinctrl_adc0_ad4: adc0_ad4 {
440 atmel,pins =
c9d0f317 441 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
655ff266
LD		 442 };
443 pinctrl_adc0_ad5: adc0_ad5 {
444 atmel,pins =
c9d0f317 445 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
655ff266
LD		 446 };
447 pinctrl_adc0_ad6: adc0_ad6 {
448 atmel,pins =
c9d0f317 449 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
655ff266
LD		 450 };
451 pinctrl_adc0_ad7: adc0_ad7 {
452 atmel,pins =
c9d0f317 453 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
655ff266
LD		 454 };
455 pinctrl_adc0_ad8: adc0_ad8 {
456 atmel,pins =
c9d0f317 457 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
655ff266
LD		 458 };
459 pinctrl_adc0_ad9: adc0_ad9 {
460 atmel,pins =
c9d0f317 461 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
655ff266
LD		 462 };
463 pinctrl_adc0_ad10: adc0_ad10 {
464 atmel,pins =
c9d0f317 465 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
655ff266
LD		 466 };
467 pinctrl_adc0_ad11: adc0_ad11 {
468 atmel,pins =
c9d0f317 469 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
655ff266
LD		 470 };
471 };
472
655ff266
LD		 473 dbgu {
474 pinctrl_dbgu: dbgu-0 {
475 atmel,pins =
c9d0f317
JCPV		 476 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
477 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
655ff266
LD		 478 };
479 };
480
481 i2c0 {
482 pinctrl_i2c0: i2c0-0 {
483 atmel,pins =
c9d0f317
JCPV		 484 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
485 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
655ff266
LD		 486 };
487 };
488
489 i2c1 {
490 pinctrl_i2c1: i2c1-0 {
491 atmel,pins =
c9d0f317
JCPV		 492 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
493 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
655ff266
LD		 494 };
495 };
496
497 isi {
498 pinctrl_isi: isi-0 {
499 atmel,pins =
c9d0f317
JCPV		 500 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
501 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
502 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
503 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
504 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
505 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
506 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
507 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
508 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
509 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
510 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
511 AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
512 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
655ff266
LD		 513 };
514 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
515 atmel,pins =
c9d0f317 516 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
655ff266
LD		 517 };
518 };
519
655ff266
LD		 520 mmc0 {
521 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
522 atmel,pins =
c9d0f317
JCPV		 523 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
524 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
525 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
655ff266
LD		 526 };
527 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
528 atmel,pins =
c9d0f317
JCPV		 529 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
530 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
531 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
655ff266
LD		 532 };
533 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
534 atmel,pins =
c9d0f317
JCPV		 535 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
536 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
537 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
538 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
655ff266
LD		 539 };
540 };
541
542 mmc1 {
543 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
544 atmel,pins =
c9d0f317
JCPV		 545 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
546 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
547 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
655ff266
LD		 548 };
549 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
550 atmel,pins =
c9d0f317
JCPV		 551 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
552 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
553 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
655ff266
LD		 554 };
555 };
556
655ff266
LD		 557 nand0 {
558 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
559 atmel,pins =
c9d0f317
JCPV		 560 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
561 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
655ff266
LD		 562 };
563 };
564
655ff266
LD		 565 spi0 {
566 pinctrl_spi0: spi0-0 {
567 atmel,pins =
c9d0f317
JCPV		 568 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
569 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
570 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
655ff266
LD		 571 };
572 };
573
574 spi1 {
575 pinctrl_spi1: spi1-0 {
576 atmel,pins =
c9d0f317
JCPV		 577 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
578 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
579 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
655ff266
LD		 580 };
581 };
582
583 ssc0 {
584 pinctrl_ssc0_tx: ssc0_tx {
585 atmel,pins =
c9d0f317
JCPV		 586 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
587 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
588 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
655ff266
LD		 589 };
590
591 pinctrl_ssc0_rx: ssc0_rx {
592 atmel,pins =
c9d0f317
JCPV		 593 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
594 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
595 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
655ff266
LD		 596 };
597 };
598
599 ssc1 {
600 pinctrl_ssc1_tx: ssc1_tx {
601 atmel,pins =
c9d0f317
JCPV		 602 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
603 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
604 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
655ff266
LD		 605 };
606
607 pinctrl_ssc1_rx: ssc1_rx {
608 atmel,pins =
c9d0f317
JCPV		 609 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
610 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
611 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
655ff266
LD		 612 };
613 };
614
655ff266
LD		 615 usart0 {
616 pinctrl_usart0: usart0-0 {
617 atmel,pins =
c9d0f317
JCPV		 618 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
619 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
655ff266
LD		 620 };
621
622 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
623 atmel,pins =
c9d0f317
JCPV		 624 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
625 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
655ff266
LD		 626 };
627 };
628
629 usart1 {
630 pinctrl_usart1: usart1-0 {
631 atmel,pins =
c9d0f317
JCPV		 632 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
633 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
655ff266
LD		 634 };
635
636 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
637 atmel,pins =
c9d0f317
JCPV		 638 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
639 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
655ff266
LD		 640 };
641 };
642
643 usart2 {
644 pinctrl_usart2: usart2-0 {
645 atmel,pins =
c9d0f317
JCPV		 646 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
647 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
655ff266
LD		 648 };
649
650 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
651 atmel,pins =
c9d0f317
JCPV		 652 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
653 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
655ff266
LD		 654 };
655 };
656
657 usart3 {
658 pinctrl_usart3: usart3-0 {
659 atmel,pins =
c9d0f317
JCPV		 660 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
661 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
655ff266
LD		 662 };
663
664 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
665 atmel,pins =
c9d0f317
JCPV		 666 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
667 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
655ff266
LD		 668 };
669 };
c9d0f317
JCPV		 670
671
672 pioA: gpio@fffff200 {
673 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
674 reg = <0xfffff200 0x100>;
5e8b3bc3 675 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 676 #gpio-cells = <2>;
677 gpio-controller;
678 interrupt-controller;
679 #interrupt-cells = <2>;
d2e8190b 680 clocks = <&pioA_clk>;
c9d0f317
JCPV		 681 };
682
683 pioB: gpio@fffff400 {
684 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
685 reg = <0xfffff400 0x100>;
5e8b3bc3 686 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 687 #gpio-cells = <2>;
688 gpio-controller;
689 interrupt-controller;
690 #interrupt-cells = <2>;
d2e8190b 691 clocks = <&pioB_clk>;
c9d0f317
JCPV		 692 };
693
694 pioC: gpio@fffff600 {
695 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
696 reg = <0xfffff600 0x100>;
5e8b3bc3 697 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 698 #gpio-cells = <2>;
699 gpio-controller;
700 interrupt-controller;
701 #interrupt-cells = <2>;
d2e8190b 702 clocks = <&pioC_clk>;
c9d0f317
JCPV		 703 };
704
705 pioD: gpio@fffff800 {
706 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
707 reg = <0xfffff800 0x100>;
5e8b3bc3 708 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 709 #gpio-cells = <2>;
710 gpio-controller;
711 interrupt-controller;
712 #interrupt-cells = <2>;
d2e8190b 713 clocks = <&pioD_clk>;
c9d0f317
JCPV		 714 };
715
716 pioE: gpio@fffffa00 {
717 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
718 reg = <0xfffffa00 0x100>;
5e8b3bc3 719 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 720 #gpio-cells = <2>;
721 gpio-controller;
722 interrupt-controller;
723 #interrupt-cells = <2>;
d2e8190b 724 clocks = <&pioE_clk>;
c9d0f317 725 };
655ff266
LD		 726 };
727
728 pmc: pmc@fffffc00 {
d2e8190b 729 compatible = "atmel,sama5d3-pmc";
655ff266 730 reg = <0xfffffc00 0x120>;
d2e8190b
BB		 731 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
732 interrupt-controller;
733 #address-cells = <1>;
734 #size-cells = <0>;
735 #interrupt-cells = <1>;
736
737 clk32k: slck {
738 compatible = "fixed-clock";
739 #clock-cells = <0>;
740 clock-frequency = <32768>;
741 };
742
743 main: mainck {
744 compatible = "atmel,at91rm9200-clk-main";
745 #clock-cells = <0>;
746 interrupt-parent = <&pmc>;
747 interrupts = <AT91_PMC_MOSCS>;
748 clocks = <&clk32k>;
749 };
750
751 plla: pllack {
752 compatible = "atmel,sama5d3-clk-pll";
753 #clock-cells = <0>;
754 interrupt-parent = <&pmc>;
755 interrupts = <AT91_PMC_LOCKA>;
756 clocks = <&main>;
757 reg = <0>;
758 atmel,clk-input-range = <8000000 50000000>;
759 #atmel,pll-clk-output-range-cells = <4>;
760 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
761 };
762
763 plladiv: plladivck {
764 compatible = "atmel,at91sam9x5-clk-plldiv";
765 #clock-cells = <0>;
766 clocks = <&plla>;
767 };
768
769 utmi: utmick {
770 compatible = "atmel,at91sam9x5-clk-utmi";
771 #clock-cells = <0>;
772 interrupt-parent = <&pmc>;
773 interrupts = <AT91_PMC_LOCKU>;
774 clocks = <&main>;
775 };
776
777 mck: masterck {
778 compatible = "atmel,at91sam9x5-clk-master";
779 #clock-cells = <0>;
780 interrupt-parent = <&pmc>;
781 interrupts = <AT91_PMC_MCKRDY>;
782 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
783 atmel,clk-output-range = <0 166000000>;
784 atmel,clk-divisors = <1 2 4 3>;
785 };
786
787 usb: usbck {
788 compatible = "atmel,at91sam9x5-clk-usb";
789 #clock-cells = <0>;
790 clocks = <&plladiv>, <&utmi>;
791 };
792
793 prog: progck {
794 compatible = "atmel,at91sam9x5-clk-programmable";
795 #address-cells = <1>;
796 #size-cells = <0>;
797 interrupt-parent = <&pmc>;
798 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
799
800 prog0: prog0 {
801 #clock-cells = <0>;
802 reg = <0>;
803 interrupts = <AT91_PMC_PCKRDY(0)>;
804 };
805
806 prog1: prog1 {
807 #clock-cells = <0>;
808 reg = <1>;
809 interrupts = <AT91_PMC_PCKRDY(1)>;
810 };
811
812 prog2: prog2 {
813 #clock-cells = <0>;
814 reg = <2>;
815 interrupts = <AT91_PMC_PCKRDY(2)>;
816 };
817 };
818
819 smd: smdclk {
820 compatible = "atmel,at91sam9x5-clk-smd";
821 #clock-cells = <0>;
822 clocks = <&plladiv>, <&utmi>;
823 };
824
825 systemck {
826 compatible = "atmel,at91rm9200-clk-system";
827 #address-cells = <1>;
828 #size-cells = <0>;
829
830 ddrck: ddrck {
831 #clock-cells = <0>;
832 reg = <2>;
833 clocks = <&mck>;
834 };
835
836 smdck: smdck {
837 #clock-cells = <0>;
838 reg = <4>;
839 clocks = <&smd>;
840 };
841
842 uhpck: uhpck {
843 #clock-cells = <0>;
844 reg = <6>;
845 clocks = <&usb>;
846 };
847
848 udpck: udpck {
849 #clock-cells = <0>;
850 reg = <7>;
851 clocks = <&usb>;
852 };
853
854 pck0: pck0 {
855 #clock-cells = <0>;
856 reg = <8>;
857 clocks = <&prog0>;
858 };
859
860 pck1: pck1 {
861 #clock-cells = <0>;
862 reg = <9>;
863 clocks = <&prog1>;
864 };
865
866 pck2: pck2 {
867 #clock-cells = <0>;
868 reg = <10>;
869 clocks = <&prog2>;
870 };
871 };
872
873 periphck {
874 compatible = "atmel,at91sam9x5-clk-peripheral";
875 #address-cells = <1>;
876 #size-cells = <0>;
877 clocks = <&mck>;
878
879 dbgu_clk: dbgu_clk {
880 #clock-cells = <0>;
881 reg = <2>;
882 };
883
884 pioA_clk: pioA_clk {
885 #clock-cells = <0>;
886 reg = <6>;
887 };
888
889 pioB_clk: pioB_clk {
890 #clock-cells = <0>;
891 reg = <7>;
892 };
893
894 pioC_clk: pioC_clk {
895 #clock-cells = <0>;
896 reg = <8>;
897 };
898
899 pioD_clk: pioD_clk {
900 #clock-cells = <0>;
901 reg = <9>;
902 };
903
904 pioE_clk: pioE_clk {
905 #clock-cells = <0>;
906 reg = <10>;
907 };
908
909 usart0_clk: usart0_clk {
910 #clock-cells = <0>;
911 reg = <12>;
912 atmel,clk-output-range = <0 66000000>;
913 };
914
915 usart1_clk: usart1_clk {
916 #clock-cells = <0>;
917 reg = <13>;
918 atmel,clk-output-range = <0 66000000>;
919 };
920
921 usart2_clk: usart2_clk {
922 #clock-cells = <0>;
923 reg = <14>;
924 atmel,clk-output-range = <0 66000000>;
925 };
926
927 usart3_clk: usart3_clk {
928 #clock-cells = <0>;
929 reg = <15>;
930 atmel,clk-output-range = <0 66000000>;
931 };
932
933 twi0_clk: twi0_clk {
934 reg = <18>;
935 #clock-cells = <0>;
936 atmel,clk-output-range = <0 16625000>;
937 };
938
939 twi1_clk: twi1_clk {
940 #clock-cells = <0>;
941 reg = <19>;
942 atmel,clk-output-range = <0 16625000>;
943 };
944
945 twi2_clk: twi2_clk {
946 #clock-cells = <0>;
947 reg = <20>;
948 atmel,clk-output-range = <0 16625000>;
949 };
950
951 mci0_clk: mci0_clk {
952 #clock-cells = <0>;
953 reg = <21>;
954 };
955
956 mci1_clk: mci1_clk {
957 #clock-cells = <0>;
958 reg = <22>;
959 };
960
961 spi0_clk: spi0_clk {
962 #clock-cells = <0>;
963 reg = <24>;
964 atmel,clk-output-range = <0 133000000>;
965 };
966
967 spi1_clk: spi1_clk {
968 #clock-cells = <0>;
969 reg = <25>;
970 atmel,clk-output-range = <0 133000000>;
971 };
972
973 tcb0_clk: tcb0_clk {
974 #clock-cells = <0>;
975 reg = <26>;
976 atmel,clk-output-range = <0 133000000>;
977 };
978
979 pwm_clk: pwm_clk {
980 #clock-cells = <0>;
981 reg = <28>;
982 };
983
984 adc_clk: adc_clk {
985 #clock-cells = <0>;
986 reg = <29>;
987 atmel,clk-output-range = <0 66000000>;
988 };
989
990 dma0_clk: dma0_clk {
991 #clock-cells = <0>;
992 reg = <30>;
993 };
994
995 dma1_clk: dma1_clk {
996 #clock-cells = <0>;
997 reg = <31>;
998 };
999
1000 uhphs_clk: uhphs_clk {
1001 #clock-cells = <0>;
1002 reg = <32>;
1003 };
1004
1005 udphs_clk: udphs_clk {
1006 #clock-cells = <0>;
1007 reg = <33>;
1008 };
1009
1010 isi_clk: isi_clk {
1011 #clock-cells = <0>;
1012 reg = <37>;
1013 };
1014
1015 ssc0_clk: ssc0_clk {
1016 #clock-cells = <0>;
1017 reg = <38>;
1018 atmel,clk-output-range = <0 66000000>;
1019 };
1020
1021 ssc1_clk: ssc1_clk {
1022 #clock-cells = <0>;
1023 reg = <39>;
1024 atmel,clk-output-range = <0 66000000>;
1025 };
1026
1027 sha_clk: sha_clk {
1028 #clock-cells = <0>;
1029 reg = <42>;
1030 };
1031
1032 aes_clk: aes_clk {
1033 #clock-cells = <0>;
1034 reg = <43>;
1035 };
1036
1037 tdes_clk: tdes_clk {
1038 #clock-cells = <0>;
1039 reg = <44>;
1040 };
1041
1042 trng_clk: trng_clk {
1043 #clock-cells = <0>;
1044 reg = <45>;
1045 };
1046
1047 fuse_clk: fuse_clk {
1048 #clock-cells = <0>;
1049 reg = <48>;
1050 };
1051 };
655ff266
LD		 1052 };
1053
1054 rstc@fffffe00 {
1055 compatible = "atmel,at91sam9g45-rstc";
1056 reg = <0xfffffe00 0x10>;
1057 };
1058
1059 pit: timer@fffffe30 {
1060 compatible = "atmel,at91sam9260-pit";
1061 reg = <0xfffffe30 0xf>;
5e8b3bc3 1062 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
d2e8190b 1063 clocks = <&mck>;
655ff266
LD		 1064 };
1065
1066 watchdog@fffffe40 {
1067 compatible = "atmel,at91sam9260-wdt";
1068 reg = <0xfffffe40 0x10>;
1069 status = "disabled";
1070 };
1071
1072 rtc@fffffeb0 {
1073 compatible = "atmel,at91rm9200-rtc";
1074 reg = <0xfffffeb0 0x30>;
5e8b3bc3 1075 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 1076 };
1077 };
1078
1079 usb0: gadget@00500000 {
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1082 compatible = "atmel,at91sam9rl-udc";
1083 reg = <0x00500000 0x100000
1084 0xf8030000 0x4000>;
5e8b3bc3 1085 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1086 clocks = <&udphs_clk>, <&utmi>;
1087 clock-names = "pclk", "hclk";
655ff266
LD		 1088 status = "disabled";
1089
1090 ep0 {
1091 reg = <0>;
1092 atmel,fifo-size = <64>;
1093 atmel,nb-banks = <1>;
1094 };
1095
1096 ep1 {
1097 reg = <1>;
1098 atmel,fifo-size = <1024>;
1099 atmel,nb-banks = <3>;
1100 atmel,can-dma;
1101 atmel,can-isoc;
1102 };
1103
1104 ep2 {
1105 reg = <2>;
1106 atmel,fifo-size = <1024>;
1107 atmel,nb-banks = <3>;
1108 atmel,can-dma;
1109 atmel,can-isoc;
1110 };
1111
1112 ep3 {
1113 reg = <3>;
1114 atmel,fifo-size = <1024>;
1115 atmel,nb-banks = <2>;
1116 atmel,can-dma;
1117 };
1118
1119 ep4 {
1120 reg = <4>;
1121 atmel,fifo-size = <1024>;
1122 atmel,nb-banks = <2>;
1123 atmel,can-dma;
1124 };
1125
1126 ep5 {
1127 reg = <5>;
1128 atmel,fifo-size = <1024>;
1129 atmel,nb-banks = <2>;
1130 atmel,can-dma;
1131 };
1132
1133 ep6 {
1134 reg = <6>;
1135 atmel,fifo-size = <1024>;
1136 atmel,nb-banks = <2>;
1137 atmel,can-dma;
1138 };
1139
1140 ep7 {
1141 reg = <7>;
1142 atmel,fifo-size = <1024>;
1143 atmel,nb-banks = <2>;
1144 atmel,can-dma;
1145 };
1146
1147 ep8 {
1148 reg = <8>;
1149 atmel,fifo-size = <1024>;
1150 atmel,nb-banks = <2>;
1151 };
1152
1153 ep9 {
1154 reg = <9>;
1155 atmel,fifo-size = <1024>;
1156 atmel,nb-banks = <2>;
1157 };
1158
1159 ep10 {
1160 reg = <10>;
1161 atmel,fifo-size = <1024>;
1162 atmel,nb-banks = <2>;
1163 };
1164
1165 ep11 {
1166 reg = <11>;
1167 atmel,fifo-size = <1024>;
1168 atmel,nb-banks = <2>;
1169 };
1170
1171 ep12 {
1172 reg = <12>;
1173 atmel,fifo-size = <1024>;
1174 atmel,nb-banks = <2>;
1175 };
1176
1177 ep13 {
1178 reg = <13>;
1179 atmel,fifo-size = <1024>;
1180 atmel,nb-banks = <2>;
1181 };
1182
1183 ep14 {
1184 reg = <14>;
1185 atmel,fifo-size = <1024>;
1186 atmel,nb-banks = <2>;
1187 };
1188
1189 ep15 {
1190 reg = <15>;
1191 atmel,fifo-size = <1024>;
1192 atmel,nb-banks = <2>;
1193 };
1194 };
1195
1196 usb1: ohci@00600000 {
1197 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1198 reg = <0x00600000 0x100000>;
5e8b3bc3 1199 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1200 clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
1201 <&uhpck>;
1202 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
655ff266
LD		 1203 status = "disabled";
1204 };
1205
1206 usb2: ehci@00700000 {
1207 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1208 reg = <0x00700000 0x100000>;
5e8b3bc3 1209 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1210 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1211 clock-names = "usb_clk", "ehci_clk", "uhpck";
655ff266
LD		 1212 status = "disabled";
1213 };
1214
1215 nand0: nand@60000000 {
1216 compatible = "atmel,at91rm9200-nand";
1217 #address-cells = <1>;
1218 #size-cells = <1>;
8ae599ef 1219 ranges;
655ff266
LD		 1220 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1221 0xffffc070 0x00000490 /* SMC PMECC regs */
1222 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
afa6a2a7 1223 0x00110000 0x00018000 /* ROM code */
655ff266 1224 >;
5e8b3bc3 1225 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
655ff266
LD		 1226 atmel,nand-addr-offset = <21>;
1227 atmel,nand-cmd-offset = <22>;
1228 pinctrl-names = "default";
1229 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
afa6a2a7 1230 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
655ff266 1231 status = "disabled";
8ae599ef
JW		 1232
1233 nfc@70000000 {
1234 compatible = "atmel,sama5d3-nfc";
1235 #address-cells = <1>;
1236 #size-cells = <1>;
1237 reg = <
1238 0x70000000 0x10000000 /* NFC Command Registers */
1239 0xffffc000 0x00000070 /* NFC HSMC regs */
1240 0x00200000 0x00100000 /* NFC SRAM banks */
1241 >;
1242 };
655ff266
LD		 1243 };
1244 };
1245};
Linux kernel - Deliverables
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