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655ff266 LD |
1 | /* |
2 | * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC | |
3 | * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC | |
4 | * | |
5 | * Copyright (C) 2013 Atmel, | |
6 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | |
7 | * | |
8 | * Licensed under GPLv2 or later. | |
9 | */ | |
10 | ||
6db64d29 | 11 | #include "skeleton.dtsi" |
d4ae89c8 | 12 | #include <dt-bindings/dma/at91.h> |
c9d0f317 | 13 | #include <dt-bindings/pinctrl/at91.h> |
5e8b3bc3 | 14 | #include <dt-bindings/interrupt-controller/irq.h> |
92f8629b | 15 | #include <dt-bindings/gpio/gpio.h> |
d2e8190b | 16 | #include <dt-bindings/clk/at91.h> |
655ff266 LD |
17 | |
18 | / { | |
19 | model = "Atmel SAMA5D3 family SoC"; | |
20 | compatible = "atmel,sama5d3", "atmel,sama5"; | |
21 | interrupt-parent = <&aic>; | |
22 | ||
23 | aliases { | |
24 | serial0 = &dbgu; | |
25 | serial1 = &usart0; | |
26 | serial2 = &usart1; | |
27 | serial3 = &usart2; | |
28 | serial4 = &usart3; | |
29 | gpio0 = &pioA; | |
30 | gpio1 = &pioB; | |
31 | gpio2 = &pioC; | |
32 | gpio3 = &pioD; | |
33 | gpio4 = &pioE; | |
34 | tcb0 = &tcb0; | |
655ff266 LD |
35 | i2c0 = &i2c0; |
36 | i2c1 = &i2c1; | |
37 | i2c2 = &i2c2; | |
38 | ssc0 = &ssc0; | |
39 | ssc1 = &ssc1; | |
f3ab0527 | 40 | pwm0 = &pwm0; |
655ff266 LD |
41 | }; |
42 | cpus { | |
8b2efa89 AB |
43 | #address-cells = <1>; |
44 | #size-cells = <0>; | |
655ff266 | 45 | cpu@0 { |
e757a6ee | 46 | device_type = "cpu"; |
655ff266 | 47 | compatible = "arm,cortex-a5"; |
e757a6ee | 48 | reg = <0x0>; |
655ff266 LD |
49 | }; |
50 | }; | |
51 | ||
d9da9778 AB |
52 | pmu { |
53 | compatible = "arm,cortex-a5-pmu"; | |
54 | interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; | |
55 | }; | |
56 | ||
655ff266 LD |
57 | memory { |
58 | reg = <0x20000000 0x8000000>; | |
59 | }; | |
60 | ||
d2e8190b BB |
61 | clocks { |
62 | adc_op_clk: adc_op_clk{ | |
63 | compatible = "fixed-clock"; | |
64 | #clock-cells = <0>; | |
65 | clock-frequency = <20000000>; | |
66 | }; | |
67 | }; | |
68 | ||
655ff266 LD |
69 | ahb { |
70 | compatible = "simple-bus"; | |
71 | #address-cells = <1>; | |
72 | #size-cells = <1>; | |
73 | ranges; | |
74 | ||
75 | apb { | |
76 | compatible = "simple-bus"; | |
77 | #address-cells = <1>; | |
78 | #size-cells = <1>; | |
79 | ranges; | |
80 | ||
81 | mmc0: mmc@f0000000 { | |
82 | compatible = "atmel,hsmci"; | |
83 | reg = <0xf0000000 0x600>; | |
5e8b3bc3 | 84 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; |
d4ae89c8 | 85 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; |
05c1bc97 | 86 | dma-names = "rxtx"; |
655ff266 LD |
87 | pinctrl-names = "default"; |
88 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; | |
89 | status = "disabled"; | |
90 | #address-cells = <1>; | |
91 | #size-cells = <0>; | |
d2e8190b BB |
92 | clocks = <&mci0_clk>; |
93 | clock-names = "mci_clk"; | |
655ff266 LD |
94 | }; |
95 | ||
96 | spi0: spi@f0004000 { | |
97 | #address-cells = <1>; | |
98 | #size-cells = <0>; | |
b7ef678e | 99 | compatible = "atmel,at91rm9200-spi"; |
655ff266 | 100 | reg = <0xf0004000 0x100>; |
5e8b3bc3 | 101 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; |
e543a73a NF |
102 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, |
103 | <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; | |
104 | dma-names = "tx", "rx"; | |
655ff266 LD |
105 | pinctrl-names = "default"; |
106 | pinctrl-0 = <&pinctrl_spi0>; | |
d2e8190b BB |
107 | clocks = <&spi0_clk>; |
108 | clock-names = "spi_clk"; | |
655ff266 LD |
109 | status = "disabled"; |
110 | }; | |
111 | ||
112 | ssc0: ssc@f0008000 { | |
113 | compatible = "atmel,at91sam9g45-ssc"; | |
114 | reg = <0xf0008000 0x4000>; | |
5e8b3bc3 | 115 | interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; |
655ff266 LD |
116 | pinctrl-names = "default"; |
117 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | |
d2e8190b BB |
118 | clocks = <&ssc0_clk>; |
119 | clock-names = "pclk"; | |
655ff266 LD |
120 | status = "disabled"; |
121 | }; | |
122 | ||
655ff266 LD |
123 | tcb0: timer@f0010000 { |
124 | compatible = "atmel,at91sam9x5-tcb"; | |
125 | reg = <0xf0010000 0x100>; | |
5e8b3bc3 | 126 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; |
d2e8190b BB |
127 | clocks = <&tcb0_clk>; |
128 | clock-names = "t0_clk"; | |
655ff266 LD |
129 | }; |
130 | ||
131 | i2c0: i2c@f0014000 { | |
132 | compatible = "atmel,at91sam9x5-i2c"; | |
133 | reg = <0xf0014000 0x4000>; | |
5e8b3bc3 | 134 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; |
d4ae89c8 LD |
135 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, |
136 | <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; | |
d9a63a45 | 137 | dma-names = "tx", "rx"; |
655ff266 LD |
138 | pinctrl-names = "default"; |
139 | pinctrl-0 = <&pinctrl_i2c0>; | |
140 | #address-cells = <1>; | |
141 | #size-cells = <0>; | |
d2e8190b | 142 | clocks = <&twi0_clk>; |
655ff266 LD |
143 | status = "disabled"; |
144 | }; | |
145 | ||
146 | i2c1: i2c@f0018000 { | |
147 | compatible = "atmel,at91sam9x5-i2c"; | |
148 | reg = <0xf0018000 0x4000>; | |
5e8b3bc3 | 149 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; |
d4ae89c8 LD |
150 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, |
151 | <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; | |
d9a63a45 | 152 | dma-names = "tx", "rx"; |
655ff266 LD |
153 | pinctrl-names = "default"; |
154 | pinctrl-0 = <&pinctrl_i2c1>; | |
155 | #address-cells = <1>; | |
156 | #size-cells = <0>; | |
d2e8190b | 157 | clocks = <&twi1_clk>; |
655ff266 LD |
158 | status = "disabled"; |
159 | }; | |
160 | ||
161 | usart0: serial@f001c000 { | |
162 | compatible = "atmel,at91sam9260-usart"; | |
163 | reg = <0xf001c000 0x100>; | |
5e8b3bc3 | 164 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; |
655ff266 LD |
165 | pinctrl-names = "default"; |
166 | pinctrl-0 = <&pinctrl_usart0>; | |
d2e8190b BB |
167 | clocks = <&usart0_clk>; |
168 | clock-names = "usart"; | |
655ff266 LD |
169 | status = "disabled"; |
170 | }; | |
171 | ||
172 | usart1: serial@f0020000 { | |
173 | compatible = "atmel,at91sam9260-usart"; | |
174 | reg = <0xf0020000 0x100>; | |
5e8b3bc3 | 175 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; |
655ff266 LD |
176 | pinctrl-names = "default"; |
177 | pinctrl-0 = <&pinctrl_usart1>; | |
d2e8190b BB |
178 | clocks = <&usart1_clk>; |
179 | clock-names = "usart"; | |
655ff266 LD |
180 | status = "disabled"; |
181 | }; | |
f3ab0527 BS |
182 | |
183 | pwm0: pwm@f002c000 { | |
184 | compatible = "atmel,sama5d3-pwm"; | |
185 | reg = <0xf002c000 0x300>; | |
186 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; | |
187 | #pwm-cells = <3>; | |
188 | clocks = <&pwm_clk>; | |
189 | status = "disabled"; | |
190 | }; | |
655ff266 | 191 | |
655ff266 LD |
192 | isi: isi@f0034000 { |
193 | compatible = "atmel,at91sam9g45-isi"; | |
194 | reg = <0xf0034000 0x4000>; | |
5e8b3bc3 | 195 | interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; |
655ff266 LD |
196 | status = "disabled"; |
197 | }; | |
198 | ||
199 | mmc1: mmc@f8000000 { | |
200 | compatible = "atmel,hsmci"; | |
201 | reg = <0xf8000000 0x600>; | |
5e8b3bc3 | 202 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; |
d4ae89c8 | 203 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; |
05c1bc97 | 204 | dma-names = "rxtx"; |
655ff266 LD |
205 | pinctrl-names = "default"; |
206 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; | |
207 | status = "disabled"; | |
208 | #address-cells = <1>; | |
209 | #size-cells = <0>; | |
d2e8190b BB |
210 | clocks = <&mci1_clk>; |
211 | clock-names = "mci_clk"; | |
655ff266 LD |
212 | }; |
213 | ||
655ff266 LD |
214 | spi1: spi@f8008000 { |
215 | #address-cells = <1>; | |
216 | #size-cells = <0>; | |
b7ef678e | 217 | compatible = "atmel,at91rm9200-spi"; |
655ff266 | 218 | reg = <0xf8008000 0x100>; |
5e8b3bc3 | 219 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; |
e543a73a NF |
220 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, |
221 | <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; | |
222 | dma-names = "tx", "rx"; | |
655ff266 LD |
223 | pinctrl-names = "default"; |
224 | pinctrl-0 = <&pinctrl_spi1>; | |
d2e8190b BB |
225 | clocks = <&spi1_clk>; |
226 | clock-names = "spi_clk"; | |
655ff266 LD |
227 | status = "disabled"; |
228 | }; | |
229 | ||
230 | ssc1: ssc@f800c000 { | |
231 | compatible = "atmel,at91sam9g45-ssc"; | |
232 | reg = <0xf800c000 0x4000>; | |
5e8b3bc3 | 233 | interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; |
655ff266 LD |
234 | pinctrl-names = "default"; |
235 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | |
d2e8190b BB |
236 | clocks = <&ssc1_clk>; |
237 | clock-names = "pclk"; | |
655ff266 LD |
238 | status = "disabled"; |
239 | }; | |
240 | ||
655ff266 LD |
241 | adc0: adc@f8018000 { |
242 | compatible = "atmel,at91sam9260-adc"; | |
243 | reg = <0xf8018000 0x100>; | |
5e8b3bc3 | 244 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; |
655ff266 LD |
245 | pinctrl-names = "default"; |
246 | pinctrl-0 = < | |
247 | &pinctrl_adc0_adtrg | |
248 | &pinctrl_adc0_ad0 | |
249 | &pinctrl_adc0_ad1 | |
250 | &pinctrl_adc0_ad2 | |
251 | &pinctrl_adc0_ad3 | |
252 | &pinctrl_adc0_ad4 | |
253 | &pinctrl_adc0_ad5 | |
254 | &pinctrl_adc0_ad6 | |
255 | &pinctrl_adc0_ad7 | |
256 | &pinctrl_adc0_ad8 | |
257 | &pinctrl_adc0_ad9 | |
258 | &pinctrl_adc0_ad10 | |
259 | &pinctrl_adc0_ad11 | |
260 | >; | |
d2e8190b BB |
261 | clocks = <&adc_clk>, |
262 | <&adc_op_clk>; | |
263 | clock-names = "adc_clk", "adc_op_clk"; | |
655ff266 LD |
264 | atmel,adc-channel-base = <0x50>; |
265 | atmel,adc-channels-used = <0xfff>; | |
266 | atmel,adc-drdy-mask = <0x1000000>; | |
267 | atmel,adc-num-channels = <12>; | |
268 | atmel,adc-startup-time = <40>; | |
269 | atmel,adc-status-register = <0x30>; | |
270 | atmel,adc-trigger-register = <0xc0>; | |
271 | atmel,adc-use-external; | |
272 | atmel,adc-vref = <3000>; | |
273 | atmel,adc-res = <10 12>; | |
274 | atmel,adc-res-names = "lowres", "highres"; | |
275 | status = "disabled"; | |
276 | ||
277 | trigger@0 { | |
278 | trigger-name = "external-rising"; | |
279 | trigger-value = <0x1>; | |
280 | trigger-external; | |
281 | }; | |
282 | trigger@1 { | |
283 | trigger-name = "external-falling"; | |
284 | trigger-value = <0x2>; | |
285 | trigger-external; | |
286 | }; | |
287 | trigger@2 { | |
288 | trigger-name = "external-any"; | |
289 | trigger-value = <0x3>; | |
290 | trigger-external; | |
291 | }; | |
292 | trigger@3 { | |
293 | trigger-name = "continuous"; | |
294 | trigger-value = <0x6>; | |
295 | }; | |
296 | }; | |
297 | ||
298 | tsadcc: tsadcc@f8018000 { | |
299 | compatible = "atmel,at91sam9x5-tsadcc"; | |
300 | reg = <0xf8018000 0x4000>; | |
5e8b3bc3 | 301 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; |
655ff266 LD |
302 | atmel,tsadcc_clock = <300000>; |
303 | atmel,filtering_average = <0x03>; | |
304 | atmel,pendet_debounce = <0x08>; | |
305 | atmel,pendet_sensitivity = <0x02>; | |
306 | atmel,ts_sample_hold_time = <0x0a>; | |
307 | status = "disabled"; | |
308 | }; | |
309 | ||
310 | i2c2: i2c@f801c000 { | |
311 | compatible = "atmel,at91sam9x5-i2c"; | |
312 | reg = <0xf801c000 0x4000>; | |
5e8b3bc3 | 313 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; |
d4ae89c8 LD |
314 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, |
315 | <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; | |
d9a63a45 | 316 | dma-names = "tx", "rx"; |
557844ec NF |
317 | pinctrl-names = "default"; |
318 | pinctrl-0 = <&pinctrl_i2c2>; | |
655ff266 LD |
319 | #address-cells = <1>; |
320 | #size-cells = <0>; | |
d2e8190b | 321 | clocks = <&twi2_clk>; |
655ff266 LD |
322 | status = "disabled"; |
323 | }; | |
324 | ||
325 | usart2: serial@f8020000 { | |
326 | compatible = "atmel,at91sam9260-usart"; | |
327 | reg = <0xf8020000 0x100>; | |
5e8b3bc3 | 328 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; |
655ff266 LD |
329 | pinctrl-names = "default"; |
330 | pinctrl-0 = <&pinctrl_usart2>; | |
d2e8190b BB |
331 | clocks = <&usart2_clk>; |
332 | clock-names = "usart"; | |
655ff266 LD |
333 | status = "disabled"; |
334 | }; | |
335 | ||
336 | usart3: serial@f8024000 { | |
337 | compatible = "atmel,at91sam9260-usart"; | |
338 | reg = <0xf8024000 0x100>; | |
5e8b3bc3 | 339 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; |
655ff266 LD |
340 | pinctrl-names = "default"; |
341 | pinctrl-0 = <&pinctrl_usart3>; | |
d2e8190b BB |
342 | clocks = <&usart3_clk>; |
343 | clock-names = "usart"; | |
655ff266 LD |
344 | status = "disabled"; |
345 | }; | |
346 | ||
655ff266 | 347 | sha@f8034000 { |
c76f266d | 348 | compatible = "atmel,at91sam9g46-sha"; |
655ff266 | 349 | reg = <0xf8034000 0x100>; |
5e8b3bc3 | 350 | interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; |
9860c515 NF |
351 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; |
352 | dma-names = "tx"; | |
4df4f446 BB |
353 | clocks = <&sha_clk>; |
354 | clock-names = "sha_clk"; | |
655ff266 LD |
355 | }; |
356 | ||
357 | aes@f8038000 { | |
c76f266d | 358 | compatible = "atmel,at91sam9g46-aes"; |
655ff266 | 359 | reg = <0xf8038000 0x100>; |
07f7d503 | 360 | interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; |
9860c515 NF |
361 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, |
362 | <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; | |
363 | dma-names = "tx", "rx"; | |
655ff266 LD |
364 | }; |
365 | ||
366 | tdes@f803c000 { | |
c76f266d | 367 | compatible = "atmel,at91sam9g46-tdes"; |
655ff266 | 368 | reg = <0xf803c000 0x100>; |
5e8b3bc3 | 369 | interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; |
9860c515 NF |
370 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, |
371 | <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; | |
372 | dma-names = "tx", "rx"; | |
655ff266 LD |
373 | }; |
374 | ||
375 | dma0: dma-controller@ffffe600 { | |
376 | compatible = "atmel,at91sam9g45-dma"; | |
377 | reg = <0xffffe600 0x200>; | |
5e8b3bc3 | 378 | interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; |
980ce7d9 | 379 | #dma-cells = <2>; |
d2e8190b BB |
380 | clocks = <&dma0_clk>; |
381 | clock-names = "dma_clk"; | |
655ff266 LD |
382 | }; |
383 | ||
384 | dma1: dma-controller@ffffe800 { | |
385 | compatible = "atmel,at91sam9g45-dma"; | |
386 | reg = <0xffffe800 0x200>; | |
5e8b3bc3 | 387 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; |
980ce7d9 | 388 | #dma-cells = <2>; |
d2e8190b BB |
389 | clocks = <&dma1_clk>; |
390 | clock-names = "dma_clk"; | |
655ff266 LD |
391 | }; |
392 | ||
393 | ramc0: ramc@ffffea00 { | |
394 | compatible = "atmel,at91sam9g45-ddramc"; | |
395 | reg = <0xffffea00 0x200>; | |
396 | }; | |
397 | ||
398 | dbgu: serial@ffffee00 { | |
399 | compatible = "atmel,at91sam9260-usart"; | |
400 | reg = <0xffffee00 0x200>; | |
5e8b3bc3 | 401 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; |
655ff266 LD |
402 | pinctrl-names = "default"; |
403 | pinctrl-0 = <&pinctrl_dbgu>; | |
d2e8190b BB |
404 | clocks = <&dbgu_clk>; |
405 | clock-names = "usart"; | |
655ff266 LD |
406 | status = "disabled"; |
407 | }; | |
408 | ||
409 | aic: interrupt-controller@fffff000 { | |
410 | #interrupt-cells = <3>; | |
411 | compatible = "atmel,sama5d3-aic"; | |
412 | interrupt-controller; | |
413 | reg = <0xfffff000 0x200>; | |
414 | atmel,external-irqs = <47>; | |
415 | }; | |
416 | ||
417 | pinctrl@fffff200 { | |
418 | #address-cells = <1>; | |
419 | #size-cells = <1>; | |
420 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; | |
421 | ranges = <0xfffff200 0xfffff200 0xa00>; | |
422 | atmel,mux-mask = < | |
423 | /* A B C */ | |
424 | 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ | |
425 | 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ | |
426 | 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ | |
427 | 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ | |
428 | 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ | |
429 | >; | |
430 | ||
431 | /* shared pinctrl settings */ | |
432 | adc0 { | |
433 | pinctrl_adc0_adtrg: adc0_adtrg { | |
434 | atmel,pins = | |
c9d0f317 | 435 | <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */ |
655ff266 LD |
436 | }; |
437 | pinctrl_adc0_ad0: adc0_ad0 { | |
438 | atmel,pins = | |
c9d0f317 | 439 | <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */ |
655ff266 LD |
440 | }; |
441 | pinctrl_adc0_ad1: adc0_ad1 { | |
442 | atmel,pins = | |
c9d0f317 | 443 | <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */ |
655ff266 LD |
444 | }; |
445 | pinctrl_adc0_ad2: adc0_ad2 { | |
446 | atmel,pins = | |
c9d0f317 | 447 | <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */ |
655ff266 LD |
448 | }; |
449 | pinctrl_adc0_ad3: adc0_ad3 { | |
450 | atmel,pins = | |
c9d0f317 | 451 | <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */ |
655ff266 LD |
452 | }; |
453 | pinctrl_adc0_ad4: adc0_ad4 { | |
454 | atmel,pins = | |
c9d0f317 | 455 | <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */ |
655ff266 LD |
456 | }; |
457 | pinctrl_adc0_ad5: adc0_ad5 { | |
458 | atmel,pins = | |
c9d0f317 | 459 | <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */ |
655ff266 LD |
460 | }; |
461 | pinctrl_adc0_ad6: adc0_ad6 { | |
462 | atmel,pins = | |
c9d0f317 | 463 | <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */ |
655ff266 LD |
464 | }; |
465 | pinctrl_adc0_ad7: adc0_ad7 { | |
466 | atmel,pins = | |
c9d0f317 | 467 | <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */ |
655ff266 LD |
468 | }; |
469 | pinctrl_adc0_ad8: adc0_ad8 { | |
470 | atmel,pins = | |
c9d0f317 | 471 | <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */ |
655ff266 LD |
472 | }; |
473 | pinctrl_adc0_ad9: adc0_ad9 { | |
474 | atmel,pins = | |
c9d0f317 | 475 | <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */ |
655ff266 LD |
476 | }; |
477 | pinctrl_adc0_ad10: adc0_ad10 { | |
478 | atmel,pins = | |
c9d0f317 | 479 | <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */ |
655ff266 LD |
480 | }; |
481 | pinctrl_adc0_ad11: adc0_ad11 { | |
482 | atmel,pins = | |
c9d0f317 | 483 | <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */ |
655ff266 LD |
484 | }; |
485 | }; | |
486 | ||
655ff266 LD |
487 | dbgu { |
488 | pinctrl_dbgu: dbgu-0 { | |
489 | atmel,pins = | |
c9d0f317 JCPV |
490 | <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */ |
491 | AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */ | |
655ff266 LD |
492 | }; |
493 | }; | |
494 | ||
495 | i2c0 { | |
496 | pinctrl_i2c0: i2c0-0 { | |
497 | atmel,pins = | |
c9d0f317 JCPV |
498 | <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ |
499 | AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ | |
655ff266 LD |
500 | }; |
501 | }; | |
502 | ||
503 | i2c1 { | |
504 | pinctrl_i2c1: i2c1-0 { | |
505 | atmel,pins = | |
c9d0f317 JCPV |
506 | <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ |
507 | AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ | |
655ff266 LD |
508 | }; |
509 | }; | |
510 | ||
557844ec NF |
511 | i2c2 { |
512 | pinctrl_i2c2: i2c2-0 { | |
513 | atmel,pins = | |
514 | <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */ | |
515 | AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ | |
516 | }; | |
517 | }; | |
518 | ||
655ff266 LD |
519 | isi { |
520 | pinctrl_isi: isi-0 { | |
521 | atmel,pins = | |
c9d0f317 JCPV |
522 | <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ |
523 | AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ | |
524 | AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ | |
525 | AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ | |
526 | AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ | |
527 | AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ | |
528 | AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ | |
529 | AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ | |
530 | AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ | |
531 | AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ | |
532 | AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ | |
533 | AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ | |
534 | AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ | |
655ff266 LD |
535 | }; |
536 | pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { | |
537 | atmel,pins = | |
c9d0f317 | 538 | <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */ |
655ff266 LD |
539 | }; |
540 | }; | |
541 | ||
655ff266 LD |
542 | mmc0 { |
543 | pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { | |
544 | atmel,pins = | |
c9d0f317 JCPV |
545 | <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */ |
546 | AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */ | |
547 | AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */ | |
655ff266 LD |
548 | }; |
549 | pinctrl_mmc0_dat1_3: mmc0_dat1_3 { | |
550 | atmel,pins = | |
c9d0f317 JCPV |
551 | <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */ |
552 | AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */ | |
553 | AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */ | |
655ff266 LD |
554 | }; |
555 | pinctrl_mmc0_dat4_7: mmc0_dat4_7 { | |
556 | atmel,pins = | |
c9d0f317 JCPV |
557 | <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ |
558 | AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ | |
559 | AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ | |
560 | AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ | |
655ff266 LD |
561 | }; |
562 | }; | |
563 | ||
564 | mmc1 { | |
565 | pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { | |
566 | atmel,pins = | |
c9d0f317 JCPV |
567 | <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */ |
568 | AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ | |
569 | AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ | |
655ff266 LD |
570 | }; |
571 | pinctrl_mmc1_dat1_3: mmc1_dat1_3 { | |
572 | atmel,pins = | |
c9d0f317 JCPV |
573 | <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ |
574 | AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ | |
575 | AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ | |
655ff266 LD |
576 | }; |
577 | }; | |
578 | ||
655ff266 LD |
579 | nand0 { |
580 | pinctrl_nand0_ale_cle: nand0_ale_cle-0 { | |
581 | atmel,pins = | |
c9d0f317 JCPV |
582 | <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */ |
583 | AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */ | |
655ff266 LD |
584 | }; |
585 | }; | |
586 | ||
655ff266 LD |
587 | spi0 { |
588 | pinctrl_spi0: spi0-0 { | |
589 | atmel,pins = | |
c9d0f317 JCPV |
590 | <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */ |
591 | AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */ | |
592 | AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */ | |
655ff266 LD |
593 | }; |
594 | }; | |
595 | ||
596 | spi1 { | |
597 | pinctrl_spi1: spi1-0 { | |
598 | atmel,pins = | |
c9d0f317 JCPV |
599 | <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */ |
600 | AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */ | |
601 | AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */ | |
655ff266 LD |
602 | }; |
603 | }; | |
604 | ||
605 | ssc0 { | |
606 | pinctrl_ssc0_tx: ssc0_tx { | |
607 | atmel,pins = | |
c9d0f317 JCPV |
608 | <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */ |
609 | AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */ | |
610 | AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */ | |
655ff266 LD |
611 | }; |
612 | ||
613 | pinctrl_ssc0_rx: ssc0_rx { | |
614 | atmel,pins = | |
c9d0f317 JCPV |
615 | <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */ |
616 | AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */ | |
617 | AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */ | |
655ff266 LD |
618 | }; |
619 | }; | |
620 | ||
621 | ssc1 { | |
622 | pinctrl_ssc1_tx: ssc1_tx { | |
623 | atmel,pins = | |
c9d0f317 JCPV |
624 | <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */ |
625 | AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */ | |
626 | AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */ | |
655ff266 LD |
627 | }; |
628 | ||
629 | pinctrl_ssc1_rx: ssc1_rx { | |
630 | atmel,pins = | |
c9d0f317 JCPV |
631 | <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */ |
632 | AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */ | |
633 | AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */ | |
655ff266 LD |
634 | }; |
635 | }; | |
636 | ||
655ff266 LD |
637 | usart0 { |
638 | pinctrl_usart0: usart0-0 { | |
639 | atmel,pins = | |
c9d0f317 JCPV |
640 | <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */ |
641 | AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */ | |
655ff266 LD |
642 | }; |
643 | ||
644 | pinctrl_usart0_rts_cts: usart0_rts_cts-0 { | |
645 | atmel,pins = | |
c9d0f317 JCPV |
646 | <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ |
647 | AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ | |
655ff266 LD |
648 | }; |
649 | }; | |
650 | ||
651 | usart1 { | |
652 | pinctrl_usart1: usart1-0 { | |
653 | atmel,pins = | |
c9d0f317 JCPV |
654 | <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */ |
655 | AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */ | |
655ff266 LD |
656 | }; |
657 | ||
658 | pinctrl_usart1_rts_cts: usart1_rts_cts-0 { | |
659 | atmel,pins = | |
c9d0f317 JCPV |
660 | <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */ |
661 | AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */ | |
655ff266 LD |
662 | }; |
663 | }; | |
664 | ||
665 | usart2 { | |
666 | pinctrl_usart2: usart2-0 { | |
667 | atmel,pins = | |
c9d0f317 JCPV |
668 | <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */ |
669 | AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */ | |
655ff266 LD |
670 | }; |
671 | ||
672 | pinctrl_usart2_rts_cts: usart2_rts_cts-0 { | |
673 | atmel,pins = | |
c9d0f317 JCPV |
674 | <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */ |
675 | AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */ | |
655ff266 LD |
676 | }; |
677 | }; | |
678 | ||
679 | usart3 { | |
680 | pinctrl_usart3: usart3-0 { | |
681 | atmel,pins = | |
c9d0f317 JCPV |
682 | <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */ |
683 | AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */ | |
655ff266 LD |
684 | }; |
685 | ||
686 | pinctrl_usart3_rts_cts: usart3_rts_cts-0 { | |
687 | atmel,pins = | |
c9d0f317 JCPV |
688 | <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */ |
689 | AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */ | |
655ff266 LD |
690 | }; |
691 | }; | |
c9d0f317 JCPV |
692 | |
693 | ||
694 | pioA: gpio@fffff200 { | |
695 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
696 | reg = <0xfffff200 0x100>; | |
5e8b3bc3 | 697 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; |
c9d0f317 JCPV |
698 | #gpio-cells = <2>; |
699 | gpio-controller; | |
700 | interrupt-controller; | |
701 | #interrupt-cells = <2>; | |
d2e8190b | 702 | clocks = <&pioA_clk>; |
c9d0f317 JCPV |
703 | }; |
704 | ||
705 | pioB: gpio@fffff400 { | |
706 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
707 | reg = <0xfffff400 0x100>; | |
5e8b3bc3 | 708 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; |
c9d0f317 JCPV |
709 | #gpio-cells = <2>; |
710 | gpio-controller; | |
711 | interrupt-controller; | |
712 | #interrupt-cells = <2>; | |
d2e8190b | 713 | clocks = <&pioB_clk>; |
c9d0f317 JCPV |
714 | }; |
715 | ||
716 | pioC: gpio@fffff600 { | |
717 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
718 | reg = <0xfffff600 0x100>; | |
5e8b3bc3 | 719 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; |
c9d0f317 JCPV |
720 | #gpio-cells = <2>; |
721 | gpio-controller; | |
722 | interrupt-controller; | |
723 | #interrupt-cells = <2>; | |
d2e8190b | 724 | clocks = <&pioC_clk>; |
c9d0f317 JCPV |
725 | }; |
726 | ||
727 | pioD: gpio@fffff800 { | |
728 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
729 | reg = <0xfffff800 0x100>; | |
5e8b3bc3 | 730 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; |
c9d0f317 JCPV |
731 | #gpio-cells = <2>; |
732 | gpio-controller; | |
733 | interrupt-controller; | |
734 | #interrupt-cells = <2>; | |
d2e8190b | 735 | clocks = <&pioD_clk>; |
c9d0f317 JCPV |
736 | }; |
737 | ||
738 | pioE: gpio@fffffa00 { | |
739 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
740 | reg = <0xfffffa00 0x100>; | |
5e8b3bc3 | 741 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; |
c9d0f317 JCPV |
742 | #gpio-cells = <2>; |
743 | gpio-controller; | |
744 | interrupt-controller; | |
745 | #interrupt-cells = <2>; | |
d2e8190b | 746 | clocks = <&pioE_clk>; |
c9d0f317 | 747 | }; |
655ff266 LD |
748 | }; |
749 | ||
750 | pmc: pmc@fffffc00 { | |
d2e8190b | 751 | compatible = "atmel,sama5d3-pmc"; |
655ff266 | 752 | reg = <0xfffffc00 0x120>; |
d2e8190b BB |
753 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
754 | interrupt-controller; | |
755 | #address-cells = <1>; | |
756 | #size-cells = <0>; | |
757 | #interrupt-cells = <1>; | |
758 | ||
759 | clk32k: slck { | |
760 | compatible = "fixed-clock"; | |
761 | #clock-cells = <0>; | |
762 | clock-frequency = <32768>; | |
763 | }; | |
764 | ||
765 | main: mainck { | |
766 | compatible = "atmel,at91rm9200-clk-main"; | |
767 | #clock-cells = <0>; | |
768 | interrupt-parent = <&pmc>; | |
769 | interrupts = <AT91_PMC_MOSCS>; | |
770 | clocks = <&clk32k>; | |
771 | }; | |
772 | ||
773 | plla: pllack { | |
774 | compatible = "atmel,sama5d3-clk-pll"; | |
775 | #clock-cells = <0>; | |
776 | interrupt-parent = <&pmc>; | |
777 | interrupts = <AT91_PMC_LOCKA>; | |
778 | clocks = <&main>; | |
779 | reg = <0>; | |
780 | atmel,clk-input-range = <8000000 50000000>; | |
781 | #atmel,pll-clk-output-range-cells = <4>; | |
782 | atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; | |
783 | }; | |
784 | ||
785 | plladiv: plladivck { | |
786 | compatible = "atmel,at91sam9x5-clk-plldiv"; | |
787 | #clock-cells = <0>; | |
788 | clocks = <&plla>; | |
789 | }; | |
790 | ||
791 | utmi: utmick { | |
792 | compatible = "atmel,at91sam9x5-clk-utmi"; | |
793 | #clock-cells = <0>; | |
794 | interrupt-parent = <&pmc>; | |
795 | interrupts = <AT91_PMC_LOCKU>; | |
796 | clocks = <&main>; | |
797 | }; | |
798 | ||
799 | mck: masterck { | |
800 | compatible = "atmel,at91sam9x5-clk-master"; | |
801 | #clock-cells = <0>; | |
802 | interrupt-parent = <&pmc>; | |
803 | interrupts = <AT91_PMC_MCKRDY>; | |
804 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; | |
805 | atmel,clk-output-range = <0 166000000>; | |
806 | atmel,clk-divisors = <1 2 4 3>; | |
807 | }; | |
808 | ||
809 | usb: usbck { | |
810 | compatible = "atmel,at91sam9x5-clk-usb"; | |
811 | #clock-cells = <0>; | |
812 | clocks = <&plladiv>, <&utmi>; | |
813 | }; | |
814 | ||
815 | prog: progck { | |
816 | compatible = "atmel,at91sam9x5-clk-programmable"; | |
817 | #address-cells = <1>; | |
818 | #size-cells = <0>; | |
819 | interrupt-parent = <&pmc>; | |
820 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; | |
821 | ||
822 | prog0: prog0 { | |
823 | #clock-cells = <0>; | |
824 | reg = <0>; | |
825 | interrupts = <AT91_PMC_PCKRDY(0)>; | |
826 | }; | |
827 | ||
828 | prog1: prog1 { | |
829 | #clock-cells = <0>; | |
830 | reg = <1>; | |
831 | interrupts = <AT91_PMC_PCKRDY(1)>; | |
832 | }; | |
833 | ||
834 | prog2: prog2 { | |
835 | #clock-cells = <0>; | |
836 | reg = <2>; | |
837 | interrupts = <AT91_PMC_PCKRDY(2)>; | |
838 | }; | |
839 | }; | |
840 | ||
841 | smd: smdclk { | |
842 | compatible = "atmel,at91sam9x5-clk-smd"; | |
843 | #clock-cells = <0>; | |
844 | clocks = <&plladiv>, <&utmi>; | |
845 | }; | |
846 | ||
847 | systemck { | |
848 | compatible = "atmel,at91rm9200-clk-system"; | |
849 | #address-cells = <1>; | |
850 | #size-cells = <0>; | |
851 | ||
852 | ddrck: ddrck { | |
853 | #clock-cells = <0>; | |
854 | reg = <2>; | |
855 | clocks = <&mck>; | |
856 | }; | |
857 | ||
858 | smdck: smdck { | |
859 | #clock-cells = <0>; | |
860 | reg = <4>; | |
861 | clocks = <&smd>; | |
862 | }; | |
863 | ||
864 | uhpck: uhpck { | |
865 | #clock-cells = <0>; | |
866 | reg = <6>; | |
867 | clocks = <&usb>; | |
868 | }; | |
869 | ||
870 | udpck: udpck { | |
871 | #clock-cells = <0>; | |
872 | reg = <7>; | |
873 | clocks = <&usb>; | |
874 | }; | |
875 | ||
876 | pck0: pck0 { | |
877 | #clock-cells = <0>; | |
878 | reg = <8>; | |
879 | clocks = <&prog0>; | |
880 | }; | |
881 | ||
882 | pck1: pck1 { | |
883 | #clock-cells = <0>; | |
884 | reg = <9>; | |
885 | clocks = <&prog1>; | |
886 | }; | |
887 | ||
888 | pck2: pck2 { | |
889 | #clock-cells = <0>; | |
890 | reg = <10>; | |
891 | clocks = <&prog2>; | |
892 | }; | |
893 | }; | |
894 | ||
895 | periphck { | |
896 | compatible = "atmel,at91sam9x5-clk-peripheral"; | |
897 | #address-cells = <1>; | |
898 | #size-cells = <0>; | |
899 | clocks = <&mck>; | |
900 | ||
901 | dbgu_clk: dbgu_clk { | |
902 | #clock-cells = <0>; | |
903 | reg = <2>; | |
904 | }; | |
905 | ||
906 | pioA_clk: pioA_clk { | |
907 | #clock-cells = <0>; | |
908 | reg = <6>; | |
909 | }; | |
910 | ||
911 | pioB_clk: pioB_clk { | |
912 | #clock-cells = <0>; | |
913 | reg = <7>; | |
914 | }; | |
915 | ||
916 | pioC_clk: pioC_clk { | |
917 | #clock-cells = <0>; | |
918 | reg = <8>; | |
919 | }; | |
920 | ||
921 | pioD_clk: pioD_clk { | |
922 | #clock-cells = <0>; | |
923 | reg = <9>; | |
924 | }; | |
925 | ||
926 | pioE_clk: pioE_clk { | |
927 | #clock-cells = <0>; | |
928 | reg = <10>; | |
929 | }; | |
930 | ||
931 | usart0_clk: usart0_clk { | |
932 | #clock-cells = <0>; | |
933 | reg = <12>; | |
934 | atmel,clk-output-range = <0 66000000>; | |
935 | }; | |
936 | ||
937 | usart1_clk: usart1_clk { | |
938 | #clock-cells = <0>; | |
939 | reg = <13>; | |
940 | atmel,clk-output-range = <0 66000000>; | |
941 | }; | |
942 | ||
943 | usart2_clk: usart2_clk { | |
944 | #clock-cells = <0>; | |
945 | reg = <14>; | |
946 | atmel,clk-output-range = <0 66000000>; | |
947 | }; | |
948 | ||
949 | usart3_clk: usart3_clk { | |
950 | #clock-cells = <0>; | |
951 | reg = <15>; | |
952 | atmel,clk-output-range = <0 66000000>; | |
953 | }; | |
954 | ||
955 | twi0_clk: twi0_clk { | |
956 | reg = <18>; | |
957 | #clock-cells = <0>; | |
958 | atmel,clk-output-range = <0 16625000>; | |
959 | }; | |
960 | ||
961 | twi1_clk: twi1_clk { | |
962 | #clock-cells = <0>; | |
963 | reg = <19>; | |
964 | atmel,clk-output-range = <0 16625000>; | |
965 | }; | |
966 | ||
967 | twi2_clk: twi2_clk { | |
968 | #clock-cells = <0>; | |
969 | reg = <20>; | |
970 | atmel,clk-output-range = <0 16625000>; | |
971 | }; | |
972 | ||
973 | mci0_clk: mci0_clk { | |
974 | #clock-cells = <0>; | |
975 | reg = <21>; | |
976 | }; | |
977 | ||
978 | mci1_clk: mci1_clk { | |
979 | #clock-cells = <0>; | |
980 | reg = <22>; | |
981 | }; | |
982 | ||
983 | spi0_clk: spi0_clk { | |
984 | #clock-cells = <0>; | |
985 | reg = <24>; | |
986 | atmel,clk-output-range = <0 133000000>; | |
987 | }; | |
988 | ||
989 | spi1_clk: spi1_clk { | |
990 | #clock-cells = <0>; | |
991 | reg = <25>; | |
992 | atmel,clk-output-range = <0 133000000>; | |
993 | }; | |
994 | ||
995 | tcb0_clk: tcb0_clk { | |
996 | #clock-cells = <0>; | |
997 | reg = <26>; | |
998 | atmel,clk-output-range = <0 133000000>; | |
999 | }; | |
1000 | ||
1001 | pwm_clk: pwm_clk { | |
1002 | #clock-cells = <0>; | |
1003 | reg = <28>; | |
1004 | }; | |
1005 | ||
1006 | adc_clk: adc_clk { | |
1007 | #clock-cells = <0>; | |
1008 | reg = <29>; | |
1009 | atmel,clk-output-range = <0 66000000>; | |
1010 | }; | |
1011 | ||
1012 | dma0_clk: dma0_clk { | |
1013 | #clock-cells = <0>; | |
1014 | reg = <30>; | |
1015 | }; | |
1016 | ||
1017 | dma1_clk: dma1_clk { | |
1018 | #clock-cells = <0>; | |
1019 | reg = <31>; | |
1020 | }; | |
1021 | ||
1022 | uhphs_clk: uhphs_clk { | |
1023 | #clock-cells = <0>; | |
1024 | reg = <32>; | |
1025 | }; | |
1026 | ||
1027 | udphs_clk: udphs_clk { | |
1028 | #clock-cells = <0>; | |
1029 | reg = <33>; | |
1030 | }; | |
1031 | ||
1032 | isi_clk: isi_clk { | |
1033 | #clock-cells = <0>; | |
1034 | reg = <37>; | |
1035 | }; | |
1036 | ||
1037 | ssc0_clk: ssc0_clk { | |
1038 | #clock-cells = <0>; | |
1039 | reg = <38>; | |
1040 | atmel,clk-output-range = <0 66000000>; | |
1041 | }; | |
1042 | ||
1043 | ssc1_clk: ssc1_clk { | |
1044 | #clock-cells = <0>; | |
1045 | reg = <39>; | |
1046 | atmel,clk-output-range = <0 66000000>; | |
1047 | }; | |
1048 | ||
1049 | sha_clk: sha_clk { | |
1050 | #clock-cells = <0>; | |
1051 | reg = <42>; | |
1052 | }; | |
1053 | ||
1054 | aes_clk: aes_clk { | |
1055 | #clock-cells = <0>; | |
1056 | reg = <43>; | |
1057 | }; | |
1058 | ||
1059 | tdes_clk: tdes_clk { | |
1060 | #clock-cells = <0>; | |
1061 | reg = <44>; | |
1062 | }; | |
1063 | ||
1064 | trng_clk: trng_clk { | |
1065 | #clock-cells = <0>; | |
1066 | reg = <45>; | |
1067 | }; | |
1068 | ||
1069 | fuse_clk: fuse_clk { | |
1070 | #clock-cells = <0>; | |
1071 | reg = <48>; | |
1072 | }; | |
1073 | }; | |
655ff266 LD |
1074 | }; |
1075 | ||
1076 | rstc@fffffe00 { | |
1077 | compatible = "atmel,at91sam9g45-rstc"; | |
1078 | reg = <0xfffffe00 0x10>; | |
1079 | }; | |
1080 | ||
1081 | pit: timer@fffffe30 { | |
1082 | compatible = "atmel,at91sam9260-pit"; | |
1083 | reg = <0xfffffe30 0xf>; | |
5e8b3bc3 | 1084 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; |
d2e8190b | 1085 | clocks = <&mck>; |
655ff266 LD |
1086 | }; |
1087 | ||
1088 | watchdog@fffffe40 { | |
1089 | compatible = "atmel,at91sam9260-wdt"; | |
1090 | reg = <0xfffffe40 0x10>; | |
1091 | status = "disabled"; | |
1092 | }; | |
1093 | ||
1094 | rtc@fffffeb0 { | |
1095 | compatible = "atmel,at91rm9200-rtc"; | |
1096 | reg = <0xfffffeb0 0x30>; | |
5e8b3bc3 | 1097 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
655ff266 LD |
1098 | }; |
1099 | }; | |
1100 | ||
1101 | usb0: gadget@00500000 { | |
1102 | #address-cells = <1>; | |
1103 | #size-cells = <0>; | |
1104 | compatible = "atmel,at91sam9rl-udc"; | |
1105 | reg = <0x00500000 0x100000 | |
1106 | 0xf8030000 0x4000>; | |
5e8b3bc3 | 1107 | interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; |
d2e8190b BB |
1108 | clocks = <&udphs_clk>, <&utmi>; |
1109 | clock-names = "pclk", "hclk"; | |
655ff266 LD |
1110 | status = "disabled"; |
1111 | ||
1112 | ep0 { | |
1113 | reg = <0>; | |
1114 | atmel,fifo-size = <64>; | |
1115 | atmel,nb-banks = <1>; | |
1116 | }; | |
1117 | ||
1118 | ep1 { | |
1119 | reg = <1>; | |
1120 | atmel,fifo-size = <1024>; | |
1121 | atmel,nb-banks = <3>; | |
1122 | atmel,can-dma; | |
1123 | atmel,can-isoc; | |
1124 | }; | |
1125 | ||
1126 | ep2 { | |
1127 | reg = <2>; | |
1128 | atmel,fifo-size = <1024>; | |
1129 | atmel,nb-banks = <3>; | |
1130 | atmel,can-dma; | |
1131 | atmel,can-isoc; | |
1132 | }; | |
1133 | ||
1134 | ep3 { | |
1135 | reg = <3>; | |
1136 | atmel,fifo-size = <1024>; | |
1137 | atmel,nb-banks = <2>; | |
1138 | atmel,can-dma; | |
1139 | }; | |
1140 | ||
1141 | ep4 { | |
1142 | reg = <4>; | |
1143 | atmel,fifo-size = <1024>; | |
1144 | atmel,nb-banks = <2>; | |
1145 | atmel,can-dma; | |
1146 | }; | |
1147 | ||
1148 | ep5 { | |
1149 | reg = <5>; | |
1150 | atmel,fifo-size = <1024>; | |
1151 | atmel,nb-banks = <2>; | |
1152 | atmel,can-dma; | |
1153 | }; | |
1154 | ||
1155 | ep6 { | |
1156 | reg = <6>; | |
1157 | atmel,fifo-size = <1024>; | |
1158 | atmel,nb-banks = <2>; | |
1159 | atmel,can-dma; | |
1160 | }; | |
1161 | ||
1162 | ep7 { | |
1163 | reg = <7>; | |
1164 | atmel,fifo-size = <1024>; | |
1165 | atmel,nb-banks = <2>; | |
1166 | atmel,can-dma; | |
1167 | }; | |
1168 | ||
1169 | ep8 { | |
1170 | reg = <8>; | |
1171 | atmel,fifo-size = <1024>; | |
1172 | atmel,nb-banks = <2>; | |
1173 | }; | |
1174 | ||
1175 | ep9 { | |
1176 | reg = <9>; | |
1177 | atmel,fifo-size = <1024>; | |
1178 | atmel,nb-banks = <2>; | |
1179 | }; | |
1180 | ||
1181 | ep10 { | |
1182 | reg = <10>; | |
1183 | atmel,fifo-size = <1024>; | |
1184 | atmel,nb-banks = <2>; | |
1185 | }; | |
1186 | ||
1187 | ep11 { | |
1188 | reg = <11>; | |
1189 | atmel,fifo-size = <1024>; | |
1190 | atmel,nb-banks = <2>; | |
1191 | }; | |
1192 | ||
1193 | ep12 { | |
1194 | reg = <12>; | |
1195 | atmel,fifo-size = <1024>; | |
1196 | atmel,nb-banks = <2>; | |
1197 | }; | |
1198 | ||
1199 | ep13 { | |
1200 | reg = <13>; | |
1201 | atmel,fifo-size = <1024>; | |
1202 | atmel,nb-banks = <2>; | |
1203 | }; | |
1204 | ||
1205 | ep14 { | |
1206 | reg = <14>; | |
1207 | atmel,fifo-size = <1024>; | |
1208 | atmel,nb-banks = <2>; | |
1209 | }; | |
1210 | ||
1211 | ep15 { | |
1212 | reg = <15>; | |
1213 | atmel,fifo-size = <1024>; | |
1214 | atmel,nb-banks = <2>; | |
1215 | }; | |
1216 | }; | |
1217 | ||
1218 | usb1: ohci@00600000 { | |
1219 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
1220 | reg = <0x00600000 0x100000>; | |
5e8b3bc3 | 1221 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; |
d2e8190b BB |
1222 | clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>, |
1223 | <&uhpck>; | |
1224 | clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; | |
655ff266 LD |
1225 | status = "disabled"; |
1226 | }; | |
1227 | ||
1228 | usb2: ehci@00700000 { | |
1229 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
1230 | reg = <0x00700000 0x100000>; | |
5e8b3bc3 | 1231 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; |
d2e8190b BB |
1232 | clocks = <&usb>, <&uhphs_clk>, <&uhpck>; |
1233 | clock-names = "usb_clk", "ehci_clk", "uhpck"; | |
655ff266 LD |
1234 | status = "disabled"; |
1235 | }; | |
1236 | ||
1237 | nand0: nand@60000000 { | |
1238 | compatible = "atmel,at91rm9200-nand"; | |
1239 | #address-cells = <1>; | |
1240 | #size-cells = <1>; | |
8ae599ef | 1241 | ranges; |
655ff266 LD |
1242 | reg = < 0x60000000 0x01000000 /* EBI CS3 */ |
1243 | 0xffffc070 0x00000490 /* SMC PMECC regs */ | |
1244 | 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ | |
afa6a2a7 | 1245 | 0x00110000 0x00018000 /* ROM code */ |
655ff266 | 1246 | >; |
5e8b3bc3 | 1247 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; |
655ff266 LD |
1248 | atmel,nand-addr-offset = <21>; |
1249 | atmel,nand-cmd-offset = <22>; | |
1250 | pinctrl-names = "default"; | |
1251 | pinctrl-0 = <&pinctrl_nand0_ale_cle>; | |
afa6a2a7 | 1252 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; |
655ff266 | 1253 | status = "disabled"; |
8ae599ef JW |
1254 | |
1255 | nfc@70000000 { | |
1256 | compatible = "atmel,sama5d3-nfc"; | |
1257 | #address-cells = <1>; | |
1258 | #size-cells = <1>; | |
1259 | reg = < | |
1260 | 0x70000000 0x10000000 /* NFC Command Registers */ | |
1261 | 0xffffc000 0x00000070 /* NFC HSMC regs */ | |
1262 | 0x00200000 0x00100000 /* NFC SRAM banks */ | |
1263 | >; | |
1264 | }; | |
655ff266 LD |
1265 | }; |
1266 | }; | |
1267 | }; |