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ARM: at91: remove phy fixup for sama5d3xek boards
[deliverable/linux.git] / arch / arm / boot / dts / sama5d3.dtsi
CommitLineData
655ff266
LD		 1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
b32313c6 3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
655ff266
LD		 4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
6db64d29 11#include "skeleton.dtsi"
d4ae89c8 12#include <dt-bindings/dma/at91.h>
c9d0f317 13#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 14#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 15#include <dt-bindings/gpio/gpio.h>
35d35aae 16#include <dt-bindings/clock/at91.h>
655ff266
LD		 17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 gpio4 = &pioE;
34 tcb0 = &tcb0;
655ff266
LD		 35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 ssc0 = &ssc0;
39 ssc1 = &ssc1;
f3ab0527 40 pwm0 = &pwm0;
655ff266
LD		 41 };
42 cpus {
8b2efa89
AB		 43 #address-cells = <1>;
44 #size-cells = <0>;
655ff266 45 cpu@0 {
e757a6ee 46 device_type = "cpu";
655ff266 47 compatible = "arm,cortex-a5";
e757a6ee 48 reg = <0x0>;
655ff266
LD		 49 };
50 };
51
d9da9778
AB		 52 pmu {
53 compatible = "arm,cortex-a5-pmu";
54 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
55 };
56
655ff266
LD		 57 memory {
58 reg = <0x20000000 0x8000000>;
59 };
60
334394c0
AB		 61 clocks {
62 slow_xtal: slow_xtal {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 };
4753219d 67
334394c0
AB		 68 main_xtal: main_xtal {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <0>;
72 };
4753219d 73
d2e8190b
BB		 74 adc_op_clk: adc_op_clk{
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <20000000>;
78 };
79 };
80
655ff266
LD		 81 ahb {
82 compatible = "simple-bus";
83 #address-cells = <1>;
84 #size-cells = <1>;
85 ranges;
86
87 apb {
88 compatible = "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges;
92
93 mmc0: mmc@f0000000 {
94 compatible = "atmel,hsmci";
95 reg = <0xf0000000 0x600>;
5e8b3bc3 96 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 97 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 98 dma-names = "rxtx";
655ff266
LD		 99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
101 status = "disabled";
102 #address-cells = <1>;
103 #size-cells = <0>;
d2e8190b
BB		 104 clocks = <&mci0_clk>;
105 clock-names = "mci_clk";
655ff266
LD		 106 };
107
108 spi0: spi@f0004000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
b7ef678e 111 compatible = "atmel,at91rm9200-spi";
655ff266 112 reg = <0xf0004000 0x100>;
5e8b3bc3 113 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 114 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
115 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
116 dma-names = "tx", "rx";
655ff266
LD		 117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_spi0>;
d2e8190b
BB		 119 clocks = <&spi0_clk>;
120 clock-names = "spi_clk";
655ff266
LD		 121 status = "disabled";
122 };
123
124 ssc0: ssc@f0008000 {
125 compatible = "atmel,at91sam9g45-ssc";
126 reg = <0xf0008000 0x4000>;
5e8b3bc3 127 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
58962b74
BS		 128 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
129 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
130 dma-names = "tx", "rx";
655ff266
LD		 131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
d2e8190b
BB		 133 clocks = <&ssc0_clk>;
134 clock-names = "pclk";
655ff266
LD		 135 status = "disabled";
136 };
137
655ff266
LD		 138 tcb0: timer@f0010000 {
139 compatible = "atmel,at91sam9x5-tcb";
140 reg = <0xf0010000 0x100>;
5e8b3bc3 141 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
d2e8190b
BB		 142 clocks = <&tcb0_clk>;
143 clock-names = "t0_clk";
655ff266
LD		 144 };
145
146 i2c0: i2c@f0014000 {
147 compatible = "atmel,at91sam9x5-i2c";
148 reg = <0xf0014000 0x4000>;
5e8b3bc3 149 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 150 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
151 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
d9a63a45 152 dma-names = "tx", "rx";
655ff266
LD		 153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_i2c0>;
155 #address-cells = <1>;
156 #size-cells = <0>;
d2e8190b 157 clocks = <&twi0_clk>;
655ff266
LD		 158 status = "disabled";
159 };
160
161 i2c1: i2c@f0018000 {
162 compatible = "atmel,at91sam9x5-i2c";
163 reg = <0xf0018000 0x4000>;
5e8b3bc3 164 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 165 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
166 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
d9a63a45 167 dma-names = "tx", "rx";
655ff266
LD		 168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_i2c1>;
170 #address-cells = <1>;
171 #size-cells = <0>;
d2e8190b 172 clocks = <&twi1_clk>;
655ff266
LD		 173 status = "disabled";
174 };
175
176 usart0: serial@f001c000 {
177 compatible = "atmel,at91sam9260-usart";
178 reg = <0xf001c000 0x100>;
5e8b3bc3 179 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_usart0>;
d2e8190b
BB		 182 clocks = <&usart0_clk>;
183 clock-names = "usart";
655ff266
LD		 184 status = "disabled";
185 };
186
187 usart1: serial@f0020000 {
188 compatible = "atmel,at91sam9260-usart";
189 reg = <0xf0020000 0x100>;
5e8b3bc3 190 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_usart1>;
d2e8190b
BB		 193 clocks = <&usart1_clk>;
194 clock-names = "usart";
655ff266
LD		 195 status = "disabled";
196 };
197
f3ab0527
BS		 198 pwm0: pwm@f002c000 {
199 compatible = "atmel,sama5d3-pwm";
200 reg = <0xf002c000 0x300>;
201 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
202 #pwm-cells = <3>;
203 clocks = <&pwm_clk>;
204 status = "disabled";
205 };
655ff266 206
655ff266
LD		 207 isi: isi@f0034000 {
208 compatible = "atmel,at91sam9g45-isi";
209 reg = <0xf0034000 0x4000>;
5e8b3bc3 210 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 211 status = "disabled";
212 };
213
214 mmc1: mmc@f8000000 {
215 compatible = "atmel,hsmci";
216 reg = <0xf8000000 0x600>;
5e8b3bc3 217 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 218 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 219 dma-names = "rxtx";
655ff266
LD		 220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
222 status = "disabled";
223 #address-cells = <1>;
224 #size-cells = <0>;
d2e8190b
BB		 225 clocks = <&mci1_clk>;
226 clock-names = "mci_clk";
655ff266
LD		 227 };
228
655ff266
LD		 229 spi1: spi@f8008000 {
230 #address-cells = <1>;
231 #size-cells = <0>;
b7ef678e 232 compatible = "atmel,at91rm9200-spi";
655ff266 233 reg = <0xf8008000 0x100>;
5e8b3bc3 234 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 235 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
236 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
237 dma-names = "tx", "rx";
655ff266
LD		 238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_spi1>;
d2e8190b
BB		 240 clocks = <&spi1_clk>;
241 clock-names = "spi_clk";
655ff266
LD		 242 status = "disabled";
243 };
244
245 ssc1: ssc@f800c000 {
246 compatible = "atmel,at91sam9g45-ssc";
247 reg = <0xf800c000 0x4000>;
5e8b3bc3 248 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
58962b74
BS		 249 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
250 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
251 dma-names = "tx", "rx";
655ff266
LD		 252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
d2e8190b
BB		 254 clocks = <&ssc1_clk>;
255 clock-names = "pclk";
655ff266
LD		 256 status = "disabled";
257 };
258
655ff266 259 adc0: adc@f8018000 {
b3b84dec
AB		 260 #address-cells = <1>;
261 #size-cells = <0>;
9879b96d 262 compatible = "atmel,at91sam9x5-adc";
655ff266 263 reg = <0xf8018000 0x100>;
5e8b3bc3 264 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 265 pinctrl-names = "default";
266 pinctrl-0 = <
267 &pinctrl_adc0_adtrg
268 &pinctrl_adc0_ad0
269 &pinctrl_adc0_ad1
270 &pinctrl_adc0_ad2
271 &pinctrl_adc0_ad3
272 &pinctrl_adc0_ad4
273 &pinctrl_adc0_ad5
274 &pinctrl_adc0_ad6
275 &pinctrl_adc0_ad7
276 &pinctrl_adc0_ad8
277 &pinctrl_adc0_ad9
278 &pinctrl_adc0_ad10
279 &pinctrl_adc0_ad11
280 >;
d2e8190b
BB		 281 clocks = <&adc_clk>,
282 <&adc_op_clk>;
283 clock-names = "adc_clk", "adc_op_clk";
655ff266 284 atmel,adc-channels-used = <0xfff>;
655ff266 285 atmel,adc-startup-time = <40>;
b3b84dec 286 atmel,adc-use-external-triggers;
655ff266
LD		 287 atmel,adc-vref = <3000>;
288 atmel,adc-res = <10 12>;
289 atmel,adc-res-names = "lowres", "highres";
290 status = "disabled";
291
292 trigger@0 {
b3b84dec 293 reg = <0>;
655ff266
LD		 294 trigger-name = "external-rising";
295 trigger-value = <0x1>;
296 trigger-external;
297 };
298 trigger@1 {
b3b84dec 299 reg = <1>;
655ff266
LD		 300 trigger-name = "external-falling";
301 trigger-value = <0x2>;
302 trigger-external;
303 };
304 trigger@2 {
b3b84dec 305 reg = <2>;
655ff266
LD		 306 trigger-name = "external-any";
307 trigger-value = <0x3>;
308 trigger-external;
309 };
310 trigger@3 {
b3b84dec 311 reg = <3>;
655ff266
LD		 312 trigger-name = "continuous";
313 trigger-value = <0x6>;
314 };
315 };
316
655ff266
LD		 317 i2c2: i2c@f801c000 {
318 compatible = "atmel,at91sam9x5-i2c";
319 reg = <0xf801c000 0x4000>;
5e8b3bc3 320 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 321 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
322 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
d9a63a45 323 dma-names = "tx", "rx";
557844ec
NF		 324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_i2c2>;
655ff266
LD		 326 #address-cells = <1>;
327 #size-cells = <0>;
d2e8190b 328 clocks = <&twi2_clk>;
655ff266
LD		 329 status = "disabled";
330 };
331
332 usart2: serial@f8020000 {
333 compatible = "atmel,at91sam9260-usart";
334 reg = <0xf8020000 0x100>;
5e8b3bc3 335 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_usart2>;
d2e8190b
BB		 338 clocks = <&usart2_clk>;
339 clock-names = "usart";
655ff266
LD		 340 status = "disabled";
341 };
342
343 usart3: serial@f8024000 {
344 compatible = "atmel,at91sam9260-usart";
345 reg = <0xf8024000 0x100>;
5e8b3bc3 346 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_usart3>;
d2e8190b
BB		 349 clocks = <&usart3_clk>;
350 clock-names = "usart";
655ff266
LD		 351 status = "disabled";
352 };
353
655ff266 354 sha@f8034000 {
c76f266d 355 compatible = "atmel,at91sam9g46-sha";
655ff266 356 reg = <0xf8034000 0x100>;
5e8b3bc3 357 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 358 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
359 dma-names = "tx";
4df4f446
BB		 360 clocks = <&sha_clk>;
361 clock-names = "sha_clk";
655ff266
LD		 362 };
363
364 aes@f8038000 {
c76f266d 365 compatible = "atmel,at91sam9g46-aes";
655ff266 366 reg = <0xf8038000 0x100>;
07f7d503 367 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 368 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
369 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
370 dma-names = "tx", "rx";
f68cd356
BB		 371 clocks = <&aes_clk>;
372 clock-names = "aes_clk";
655ff266
LD		 373 };
374
375 tdes@f803c000 {
c76f266d 376 compatible = "atmel,at91sam9g46-tdes";
655ff266 377 reg = <0xf803c000 0x100>;
5e8b3bc3 378 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 379 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
380 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
381 dma-names = "tx", "rx";
45e5c2cb
BB		 382 clocks = <&tdes_clk>;
383 clock-names = "tdes_clk";
655ff266
LD		 384 };
385
386 dma0: dma-controller@ffffe600 {
387 compatible = "atmel,at91sam9g45-dma";
388 reg = <0xffffe600 0x200>;
5e8b3bc3 389 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 390 #dma-cells = <2>;
d2e8190b
BB		 391 clocks = <&dma0_clk>;
392 clock-names = "dma_clk";
655ff266
LD		 393 };
394
395 dma1: dma-controller@ffffe800 {
396 compatible = "atmel,at91sam9g45-dma";
397 reg = <0xffffe800 0x200>;
5e8b3bc3 398 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 399 #dma-cells = <2>;
d2e8190b
BB		 400 clocks = <&dma1_clk>;
401 clock-names = "dma_clk";
655ff266
LD		 402 };
403
404 ramc0: ramc@ffffea00 {
063de897 405 compatible = "atmel,sama5d3-ddramc";
655ff266 406 reg = <0xffffea00 0x200>;
063de897
AB		 407 clocks = <&ddrck>, <&mpddr_clk>;
408 clock-names = "ddrck", "mpddr";
655ff266
LD		 409 };
410
411 dbgu: serial@ffffee00 {
412 compatible = "atmel,at91sam9260-usart";
413 reg = <0xffffee00 0x200>;
5e8b3bc3 414 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_dbgu>;
d2e8190b
BB		 417 clocks = <&dbgu_clk>;
418 clock-names = "usart";
655ff266
LD		 419 status = "disabled";
420 };
421
422 aic: interrupt-controller@fffff000 {
423 #interrupt-cells = <3>;
424 compatible = "atmel,sama5d3-aic";
425 interrupt-controller;
426 reg = <0xfffff000 0x200>;
427 atmel,external-irqs = <47>;
428 };
429
430 pinctrl@fffff200 {
431 #address-cells = <1>;
432 #size-cells = <1>;
433 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
434 ranges = <0xfffff200 0xfffff200 0xa00>;
435 atmel,mux-mask = <
436 /* A B C */
437 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
438 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
439 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
440 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
441 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
442 >;
443
444 /* shared pinctrl settings */
445 adc0 {
446 pinctrl_adc0_adtrg: adc0_adtrg {
447 atmel,pins =
c9d0f317 448 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
655ff266
LD		 449 };
450 pinctrl_adc0_ad0: adc0_ad0 {
451 atmel,pins =
c9d0f317 452 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
655ff266
LD		 453 };
454 pinctrl_adc0_ad1: adc0_ad1 {
455 atmel,pins =
c9d0f317 456 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
655ff266
LD		 457 };
458 pinctrl_adc0_ad2: adc0_ad2 {
459 atmel,pins =
c9d0f317 460 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
655ff266
LD		 461 };
462 pinctrl_adc0_ad3: adc0_ad3 {
463 atmel,pins =
c9d0f317 464 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
655ff266
LD		 465 };
466 pinctrl_adc0_ad4: adc0_ad4 {
467 atmel,pins =
c9d0f317 468 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
655ff266
LD		 469 };
470 pinctrl_adc0_ad5: adc0_ad5 {
471 atmel,pins =
c9d0f317 472 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
655ff266
LD		 473 };
474 pinctrl_adc0_ad6: adc0_ad6 {
475 atmel,pins =
c9d0f317 476 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
655ff266
LD		 477 };
478 pinctrl_adc0_ad7: adc0_ad7 {
479 atmel,pins =
c9d0f317 480 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
655ff266
LD		 481 };
482 pinctrl_adc0_ad8: adc0_ad8 {
483 atmel,pins =
c9d0f317 484 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
655ff266
LD		 485 };
486 pinctrl_adc0_ad9: adc0_ad9 {
487 atmel,pins =
c9d0f317 488 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
655ff266
LD		 489 };
490 pinctrl_adc0_ad10: adc0_ad10 {
491 atmel,pins =
c9d0f317 492 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
655ff266
LD		 493 };
494 pinctrl_adc0_ad11: adc0_ad11 {
495 atmel,pins =
c9d0f317 496 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
655ff266
LD		 497 };
498 };
499
655ff266
LD		 500 dbgu {
501 pinctrl_dbgu: dbgu-0 {
502 atmel,pins =
c9d0f317
JCPV		 503 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
504 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
655ff266
LD		 505 };
506 };
507
508 i2c0 {
509 pinctrl_i2c0: i2c0-0 {
510 atmel,pins =
c9d0f317
JCPV		 511 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
512 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
655ff266
LD		 513 };
514 };
515
516 i2c1 {
517 pinctrl_i2c1: i2c1-0 {
518 atmel,pins =
c9d0f317
JCPV		 519 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
520 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
655ff266
LD		 521 };
522 };
523
557844ec
NF		 524 i2c2 {
525 pinctrl_i2c2: i2c2-0 {
526 atmel,pins =
527 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
528 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
529 };
530 };
531
655ff266
LD		 532 isi {
533 pinctrl_isi: isi-0 {
534 atmel,pins =
c9d0f317
JCPV		 535 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
536 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
537 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
538 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
539 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
540 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
541 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
542 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
543 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
544 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
545 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
546 AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
547 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
655ff266
LD		 548 };
549 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
550 atmel,pins =
c9d0f317 551 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
655ff266
LD		 552 };
553 };
554
655ff266
LD		 555 mmc0 {
556 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
557 atmel,pins =
c9d0f317
JCPV		 558 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
559 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
560 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
655ff266
LD		 561 };
562 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
563 atmel,pins =
c9d0f317
JCPV		 564 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
565 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
566 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
655ff266
LD		 567 };
568 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
569 atmel,pins =
c9d0f317
JCPV		 570 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
571 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
572 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
573 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
655ff266
LD		 574 };
575 };
576
577 mmc1 {
578 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
579 atmel,pins =
c9d0f317
JCPV		 580 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
581 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
582 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
655ff266
LD		 583 };
584 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
585 atmel,pins =
c9d0f317
JCPV		 586 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
587 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
588 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
655ff266
LD		 589 };
590 };
591
655ff266
LD		 592 nand0 {
593 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
594 atmel,pins =
c9d0f317
JCPV		 595 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
596 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
655ff266
LD		 597 };
598 };
599
5eefd5f4
NF		 600 pwm0 {
601 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
602 atmel,pins =
603 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */
604 };
605 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
606 atmel,pins =
607 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
608 };
609 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
610 atmel,pins =
611 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */
612 };
613 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 {
614 atmel,pins =
615 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */
616 };
617
618 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
619 atmel,pins =
620 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */
621 };
622 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
623 atmel,pins =
624 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */
625 };
626 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
627 atmel,pins =
628 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */
629 };
630 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
631 atmel,pins =
632 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */
633 };
634 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 {
635 atmel,pins =
636 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */
637 };
638 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 {
639 atmel,pins =
640 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */
641 };
642
643 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
644 atmel,pins =
645 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */
646 };
647 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
648 atmel,pins =
649 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */
650 };
651 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
652 atmel,pins =
653 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */
654 };
655 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 {
656 atmel,pins =
657 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */
658 };
659
660 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
661 atmel,pins =
662 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */
663 };
664 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
665 atmel,pins =
666 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */
667 };
668 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
669 atmel,pins =
670 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */
671 };
672 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 {
673 atmel,pins =
674 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */
675 };
676 };
677
655ff266
LD		 678 spi0 {
679 pinctrl_spi0: spi0-0 {
680 atmel,pins =
c9d0f317
JCPV		 681 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
682 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
683 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
655ff266
LD		 684 };
685 };
686
687 spi1 {
688 pinctrl_spi1: spi1-0 {
689 atmel,pins =
c9d0f317
JCPV		 690 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
691 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
692 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
655ff266
LD		 693 };
694 };
695
696 ssc0 {
697 pinctrl_ssc0_tx: ssc0_tx {
698 atmel,pins =
c9d0f317
JCPV		 699 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
700 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
701 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
655ff266
LD		 702 };
703
704 pinctrl_ssc0_rx: ssc0_rx {
705 atmel,pins =
c9d0f317
JCPV		 706 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
707 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
708 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
655ff266
LD		 709 };
710 };
711
712 ssc1 {
713 pinctrl_ssc1_tx: ssc1_tx {
714 atmel,pins =
c9d0f317
JCPV		 715 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
716 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
717 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
655ff266
LD		 718 };
719
720 pinctrl_ssc1_rx: ssc1_rx {
721 atmel,pins =
c9d0f317
JCPV		 722 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
723 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
724 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
655ff266
LD		 725 };
726 };
727
655ff266
LD		 728 usart0 {
729 pinctrl_usart0: usart0-0 {
730 atmel,pins =
c9d0f317
JCPV		 731 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
732 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
655ff266
LD		 733 };
734
735 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
736 atmel,pins =
c9d0f317
JCPV		 737 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
738 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
655ff266
LD		 739 };
740 };
741
742 usart1 {
743 pinctrl_usart1: usart1-0 {
744 atmel,pins =
c9d0f317
JCPV		 745 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
746 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
655ff266
LD		 747 };
748
749 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
750 atmel,pins =
c9d0f317
JCPV		 751 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
752 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
655ff266
LD		 753 };
754 };
755
756 usart2 {
757 pinctrl_usart2: usart2-0 {
758 atmel,pins =
c9d0f317
JCPV		 759 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
760 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
655ff266
LD		 761 };
762
763 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
764 atmel,pins =
c9d0f317
JCPV		 765 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
766 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
655ff266
LD		 767 };
768 };
769
770 usart3 {
771 pinctrl_usart3: usart3-0 {
772 atmel,pins =
c9d0f317
JCPV		 773 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
774 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
655ff266
LD		 775 };
776
777 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
778 atmel,pins =
c9d0f317
JCPV		 779 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
780 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
655ff266
LD		 781 };
782 };
c9d0f317
JCPV		 783
784
785 pioA: gpio@fffff200 {
786 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
787 reg = <0xfffff200 0x100>;
5e8b3bc3 788 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 789 #gpio-cells = <2>;
790 gpio-controller;
791 interrupt-controller;
792 #interrupt-cells = <2>;
d2e8190b 793 clocks = <&pioA_clk>;
c9d0f317
JCPV		 794 };
795
796 pioB: gpio@fffff400 {
797 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
798 reg = <0xfffff400 0x100>;
5e8b3bc3 799 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 800 #gpio-cells = <2>;
801 gpio-controller;
802 interrupt-controller;
803 #interrupt-cells = <2>;
d2e8190b 804 clocks = <&pioB_clk>;
c9d0f317
JCPV		 805 };
806
807 pioC: gpio@fffff600 {
808 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
809 reg = <0xfffff600 0x100>;
5e8b3bc3 810 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 811 #gpio-cells = <2>;
812 gpio-controller;
813 interrupt-controller;
814 #interrupt-cells = <2>;
d2e8190b 815 clocks = <&pioC_clk>;
c9d0f317
JCPV		 816 };
817
818 pioD: gpio@fffff800 {
819 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
820 reg = <0xfffff800 0x100>;
5e8b3bc3 821 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 822 #gpio-cells = <2>;
823 gpio-controller;
824 interrupt-controller;
825 #interrupt-cells = <2>;
d2e8190b 826 clocks = <&pioD_clk>;
c9d0f317
JCPV		 827 };
828
829 pioE: gpio@fffffa00 {
830 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
831 reg = <0xfffffa00 0x100>;
5e8b3bc3 832 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 833 #gpio-cells = <2>;
834 gpio-controller;
835 interrupt-controller;
836 #interrupt-cells = <2>;
d2e8190b 837 clocks = <&pioE_clk>;
c9d0f317 838 };
655ff266
LD		 839 };
840
841 pmc: pmc@fffffc00 {
d2e8190b 842 compatible = "atmel,sama5d3-pmc";
655ff266 843 reg = <0xfffffc00 0x120>;
d2e8190b
BB		 844 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
845 interrupt-controller;
846 #address-cells = <1>;
847 #size-cells = <0>;
848 #interrupt-cells = <1>;
849
4753219d
BB		 850 main_rc_osc: main_rc_osc {
851 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
d2e8190b 852 #clock-cells = <0>;
4753219d
BB		 853 interrupt-parent = <&pmc>;
854 interrupts = <AT91_PMC_MOSCRCS>;
855 clock-frequency = <12000000>;
856 clock-accuracy = <50000000>;
d2e8190b
BB		 857 };
858
4753219d
BB		 859 main_osc: main_osc {
860 compatible = "atmel,at91rm9200-clk-main-osc";
d2e8190b
BB		 861 #clock-cells = <0>;
862 interrupt-parent = <&pmc>;
863 interrupts = <AT91_PMC_MOSCS>;
4753219d
BB		 864 clocks = <&main_xtal>;
865 };
866
867 main: mainck {
868 compatible = "atmel,at91sam9x5-clk-main";
869 #clock-cells = <0>;
870 interrupt-parent = <&pmc>;
871 interrupts = <AT91_PMC_MOSCSELS>;
872 clocks = <&main_rc_osc &main_osc>;
d2e8190b
BB		 873 };
874
875 plla: pllack {
876 compatible = "atmel,sama5d3-clk-pll";
877 #clock-cells = <0>;
878 interrupt-parent = <&pmc>;
879 interrupts = <AT91_PMC_LOCKA>;
880 clocks = <&main>;
881 reg = <0>;
882 atmel,clk-input-range = <8000000 50000000>;
883 #atmel,pll-clk-output-range-cells = <4>;
884 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
885 };
886
887 plladiv: plladivck {
888 compatible = "atmel,at91sam9x5-clk-plldiv";
889 #clock-cells = <0>;
890 clocks = <&plla>;
891 };
892
893 utmi: utmick {
894 compatible = "atmel,at91sam9x5-clk-utmi";
895 #clock-cells = <0>;
896 interrupt-parent = <&pmc>;
897 interrupts = <AT91_PMC_LOCKU>;
898 clocks = <&main>;
899 };
900
901 mck: masterck {
902 compatible = "atmel,at91sam9x5-clk-master";
903 #clock-cells = <0>;
904 interrupt-parent = <&pmc>;
905 interrupts = <AT91_PMC_MCKRDY>;
906 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
907 atmel,clk-output-range = <0 166000000>;
908 atmel,clk-divisors = <1 2 4 3>;
909 };
910
911 usb: usbck {
912 compatible = "atmel,at91sam9x5-clk-usb";
913 #clock-cells = <0>;
914 clocks = <&plladiv>, <&utmi>;
915 };
916
917 prog: progck {
918 compatible = "atmel,at91sam9x5-clk-programmable";
919 #address-cells = <1>;
920 #size-cells = <0>;
921 interrupt-parent = <&pmc>;
922 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
923
924 prog0: prog0 {
925 #clock-cells = <0>;
926 reg = <0>;
927 interrupts = <AT91_PMC_PCKRDY(0)>;
928 };
929
930 prog1: prog1 {
931 #clock-cells = <0>;
932 reg = <1>;
933 interrupts = <AT91_PMC_PCKRDY(1)>;
934 };
935
936 prog2: prog2 {
937 #clock-cells = <0>;
938 reg = <2>;
939 interrupts = <AT91_PMC_PCKRDY(2)>;
940 };
941 };
942
943 smd: smdclk {
944 compatible = "atmel,at91sam9x5-clk-smd";
945 #clock-cells = <0>;
946 clocks = <&plladiv>, <&utmi>;
947 };
948
949 systemck {
950 compatible = "atmel,at91rm9200-clk-system";
951 #address-cells = <1>;
952 #size-cells = <0>;
953
954 ddrck: ddrck {
955 #clock-cells = <0>;
956 reg = <2>;
957 clocks = <&mck>;
958 };
959
960 smdck: smdck {
961 #clock-cells = <0>;
962 reg = <4>;
963 clocks = <&smd>;
964 };
965
966 uhpck: uhpck {
967 #clock-cells = <0>;
968 reg = <6>;
969 clocks = <&usb>;
970 };
971
972 udpck: udpck {
973 #clock-cells = <0>;
974 reg = <7>;
975 clocks = <&usb>;
976 };
977
978 pck0: pck0 {
979 #clock-cells = <0>;
980 reg = <8>;
981 clocks = <&prog0>;
982 };
983
984 pck1: pck1 {
985 #clock-cells = <0>;
986 reg = <9>;
987 clocks = <&prog1>;
988 };
989
990 pck2: pck2 {
991 #clock-cells = <0>;
992 reg = <10>;
993 clocks = <&prog2>;
994 };
995 };
996
997 periphck {
998 compatible = "atmel,at91sam9x5-clk-peripheral";
999 #address-cells = <1>;
1000 #size-cells = <0>;
1001 clocks = <&mck>;
1002
1003 dbgu_clk: dbgu_clk {
1004 #clock-cells = <0>;
1005 reg = <2>;
1006 };
1007
1008 pioA_clk: pioA_clk {
1009 #clock-cells = <0>;
1010 reg = <6>;
1011 };
1012
1013 pioB_clk: pioB_clk {
1014 #clock-cells = <0>;
1015 reg = <7>;
1016 };
1017
1018 pioC_clk: pioC_clk {
1019 #clock-cells = <0>;
1020 reg = <8>;
1021 };
1022
1023 pioD_clk: pioD_clk {
1024 #clock-cells = <0>;
1025 reg = <9>;
1026 };
1027
1028 pioE_clk: pioE_clk {
1029 #clock-cells = <0>;
1030 reg = <10>;
1031 };
1032
1033 usart0_clk: usart0_clk {
1034 #clock-cells = <0>;
1035 reg = <12>;
1036 atmel,clk-output-range = <0 66000000>;
1037 };
1038
1039 usart1_clk: usart1_clk {
1040 #clock-cells = <0>;
1041 reg = <13>;
1042 atmel,clk-output-range = <0 66000000>;
1043 };
1044
1045 usart2_clk: usart2_clk {
1046 #clock-cells = <0>;
1047 reg = <14>;
1048 atmel,clk-output-range = <0 66000000>;
1049 };
1050
1051 usart3_clk: usart3_clk {
1052 #clock-cells = <0>;
1053 reg = <15>;
1054 atmel,clk-output-range = <0 66000000>;
1055 };
1056
1057 twi0_clk: twi0_clk {
1058 reg = <18>;
1059 #clock-cells = <0>;
1060 atmel,clk-output-range = <0 16625000>;
1061 };
1062
1063 twi1_clk: twi1_clk {
1064 #clock-cells = <0>;
1065 reg = <19>;
1066 atmel,clk-output-range = <0 16625000>;
1067 };
1068
1069 twi2_clk: twi2_clk {
1070 #clock-cells = <0>;
1071 reg = <20>;
1072 atmel,clk-output-range = <0 16625000>;
1073 };
1074
1075 mci0_clk: mci0_clk {
1076 #clock-cells = <0>;
1077 reg = <21>;
1078 };
1079
1080 mci1_clk: mci1_clk {
1081 #clock-cells = <0>;
1082 reg = <22>;
1083 };
1084
1085 spi0_clk: spi0_clk {
1086 #clock-cells = <0>;
1087 reg = <24>;
1088 atmel,clk-output-range = <0 133000000>;
1089 };
1090
1091 spi1_clk: spi1_clk {
1092 #clock-cells = <0>;
1093 reg = <25>;
1094 atmel,clk-output-range = <0 133000000>;
1095 };
1096
1097 tcb0_clk: tcb0_clk {
1098 #clock-cells = <0>;
1099 reg = <26>;
1100 atmel,clk-output-range = <0 133000000>;
1101 };
1102
1103 pwm_clk: pwm_clk {
1104 #clock-cells = <0>;
1105 reg = <28>;
1106 };
1107
1108 adc_clk: adc_clk {
1109 #clock-cells = <0>;
1110 reg = <29>;
1111 atmel,clk-output-range = <0 66000000>;
1112 };
1113
1114 dma0_clk: dma0_clk {
1115 #clock-cells = <0>;
1116 reg = <30>;
1117 };
1118
1119 dma1_clk: dma1_clk {
1120 #clock-cells = <0>;
1121 reg = <31>;
1122 };
1123
1124 uhphs_clk: uhphs_clk {
1125 #clock-cells = <0>;
1126 reg = <32>;
1127 };
1128
1129 udphs_clk: udphs_clk {
1130 #clock-cells = <0>;
1131 reg = <33>;
1132 };
1133
1134 isi_clk: isi_clk {
1135 #clock-cells = <0>;
1136 reg = <37>;
1137 };
1138
1139 ssc0_clk: ssc0_clk {
1140 #clock-cells = <0>;
1141 reg = <38>;
1142 atmel,clk-output-range = <0 66000000>;
1143 };
1144
1145 ssc1_clk: ssc1_clk {
1146 #clock-cells = <0>;
1147 reg = <39>;
1148 atmel,clk-output-range = <0 66000000>;
1149 };
1150
1151 sha_clk: sha_clk {
1152 #clock-cells = <0>;
1153 reg = <42>;
1154 };
1155
1156 aes_clk: aes_clk {
1157 #clock-cells = <0>;
1158 reg = <43>;
1159 };
1160
1161 tdes_clk: tdes_clk {
1162 #clock-cells = <0>;
1163 reg = <44>;
1164 };
1165
1166 trng_clk: trng_clk {
1167 #clock-cells = <0>;
1168 reg = <45>;
1169 };
1170
1171 fuse_clk: fuse_clk {
1172 #clock-cells = <0>;
1173 reg = <48>;
1174 };
063de897
AB		 1175
1176 mpddr_clk: mpddr_clk {
1177 #clock-cells = <0>;
1178 reg = <49>;
1179 };
d2e8190b 1180 };
655ff266
LD		 1181 };
1182
1183 rstc@fffffe00 {
1184 compatible = "atmel,at91sam9g45-rstc";
1185 reg = <0xfffffe00 0x10>;
1186 };
1187
16aa7f1f
MR		 1188 shutdown-controller@fffffe10 {
1189 compatible = "atmel,at91sam9x5-shdwc";
1190 reg = <0xfffffe10 0x10>;
1191 };
1192
655ff266
LD		 1193 pit: timer@fffffe30 {
1194 compatible = "atmel,at91sam9260-pit";
1195 reg = <0xfffffe30 0xf>;
5e8b3bc3 1196 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
d2e8190b 1197 clocks = <&mck>;
655ff266
LD		 1198 };
1199
1200 watchdog@fffffe40 {
1201 compatible = "atmel,at91sam9260-wdt";
1202 reg = <0xfffffe40 0x10>;
fe46aa67
BB		 1203 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1204 atmel,watchdog-type = "hardware";
1205 atmel,reset-type = "all";
1206 atmel,dbg-halt;
1207 atmel,idle-halt;
655ff266
LD		 1208 status = "disabled";
1209 };
1210
4753219d
BB		 1211 sckc@fffffe50 {
1212 compatible = "atmel,at91sam9x5-sckc";
1213 reg = <0xfffffe50 0x4>;
1214
1215 slow_rc_osc: slow_rc_osc {
1216 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1217 #clock-cells = <0>;
1218 clock-frequency = <32768>;
1219 clock-accuracy = <50000000>;
1220 atmel,startup-time-usec = <75>;
1221 };
1222
1223 slow_osc: slow_osc {
1224 compatible = "atmel,at91sam9x5-clk-slow-osc";
1225 #clock-cells = <0>;
1226 clocks = <&slow_xtal>;
1227 atmel,startup-time-usec = <1200000>;
1228 };
1229
1230 clk32k: slowck {
1231 compatible = "atmel,at91sam9x5-clk-slow";
1232 #clock-cells = <0>;
1233 clocks = <&slow_rc_osc &slow_osc>;
1234 };
1235 };
1236
655ff266
LD		 1237 rtc@fffffeb0 {
1238 compatible = "atmel,at91rm9200-rtc";
1239 reg = <0xfffffeb0 0x30>;
5e8b3bc3 1240 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 1241 };
1242 };
1243
1244 usb0: gadget@00500000 {
1245 #address-cells = <1>;
1246 #size-cells = <0>;
1247 compatible = "atmel,at91sam9rl-udc";
1248 reg = <0x00500000 0x100000
1249 0xf8030000 0x4000>;
5e8b3bc3 1250 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1251 clocks = <&udphs_clk>, <&utmi>;
1252 clock-names = "pclk", "hclk";
655ff266
LD		 1253 status = "disabled";
1254
1255 ep0 {
1256 reg = <0>;
1257 atmel,fifo-size = <64>;
1258 atmel,nb-banks = <1>;
1259 };
1260
1261 ep1 {
1262 reg = <1>;
1263 atmel,fifo-size = <1024>;
1264 atmel,nb-banks = <3>;
1265 atmel,can-dma;
1266 atmel,can-isoc;
1267 };
1268
1269 ep2 {
1270 reg = <2>;
1271 atmel,fifo-size = <1024>;
1272 atmel,nb-banks = <3>;
1273 atmel,can-dma;
1274 atmel,can-isoc;
1275 };
1276
1277 ep3 {
1278 reg = <3>;
1279 atmel,fifo-size = <1024>;
1280 atmel,nb-banks = <2>;
1281 atmel,can-dma;
1282 };
1283
1284 ep4 {
1285 reg = <4>;
1286 atmel,fifo-size = <1024>;
1287 atmel,nb-banks = <2>;
1288 atmel,can-dma;
1289 };
1290
1291 ep5 {
1292 reg = <5>;
1293 atmel,fifo-size = <1024>;
1294 atmel,nb-banks = <2>;
1295 atmel,can-dma;
1296 };
1297
1298 ep6 {
1299 reg = <6>;
1300 atmel,fifo-size = <1024>;
1301 atmel,nb-banks = <2>;
1302 atmel,can-dma;
1303 };
1304
1305 ep7 {
1306 reg = <7>;
1307 atmel,fifo-size = <1024>;
1308 atmel,nb-banks = <2>;
1309 atmel,can-dma;
1310 };
1311
1312 ep8 {
1313 reg = <8>;
1314 atmel,fifo-size = <1024>;
1315 atmel,nb-banks = <2>;
1316 };
1317
1318 ep9 {
1319 reg = <9>;
1320 atmel,fifo-size = <1024>;
1321 atmel,nb-banks = <2>;
1322 };
1323
1324 ep10 {
1325 reg = <10>;
1326 atmel,fifo-size = <1024>;
1327 atmel,nb-banks = <2>;
1328 };
1329
1330 ep11 {
1331 reg = <11>;
1332 atmel,fifo-size = <1024>;
1333 atmel,nb-banks = <2>;
1334 };
1335
1336 ep12 {
1337 reg = <12>;
1338 atmel,fifo-size = <1024>;
1339 atmel,nb-banks = <2>;
1340 };
1341
1342 ep13 {
1343 reg = <13>;
1344 atmel,fifo-size = <1024>;
1345 atmel,nb-banks = <2>;
1346 };
1347
1348 ep14 {
1349 reg = <14>;
1350 atmel,fifo-size = <1024>;
1351 atmel,nb-banks = <2>;
1352 };
1353
1354 ep15 {
1355 reg = <15>;
1356 atmel,fifo-size = <1024>;
1357 atmel,nb-banks = <2>;
1358 };
1359 };
1360
1361 usb1: ohci@00600000 {
1362 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1363 reg = <0x00600000 0x100000>;
5e8b3bc3 1364 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
5f877518 1365 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
d2e8190b
BB		 1366 <&uhpck>;
1367 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
655ff266
LD		 1368 status = "disabled";
1369 };
1370
1371 usb2: ehci@00700000 {
1372 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1373 reg = <0x00700000 0x100000>;
5e8b3bc3 1374 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1375 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1376 clock-names = "usb_clk", "ehci_clk", "uhpck";
655ff266
LD		 1377 status = "disabled";
1378 };
1379
1380 nand0: nand@60000000 {
1381 compatible = "atmel,at91rm9200-nand";
1382 #address-cells = <1>;
1383 #size-cells = <1>;
8ae599ef 1384 ranges;
655ff266
LD		 1385 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1386 0xffffc070 0x00000490 /* SMC PMECC regs */
1387 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
afa6a2a7 1388 0x00110000 0x00018000 /* ROM code */
655ff266 1389 >;
5e8b3bc3 1390 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
655ff266
LD		 1391 atmel,nand-addr-offset = <21>;
1392 atmel,nand-cmd-offset = <22>;
e8b2da6e 1393 atmel,nand-has-dma;
655ff266
LD		 1394 pinctrl-names = "default";
1395 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
afa6a2a7 1396 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
655ff266 1397 status = "disabled";
8ae599ef
JW		 1398
1399 nfc@70000000 {
1400 compatible = "atmel,sama5d3-nfc";
1401 #address-cells = <1>;
1402 #size-cells = <1>;
1403 reg = <
1404 0x70000000 0x10000000 /* NFC Command Registers */
1405 0xffffc000 0x00000070 /* NFC HSMC regs */
1406 0x00200000 0x00100000 /* NFC SRAM banks */
1407 >;
1408 };
655ff266
LD		 1409 };
1410 };
1411};
Linux kernel - Deliverables
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