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ARM: at91/dt: at91sam9m10g45ek PWM leds polarity is inversed
[deliverable/linux.git] / arch / arm / boot / dts / sama5d3.dtsi
CommitLineData
655ff266
LD		 1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
b32313c6 3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
655ff266
LD		 4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
6db64d29 11#include "skeleton.dtsi"
d4ae89c8 12#include <dt-bindings/dma/at91.h>
c9d0f317 13#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 14#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 15#include <dt-bindings/gpio/gpio.h>
d2e8190b 16#include <dt-bindings/clk/at91.h>
655ff266
LD		 17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 gpio4 = &pioE;
34 tcb0 = &tcb0;
655ff266
LD		 35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 ssc0 = &ssc0;
39 ssc1 = &ssc1;
f3ab0527 40 pwm0 = &pwm0;
655ff266
LD		 41 };
42 cpus {
8b2efa89
AB		 43 #address-cells = <1>;
44 #size-cells = <0>;
655ff266 45 cpu@0 {
e757a6ee 46 device_type = "cpu";
655ff266 47 compatible = "arm,cortex-a5";
e757a6ee 48 reg = <0x0>;
655ff266
LD		 49 };
50 };
51
d9da9778
AB		 52 pmu {
53 compatible = "arm,cortex-a5-pmu";
54 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
55 };
56
655ff266
LD		 57 memory {
58 reg = <0x20000000 0x8000000>;
59 };
60
d2e8190b
BB		 61 clocks {
62 adc_op_clk: adc_op_clk{
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <20000000>;
66 };
67 };
68
655ff266
LD		 69 ahb {
70 compatible = "simple-bus";
71 #address-cells = <1>;
72 #size-cells = <1>;
73 ranges;
74
75 apb {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80
81 mmc0: mmc@f0000000 {
82 compatible = "atmel,hsmci";
83 reg = <0xf0000000 0x600>;
5e8b3bc3 84 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 85 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 86 dma-names = "rxtx";
655ff266
LD		 87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
89 status = "disabled";
90 #address-cells = <1>;
91 #size-cells = <0>;
d2e8190b
BB		 92 clocks = <&mci0_clk>;
93 clock-names = "mci_clk";
655ff266
LD		 94 };
95
96 spi0: spi@f0004000 {
97 #address-cells = <1>;
98 #size-cells = <0>;
b7ef678e 99 compatible = "atmel,at91rm9200-spi";
655ff266 100 reg = <0xf0004000 0x100>;
5e8b3bc3 101 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 102 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
103 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
104 dma-names = "tx", "rx";
655ff266
LD		 105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_spi0>;
d2e8190b
BB		 107 clocks = <&spi0_clk>;
108 clock-names = "spi_clk";
655ff266
LD		 109 status = "disabled";
110 };
111
112 ssc0: ssc@f0008000 {
113 compatible = "atmel,at91sam9g45-ssc";
114 reg = <0xf0008000 0x4000>;
5e8b3bc3 115 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
655ff266
LD		 116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
d2e8190b
BB		 118 clocks = <&ssc0_clk>;
119 clock-names = "pclk";
655ff266
LD		 120 status = "disabled";
121 };
122
655ff266
LD		 123 tcb0: timer@f0010000 {
124 compatible = "atmel,at91sam9x5-tcb";
125 reg = <0xf0010000 0x100>;
5e8b3bc3 126 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
d2e8190b
BB		 127 clocks = <&tcb0_clk>;
128 clock-names = "t0_clk";
655ff266
LD		 129 };
130
131 i2c0: i2c@f0014000 {
132 compatible = "atmel,at91sam9x5-i2c";
133 reg = <0xf0014000 0x4000>;
5e8b3bc3 134 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 135 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
136 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
d9a63a45 137 dma-names = "tx", "rx";
655ff266
LD		 138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_i2c0>;
140 #address-cells = <1>;
141 #size-cells = <0>;
d2e8190b 142 clocks = <&twi0_clk>;
655ff266
LD		 143 status = "disabled";
144 };
145
146 i2c1: i2c@f0018000 {
147 compatible = "atmel,at91sam9x5-i2c";
148 reg = <0xf0018000 0x4000>;
5e8b3bc3 149 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 150 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
151 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
d9a63a45 152 dma-names = "tx", "rx";
655ff266
LD		 153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_i2c1>;
155 #address-cells = <1>;
156 #size-cells = <0>;
d2e8190b 157 clocks = <&twi1_clk>;
655ff266
LD		 158 status = "disabled";
159 };
160
161 usart0: serial@f001c000 {
162 compatible = "atmel,at91sam9260-usart";
163 reg = <0xf001c000 0x100>;
5e8b3bc3 164 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_usart0>;
d2e8190b
BB		 167 clocks = <&usart0_clk>;
168 clock-names = "usart";
655ff266
LD		 169 status = "disabled";
170 };
171
172 usart1: serial@f0020000 {
173 compatible = "atmel,at91sam9260-usart";
174 reg = <0xf0020000 0x100>;
5e8b3bc3 175 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_usart1>;
d2e8190b
BB		 178 clocks = <&usart1_clk>;
179 clock-names = "usart";
655ff266
LD		 180 status = "disabled";
181 };
182
f3ab0527
BS		 183 pwm0: pwm@f002c000 {
184 compatible = "atmel,sama5d3-pwm";
185 reg = <0xf002c000 0x300>;
186 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
187 #pwm-cells = <3>;
188 clocks = <&pwm_clk>;
189 status = "disabled";
190 };
655ff266 191
655ff266
LD		 192 isi: isi@f0034000 {
193 compatible = "atmel,at91sam9g45-isi";
194 reg = <0xf0034000 0x4000>;
5e8b3bc3 195 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 196 status = "disabled";
197 };
198
199 mmc1: mmc@f8000000 {
200 compatible = "atmel,hsmci";
201 reg = <0xf8000000 0x600>;
5e8b3bc3 202 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 203 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 204 dma-names = "rxtx";
655ff266
LD		 205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
207 status = "disabled";
208 #address-cells = <1>;
209 #size-cells = <0>;
d2e8190b
BB		 210 clocks = <&mci1_clk>;
211 clock-names = "mci_clk";
655ff266
LD		 212 };
213
655ff266
LD		 214 spi1: spi@f8008000 {
215 #address-cells = <1>;
216 #size-cells = <0>;
b7ef678e 217 compatible = "atmel,at91rm9200-spi";
655ff266 218 reg = <0xf8008000 0x100>;
5e8b3bc3 219 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 220 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
221 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
222 dma-names = "tx", "rx";
655ff266
LD		 223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_spi1>;
d2e8190b
BB		 225 clocks = <&spi1_clk>;
226 clock-names = "spi_clk";
655ff266
LD		 227 status = "disabled";
228 };
229
230 ssc1: ssc@f800c000 {
231 compatible = "atmel,at91sam9g45-ssc";
232 reg = <0xf800c000 0x4000>;
5e8b3bc3 233 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
655ff266
LD		 234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
d2e8190b
BB		 236 clocks = <&ssc1_clk>;
237 clock-names = "pclk";
655ff266
LD		 238 status = "disabled";
239 };
240
655ff266 241 adc0: adc@f8018000 {
b3b84dec
AB		 242 #address-cells = <1>;
243 #size-cells = <0>;
9879b96d 244 compatible = "atmel,at91sam9x5-adc";
655ff266 245 reg = <0xf8018000 0x100>;
5e8b3bc3 246 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 247 pinctrl-names = "default";
248 pinctrl-0 = <
249 &pinctrl_adc0_adtrg
250 &pinctrl_adc0_ad0
251 &pinctrl_adc0_ad1
252 &pinctrl_adc0_ad2
253 &pinctrl_adc0_ad3
254 &pinctrl_adc0_ad4
255 &pinctrl_adc0_ad5
256 &pinctrl_adc0_ad6
257 &pinctrl_adc0_ad7
258 &pinctrl_adc0_ad8
259 &pinctrl_adc0_ad9
260 &pinctrl_adc0_ad10
261 &pinctrl_adc0_ad11
262 >;
d2e8190b
BB		 263 clocks = <&adc_clk>,
264 <&adc_op_clk>;
265 clock-names = "adc_clk", "adc_op_clk";
655ff266 266 atmel,adc-channels-used = <0xfff>;
655ff266 267 atmel,adc-startup-time = <40>;
b3b84dec 268 atmel,adc-use-external-triggers;
655ff266
LD		 269 atmel,adc-vref = <3000>;
270 atmel,adc-res = <10 12>;
271 atmel,adc-res-names = "lowres", "highres";
272 status = "disabled";
273
274 trigger@0 {
b3b84dec 275 reg = <0>;
655ff266
LD		 276 trigger-name = "external-rising";
277 trigger-value = <0x1>;
278 trigger-external;
279 };
280 trigger@1 {
b3b84dec 281 reg = <1>;
655ff266
LD		 282 trigger-name = "external-falling";
283 trigger-value = <0x2>;
284 trigger-external;
285 };
286 trigger@2 {
b3b84dec 287 reg = <2>;
655ff266
LD		 288 trigger-name = "external-any";
289 trigger-value = <0x3>;
290 trigger-external;
291 };
292 trigger@3 {
b3b84dec 293 reg = <3>;
655ff266
LD		 294 trigger-name = "continuous";
295 trigger-value = <0x6>;
296 };
297 };
298
655ff266
LD		 299 i2c2: i2c@f801c000 {
300 compatible = "atmel,at91sam9x5-i2c";
301 reg = <0xf801c000 0x4000>;
5e8b3bc3 302 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 303 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
304 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
d9a63a45 305 dma-names = "tx", "rx";
557844ec
NF		 306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_i2c2>;
655ff266
LD		 308 #address-cells = <1>;
309 #size-cells = <0>;
d2e8190b 310 clocks = <&twi2_clk>;
655ff266
LD		 311 status = "disabled";
312 };
313
314 usart2: serial@f8020000 {
315 compatible = "atmel,at91sam9260-usart";
316 reg = <0xf8020000 0x100>;
5e8b3bc3 317 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_usart2>;
d2e8190b
BB		 320 clocks = <&usart2_clk>;
321 clock-names = "usart";
655ff266
LD		 322 status = "disabled";
323 };
324
325 usart3: serial@f8024000 {
326 compatible = "atmel,at91sam9260-usart";
327 reg = <0xf8024000 0x100>;
5e8b3bc3 328 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_usart3>;
d2e8190b
BB		 331 clocks = <&usart3_clk>;
332 clock-names = "usart";
655ff266
LD		 333 status = "disabled";
334 };
335
655ff266 336 sha@f8034000 {
c76f266d 337 compatible = "atmel,at91sam9g46-sha";
655ff266 338 reg = <0xf8034000 0x100>;
5e8b3bc3 339 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 340 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
341 dma-names = "tx";
4df4f446
BB		 342 clocks = <&sha_clk>;
343 clock-names = "sha_clk";
655ff266
LD		 344 };
345
346 aes@f8038000 {
c76f266d 347 compatible = "atmel,at91sam9g46-aes";
655ff266 348 reg = <0xf8038000 0x100>;
07f7d503 349 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 350 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
351 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
352 dma-names = "tx", "rx";
f68cd356
BB		 353 clocks = <&aes_clk>;
354 clock-names = "aes_clk";
655ff266
LD		 355 };
356
357 tdes@f803c000 {
c76f266d 358 compatible = "atmel,at91sam9g46-tdes";
655ff266 359 reg = <0xf803c000 0x100>;
5e8b3bc3 360 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 361 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
362 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
363 dma-names = "tx", "rx";
45e5c2cb
BB		 364 clocks = <&tdes_clk>;
365 clock-names = "tdes_clk";
655ff266
LD		 366 };
367
368 dma0: dma-controller@ffffe600 {
369 compatible = "atmel,at91sam9g45-dma";
370 reg = <0xffffe600 0x200>;
5e8b3bc3 371 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 372 #dma-cells = <2>;
d2e8190b
BB		 373 clocks = <&dma0_clk>;
374 clock-names = "dma_clk";
655ff266
LD		 375 };
376
377 dma1: dma-controller@ffffe800 {
378 compatible = "atmel,at91sam9g45-dma";
379 reg = <0xffffe800 0x200>;
5e8b3bc3 380 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 381 #dma-cells = <2>;
d2e8190b
BB		 382 clocks = <&dma1_clk>;
383 clock-names = "dma_clk";
655ff266
LD		 384 };
385
386 ramc0: ramc@ffffea00 {
387 compatible = "atmel,at91sam9g45-ddramc";
388 reg = <0xffffea00 0x200>;
389 };
390
391 dbgu: serial@ffffee00 {
392 compatible = "atmel,at91sam9260-usart";
393 reg = <0xffffee00 0x200>;
5e8b3bc3 394 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_dbgu>;
d2e8190b
BB		 397 clocks = <&dbgu_clk>;
398 clock-names = "usart";
655ff266
LD		 399 status = "disabled";
400 };
401
402 aic: interrupt-controller@fffff000 {
403 #interrupt-cells = <3>;
404 compatible = "atmel,sama5d3-aic";
405 interrupt-controller;
406 reg = <0xfffff000 0x200>;
407 atmel,external-irqs = <47>;
408 };
409
410 pinctrl@fffff200 {
411 #address-cells = <1>;
412 #size-cells = <1>;
413 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
414 ranges = <0xfffff200 0xfffff200 0xa00>;
415 atmel,mux-mask = <
416 /* A B C */
417 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
418 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
419 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
420 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
421 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
422 >;
423
424 /* shared pinctrl settings */
425 adc0 {
426 pinctrl_adc0_adtrg: adc0_adtrg {
427 atmel,pins =
c9d0f317 428 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
655ff266
LD		 429 };
430 pinctrl_adc0_ad0: adc0_ad0 {
431 atmel,pins =
c9d0f317 432 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
655ff266
LD		 433 };
434 pinctrl_adc0_ad1: adc0_ad1 {
435 atmel,pins =
c9d0f317 436 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
655ff266
LD		 437 };
438 pinctrl_adc0_ad2: adc0_ad2 {
439 atmel,pins =
c9d0f317 440 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
655ff266
LD		 441 };
442 pinctrl_adc0_ad3: adc0_ad3 {
443 atmel,pins =
c9d0f317 444 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
655ff266
LD		 445 };
446 pinctrl_adc0_ad4: adc0_ad4 {
447 atmel,pins =
c9d0f317 448 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
655ff266
LD		 449 };
450 pinctrl_adc0_ad5: adc0_ad5 {
451 atmel,pins =
c9d0f317 452 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
655ff266
LD		 453 };
454 pinctrl_adc0_ad6: adc0_ad6 {
455 atmel,pins =
c9d0f317 456 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
655ff266
LD		 457 };
458 pinctrl_adc0_ad7: adc0_ad7 {
459 atmel,pins =
c9d0f317 460 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
655ff266
LD		 461 };
462 pinctrl_adc0_ad8: adc0_ad8 {
463 atmel,pins =
c9d0f317 464 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
655ff266
LD		 465 };
466 pinctrl_adc0_ad9: adc0_ad9 {
467 atmel,pins =
c9d0f317 468 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
655ff266
LD		 469 };
470 pinctrl_adc0_ad10: adc0_ad10 {
471 atmel,pins =
c9d0f317 472 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
655ff266
LD		 473 };
474 pinctrl_adc0_ad11: adc0_ad11 {
475 atmel,pins =
c9d0f317 476 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
655ff266
LD		 477 };
478 };
479
655ff266
LD		 480 dbgu {
481 pinctrl_dbgu: dbgu-0 {
482 atmel,pins =
c9d0f317
JCPV		 483 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
484 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
655ff266
LD		 485 };
486 };
487
488 i2c0 {
489 pinctrl_i2c0: i2c0-0 {
490 atmel,pins =
c9d0f317
JCPV		 491 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
492 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
655ff266
LD		 493 };
494 };
495
496 i2c1 {
497 pinctrl_i2c1: i2c1-0 {
498 atmel,pins =
c9d0f317
JCPV		 499 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
500 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
655ff266
LD		 501 };
502 };
503
557844ec
NF		 504 i2c2 {
505 pinctrl_i2c2: i2c2-0 {
506 atmel,pins =
507 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
508 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
509 };
510 };
511
655ff266
LD		 512 isi {
513 pinctrl_isi: isi-0 {
514 atmel,pins =
c9d0f317
JCPV		 515 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
516 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
517 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
518 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
519 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
520 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
521 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
522 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
523 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
524 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
525 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
526 AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
527 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
655ff266
LD		 528 };
529 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
530 atmel,pins =
c9d0f317 531 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
655ff266
LD		 532 };
533 };
534
655ff266
LD		 535 mmc0 {
536 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
537 atmel,pins =
c9d0f317
JCPV		 538 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
539 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
540 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
655ff266
LD		 541 };
542 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
543 atmel,pins =
c9d0f317
JCPV		 544 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
545 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
546 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
655ff266
LD		 547 };
548 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
549 atmel,pins =
c9d0f317
JCPV		 550 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
551 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
552 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
553 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
655ff266
LD		 554 };
555 };
556
557 mmc1 {
558 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
559 atmel,pins =
c9d0f317
JCPV		 560 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
561 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
562 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
655ff266
LD		 563 };
564 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
565 atmel,pins =
c9d0f317
JCPV		 566 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
567 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
568 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
655ff266
LD		 569 };
570 };
571
655ff266
LD		 572 nand0 {
573 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
574 atmel,pins =
c9d0f317
JCPV		 575 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
576 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
655ff266
LD		 577 };
578 };
579
655ff266
LD		 580 spi0 {
581 pinctrl_spi0: spi0-0 {
582 atmel,pins =
c9d0f317
JCPV		 583 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
584 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
585 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
655ff266
LD		 586 };
587 };
588
589 spi1 {
590 pinctrl_spi1: spi1-0 {
591 atmel,pins =
c9d0f317
JCPV		 592 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
593 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
594 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
655ff266
LD		 595 };
596 };
597
598 ssc0 {
599 pinctrl_ssc0_tx: ssc0_tx {
600 atmel,pins =
c9d0f317
JCPV		 601 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
602 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
603 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
655ff266
LD		 604 };
605
606 pinctrl_ssc0_rx: ssc0_rx {
607 atmel,pins =
c9d0f317
JCPV		 608 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
609 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
610 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
655ff266
LD		 611 };
612 };
613
614 ssc1 {
615 pinctrl_ssc1_tx: ssc1_tx {
616 atmel,pins =
c9d0f317
JCPV		 617 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
618 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
619 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
655ff266
LD		 620 };
621
622 pinctrl_ssc1_rx: ssc1_rx {
623 atmel,pins =
c9d0f317
JCPV		 624 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
625 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
626 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
655ff266
LD		 627 };
628 };
629
655ff266
LD		 630 usart0 {
631 pinctrl_usart0: usart0-0 {
632 atmel,pins =
c9d0f317
JCPV		 633 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
634 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
655ff266
LD		 635 };
636
637 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
638 atmel,pins =
c9d0f317
JCPV		 639 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
640 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
655ff266
LD		 641 };
642 };
643
644 usart1 {
645 pinctrl_usart1: usart1-0 {
646 atmel,pins =
c9d0f317
JCPV		 647 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
648 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
655ff266
LD		 649 };
650
651 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
652 atmel,pins =
c9d0f317
JCPV		 653 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
654 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
655ff266
LD		 655 };
656 };
657
658 usart2 {
659 pinctrl_usart2: usart2-0 {
660 atmel,pins =
c9d0f317
JCPV		 661 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
662 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
655ff266
LD		 663 };
664
665 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
666 atmel,pins =
c9d0f317
JCPV		 667 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
668 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
655ff266
LD		 669 };
670 };
671
672 usart3 {
673 pinctrl_usart3: usart3-0 {
674 atmel,pins =
c9d0f317
JCPV		 675 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
676 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
655ff266
LD		 677 };
678
679 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
680 atmel,pins =
c9d0f317
JCPV		 681 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
682 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
655ff266
LD		 683 };
684 };
c9d0f317
JCPV		 685
686
687 pioA: gpio@fffff200 {
688 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
689 reg = <0xfffff200 0x100>;
5e8b3bc3 690 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 691 #gpio-cells = <2>;
692 gpio-controller;
693 interrupt-controller;
694 #interrupt-cells = <2>;
d2e8190b 695 clocks = <&pioA_clk>;
c9d0f317
JCPV		 696 };
697
698 pioB: gpio@fffff400 {
699 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
700 reg = <0xfffff400 0x100>;
5e8b3bc3 701 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 702 #gpio-cells = <2>;
703 gpio-controller;
704 interrupt-controller;
705 #interrupt-cells = <2>;
d2e8190b 706 clocks = <&pioB_clk>;
c9d0f317
JCPV		 707 };
708
709 pioC: gpio@fffff600 {
710 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
711 reg = <0xfffff600 0x100>;
5e8b3bc3 712 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 713 #gpio-cells = <2>;
714 gpio-controller;
715 interrupt-controller;
716 #interrupt-cells = <2>;
d2e8190b 717 clocks = <&pioC_clk>;
c9d0f317
JCPV		 718 };
719
720 pioD: gpio@fffff800 {
721 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
722 reg = <0xfffff800 0x100>;
5e8b3bc3 723 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 724 #gpio-cells = <2>;
725 gpio-controller;
726 interrupt-controller;
727 #interrupt-cells = <2>;
d2e8190b 728 clocks = <&pioD_clk>;
c9d0f317
JCPV		 729 };
730
731 pioE: gpio@fffffa00 {
732 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
733 reg = <0xfffffa00 0x100>;
5e8b3bc3 734 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 735 #gpio-cells = <2>;
736 gpio-controller;
737 interrupt-controller;
738 #interrupt-cells = <2>;
d2e8190b 739 clocks = <&pioE_clk>;
c9d0f317 740 };
655ff266
LD		 741 };
742
743 pmc: pmc@fffffc00 {
d2e8190b 744 compatible = "atmel,sama5d3-pmc";
655ff266 745 reg = <0xfffffc00 0x120>;
d2e8190b
BB		 746 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
747 interrupt-controller;
748 #address-cells = <1>;
749 #size-cells = <0>;
750 #interrupt-cells = <1>;
751
752 clk32k: slck {
753 compatible = "fixed-clock";
754 #clock-cells = <0>;
755 clock-frequency = <32768>;
756 };
757
758 main: mainck {
759 compatible = "atmel,at91rm9200-clk-main";
760 #clock-cells = <0>;
761 interrupt-parent = <&pmc>;
762 interrupts = <AT91_PMC_MOSCS>;
763 clocks = <&clk32k>;
764 };
765
766 plla: pllack {
767 compatible = "atmel,sama5d3-clk-pll";
768 #clock-cells = <0>;
769 interrupt-parent = <&pmc>;
770 interrupts = <AT91_PMC_LOCKA>;
771 clocks = <&main>;
772 reg = <0>;
773 atmel,clk-input-range = <8000000 50000000>;
774 #atmel,pll-clk-output-range-cells = <4>;
775 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
776 };
777
778 plladiv: plladivck {
779 compatible = "atmel,at91sam9x5-clk-plldiv";
780 #clock-cells = <0>;
781 clocks = <&plla>;
782 };
783
784 utmi: utmick {
785 compatible = "atmel,at91sam9x5-clk-utmi";
786 #clock-cells = <0>;
787 interrupt-parent = <&pmc>;
788 interrupts = <AT91_PMC_LOCKU>;
789 clocks = <&main>;
790 };
791
792 mck: masterck {
793 compatible = "atmel,at91sam9x5-clk-master";
794 #clock-cells = <0>;
795 interrupt-parent = <&pmc>;
796 interrupts = <AT91_PMC_MCKRDY>;
797 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
798 atmel,clk-output-range = <0 166000000>;
799 atmel,clk-divisors = <1 2 4 3>;
800 };
801
802 usb: usbck {
803 compatible = "atmel,at91sam9x5-clk-usb";
804 #clock-cells = <0>;
805 clocks = <&plladiv>, <&utmi>;
806 };
807
808 prog: progck {
809 compatible = "atmel,at91sam9x5-clk-programmable";
810 #address-cells = <1>;
811 #size-cells = <0>;
812 interrupt-parent = <&pmc>;
813 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
814
815 prog0: prog0 {
816 #clock-cells = <0>;
817 reg = <0>;
818 interrupts = <AT91_PMC_PCKRDY(0)>;
819 };
820
821 prog1: prog1 {
822 #clock-cells = <0>;
823 reg = <1>;
824 interrupts = <AT91_PMC_PCKRDY(1)>;
825 };
826
827 prog2: prog2 {
828 #clock-cells = <0>;
829 reg = <2>;
830 interrupts = <AT91_PMC_PCKRDY(2)>;
831 };
832 };
833
834 smd: smdclk {
835 compatible = "atmel,at91sam9x5-clk-smd";
836 #clock-cells = <0>;
837 clocks = <&plladiv>, <&utmi>;
838 };
839
840 systemck {
841 compatible = "atmel,at91rm9200-clk-system";
842 #address-cells = <1>;
843 #size-cells = <0>;
844
845 ddrck: ddrck {
846 #clock-cells = <0>;
847 reg = <2>;
848 clocks = <&mck>;
849 };
850
851 smdck: smdck {
852 #clock-cells = <0>;
853 reg = <4>;
854 clocks = <&smd>;
855 };
856
857 uhpck: uhpck {
858 #clock-cells = <0>;
859 reg = <6>;
860 clocks = <&usb>;
861 };
862
863 udpck: udpck {
864 #clock-cells = <0>;
865 reg = <7>;
866 clocks = <&usb>;
867 };
868
869 pck0: pck0 {
870 #clock-cells = <0>;
871 reg = <8>;
872 clocks = <&prog0>;
873 };
874
875 pck1: pck1 {
876 #clock-cells = <0>;
877 reg = <9>;
878 clocks = <&prog1>;
879 };
880
881 pck2: pck2 {
882 #clock-cells = <0>;
883 reg = <10>;
884 clocks = <&prog2>;
885 };
886 };
887
888 periphck {
889 compatible = "atmel,at91sam9x5-clk-peripheral";
890 #address-cells = <1>;
891 #size-cells = <0>;
892 clocks = <&mck>;
893
894 dbgu_clk: dbgu_clk {
895 #clock-cells = <0>;
896 reg = <2>;
897 };
898
899 pioA_clk: pioA_clk {
900 #clock-cells = <0>;
901 reg = <6>;
902 };
903
904 pioB_clk: pioB_clk {
905 #clock-cells = <0>;
906 reg = <7>;
907 };
908
909 pioC_clk: pioC_clk {
910 #clock-cells = <0>;
911 reg = <8>;
912 };
913
914 pioD_clk: pioD_clk {
915 #clock-cells = <0>;
916 reg = <9>;
917 };
918
919 pioE_clk: pioE_clk {
920 #clock-cells = <0>;
921 reg = <10>;
922 };
923
924 usart0_clk: usart0_clk {
925 #clock-cells = <0>;
926 reg = <12>;
927 atmel,clk-output-range = <0 66000000>;
928 };
929
930 usart1_clk: usart1_clk {
931 #clock-cells = <0>;
932 reg = <13>;
933 atmel,clk-output-range = <0 66000000>;
934 };
935
936 usart2_clk: usart2_clk {
937 #clock-cells = <0>;
938 reg = <14>;
939 atmel,clk-output-range = <0 66000000>;
940 };
941
942 usart3_clk: usart3_clk {
943 #clock-cells = <0>;
944 reg = <15>;
945 atmel,clk-output-range = <0 66000000>;
946 };
947
948 twi0_clk: twi0_clk {
949 reg = <18>;
950 #clock-cells = <0>;
951 atmel,clk-output-range = <0 16625000>;
952 };
953
954 twi1_clk: twi1_clk {
955 #clock-cells = <0>;
956 reg = <19>;
957 atmel,clk-output-range = <0 16625000>;
958 };
959
960 twi2_clk: twi2_clk {
961 #clock-cells = <0>;
962 reg = <20>;
963 atmel,clk-output-range = <0 16625000>;
964 };
965
966 mci0_clk: mci0_clk {
967 #clock-cells = <0>;
968 reg = <21>;
969 };
970
971 mci1_clk: mci1_clk {
972 #clock-cells = <0>;
973 reg = <22>;
974 };
975
976 spi0_clk: spi0_clk {
977 #clock-cells = <0>;
978 reg = <24>;
979 atmel,clk-output-range = <0 133000000>;
980 };
981
982 spi1_clk: spi1_clk {
983 #clock-cells = <0>;
984 reg = <25>;
985 atmel,clk-output-range = <0 133000000>;
986 };
987
988 tcb0_clk: tcb0_clk {
989 #clock-cells = <0>;
990 reg = <26>;
991 atmel,clk-output-range = <0 133000000>;
992 };
993
994 pwm_clk: pwm_clk {
995 #clock-cells = <0>;
996 reg = <28>;
997 };
998
999 adc_clk: adc_clk {
1000 #clock-cells = <0>;
1001 reg = <29>;
1002 atmel,clk-output-range = <0 66000000>;
1003 };
1004
1005 dma0_clk: dma0_clk {
1006 #clock-cells = <0>;
1007 reg = <30>;
1008 };
1009
1010 dma1_clk: dma1_clk {
1011 #clock-cells = <0>;
1012 reg = <31>;
1013 };
1014
1015 uhphs_clk: uhphs_clk {
1016 #clock-cells = <0>;
1017 reg = <32>;
1018 };
1019
1020 udphs_clk: udphs_clk {
1021 #clock-cells = <0>;
1022 reg = <33>;
1023 };
1024
1025 isi_clk: isi_clk {
1026 #clock-cells = <0>;
1027 reg = <37>;
1028 };
1029
1030 ssc0_clk: ssc0_clk {
1031 #clock-cells = <0>;
1032 reg = <38>;
1033 atmel,clk-output-range = <0 66000000>;
1034 };
1035
1036 ssc1_clk: ssc1_clk {
1037 #clock-cells = <0>;
1038 reg = <39>;
1039 atmel,clk-output-range = <0 66000000>;
1040 };
1041
1042 sha_clk: sha_clk {
1043 #clock-cells = <0>;
1044 reg = <42>;
1045 };
1046
1047 aes_clk: aes_clk {
1048 #clock-cells = <0>;
1049 reg = <43>;
1050 };
1051
1052 tdes_clk: tdes_clk {
1053 #clock-cells = <0>;
1054 reg = <44>;
1055 };
1056
1057 trng_clk: trng_clk {
1058 #clock-cells = <0>;
1059 reg = <45>;
1060 };
1061
1062 fuse_clk: fuse_clk {
1063 #clock-cells = <0>;
1064 reg = <48>;
1065 };
1066 };
655ff266
LD		 1067 };
1068
1069 rstc@fffffe00 {
1070 compatible = "atmel,at91sam9g45-rstc";
1071 reg = <0xfffffe00 0x10>;
1072 };
1073
1074 pit: timer@fffffe30 {
1075 compatible = "atmel,at91sam9260-pit";
1076 reg = <0xfffffe30 0xf>;
5e8b3bc3 1077 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
d2e8190b 1078 clocks = <&mck>;
655ff266
LD		 1079 };
1080
1081 watchdog@fffffe40 {
1082 compatible = "atmel,at91sam9260-wdt";
1083 reg = <0xfffffe40 0x10>;
fe46aa67
BB		 1084 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1085 atmel,watchdog-type = "hardware";
1086 atmel,reset-type = "all";
1087 atmel,dbg-halt;
1088 atmel,idle-halt;
655ff266
LD		 1089 status = "disabled";
1090 };
1091
1092 rtc@fffffeb0 {
1093 compatible = "atmel,at91rm9200-rtc";
1094 reg = <0xfffffeb0 0x30>;
5e8b3bc3 1095 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 1096 };
1097 };
1098
1099 usb0: gadget@00500000 {
1100 #address-cells = <1>;
1101 #size-cells = <0>;
1102 compatible = "atmel,at91sam9rl-udc";
1103 reg = <0x00500000 0x100000
1104 0xf8030000 0x4000>;
5e8b3bc3 1105 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1106 clocks = <&udphs_clk>, <&utmi>;
1107 clock-names = "pclk", "hclk";
655ff266
LD		 1108 status = "disabled";
1109
1110 ep0 {
1111 reg = <0>;
1112 atmel,fifo-size = <64>;
1113 atmel,nb-banks = <1>;
1114 };
1115
1116 ep1 {
1117 reg = <1>;
1118 atmel,fifo-size = <1024>;
1119 atmel,nb-banks = <3>;
1120 atmel,can-dma;
1121 atmel,can-isoc;
1122 };
1123
1124 ep2 {
1125 reg = <2>;
1126 atmel,fifo-size = <1024>;
1127 atmel,nb-banks = <3>;
1128 atmel,can-dma;
1129 atmel,can-isoc;
1130 };
1131
1132 ep3 {
1133 reg = <3>;
1134 atmel,fifo-size = <1024>;
1135 atmel,nb-banks = <2>;
1136 atmel,can-dma;
1137 };
1138
1139 ep4 {
1140 reg = <4>;
1141 atmel,fifo-size = <1024>;
1142 atmel,nb-banks = <2>;
1143 atmel,can-dma;
1144 };
1145
1146 ep5 {
1147 reg = <5>;
1148 atmel,fifo-size = <1024>;
1149 atmel,nb-banks = <2>;
1150 atmel,can-dma;
1151 };
1152
1153 ep6 {
1154 reg = <6>;
1155 atmel,fifo-size = <1024>;
1156 atmel,nb-banks = <2>;
1157 atmel,can-dma;
1158 };
1159
1160 ep7 {
1161 reg = <7>;
1162 atmel,fifo-size = <1024>;
1163 atmel,nb-banks = <2>;
1164 atmel,can-dma;
1165 };
1166
1167 ep8 {
1168 reg = <8>;
1169 atmel,fifo-size = <1024>;
1170 atmel,nb-banks = <2>;
1171 };
1172
1173 ep9 {
1174 reg = <9>;
1175 atmel,fifo-size = <1024>;
1176 atmel,nb-banks = <2>;
1177 };
1178
1179 ep10 {
1180 reg = <10>;
1181 atmel,fifo-size = <1024>;
1182 atmel,nb-banks = <2>;
1183 };
1184
1185 ep11 {
1186 reg = <11>;
1187 atmel,fifo-size = <1024>;
1188 atmel,nb-banks = <2>;
1189 };
1190
1191 ep12 {
1192 reg = <12>;
1193 atmel,fifo-size = <1024>;
1194 atmel,nb-banks = <2>;
1195 };
1196
1197 ep13 {
1198 reg = <13>;
1199 atmel,fifo-size = <1024>;
1200 atmel,nb-banks = <2>;
1201 };
1202
1203 ep14 {
1204 reg = <14>;
1205 atmel,fifo-size = <1024>;
1206 atmel,nb-banks = <2>;
1207 };
1208
1209 ep15 {
1210 reg = <15>;
1211 atmel,fifo-size = <1024>;
1212 atmel,nb-banks = <2>;
1213 };
1214 };
1215
1216 usb1: ohci@00600000 {
1217 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1218 reg = <0x00600000 0x100000>;
5e8b3bc3 1219 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
5f877518 1220 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
d2e8190b
BB		 1221 <&uhpck>;
1222 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
655ff266
LD		 1223 status = "disabled";
1224 };
1225
1226 usb2: ehci@00700000 {
1227 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1228 reg = <0x00700000 0x100000>;
5e8b3bc3 1229 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1230 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1231 clock-names = "usb_clk", "ehci_clk", "uhpck";
655ff266
LD		 1232 status = "disabled";
1233 };
1234
1235 nand0: nand@60000000 {
1236 compatible = "atmel,at91rm9200-nand";
1237 #address-cells = <1>;
1238 #size-cells = <1>;
8ae599ef 1239 ranges;
655ff266
LD		 1240 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1241 0xffffc070 0x00000490 /* SMC PMECC regs */
1242 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
afa6a2a7 1243 0x00110000 0x00018000 /* ROM code */
655ff266 1244 >;
5e8b3bc3 1245 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
655ff266
LD		 1246 atmel,nand-addr-offset = <21>;
1247 atmel,nand-cmd-offset = <22>;
e8b2da6e 1248 atmel,nand-has-dma;
655ff266
LD		 1249 pinctrl-names = "default";
1250 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
afa6a2a7 1251 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
655ff266 1252 status = "disabled";
8ae599ef
JW		 1253
1254 nfc@70000000 {
1255 compatible = "atmel,sama5d3-nfc";
1256 #address-cells = <1>;
1257 #size-cells = <1>;
1258 reg = <
1259 0x70000000 0x10000000 /* NFC Command Registers */
1260 0xffffc000 0x00000070 /* NFC HSMC regs */
1261 0x00200000 0x00100000 /* NFC SRAM banks */
1262 >;
1263 };
655ff266
LD		 1264 };
1265 };
1266};
Linux kernel - Deliverables
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