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ARM: at91: dt: switch to pinctrl to pre-processor
[deliverable/linux.git] / arch / arm / boot / dts / sama5d3.dtsi
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655ff266
LD		 1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC
4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
6db64d29 11#include "skeleton.dtsi"
c9d0f317 12#include <dt-bindings/pinctrl/at91.h>
92f8629b 13#include <dt-bindings/gpio/gpio.h>
655ff266
LD		 14
15/ {
16 model = "Atmel SAMA5D3 family SoC";
17 compatible = "atmel,sama5d3", "atmel,sama5";
18 interrupt-parent = <&aic>;
19
20 aliases {
21 serial0 = &dbgu;
22 serial1 = &usart0;
23 serial2 = &usart1;
24 serial3 = &usart2;
25 serial4 = &usart3;
26 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 gpio3 = &pioD;
30 gpio4 = &pioE;
31 tcb0 = &tcb0;
32 tcb1 = &tcb1;
33 i2c0 = &i2c0;
34 i2c1 = &i2c1;
35 i2c2 = &i2c2;
36 ssc0 = &ssc0;
37 ssc1 = &ssc1;
38 };
39 cpus {
40 cpu@0 {
41 compatible = "arm,cortex-a5";
42 };
43 };
44
45 memory {
46 reg = <0x20000000 0x8000000>;
47 };
48
49 ahb {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges;
54
55 apb {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges;
60
61 mmc0: mmc@f0000000 {
62 compatible = "atmel,hsmci";
63 reg = <0xf0000000 0x600>;
64 interrupts = <21 4 0>;
05c1bc97
LD		 65 dmas = <&dma0 2 0>;
66 dma-names = "rxtx";
655ff266
LD		 67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
69 status = "disabled";
70 #address-cells = <1>;
71 #size-cells = <0>;
72 };
73
74 spi0: spi@f0004000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 compatible = "atmel,at91sam9x5-spi";
78 reg = <0xf0004000 0x100>;
79 interrupts = <24 4 3>;
80 cs-gpios = <&pioD 13 0
81 &pioD 14 0 /* conflicts with SCK0 and CANRX0 */
82 &pioD 15 0 /* conflicts with CTS0 and CANTX0 */
83 &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */
84 >;
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_spi0>;
87 status = "disabled";
88 };
89
90 ssc0: ssc@f0008000 {
91 compatible = "atmel,at91sam9g45-ssc";
92 reg = <0xf0008000 0x4000>;
93 interrupts = <38 4 4>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
96 status = "disabled";
97 };
98
99 can0: can@f000c000 {
100 compatible = "atmel,at91sam9x5-can";
101 reg = <0xf000c000 0x300>;
102 interrupts = <40 4 3>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_can0_rx_tx>;
105 status = "disabled";
106 };
107
108 tcb0: timer@f0010000 {
109 compatible = "atmel,at91sam9x5-tcb";
110 reg = <0xf0010000 0x100>;
111 interrupts = <26 4 0>;
112 };
113
114 i2c0: i2c@f0014000 {
115 compatible = "atmel,at91sam9x5-i2c";
116 reg = <0xf0014000 0x4000>;
117 interrupts = <18 4 6>;
d9a63a45
LD		 118 dmas = <&dma0 2 7>,
119 <&dma0 2 8>;
120 dma-names = "tx", "rx";
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LD		 121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_i2c0>;
123 #address-cells = <1>;
124 #size-cells = <0>;
125 status = "disabled";
126 };
127
128 i2c1: i2c@f0018000 {
129 compatible = "atmel,at91sam9x5-i2c";
130 reg = <0xf0018000 0x4000>;
131 interrupts = <19 4 6>;
d9a63a45
LD		 132 dmas = <&dma0 2 9>,
133 <&dma0 2 10>;
134 dma-names = "tx", "rx";
655ff266
LD		 135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_i2c1>;
137 #address-cells = <1>;
138 #size-cells = <0>;
139 status = "disabled";
140 };
141
142 usart0: serial@f001c000 {
143 compatible = "atmel,at91sam9260-usart";
144 reg = <0xf001c000 0x100>;
145 interrupts = <12 4 5>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_usart0>;
148 status = "disabled";
149 };
150
151 usart1: serial@f0020000 {
152 compatible = "atmel,at91sam9260-usart";
153 reg = <0xf0020000 0x100>;
154 interrupts = <13 4 5>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_usart1>;
157 status = "disabled";
158 };
159
160 macb0: ethernet@f0028000 {
161 compatible = "cnds,pc302-gem", "cdns,gem";
162 reg = <0xf0028000 0x100>;
163 interrupts = <34 4 3>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
166 status = "disabled";
167 };
168
169 isi: isi@f0034000 {
170 compatible = "atmel,at91sam9g45-isi";
171 reg = <0xf0034000 0x4000>;
172 interrupts = <37 4 5>;
173 status = "disabled";
174 };
175
176 mmc1: mmc@f8000000 {
177 compatible = "atmel,hsmci";
178 reg = <0xf8000000 0x600>;
179 interrupts = <22 4 0>;
05c1bc97
LD		 180 dmas = <&dma1 2 0>;
181 dma-names = "rxtx";
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LD		 182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
184 status = "disabled";
185 #address-cells = <1>;
186 #size-cells = <0>;
187 };
188
189 mmc2: mmc@f8004000 {
190 compatible = "atmel,hsmci";
191 reg = <0xf8004000 0x600>;
192 interrupts = <23 4 0>;
05c1bc97
LD		 193 dmas = <&dma1 2 1>;
194 dma-names = "rxtx";
655ff266
LD		 195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
197 status = "disabled";
198 #address-cells = <1>;
199 #size-cells = <0>;
200 };
201
202 spi1: spi@f8008000 {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "atmel,at91sam9x5-spi";
206 reg = <0xf8008000 0x100>;
207 interrupts = <25 4 3>;
208 cs-gpios = <&pioC 25 0
209 &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */
210 &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */
211 &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */
212 >;
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_spi1>;
215 status = "disabled";
216 };
217
218 ssc1: ssc@f800c000 {
219 compatible = "atmel,at91sam9g45-ssc";
220 reg = <0xf800c000 0x4000>;
221 interrupts = <39 4 4>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
224 status = "disabled";
225 };
226
227 can1: can@f8010000 {
228 compatible = "atmel,at91sam9x5-can";
229 reg = <0xf8010000 0x300>;
230 interrupts = <41 4 3>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_can1_rx_tx>;
233 };
234
235 tcb1: timer@f8014000 {
236 compatible = "atmel,at91sam9x5-tcb";
237 reg = <0xf8014000 0x100>;
238 interrupts = <27 4 0>;
239 };
240
241 adc0: adc@f8018000 {
242 compatible = "atmel,at91sam9260-adc";
243 reg = <0xf8018000 0x100>;
244 interrupts = <29 4 5>;
245 pinctrl-names = "default";
246 pinctrl-0 = <
247 &pinctrl_adc0_adtrg
248 &pinctrl_adc0_ad0
249 &pinctrl_adc0_ad1
250 &pinctrl_adc0_ad2
251 &pinctrl_adc0_ad3
252 &pinctrl_adc0_ad4
253 &pinctrl_adc0_ad5
254 &pinctrl_adc0_ad6
255 &pinctrl_adc0_ad7
256 &pinctrl_adc0_ad8
257 &pinctrl_adc0_ad9
258 &pinctrl_adc0_ad10
259 &pinctrl_adc0_ad11
260 >;
261 atmel,adc-channel-base = <0x50>;
262 atmel,adc-channels-used = <0xfff>;
263 atmel,adc-drdy-mask = <0x1000000>;
264 atmel,adc-num-channels = <12>;
265 atmel,adc-startup-time = <40>;
266 atmel,adc-status-register = <0x30>;
267 atmel,adc-trigger-register = <0xc0>;
268 atmel,adc-use-external;
269 atmel,adc-vref = <3000>;
270 atmel,adc-res = <10 12>;
271 atmel,adc-res-names = "lowres", "highres";
272 status = "disabled";
273
274 trigger@0 {
275 trigger-name = "external-rising";
276 trigger-value = <0x1>;
277 trigger-external;
278 };
279 trigger@1 {
280 trigger-name = "external-falling";
281 trigger-value = <0x2>;
282 trigger-external;
283 };
284 trigger@2 {
285 trigger-name = "external-any";
286 trigger-value = <0x3>;
287 trigger-external;
288 };
289 trigger@3 {
290 trigger-name = "continuous";
291 trigger-value = <0x6>;
292 };
293 };
294
295 tsadcc: tsadcc@f8018000 {
296 compatible = "atmel,at91sam9x5-tsadcc";
297 reg = <0xf8018000 0x4000>;
298 interrupts = <29 4 5>;
299 atmel,tsadcc_clock = <300000>;
300 atmel,filtering_average = <0x03>;
301 atmel,pendet_debounce = <0x08>;
302 atmel,pendet_sensitivity = <0x02>;
303 atmel,ts_sample_hold_time = <0x0a>;
304 status = "disabled";
305 };
306
307 i2c2: i2c@f801c000 {
308 compatible = "atmel,at91sam9x5-i2c";
309 reg = <0xf801c000 0x4000>;
310 interrupts = <20 4 6>;
d9a63a45
LD		 311 dmas = <&dma1 2 11>,
312 <&dma1 2 12>;
313 dma-names = "tx", "rx";
655ff266
LD		 314 #address-cells = <1>;
315 #size-cells = <0>;
316 status = "disabled";
317 };
318
319 usart2: serial@f8020000 {
320 compatible = "atmel,at91sam9260-usart";
321 reg = <0xf8020000 0x100>;
322 interrupts = <14 4 5>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_usart2>;
325 status = "disabled";
326 };
327
328 usart3: serial@f8024000 {
329 compatible = "atmel,at91sam9260-usart";
330 reg = <0xf8024000 0x100>;
331 interrupts = <15 4 5>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_usart3>;
334 status = "disabled";
335 };
336
337 macb1: ethernet@f802c000 {
338 compatible = "cdns,at32ap7000-macb", "cdns,macb";
339 reg = <0xf802c000 0x100>;
340 interrupts = <35 4 3>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_macb1_rmii>;
343 status = "disabled";
344 };
345
346 sha@f8034000 {
347 compatible = "atmel,sam9g46-sha";
348 reg = <0xf8034000 0x100>;
349 interrupts = <42 4 0>;
350 };
351
352 aes@f8038000 {
353 compatible = "atmel,sam9g46-aes";
354 reg = <0xf8038000 0x100>;
355 interrupts = <43 4 0>;
356 };
357
358 tdes@f803c000 {
359 compatible = "atmel,sam9g46-tdes";
360 reg = <0xf803c000 0x100>;
361 interrupts = <44 4 0>;
362 };
363
364 dma0: dma-controller@ffffe600 {
365 compatible = "atmel,at91sam9g45-dma";
366 reg = <0xffffe600 0x200>;
367 interrupts = <30 4 0>;
980ce7d9 368 #dma-cells = <2>;
655ff266
LD		 369 };
370
371 dma1: dma-controller@ffffe800 {
372 compatible = "atmel,at91sam9g45-dma";
373 reg = <0xffffe800 0x200>;
374 interrupts = <31 4 0>;
980ce7d9 375 #dma-cells = <2>;
655ff266
LD		 376 };
377
378 ramc0: ramc@ffffea00 {
379 compatible = "atmel,at91sam9g45-ddramc";
380 reg = <0xffffea00 0x200>;
381 };
382
383 dbgu: serial@ffffee00 {
384 compatible = "atmel,at91sam9260-usart";
385 reg = <0xffffee00 0x200>;
386 interrupts = <2 4 7>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_dbgu>;
389 status = "disabled";
390 };
391
392 aic: interrupt-controller@fffff000 {
393 #interrupt-cells = <3>;
394 compatible = "atmel,sama5d3-aic";
395 interrupt-controller;
396 reg = <0xfffff000 0x200>;
397 atmel,external-irqs = <47>;
398 };
399
400 pinctrl@fffff200 {
401 #address-cells = <1>;
402 #size-cells = <1>;
403 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
404 ranges = <0xfffff200 0xfffff200 0xa00>;
405 atmel,mux-mask = <
406 /* A B C */
407 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
408 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
409 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
410 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
411 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
412 >;
413
414 /* shared pinctrl settings */
415 adc0 {
416 pinctrl_adc0_adtrg: adc0_adtrg {
417 atmel,pins =
c9d0f317 418 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
655ff266
LD		 419 };
420 pinctrl_adc0_ad0: adc0_ad0 {
421 atmel,pins =
c9d0f317 422 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
655ff266
LD		 423 };
424 pinctrl_adc0_ad1: adc0_ad1 {
425 atmel,pins =
c9d0f317 426 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
655ff266
LD		 427 };
428 pinctrl_adc0_ad2: adc0_ad2 {
429 atmel,pins =
c9d0f317 430 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
655ff266
LD		 431 };
432 pinctrl_adc0_ad3: adc0_ad3 {
433 atmel,pins =
c9d0f317 434 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
655ff266
LD		 435 };
436 pinctrl_adc0_ad4: adc0_ad4 {
437 atmel,pins =
c9d0f317 438 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
655ff266
LD		 439 };
440 pinctrl_adc0_ad5: adc0_ad5 {
441 atmel,pins =
c9d0f317 442 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
655ff266
LD		 443 };
444 pinctrl_adc0_ad6: adc0_ad6 {
445 atmel,pins =
c9d0f317 446 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
655ff266
LD		 447 };
448 pinctrl_adc0_ad7: adc0_ad7 {
449 atmel,pins =
c9d0f317 450 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
655ff266
LD		 451 };
452 pinctrl_adc0_ad8: adc0_ad8 {
453 atmel,pins =
c9d0f317 454 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
655ff266
LD		 455 };
456 pinctrl_adc0_ad9: adc0_ad9 {
457 atmel,pins =
c9d0f317 458 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
655ff266
LD		 459 };
460 pinctrl_adc0_ad10: adc0_ad10 {
461 atmel,pins =
c9d0f317 462 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
655ff266
LD		 463 };
464 pinctrl_adc0_ad11: adc0_ad11 {
465 atmel,pins =
c9d0f317 466 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
655ff266
LD		 467 };
468 };
469
470 can0 {
471 pinctrl_can0_rx_tx: can0_rx_tx {
472 atmel,pins =
c9d0f317
JCPV		 473 <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
474 AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
655ff266
LD		 475 };
476 };
477
478 can1 {
479 pinctrl_can1_rx_tx: can1_rx_tx {
480 atmel,pins =
c9d0f317
JCPV		 481 <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
482 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
655ff266
LD		 483 };
484 };
485
486 dbgu {
487 pinctrl_dbgu: dbgu-0 {
488 atmel,pins =
c9d0f317
JCPV		 489 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
490 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
655ff266
LD		 491 };
492 };
493
494 i2c0 {
495 pinctrl_i2c0: i2c0-0 {
496 atmel,pins =
c9d0f317
JCPV		 497 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
498 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
655ff266
LD		 499 };
500 };
501
502 i2c1 {
503 pinctrl_i2c1: i2c1-0 {
504 atmel,pins =
c9d0f317
JCPV		 505 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
506 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
655ff266
LD		 507 };
508 };
509
510 isi {
511 pinctrl_isi: isi-0 {
512 atmel,pins =
c9d0f317
JCPV		 513 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
514 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
515 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
516 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
517 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
518 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
519 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
520 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
521 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
522 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
523 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
524 AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
525 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
655ff266
LD		 526 };
527 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
528 atmel,pins =
c9d0f317 529 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
655ff266
LD		 530 };
531 };
532
533 lcd {
534 pinctrl_lcd: lcd-0 {
535 atmel,pins =
c9d0f317
JCPV		 536 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */
537 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */
538 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */
539 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */
540 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */
541 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */
542 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */
543 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */
544 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */
545 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */
546 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */
547 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */
548 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */
549 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */
550 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */
551 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */
552 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */
553 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */
554 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */
555 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */
556 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */
557 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */
558 AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */
559 AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */
560 AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */
561 AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */
562 AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */
563 AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */
564 AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */
565 AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
655ff266
LD		 566 };
567 };
568
569 macb0 {
570 pinctrl_macb0_data_rgmii: macb0_data_rgmii {
571 atmel,pins =
c9d0f317
JCPV		 572 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
573 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
574 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
575 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
576 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
577 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
578 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
579 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
655ff266
LD		 580 };
581 pinctrl_macb0_data_gmii: macb0_data_gmii {
582 atmel,pins =
c9d0f317
JCPV		 583 <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
584 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
585 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
586 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
587 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
588 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */
589 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */
590 AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
655ff266
LD		 591 };
592 pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
593 atmel,pins =
c9d0f317
JCPV		 594 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
595 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
596 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
597 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
598 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
599 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
600 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
655ff266
LD		 601 };
602 pinctrl_macb0_signal_gmii: macb0_signal_gmii {
603 atmel,pins =
c9d0f317
JCPV		 604 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
605 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */
606 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
607 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */
608 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
609 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */
610 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */
611 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
612 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
613 AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
655ff266
LD		 614 };
615
616 };
617
618 macb1 {
619 pinctrl_macb1_rmii: macb1_rmii-0 {
620 atmel,pins =
c9d0f317
JCPV		 621 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
622 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
623 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
624 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
625 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
626 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
627 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
628 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
629 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
630 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */
655ff266
LD		 631 };
632 };
633
634 mmc0 {
635 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
636 atmel,pins =
c9d0f317
JCPV		 637 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
638 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
639 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
655ff266
LD		 640 };
641 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
642 atmel,pins =
c9d0f317
JCPV		 643 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
644 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
645 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
655ff266
LD		 646 };
647 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
648 atmel,pins =
c9d0f317
JCPV		 649 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
650 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
651 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
652 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
655ff266
LD		 653 };
654 };
655
656 mmc1 {
657 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
658 atmel,pins =
c9d0f317
JCPV		 659 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
660 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
661 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
655ff266
LD		 662 };
663 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
664 atmel,pins =
c9d0f317
JCPV		 665 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
666 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
667 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
655ff266
LD		 668 };
669 };
670
671 mmc2 {
672 pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
673 atmel,pins =
c9d0f317
JCPV		 674 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
675 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
676 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
655ff266
LD		 677 };
678 pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
679 atmel,pins =
c9d0f317
JCPV		 680 <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
681 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
682 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
655ff266
LD		 683 };
684 };
685
686 nand0 {
687 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
688 atmel,pins =
c9d0f317
JCPV		 689 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
690 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
655ff266
LD		 691 };
692 };
693
655ff266
LD		 694 spi0 {
695 pinctrl_spi0: spi0-0 {
696 atmel,pins =
c9d0f317
JCPV		 697 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
698 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
699 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
655ff266
LD		 700 };
701 };
702
703 spi1 {
704 pinctrl_spi1: spi1-0 {
705 atmel,pins =
c9d0f317
JCPV		 706 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
707 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
708 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
655ff266
LD		 709 };
710 };
711
712 ssc0 {
713 pinctrl_ssc0_tx: ssc0_tx {
714 atmel,pins =
c9d0f317
JCPV		 715 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
716 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
717 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
655ff266
LD		 718 };
719
720 pinctrl_ssc0_rx: ssc0_rx {
721 atmel,pins =
c9d0f317
JCPV		 722 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
723 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
724 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
655ff266
LD		 725 };
726 };
727
728 ssc1 {
729 pinctrl_ssc1_tx: ssc1_tx {
730 atmel,pins =
c9d0f317
JCPV		 731 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
732 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
733 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
655ff266
LD		 734 };
735
736 pinctrl_ssc1_rx: ssc1_rx {
737 atmel,pins =
c9d0f317
JCPV		 738 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
739 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
740 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
655ff266
LD		 741 };
742 };
743
744 uart0 {
745 pinctrl_uart0: uart0-0 {
746 atmel,pins =
c9d0f317
JCPV		 747 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
748 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
655ff266
LD		 749 };
750 };
751
752 uart1 {
753 pinctrl_uart1: uart1-0 {
754 atmel,pins =
c9d0f317
JCPV		 755 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
756 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
655ff266
LD		 757 };
758 };
759
760 usart0 {
761 pinctrl_usart0: usart0-0 {
762 atmel,pins =
c9d0f317
JCPV		 763 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
764 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
655ff266
LD		 765 };
766
767 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
768 atmel,pins =
c9d0f317
JCPV		 769 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
770 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
655ff266
LD		 771 };
772 };
773
774 usart1 {
775 pinctrl_usart1: usart1-0 {
776 atmel,pins =
c9d0f317
JCPV		 777 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
778 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
655ff266
LD		 779 };
780
781 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
782 atmel,pins =
c9d0f317
JCPV		 783 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
784 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
655ff266
LD		 785 };
786 };
787
788 usart2 {
789 pinctrl_usart2: usart2-0 {
790 atmel,pins =
c9d0f317
JCPV		 791 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
792 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
655ff266
LD		 793 };
794
795 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
796 atmel,pins =
c9d0f317
JCPV		 797 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
798 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
655ff266
LD		 799 };
800 };
801
802 usart3 {
803 pinctrl_usart3: usart3-0 {
804 atmel,pins =
c9d0f317
JCPV		 805 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
806 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
655ff266
LD		 807 };
808
809 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
810 atmel,pins =
c9d0f317
JCPV		 811 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
812 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
655ff266
LD		 813 };
814 };
c9d0f317
JCPV		 815
816
817 pioA: gpio@fffff200 {
818 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
819 reg = <0xfffff200 0x100>;
820 interrupts = <6 4 1>;
821 #gpio-cells = <2>;
822 gpio-controller;
823 interrupt-controller;
824 #interrupt-cells = <2>;
825 };
826
827 pioB: gpio@fffff400 {
828 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
829 reg = <0xfffff400 0x100>;
830 interrupts = <7 4 1>;
831 #gpio-cells = <2>;
832 gpio-controller;
833 interrupt-controller;
834 #interrupt-cells = <2>;
835 };
836
837 pioC: gpio@fffff600 {
838 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
839 reg = <0xfffff600 0x100>;
840 interrupts = <8 4 1>;
841 #gpio-cells = <2>;
842 gpio-controller;
843 interrupt-controller;
844 #interrupt-cells = <2>;
845 };
846
847 pioD: gpio@fffff800 {
848 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
849 reg = <0xfffff800 0x100>;
850 interrupts = <9 4 1>;
851 #gpio-cells = <2>;
852 gpio-controller;
853 interrupt-controller;
854 #interrupt-cells = <2>;
855 };
856
857 pioE: gpio@fffffa00 {
858 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
859 reg = <0xfffffa00 0x100>;
860 interrupts = <10 4 1>;
861 #gpio-cells = <2>;
862 gpio-controller;
863 interrupt-controller;
864 #interrupt-cells = <2>;
865 };
655ff266
LD		 866 };
867
868 pmc: pmc@fffffc00 {
869 compatible = "atmel,at91rm9200-pmc";
870 reg = <0xfffffc00 0x120>;
871 };
872
873 rstc@fffffe00 {
874 compatible = "atmel,at91sam9g45-rstc";
875 reg = <0xfffffe00 0x10>;
876 };
877
878 pit: timer@fffffe30 {
879 compatible = "atmel,at91sam9260-pit";
880 reg = <0xfffffe30 0xf>;
881 interrupts = <3 4 5>;
882 };
883
884 watchdog@fffffe40 {
885 compatible = "atmel,at91sam9260-wdt";
886 reg = <0xfffffe40 0x10>;
887 status = "disabled";
888 };
889
890 rtc@fffffeb0 {
891 compatible = "atmel,at91rm9200-rtc";
892 reg = <0xfffffeb0 0x30>;
893 interrupts = <1 4 7>;
894 };
895 };
896
897 usb0: gadget@00500000 {
898 #address-cells = <1>;
899 #size-cells = <0>;
900 compatible = "atmel,at91sam9rl-udc";
901 reg = <0x00500000 0x100000
902 0xf8030000 0x4000>;
903 interrupts = <33 4 2>;
904 status = "disabled";
905
906 ep0 {
907 reg = <0>;
908 atmel,fifo-size = <64>;
909 atmel,nb-banks = <1>;
910 };
911
912 ep1 {
913 reg = <1>;
914 atmel,fifo-size = <1024>;
915 atmel,nb-banks = <3>;
916 atmel,can-dma;
917 atmel,can-isoc;
918 };
919
920 ep2 {
921 reg = <2>;
922 atmel,fifo-size = <1024>;
923 atmel,nb-banks = <3>;
924 atmel,can-dma;
925 atmel,can-isoc;
926 };
927
928 ep3 {
929 reg = <3>;
930 atmel,fifo-size = <1024>;
931 atmel,nb-banks = <2>;
932 atmel,can-dma;
933 };
934
935 ep4 {
936 reg = <4>;
937 atmel,fifo-size = <1024>;
938 atmel,nb-banks = <2>;
939 atmel,can-dma;
940 };
941
942 ep5 {
943 reg = <5>;
944 atmel,fifo-size = <1024>;
945 atmel,nb-banks = <2>;
946 atmel,can-dma;
947 };
948
949 ep6 {
950 reg = <6>;
951 atmel,fifo-size = <1024>;
952 atmel,nb-banks = <2>;
953 atmel,can-dma;
954 };
955
956 ep7 {
957 reg = <7>;
958 atmel,fifo-size = <1024>;
959 atmel,nb-banks = <2>;
960 atmel,can-dma;
961 };
962
963 ep8 {
964 reg = <8>;
965 atmel,fifo-size = <1024>;
966 atmel,nb-banks = <2>;
967 };
968
969 ep9 {
970 reg = <9>;
971 atmel,fifo-size = <1024>;
972 atmel,nb-banks = <2>;
973 };
974
975 ep10 {
976 reg = <10>;
977 atmel,fifo-size = <1024>;
978 atmel,nb-banks = <2>;
979 };
980
981 ep11 {
982 reg = <11>;
983 atmel,fifo-size = <1024>;
984 atmel,nb-banks = <2>;
985 };
986
987 ep12 {
988 reg = <12>;
989 atmel,fifo-size = <1024>;
990 atmel,nb-banks = <2>;
991 };
992
993 ep13 {
994 reg = <13>;
995 atmel,fifo-size = <1024>;
996 atmel,nb-banks = <2>;
997 };
998
999 ep14 {
1000 reg = <14>;
1001 atmel,fifo-size = <1024>;
1002 atmel,nb-banks = <2>;
1003 };
1004
1005 ep15 {
1006 reg = <15>;
1007 atmel,fifo-size = <1024>;
1008 atmel,nb-banks = <2>;
1009 };
1010 };
1011
1012 usb1: ohci@00600000 {
1013 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1014 reg = <0x00600000 0x100000>;
1015 interrupts = <32 4 2>;
1016 status = "disabled";
1017 };
1018
1019 usb2: ehci@00700000 {
1020 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1021 reg = <0x00700000 0x100000>;
1022 interrupts = <32 4 2>;
1023 status = "disabled";
1024 };
1025
1026 nand0: nand@60000000 {
1027 compatible = "atmel,at91rm9200-nand";
1028 #address-cells = <1>;
1029 #size-cells = <1>;
1030 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1031 0xffffc070 0x00000490 /* SMC PMECC regs */
1032 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
1033 0x00100000 0x00100000 /* ROM code */
1034 0x70000000 0x10000000 /* NFC Command Registers */
1035 0xffffc000 0x00000070 /* NFC HSMC regs */
1036 0x00200000 0x00100000 /* NFC SRAM banks */
1037 >;
1038 interrupts = <5 4 6>;
1039 atmel,nand-addr-offset = <21>;
1040 atmel,nand-cmd-offset = <22>;
1041 pinctrl-names = "default";
1042 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1043 atmel,pmecc-lookup-table-offset = <0x10000 0x18000>;
1044 status = "disabled";
1045 };
1046 };
1047};
Linux kernel - Deliverables
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