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ARM: at91/dt: at91sam9x5: remove useless adc properties
[deliverable/linux.git] / arch / arm / boot / dts / sama5d3.dtsi
CommitLineData
655ff266
LD		 1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
b32313c6 3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
655ff266
LD		 4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
6db64d29 11#include "skeleton.dtsi"
d4ae89c8 12#include <dt-bindings/dma/at91.h>
c9d0f317 13#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 14#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 15#include <dt-bindings/gpio/gpio.h>
d2e8190b 16#include <dt-bindings/clk/at91.h>
655ff266
LD		 17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 gpio4 = &pioE;
34 tcb0 = &tcb0;
655ff266
LD		 35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 ssc0 = &ssc0;
39 ssc1 = &ssc1;
f3ab0527 40 pwm0 = &pwm0;
655ff266
LD		 41 };
42 cpus {
8b2efa89
AB		 43 #address-cells = <1>;
44 #size-cells = <0>;
655ff266 45 cpu@0 {
e757a6ee 46 device_type = "cpu";
655ff266 47 compatible = "arm,cortex-a5";
e757a6ee 48 reg = <0x0>;
655ff266
LD		 49 };
50 };
51
d9da9778
AB		 52 pmu {
53 compatible = "arm,cortex-a5-pmu";
54 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
55 };
56
655ff266
LD		 57 memory {
58 reg = <0x20000000 0x8000000>;
59 };
60
d2e8190b
BB		 61 clocks {
62 adc_op_clk: adc_op_clk{
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <20000000>;
66 };
67 };
68
655ff266
LD		 69 ahb {
70 compatible = "simple-bus";
71 #address-cells = <1>;
72 #size-cells = <1>;
73 ranges;
74
75 apb {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80
81 mmc0: mmc@f0000000 {
82 compatible = "atmel,hsmci";
83 reg = <0xf0000000 0x600>;
5e8b3bc3 84 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 85 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 86 dma-names = "rxtx";
655ff266
LD		 87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
89 status = "disabled";
90 #address-cells = <1>;
91 #size-cells = <0>;
d2e8190b
BB		 92 clocks = <&mci0_clk>;
93 clock-names = "mci_clk";
655ff266
LD		 94 };
95
96 spi0: spi@f0004000 {
97 #address-cells = <1>;
98 #size-cells = <0>;
b7ef678e 99 compatible = "atmel,at91rm9200-spi";
655ff266 100 reg = <0xf0004000 0x100>;
5e8b3bc3 101 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 102 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
103 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
104 dma-names = "tx", "rx";
655ff266
LD		 105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_spi0>;
d2e8190b
BB		 107 clocks = <&spi0_clk>;
108 clock-names = "spi_clk";
655ff266
LD		 109 status = "disabled";
110 };
111
112 ssc0: ssc@f0008000 {
113 compatible = "atmel,at91sam9g45-ssc";
114 reg = <0xf0008000 0x4000>;
5e8b3bc3 115 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
655ff266
LD		 116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
d2e8190b
BB		 118 clocks = <&ssc0_clk>;
119 clock-names = "pclk";
655ff266
LD		 120 status = "disabled";
121 };
122
655ff266
LD		 123 tcb0: timer@f0010000 {
124 compatible = "atmel,at91sam9x5-tcb";
125 reg = <0xf0010000 0x100>;
5e8b3bc3 126 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
d2e8190b
BB		 127 clocks = <&tcb0_clk>;
128 clock-names = "t0_clk";
655ff266
LD		 129 };
130
131 i2c0: i2c@f0014000 {
132 compatible = "atmel,at91sam9x5-i2c";
133 reg = <0xf0014000 0x4000>;
5e8b3bc3 134 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 135 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
136 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
d9a63a45 137 dma-names = "tx", "rx";
655ff266
LD		 138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_i2c0>;
140 #address-cells = <1>;
141 #size-cells = <0>;
d2e8190b 142 clocks = <&twi0_clk>;
655ff266
LD		 143 status = "disabled";
144 };
145
146 i2c1: i2c@f0018000 {
147 compatible = "atmel,at91sam9x5-i2c";
148 reg = <0xf0018000 0x4000>;
5e8b3bc3 149 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 150 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
151 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
d9a63a45 152 dma-names = "tx", "rx";
655ff266
LD		 153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_i2c1>;
155 #address-cells = <1>;
156 #size-cells = <0>;
d2e8190b 157 clocks = <&twi1_clk>;
655ff266
LD		 158 status = "disabled";
159 };
160
161 usart0: serial@f001c000 {
162 compatible = "atmel,at91sam9260-usart";
163 reg = <0xf001c000 0x100>;
5e8b3bc3 164 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_usart0>;
d2e8190b
BB		 167 clocks = <&usart0_clk>;
168 clock-names = "usart";
655ff266
LD		 169 status = "disabled";
170 };
171
172 usart1: serial@f0020000 {
173 compatible = "atmel,at91sam9260-usart";
174 reg = <0xf0020000 0x100>;
5e8b3bc3 175 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_usart1>;
d2e8190b
BB		 178 clocks = <&usart1_clk>;
179 clock-names = "usart";
655ff266
LD		 180 status = "disabled";
181 };
182
f3ab0527
BS		 183 pwm0: pwm@f002c000 {
184 compatible = "atmel,sama5d3-pwm";
185 reg = <0xf002c000 0x300>;
186 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
187 #pwm-cells = <3>;
188 clocks = <&pwm_clk>;
189 status = "disabled";
190 };
655ff266 191
655ff266
LD		 192 isi: isi@f0034000 {
193 compatible = "atmel,at91sam9g45-isi";
194 reg = <0xf0034000 0x4000>;
5e8b3bc3 195 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 196 status = "disabled";
197 };
198
199 mmc1: mmc@f8000000 {
200 compatible = "atmel,hsmci";
201 reg = <0xf8000000 0x600>;
5e8b3bc3 202 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 203 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 204 dma-names = "rxtx";
655ff266
LD		 205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
207 status = "disabled";
208 #address-cells = <1>;
209 #size-cells = <0>;
d2e8190b
BB		 210 clocks = <&mci1_clk>;
211 clock-names = "mci_clk";
655ff266
LD		 212 };
213
655ff266
LD		 214 spi1: spi@f8008000 {
215 #address-cells = <1>;
216 #size-cells = <0>;
b7ef678e 217 compatible = "atmel,at91rm9200-spi";
655ff266 218 reg = <0xf8008000 0x100>;
5e8b3bc3 219 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 220 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
221 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
222 dma-names = "tx", "rx";
655ff266
LD		 223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_spi1>;
d2e8190b
BB		 225 clocks = <&spi1_clk>;
226 clock-names = "spi_clk";
655ff266
LD		 227 status = "disabled";
228 };
229
230 ssc1: ssc@f800c000 {
231 compatible = "atmel,at91sam9g45-ssc";
232 reg = <0xf800c000 0x4000>;
5e8b3bc3 233 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
655ff266
LD		 234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
d2e8190b
BB		 236 clocks = <&ssc1_clk>;
237 clock-names = "pclk";
655ff266
LD		 238 status = "disabled";
239 };
240
655ff266 241 adc0: adc@f8018000 {
9879b96d 242 compatible = "atmel,at91sam9x5-adc";
655ff266 243 reg = <0xf8018000 0x100>;
5e8b3bc3 244 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 245 pinctrl-names = "default";
246 pinctrl-0 = <
247 &pinctrl_adc0_adtrg
248 &pinctrl_adc0_ad0
249 &pinctrl_adc0_ad1
250 &pinctrl_adc0_ad2
251 &pinctrl_adc0_ad3
252 &pinctrl_adc0_ad4
253 &pinctrl_adc0_ad5
254 &pinctrl_adc0_ad6
255 &pinctrl_adc0_ad7
256 &pinctrl_adc0_ad8
257 &pinctrl_adc0_ad9
258 &pinctrl_adc0_ad10
259 &pinctrl_adc0_ad11
260 >;
d2e8190b
BB		 261 clocks = <&adc_clk>,
262 <&adc_op_clk>;
263 clock-names = "adc_clk", "adc_op_clk";
655ff266
LD		 264 atmel,adc-channel-base = <0x50>;
265 atmel,adc-channels-used = <0xfff>;
266 atmel,adc-drdy-mask = <0x1000000>;
267 atmel,adc-num-channels = <12>;
268 atmel,adc-startup-time = <40>;
269 atmel,adc-status-register = <0x30>;
270 atmel,adc-trigger-register = <0xc0>;
271 atmel,adc-use-external;
272 atmel,adc-vref = <3000>;
273 atmel,adc-res = <10 12>;
274 atmel,adc-res-names = "lowres", "highres";
275 status = "disabled";
276
277 trigger@0 {
278 trigger-name = "external-rising";
279 trigger-value = <0x1>;
280 trigger-external;
281 };
282 trigger@1 {
283 trigger-name = "external-falling";
284 trigger-value = <0x2>;
285 trigger-external;
286 };
287 trigger@2 {
288 trigger-name = "external-any";
289 trigger-value = <0x3>;
290 trigger-external;
291 };
292 trigger@3 {
293 trigger-name = "continuous";
294 trigger-value = <0x6>;
295 };
296 };
297
655ff266
LD		 298 i2c2: i2c@f801c000 {
299 compatible = "atmel,at91sam9x5-i2c";
300 reg = <0xf801c000 0x4000>;
5e8b3bc3 301 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 302 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
303 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
d9a63a45 304 dma-names = "tx", "rx";
557844ec
NF		 305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_i2c2>;
655ff266
LD		 307 #address-cells = <1>;
308 #size-cells = <0>;
d2e8190b 309 clocks = <&twi2_clk>;
655ff266
LD		 310 status = "disabled";
311 };
312
313 usart2: serial@f8020000 {
314 compatible = "atmel,at91sam9260-usart";
315 reg = <0xf8020000 0x100>;
5e8b3bc3 316 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_usart2>;
d2e8190b
BB		 319 clocks = <&usart2_clk>;
320 clock-names = "usart";
655ff266
LD		 321 status = "disabled";
322 };
323
324 usart3: serial@f8024000 {
325 compatible = "atmel,at91sam9260-usart";
326 reg = <0xf8024000 0x100>;
5e8b3bc3 327 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_usart3>;
d2e8190b
BB		 330 clocks = <&usart3_clk>;
331 clock-names = "usart";
655ff266
LD		 332 status = "disabled";
333 };
334
655ff266 335 sha@f8034000 {
c76f266d 336 compatible = "atmel,at91sam9g46-sha";
655ff266 337 reg = <0xf8034000 0x100>;
5e8b3bc3 338 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 339 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
340 dma-names = "tx";
4df4f446
BB		 341 clocks = <&sha_clk>;
342 clock-names = "sha_clk";
655ff266
LD		 343 };
344
345 aes@f8038000 {
c76f266d 346 compatible = "atmel,at91sam9g46-aes";
655ff266 347 reg = <0xf8038000 0x100>;
07f7d503 348 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 349 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
350 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
351 dma-names = "tx", "rx";
f68cd356
BB		 352 clocks = <&aes_clk>;
353 clock-names = "aes_clk";
655ff266
LD		 354 };
355
356 tdes@f803c000 {
c76f266d 357 compatible = "atmel,at91sam9g46-tdes";
655ff266 358 reg = <0xf803c000 0x100>;
5e8b3bc3 359 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 360 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
361 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
362 dma-names = "tx", "rx";
45e5c2cb
BB		 363 clocks = <&tdes_clk>;
364 clock-names = "tdes_clk";
655ff266
LD		 365 };
366
367 dma0: dma-controller@ffffe600 {
368 compatible = "atmel,at91sam9g45-dma";
369 reg = <0xffffe600 0x200>;
5e8b3bc3 370 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 371 #dma-cells = <2>;
d2e8190b
BB		 372 clocks = <&dma0_clk>;
373 clock-names = "dma_clk";
655ff266
LD		 374 };
375
376 dma1: dma-controller@ffffe800 {
377 compatible = "atmel,at91sam9g45-dma";
378 reg = <0xffffe800 0x200>;
5e8b3bc3 379 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 380 #dma-cells = <2>;
d2e8190b
BB		 381 clocks = <&dma1_clk>;
382 clock-names = "dma_clk";
655ff266
LD		 383 };
384
385 ramc0: ramc@ffffea00 {
386 compatible = "atmel,at91sam9g45-ddramc";
387 reg = <0xffffea00 0x200>;
388 };
389
390 dbgu: serial@ffffee00 {
391 compatible = "atmel,at91sam9260-usart";
392 reg = <0xffffee00 0x200>;
5e8b3bc3 393 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_dbgu>;
d2e8190b
BB		 396 clocks = <&dbgu_clk>;
397 clock-names = "usart";
655ff266
LD		 398 status = "disabled";
399 };
400
401 aic: interrupt-controller@fffff000 {
402 #interrupt-cells = <3>;
403 compatible = "atmel,sama5d3-aic";
404 interrupt-controller;
405 reg = <0xfffff000 0x200>;
406 atmel,external-irqs = <47>;
407 };
408
409 pinctrl@fffff200 {
410 #address-cells = <1>;
411 #size-cells = <1>;
412 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
413 ranges = <0xfffff200 0xfffff200 0xa00>;
414 atmel,mux-mask = <
415 /* A B C */
416 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
417 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
418 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
419 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
420 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
421 >;
422
423 /* shared pinctrl settings */
424 adc0 {
425 pinctrl_adc0_adtrg: adc0_adtrg {
426 atmel,pins =
c9d0f317 427 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
655ff266
LD		 428 };
429 pinctrl_adc0_ad0: adc0_ad0 {
430 atmel,pins =
c9d0f317 431 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
655ff266
LD		 432 };
433 pinctrl_adc0_ad1: adc0_ad1 {
434 atmel,pins =
c9d0f317 435 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
655ff266
LD		 436 };
437 pinctrl_adc0_ad2: adc0_ad2 {
438 atmel,pins =
c9d0f317 439 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
655ff266
LD		 440 };
441 pinctrl_adc0_ad3: adc0_ad3 {
442 atmel,pins =
c9d0f317 443 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
655ff266
LD		 444 };
445 pinctrl_adc0_ad4: adc0_ad4 {
446 atmel,pins =
c9d0f317 447 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
655ff266
LD		 448 };
449 pinctrl_adc0_ad5: adc0_ad5 {
450 atmel,pins =
c9d0f317 451 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
655ff266
LD		 452 };
453 pinctrl_adc0_ad6: adc0_ad6 {
454 atmel,pins =
c9d0f317 455 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
655ff266
LD		 456 };
457 pinctrl_adc0_ad7: adc0_ad7 {
458 atmel,pins =
c9d0f317 459 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
655ff266
LD		 460 };
461 pinctrl_adc0_ad8: adc0_ad8 {
462 atmel,pins =
c9d0f317 463 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
655ff266
LD		 464 };
465 pinctrl_adc0_ad9: adc0_ad9 {
466 atmel,pins =
c9d0f317 467 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
655ff266
LD		 468 };
469 pinctrl_adc0_ad10: adc0_ad10 {
470 atmel,pins =
c9d0f317 471 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
655ff266
LD		 472 };
473 pinctrl_adc0_ad11: adc0_ad11 {
474 atmel,pins =
c9d0f317 475 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
655ff266
LD		 476 };
477 };
478
655ff266
LD		 479 dbgu {
480 pinctrl_dbgu: dbgu-0 {
481 atmel,pins =
c9d0f317
JCPV		 482 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
483 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
655ff266
LD		 484 };
485 };
486
487 i2c0 {
488 pinctrl_i2c0: i2c0-0 {
489 atmel,pins =
c9d0f317
JCPV		 490 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
491 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
655ff266
LD		 492 };
493 };
494
495 i2c1 {
496 pinctrl_i2c1: i2c1-0 {
497 atmel,pins =
c9d0f317
JCPV		 498 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
499 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
655ff266
LD		 500 };
501 };
502
557844ec
NF		 503 i2c2 {
504 pinctrl_i2c2: i2c2-0 {
505 atmel,pins =
506 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
507 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
508 };
509 };
510
655ff266
LD		 511 isi {
512 pinctrl_isi: isi-0 {
513 atmel,pins =
c9d0f317
JCPV		 514 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
515 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
516 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
517 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
518 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
519 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
520 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
521 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
522 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
523 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
524 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
525 AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
526 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
655ff266
LD		 527 };
528 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
529 atmel,pins =
c9d0f317 530 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
655ff266
LD		 531 };
532 };
533
655ff266
LD		 534 mmc0 {
535 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
536 atmel,pins =
c9d0f317
JCPV		 537 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
538 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
539 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
655ff266
LD		 540 };
541 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
542 atmel,pins =
c9d0f317
JCPV		 543 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
544 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
545 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
655ff266
LD		 546 };
547 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
548 atmel,pins =
c9d0f317
JCPV		 549 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
550 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
551 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
552 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
655ff266
LD		 553 };
554 };
555
556 mmc1 {
557 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
558 atmel,pins =
c9d0f317
JCPV		 559 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
560 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
561 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
655ff266
LD		 562 };
563 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
564 atmel,pins =
c9d0f317
JCPV		 565 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
566 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
567 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
655ff266
LD		 568 };
569 };
570
655ff266
LD		 571 nand0 {
572 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
573 atmel,pins =
c9d0f317
JCPV		 574 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
575 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
655ff266
LD		 576 };
577 };
578
655ff266
LD		 579 spi0 {
580 pinctrl_spi0: spi0-0 {
581 atmel,pins =
c9d0f317
JCPV		 582 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
583 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
584 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
655ff266
LD		 585 };
586 };
587
588 spi1 {
589 pinctrl_spi1: spi1-0 {
590 atmel,pins =
c9d0f317
JCPV		 591 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
592 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
593 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
655ff266
LD		 594 };
595 };
596
597 ssc0 {
598 pinctrl_ssc0_tx: ssc0_tx {
599 atmel,pins =
c9d0f317
JCPV		 600 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
601 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
602 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
655ff266
LD		 603 };
604
605 pinctrl_ssc0_rx: ssc0_rx {
606 atmel,pins =
c9d0f317
JCPV		 607 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
608 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
609 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
655ff266
LD		 610 };
611 };
612
613 ssc1 {
614 pinctrl_ssc1_tx: ssc1_tx {
615 atmel,pins =
c9d0f317
JCPV		 616 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
617 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
618 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
655ff266
LD		 619 };
620
621 pinctrl_ssc1_rx: ssc1_rx {
622 atmel,pins =
c9d0f317
JCPV		 623 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
624 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
625 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
655ff266
LD		 626 };
627 };
628
655ff266
LD		 629 usart0 {
630 pinctrl_usart0: usart0-0 {
631 atmel,pins =
c9d0f317
JCPV		 632 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
633 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
655ff266
LD		 634 };
635
636 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
637 atmel,pins =
c9d0f317
JCPV		 638 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
639 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
655ff266
LD		 640 };
641 };
642
643 usart1 {
644 pinctrl_usart1: usart1-0 {
645 atmel,pins =
c9d0f317
JCPV		 646 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
647 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
655ff266
LD		 648 };
649
650 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
651 atmel,pins =
c9d0f317
JCPV		 652 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
653 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
655ff266
LD		 654 };
655 };
656
657 usart2 {
658 pinctrl_usart2: usart2-0 {
659 atmel,pins =
c9d0f317
JCPV		 660 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
661 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
655ff266
LD		 662 };
663
664 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
665 atmel,pins =
c9d0f317
JCPV		 666 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
667 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
655ff266
LD		 668 };
669 };
670
671 usart3 {
672 pinctrl_usart3: usart3-0 {
673 atmel,pins =
c9d0f317
JCPV		 674 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
675 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
655ff266
LD		 676 };
677
678 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
679 atmel,pins =
c9d0f317
JCPV		 680 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
681 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
655ff266
LD		 682 };
683 };
c9d0f317
JCPV		 684
685
686 pioA: gpio@fffff200 {
687 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
688 reg = <0xfffff200 0x100>;
5e8b3bc3 689 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 690 #gpio-cells = <2>;
691 gpio-controller;
692 interrupt-controller;
693 #interrupt-cells = <2>;
d2e8190b 694 clocks = <&pioA_clk>;
c9d0f317
JCPV		 695 };
696
697 pioB: gpio@fffff400 {
698 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
699 reg = <0xfffff400 0x100>;
5e8b3bc3 700 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 701 #gpio-cells = <2>;
702 gpio-controller;
703 interrupt-controller;
704 #interrupt-cells = <2>;
d2e8190b 705 clocks = <&pioB_clk>;
c9d0f317
JCPV		 706 };
707
708 pioC: gpio@fffff600 {
709 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
710 reg = <0xfffff600 0x100>;
5e8b3bc3 711 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 712 #gpio-cells = <2>;
713 gpio-controller;
714 interrupt-controller;
715 #interrupt-cells = <2>;
d2e8190b 716 clocks = <&pioC_clk>;
c9d0f317
JCPV		 717 };
718
719 pioD: gpio@fffff800 {
720 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
721 reg = <0xfffff800 0x100>;
5e8b3bc3 722 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 723 #gpio-cells = <2>;
724 gpio-controller;
725 interrupt-controller;
726 #interrupt-cells = <2>;
d2e8190b 727 clocks = <&pioD_clk>;
c9d0f317
JCPV		 728 };
729
730 pioE: gpio@fffffa00 {
731 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
732 reg = <0xfffffa00 0x100>;
5e8b3bc3 733 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 734 #gpio-cells = <2>;
735 gpio-controller;
736 interrupt-controller;
737 #interrupt-cells = <2>;
d2e8190b 738 clocks = <&pioE_clk>;
c9d0f317 739 };
655ff266
LD		 740 };
741
742 pmc: pmc@fffffc00 {
d2e8190b 743 compatible = "atmel,sama5d3-pmc";
655ff266 744 reg = <0xfffffc00 0x120>;
d2e8190b
BB		 745 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
746 interrupt-controller;
747 #address-cells = <1>;
748 #size-cells = <0>;
749 #interrupt-cells = <1>;
750
751 clk32k: slck {
752 compatible = "fixed-clock";
753 #clock-cells = <0>;
754 clock-frequency = <32768>;
755 };
756
757 main: mainck {
758 compatible = "atmel,at91rm9200-clk-main";
759 #clock-cells = <0>;
760 interrupt-parent = <&pmc>;
761 interrupts = <AT91_PMC_MOSCS>;
762 clocks = <&clk32k>;
763 };
764
765 plla: pllack {
766 compatible = "atmel,sama5d3-clk-pll";
767 #clock-cells = <0>;
768 interrupt-parent = <&pmc>;
769 interrupts = <AT91_PMC_LOCKA>;
770 clocks = <&main>;
771 reg = <0>;
772 atmel,clk-input-range = <8000000 50000000>;
773 #atmel,pll-clk-output-range-cells = <4>;
774 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
775 };
776
777 plladiv: plladivck {
778 compatible = "atmel,at91sam9x5-clk-plldiv";
779 #clock-cells = <0>;
780 clocks = <&plla>;
781 };
782
783 utmi: utmick {
784 compatible = "atmel,at91sam9x5-clk-utmi";
785 #clock-cells = <0>;
786 interrupt-parent = <&pmc>;
787 interrupts = <AT91_PMC_LOCKU>;
788 clocks = <&main>;
789 };
790
791 mck: masterck {
792 compatible = "atmel,at91sam9x5-clk-master";
793 #clock-cells = <0>;
794 interrupt-parent = <&pmc>;
795 interrupts = <AT91_PMC_MCKRDY>;
796 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
797 atmel,clk-output-range = <0 166000000>;
798 atmel,clk-divisors = <1 2 4 3>;
799 };
800
801 usb: usbck {
802 compatible = "atmel,at91sam9x5-clk-usb";
803 #clock-cells = <0>;
804 clocks = <&plladiv>, <&utmi>;
805 };
806
807 prog: progck {
808 compatible = "atmel,at91sam9x5-clk-programmable";
809 #address-cells = <1>;
810 #size-cells = <0>;
811 interrupt-parent = <&pmc>;
812 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
813
814 prog0: prog0 {
815 #clock-cells = <0>;
816 reg = <0>;
817 interrupts = <AT91_PMC_PCKRDY(0)>;
818 };
819
820 prog1: prog1 {
821 #clock-cells = <0>;
822 reg = <1>;
823 interrupts = <AT91_PMC_PCKRDY(1)>;
824 };
825
826 prog2: prog2 {
827 #clock-cells = <0>;
828 reg = <2>;
829 interrupts = <AT91_PMC_PCKRDY(2)>;
830 };
831 };
832
833 smd: smdclk {
834 compatible = "atmel,at91sam9x5-clk-smd";
835 #clock-cells = <0>;
836 clocks = <&plladiv>, <&utmi>;
837 };
838
839 systemck {
840 compatible = "atmel,at91rm9200-clk-system";
841 #address-cells = <1>;
842 #size-cells = <0>;
843
844 ddrck: ddrck {
845 #clock-cells = <0>;
846 reg = <2>;
847 clocks = <&mck>;
848 };
849
850 smdck: smdck {
851 #clock-cells = <0>;
852 reg = <4>;
853 clocks = <&smd>;
854 };
855
856 uhpck: uhpck {
857 #clock-cells = <0>;
858 reg = <6>;
859 clocks = <&usb>;
860 };
861
862 udpck: udpck {
863 #clock-cells = <0>;
864 reg = <7>;
865 clocks = <&usb>;
866 };
867
868 pck0: pck0 {
869 #clock-cells = <0>;
870 reg = <8>;
871 clocks = <&prog0>;
872 };
873
874 pck1: pck1 {
875 #clock-cells = <0>;
876 reg = <9>;
877 clocks = <&prog1>;
878 };
879
880 pck2: pck2 {
881 #clock-cells = <0>;
882 reg = <10>;
883 clocks = <&prog2>;
884 };
885 };
886
887 periphck {
888 compatible = "atmel,at91sam9x5-clk-peripheral";
889 #address-cells = <1>;
890 #size-cells = <0>;
891 clocks = <&mck>;
892
893 dbgu_clk: dbgu_clk {
894 #clock-cells = <0>;
895 reg = <2>;
896 };
897
898 pioA_clk: pioA_clk {
899 #clock-cells = <0>;
900 reg = <6>;
901 };
902
903 pioB_clk: pioB_clk {
904 #clock-cells = <0>;
905 reg = <7>;
906 };
907
908 pioC_clk: pioC_clk {
909 #clock-cells = <0>;
910 reg = <8>;
911 };
912
913 pioD_clk: pioD_clk {
914 #clock-cells = <0>;
915 reg = <9>;
916 };
917
918 pioE_clk: pioE_clk {
919 #clock-cells = <0>;
920 reg = <10>;
921 };
922
923 usart0_clk: usart0_clk {
924 #clock-cells = <0>;
925 reg = <12>;
926 atmel,clk-output-range = <0 66000000>;
927 };
928
929 usart1_clk: usart1_clk {
930 #clock-cells = <0>;
931 reg = <13>;
932 atmel,clk-output-range = <0 66000000>;
933 };
934
935 usart2_clk: usart2_clk {
936 #clock-cells = <0>;
937 reg = <14>;
938 atmel,clk-output-range = <0 66000000>;
939 };
940
941 usart3_clk: usart3_clk {
942 #clock-cells = <0>;
943 reg = <15>;
944 atmel,clk-output-range = <0 66000000>;
945 };
946
947 twi0_clk: twi0_clk {
948 reg = <18>;
949 #clock-cells = <0>;
950 atmel,clk-output-range = <0 16625000>;
951 };
952
953 twi1_clk: twi1_clk {
954 #clock-cells = <0>;
955 reg = <19>;
956 atmel,clk-output-range = <0 16625000>;
957 };
958
959 twi2_clk: twi2_clk {
960 #clock-cells = <0>;
961 reg = <20>;
962 atmel,clk-output-range = <0 16625000>;
963 };
964
965 mci0_clk: mci0_clk {
966 #clock-cells = <0>;
967 reg = <21>;
968 };
969
970 mci1_clk: mci1_clk {
971 #clock-cells = <0>;
972 reg = <22>;
973 };
974
975 spi0_clk: spi0_clk {
976 #clock-cells = <0>;
977 reg = <24>;
978 atmel,clk-output-range = <0 133000000>;
979 };
980
981 spi1_clk: spi1_clk {
982 #clock-cells = <0>;
983 reg = <25>;
984 atmel,clk-output-range = <0 133000000>;
985 };
986
987 tcb0_clk: tcb0_clk {
988 #clock-cells = <0>;
989 reg = <26>;
990 atmel,clk-output-range = <0 133000000>;
991 };
992
993 pwm_clk: pwm_clk {
994 #clock-cells = <0>;
995 reg = <28>;
996 };
997
998 adc_clk: adc_clk {
999 #clock-cells = <0>;
1000 reg = <29>;
1001 atmel,clk-output-range = <0 66000000>;
1002 };
1003
1004 dma0_clk: dma0_clk {
1005 #clock-cells = <0>;
1006 reg = <30>;
1007 };
1008
1009 dma1_clk: dma1_clk {
1010 #clock-cells = <0>;
1011 reg = <31>;
1012 };
1013
1014 uhphs_clk: uhphs_clk {
1015 #clock-cells = <0>;
1016 reg = <32>;
1017 };
1018
1019 udphs_clk: udphs_clk {
1020 #clock-cells = <0>;
1021 reg = <33>;
1022 };
1023
1024 isi_clk: isi_clk {
1025 #clock-cells = <0>;
1026 reg = <37>;
1027 };
1028
1029 ssc0_clk: ssc0_clk {
1030 #clock-cells = <0>;
1031 reg = <38>;
1032 atmel,clk-output-range = <0 66000000>;
1033 };
1034
1035 ssc1_clk: ssc1_clk {
1036 #clock-cells = <0>;
1037 reg = <39>;
1038 atmel,clk-output-range = <0 66000000>;
1039 };
1040
1041 sha_clk: sha_clk {
1042 #clock-cells = <0>;
1043 reg = <42>;
1044 };
1045
1046 aes_clk: aes_clk {
1047 #clock-cells = <0>;
1048 reg = <43>;
1049 };
1050
1051 tdes_clk: tdes_clk {
1052 #clock-cells = <0>;
1053 reg = <44>;
1054 };
1055
1056 trng_clk: trng_clk {
1057 #clock-cells = <0>;
1058 reg = <45>;
1059 };
1060
1061 fuse_clk: fuse_clk {
1062 #clock-cells = <0>;
1063 reg = <48>;
1064 };
1065 };
655ff266
LD		 1066 };
1067
1068 rstc@fffffe00 {
1069 compatible = "atmel,at91sam9g45-rstc";
1070 reg = <0xfffffe00 0x10>;
1071 };
1072
1073 pit: timer@fffffe30 {
1074 compatible = "atmel,at91sam9260-pit";
1075 reg = <0xfffffe30 0xf>;
5e8b3bc3 1076 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
d2e8190b 1077 clocks = <&mck>;
655ff266
LD		 1078 };
1079
1080 watchdog@fffffe40 {
1081 compatible = "atmel,at91sam9260-wdt";
1082 reg = <0xfffffe40 0x10>;
fe46aa67
BB		 1083 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1084 atmel,watchdog-type = "hardware";
1085 atmel,reset-type = "all";
1086 atmel,dbg-halt;
1087 atmel,idle-halt;
655ff266
LD		 1088 status = "disabled";
1089 };
1090
1091 rtc@fffffeb0 {
1092 compatible = "atmel,at91rm9200-rtc";
1093 reg = <0xfffffeb0 0x30>;
5e8b3bc3 1094 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 1095 };
1096 };
1097
1098 usb0: gadget@00500000 {
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1101 compatible = "atmel,at91sam9rl-udc";
1102 reg = <0x00500000 0x100000
1103 0xf8030000 0x4000>;
5e8b3bc3 1104 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1105 clocks = <&udphs_clk>, <&utmi>;
1106 clock-names = "pclk", "hclk";
655ff266
LD		 1107 status = "disabled";
1108
1109 ep0 {
1110 reg = <0>;
1111 atmel,fifo-size = <64>;
1112 atmel,nb-banks = <1>;
1113 };
1114
1115 ep1 {
1116 reg = <1>;
1117 atmel,fifo-size = <1024>;
1118 atmel,nb-banks = <3>;
1119 atmel,can-dma;
1120 atmel,can-isoc;
1121 };
1122
1123 ep2 {
1124 reg = <2>;
1125 atmel,fifo-size = <1024>;
1126 atmel,nb-banks = <3>;
1127 atmel,can-dma;
1128 atmel,can-isoc;
1129 };
1130
1131 ep3 {
1132 reg = <3>;
1133 atmel,fifo-size = <1024>;
1134 atmel,nb-banks = <2>;
1135 atmel,can-dma;
1136 };
1137
1138 ep4 {
1139 reg = <4>;
1140 atmel,fifo-size = <1024>;
1141 atmel,nb-banks = <2>;
1142 atmel,can-dma;
1143 };
1144
1145 ep5 {
1146 reg = <5>;
1147 atmel,fifo-size = <1024>;
1148 atmel,nb-banks = <2>;
1149 atmel,can-dma;
1150 };
1151
1152 ep6 {
1153 reg = <6>;
1154 atmel,fifo-size = <1024>;
1155 atmel,nb-banks = <2>;
1156 atmel,can-dma;
1157 };
1158
1159 ep7 {
1160 reg = <7>;
1161 atmel,fifo-size = <1024>;
1162 atmel,nb-banks = <2>;
1163 atmel,can-dma;
1164 };
1165
1166 ep8 {
1167 reg = <8>;
1168 atmel,fifo-size = <1024>;
1169 atmel,nb-banks = <2>;
1170 };
1171
1172 ep9 {
1173 reg = <9>;
1174 atmel,fifo-size = <1024>;
1175 atmel,nb-banks = <2>;
1176 };
1177
1178 ep10 {
1179 reg = <10>;
1180 atmel,fifo-size = <1024>;
1181 atmel,nb-banks = <2>;
1182 };
1183
1184 ep11 {
1185 reg = <11>;
1186 atmel,fifo-size = <1024>;
1187 atmel,nb-banks = <2>;
1188 };
1189
1190 ep12 {
1191 reg = <12>;
1192 atmel,fifo-size = <1024>;
1193 atmel,nb-banks = <2>;
1194 };
1195
1196 ep13 {
1197 reg = <13>;
1198 atmel,fifo-size = <1024>;
1199 atmel,nb-banks = <2>;
1200 };
1201
1202 ep14 {
1203 reg = <14>;
1204 atmel,fifo-size = <1024>;
1205 atmel,nb-banks = <2>;
1206 };
1207
1208 ep15 {
1209 reg = <15>;
1210 atmel,fifo-size = <1024>;
1211 atmel,nb-banks = <2>;
1212 };
1213 };
1214
1215 usb1: ohci@00600000 {
1216 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1217 reg = <0x00600000 0x100000>;
5e8b3bc3 1218 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
5f877518 1219 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
d2e8190b
BB		 1220 <&uhpck>;
1221 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
655ff266
LD		 1222 status = "disabled";
1223 };
1224
1225 usb2: ehci@00700000 {
1226 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1227 reg = <0x00700000 0x100000>;
5e8b3bc3 1228 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1229 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1230 clock-names = "usb_clk", "ehci_clk", "uhpck";
655ff266
LD		 1231 status = "disabled";
1232 };
1233
1234 nand0: nand@60000000 {
1235 compatible = "atmel,at91rm9200-nand";
1236 #address-cells = <1>;
1237 #size-cells = <1>;
8ae599ef 1238 ranges;
655ff266
LD		 1239 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1240 0xffffc070 0x00000490 /* SMC PMECC regs */
1241 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
afa6a2a7 1242 0x00110000 0x00018000 /* ROM code */
655ff266 1243 >;
5e8b3bc3 1244 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
655ff266
LD		 1245 atmel,nand-addr-offset = <21>;
1246 atmel,nand-cmd-offset = <22>;
e8b2da6e 1247 atmel,nand-has-dma;
655ff266
LD		 1248 pinctrl-names = "default";
1249 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
afa6a2a7 1250 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
655ff266 1251 status = "disabled";
8ae599ef
JW		 1252
1253 nfc@70000000 {
1254 compatible = "atmel,sama5d3-nfc";
1255 #address-cells = <1>;
1256 #size-cells = <1>;
1257 reg = <
1258 0x70000000 0x10000000 /* NFC Command Registers */
1259 0xffffc000 0x00000070 /* NFC HSMC regs */
1260 0x00200000 0x00100000 /* NFC SRAM banks */
1261 >;
1262 };
655ff266
LD		 1263 };
1264 };
1265};
Linux kernel - Deliverables
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