projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7c661394 NF |
1 | /* |
| 2 | * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2014 Atmel, | |
| 5 | * 2014 Nicolas Ferre <nicolas.ferre@atmel.com> | |
| 6 | * | |
| 7 | * This file is dual-licensed: you can use it either under the terms | |
| 8 | * of the GPL or the X11 license, at your option. Note that this dual | |
| 9 | * licensing only applies to this file, and not this project as a | |
| 10 | * whole. | |
| 11 | * | |
| 1d2a0563 | 12 | * a) This file is free software; you can redistribute it and/or |
| 7c661394 NF |
13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of the | |
| 15 | * License, or (at your option) any later version. | |
| 16 | * | |
| 1d2a0563 | 17 | * This file is distributed in the hope that it will be useful, |
| 7c661394 NF |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 20 | * GNU General Public License for more details. | |
| 21 | * | |
| 22 | * Or, alternatively, | |
| 23 | * | |
| 24 | * b) Permission is hereby granted, free of charge, to any person | |
| 25 | * obtaining a copy of this software and associated documentation | |
| 26 | * files (the "Software"), to deal in the Software without | |
| 27 | * restriction, including without limitation the rights to use, | |
| 28 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 29 | * sell copies of the Software, and to permit persons to whom the | |
| 30 | * Software is furnished to do so, subject to the following | |
| 31 | * conditions: | |
| 32 | * | |
| 33 | * The above copyright notice and this permission notice shall be | |
| 34 | * included in all copies or substantial portions of the Software. | |
| 35 | * | |
| 36 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 37 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 38 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 39 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 40 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 41 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 42 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 43 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 44 | */ | |
| 45 | ||
| 46 | #include "skeleton.dtsi" | |
| 47 | #include <dt-bindings/clock/at91.h> | |
| b3c7a497 | 48 | #include <dt-bindings/dma/at91.h> |
| 7c661394 NF |
49 | #include <dt-bindings/pinctrl/at91.h> |
| 50 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 51 | #include <dt-bindings/gpio/gpio.h> | |
| 52 | ||
| 53 | / { | |
| 54 | model = "Atmel SAMA5D4 family SoC"; | |
| 55 | compatible = "atmel,sama5d4"; | |
| 56 | interrupt-parent = <&aic>; | |
| 57 | ||
| 58 | aliases { | |
| 59 | serial0 = &usart3; | |
| 60 | serial1 = &usart4; | |
| 61 | serial2 = &usart2; | |
| 62 | gpio0 = &pioA; | |
| 63 | gpio1 = &pioB; | |
| 64 | gpio2 = &pioC; | |
| 1de77b7f | 65 | gpio3 = &pioD; |
| 7c661394 | 66 | gpio4 = &pioE; |
| 0a5c5f84 | 67 | pwm0 = &pwm0; |
| 0697edd7 BS |
68 | ssc0 = &ssc0; |
| 69 | ssc1 = &ssc1; | |
| 7c661394 NF |
70 | tcb0 = &tcb0; |
| 71 | tcb1 = &tcb1; | |
| a547f60a | 72 | i2c0 = &i2c0; |
| 4cc7cdf3 | 73 | i2c1 = &i2c1; |
| 7c661394 NF |
74 | i2c2 = &i2c2; |
| 75 | }; | |
| 76 | cpus { | |
| 77 | #address-cells = <1>; | |
| 78 | #size-cells = <0>; | |
| 79 | ||
| 80 | cpu@0 { | |
| 81 | device_type = "cpu"; | |
| 82 | compatible = "arm,cortex-a5"; | |
| 83 | reg = <0>; | |
| 84 | next-level-cache = <&L2>; | |
| 85 | }; | |
| 86 | }; | |
| 87 | ||
| 88 | memory { | |
| 89 | reg = <0x20000000 0x20000000>; | |
| 90 | }; | |
| 91 | ||
| 92 | clocks { | |
| 93 | slow_xtal: slow_xtal { | |
| 94 | compatible = "fixed-clock"; | |
| 95 | #clock-cells = <0>; | |
| 96 | clock-frequency = <0>; | |
| 97 | }; | |
| 98 | ||
| 99 | main_xtal: main_xtal { | |
| 100 | compatible = "fixed-clock"; | |
| 101 | #clock-cells = <0>; | |
| 102 | clock-frequency = <0>; | |
| 103 | }; | |
| 104 | ||
| 105 | adc_op_clk: adc_op_clk{ | |
| 106 | compatible = "fixed-clock"; | |
| 107 | #clock-cells = <0>; | |
| 108 | clock-frequency = <1000000>; | |
| 109 | }; | |
| 110 | }; | |
| 111 | ||
| f04660e4 AB |
112 | ns_sram: sram@00210000 { |
| 113 | compatible = "mmio-sram"; | |
| 114 | reg = <0x00210000 0x10000>; | |
| 115 | }; | |
| 116 | ||
| 7c661394 NF |
117 | ahb { |
| 118 | compatible = "simple-bus"; | |
| 119 | #address-cells = <1>; | |
| 120 | #size-cells = <1>; | |
| 121 | ranges; | |
| 122 | ||
| 123 | usb0: gadget@00400000 { | |
| 124 | #address-cells = <1>; | |
| 125 | #size-cells = <0>; | |
| 126 | compatible = "atmel,at91sam9rl-udc"; | |
| 127 | reg = <0x00400000 0x100000 | |
| 128 | 0xfc02c000 0x4000>; | |
| 129 | interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; | |
| 130 | clocks = <&udphs_clk>, <&utmi>; | |
| 131 | clock-names = "pclk", "hclk"; | |
| 132 | status = "disabled"; | |
| 133 | ||
| 134 | ep0 { | |
| 135 | reg = <0>; | |
| 136 | atmel,fifo-size = <64>; | |
| 137 | atmel,nb-banks = <1>; | |
| 138 | }; | |
| 139 | ||
| 140 | ep1 { | |
| 141 | reg = <1>; | |
| 142 | atmel,fifo-size = <1024>; | |
| 143 | atmel,nb-banks = <3>; | |
| 144 | atmel,can-dma; | |
| 145 | atmel,can-isoc; | |
| 146 | }; | |
| 147 | ||
| 148 | ep2 { | |
| 149 | reg = <2>; | |
| 150 | atmel,fifo-size = <1024>; | |
| 151 | atmel,nb-banks = <3>; | |
| 152 | atmel,can-dma; | |
| 153 | atmel,can-isoc; | |
| 154 | }; | |
| 155 | ||
| 156 | ep3 { | |
| 157 | reg = <3>; | |
| 158 | atmel,fifo-size = <1024>; | |
| 159 | atmel,nb-banks = <2>; | |
| 160 | atmel,can-dma; | |
| 161 | atmel,can-isoc; | |
| 162 | }; | |
| 163 | ||
| 164 | ep4 { | |
| 165 | reg = <4>; | |
| 166 | atmel,fifo-size = <1024>; | |
| 167 | atmel,nb-banks = <2>; | |
| 168 | atmel,can-dma; | |
| 169 | atmel,can-isoc; | |
| 170 | }; | |
| 171 | ||
| 172 | ep5 { | |
| 173 | reg = <5>; | |
| 174 | atmel,fifo-size = <1024>; | |
| 175 | atmel,nb-banks = <2>; | |
| 176 | atmel,can-dma; | |
| 177 | atmel,can-isoc; | |
| 178 | }; | |
| 179 | ||
| 180 | ep6 { | |
| 181 | reg = <6>; | |
| 182 | atmel,fifo-size = <1024>; | |
| 183 | atmel,nb-banks = <2>; | |
| 184 | atmel,can-dma; | |
| 185 | atmel,can-isoc; | |
| 186 | }; | |
| 187 | ||
| 188 | ep7 { | |
| 189 | reg = <7>; | |
| 190 | atmel,fifo-size = <1024>; | |
| 191 | atmel,nb-banks = <2>; | |
| 192 | atmel,can-dma; | |
| 193 | atmel,can-isoc; | |
| 194 | }; | |
| 195 | ||
| 196 | ep8 { | |
| 197 | reg = <8>; | |
| 198 | atmel,fifo-size = <1024>; | |
| 199 | atmel,nb-banks = <2>; | |
| 200 | atmel,can-isoc; | |
| 201 | }; | |
| 202 | ||
| 203 | ep9 { | |
| 204 | reg = <9>; | |
| 205 | atmel,fifo-size = <1024>; | |
| 206 | atmel,nb-banks = <2>; | |
| 207 | atmel,can-isoc; | |
| 208 | }; | |
| 209 | ||
| 210 | ep10 { | |
| 211 | reg = <10>; | |
| 212 | atmel,fifo-size = <1024>; | |
| 213 | atmel,nb-banks = <2>; | |
| 214 | atmel,can-isoc; | |
| 215 | }; | |
| 216 | ||
| 217 | ep11 { | |
| 218 | reg = <11>; | |
| 219 | atmel,fifo-size = <1024>; | |
| 220 | atmel,nb-banks = <2>; | |
| 221 | atmel,can-isoc; | |
| 222 | }; | |
| 223 | ||
| 224 | ep12 { | |
| 225 | reg = <12>; | |
| 226 | atmel,fifo-size = <1024>; | |
| 227 | atmel,nb-banks = <2>; | |
| 228 | atmel,can-isoc; | |
| 229 | }; | |
| 230 | ||
| 231 | ep13 { | |
| 232 | reg = <13>; | |
| 233 | atmel,fifo-size = <1024>; | |
| 234 | atmel,nb-banks = <2>; | |
| 235 | atmel,can-isoc; | |
| 236 | }; | |
| 237 | ||
| 238 | ep14 { | |
| 239 | reg = <14>; | |
| 240 | atmel,fifo-size = <1024>; | |
| 241 | atmel,nb-banks = <2>; | |
| 242 | atmel,can-isoc; | |
| 243 | }; | |
| 244 | ||
| 245 | ep15 { | |
| 246 | reg = <15>; | |
| 247 | atmel,fifo-size = <1024>; | |
| 248 | atmel,nb-banks = <2>; | |
| 249 | atmel,can-isoc; | |
| 250 | }; | |
| 251 | }; | |
| 252 | ||
| 253 | usb1: ohci@00500000 { | |
| 254 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
| 255 | reg = <0x00500000 0x100000>; | |
| 256 | interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; | |
| 257 | clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, | |
| 258 | <&uhpck>; | |
| 259 | clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; | |
| 260 | status = "disabled"; | |
| 261 | }; | |
| 262 | ||
| 263 | usb2: ehci@00600000 { | |
| 264 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
| 265 | reg = <0x00600000 0x100000>; | |
| 266 | interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; | |
| 267 | clocks = <&usb>, <&uhphs_clk>, <&uhpck>; | |
| 268 | clock-names = "usb_clk", "ehci_clk", "uhpck"; | |
| 269 | status = "disabled"; | |
| 270 | }; | |
| 271 | ||
| 272 | L2: cache-controller@00a00000 { | |
| 273 | compatible = "arm,pl310-cache"; | |
| 274 | reg = <0x00a00000 0x1000>; | |
| 275 | interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; | |
| 276 | cache-unified; | |
| 277 | cache-level = <2>; | |
| 278 | }; | |
| 279 | ||
| 280 | nand0: nand@80000000 { | |
| fda077c0 | 281 | compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand"; |
| 7c661394 NF |
282 | #address-cells = <1>; |
| 283 | #size-cells = <1>; | |
| 284 | ranges; | |
| 285 | reg = < 0x80000000 0x08000000 /* EBI CS3 */ | |
| 286 | 0xfc05c070 0x00000490 /* SMC PMECC regs */ | |
| 287 | 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */ | |
| 288 | >; | |
| 289 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; | |
| 290 | atmel,nand-addr-offset = <21>; | |
| 291 | atmel,nand-cmd-offset = <22>; | |
| 292 | atmel,nand-has-dma; | |
| 293 | pinctrl-names = "default"; | |
| 294 | pinctrl-0 = <&pinctrl_nand>; | |
| 295 | status = "disabled"; | |
| 296 | ||
| 297 | nfc@90000000 { | |
| 298 | compatible = "atmel,sama5d3-nfc"; | |
| 299 | #address-cells = <1>; | |
| 300 | #size-cells = <1>; | |
| 301 | reg = < | |
| 302 | 0x90000000 0x10000000 /* NFC Command Registers */ | |
| 303 | 0xfc05c000 0x00000070 /* NFC HSMC regs */ | |
| 304 | 0x00100000 0x00100000 /* NFC SRAM banks */ | |
| 305 | >; | |
| 306 | clocks = <&hsmc_clk>; | |
| 307 | atmel,write-by-sram; | |
| 308 | }; | |
| 309 | }; | |
| 310 | ||
| 311 | apb { | |
| 312 | compatible = "simple-bus"; | |
| 313 | #address-cells = <1>; | |
| 314 | #size-cells = <1>; | |
| 315 | ranges; | |
| 316 | ||
| b3c7a497 LD |
317 | dma1: dma-controller@f0004000 { |
| 318 | compatible = "atmel,sama5d4-dma"; | |
| 319 | reg = <0xf0004000 0x200>; | |
| 320 | interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 321 | #dma-cells = <1>; | |
| 322 | clocks = <&dma1_clk>; | |
| 323 | clock-names = "dma_clk"; | |
| 324 | }; | |
| 325 | ||
| 7c661394 NF |
326 | ramc0: ramc@f0010000 { |
| 327 | compatible = "atmel,sama5d3-ddramc"; | |
| 328 | reg = <0xf0010000 0x200>; | |
| 329 | clocks = <&ddrck>, <&mpddr_clk>; | |
| 330 | clock-names = "ddrck", "mpddr"; | |
| 331 | }; | |
| 332 | ||
| b3c7a497 LD |
333 | dma0: dma-controller@f0014000 { |
| 334 | compatible = "atmel,sama5d4-dma"; | |
| 335 | reg = <0xf0014000 0x200>; | |
| 336 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 337 | #dma-cells = <1>; | |
| 338 | clocks = <&dma0_clk>; | |
| 339 | clock-names = "dma_clk"; | |
| 340 | }; | |
| 341 | ||
| 7c661394 NF |
342 | pmc: pmc@f0018000 { |
| 343 | compatible = "atmel,sama5d3-pmc"; | |
| 344 | reg = <0xf0018000 0x120>; | |
| 345 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
| 346 | interrupt-controller; | |
| 347 | #address-cells = <1>; | |
| 348 | #size-cells = <0>; | |
| 349 | #interrupt-cells = <1>; | |
| 350 | ||
| 351 | main_rc_osc: main_rc_osc { | |
| 352 | compatible = "atmel,at91sam9x5-clk-main-rc-osc"; | |
| 353 | #clock-cells = <0>; | |
| 354 | interrupt-parent = <&pmc>; | |
| 355 | interrupts = <AT91_PMC_MOSCRCS>; | |
| 356 | clock-frequency = <12000000>; | |
| 357 | clock-accuracy = <100000000>; | |
| 358 | }; | |
| 359 | ||
| 360 | main_osc: main_osc { | |
| 361 | compatible = "atmel,at91rm9200-clk-main-osc"; | |
| 362 | #clock-cells = <0>; | |
| 363 | interrupt-parent = <&pmc>; | |
| 364 | interrupts = <AT91_PMC_MOSCS>; | |
| 365 | clocks = <&main_xtal>; | |
| 366 | }; | |
| 367 | ||
| 368 | main: mainck { | |
| 369 | compatible = "atmel,at91sam9x5-clk-main"; | |
| 370 | #clock-cells = <0>; | |
| 371 | interrupt-parent = <&pmc>; | |
| 372 | interrupts = <AT91_PMC_MOSCSELS>; | |
| 373 | clocks = <&main_rc_osc &main_osc>; | |
| 374 | }; | |
| 375 | ||
| 376 | plla: pllack { | |
| 377 | compatible = "atmel,sama5d3-clk-pll"; | |
| 378 | #clock-cells = <0>; | |
| 379 | interrupt-parent = <&pmc>; | |
| 380 | interrupts = <AT91_PMC_LOCKA>; | |
| 381 | clocks = <&main>; | |
| 382 | reg = <0>; | |
| 383 | atmel,clk-input-range = <12000000 12000000>; | |
| 384 | #atmel,pll-clk-output-range-cells = <4>; | |
| 385 | atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; | |
| 386 | }; | |
| 387 | ||
| 388 | plladiv: plladivck { | |
| 389 | compatible = "atmel,at91sam9x5-clk-plldiv"; | |
| 390 | #clock-cells = <0>; | |
| 391 | clocks = <&plla>; | |
| 392 | }; | |
| 393 | ||
| 394 | utmi: utmick { | |
| 395 | compatible = "atmel,at91sam9x5-clk-utmi"; | |
| 396 | #clock-cells = <0>; | |
| 397 | interrupt-parent = <&pmc>; | |
| 398 | interrupts = <AT91_PMC_LOCKU>; | |
| 399 | clocks = <&main>; | |
| 400 | }; | |
| 401 | ||
| 402 | mck: masterck { | |
| 403 | compatible = "atmel,at91sam9x5-clk-master"; | |
| 404 | #clock-cells = <0>; | |
| 405 | interrupt-parent = <&pmc>; | |
| 406 | interrupts = <AT91_PMC_MCKRDY>; | |
| 407 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; | |
| 408 | atmel,clk-output-range = <125000000 177000000>; | |
| 409 | atmel,clk-divisors = <1 2 4 3>; | |
| 410 | }; | |
| 411 | ||
| 412 | h32ck: h32mxck { | |
| 413 | #clock-cells = <0>; | |
| 414 | compatible = "atmel,sama5d4-clk-h32mx"; | |
| 415 | clocks = <&mck>; | |
| 416 | }; | |
| 417 | ||
| 418 | usb: usbck { | |
| 419 | compatible = "atmel,at91sam9x5-clk-usb"; | |
| 420 | #clock-cells = <0>; | |
| 421 | clocks = <&plladiv>, <&utmi>; | |
| 422 | }; | |
| 423 | ||
| 424 | prog: progck { | |
| 425 | compatible = "atmel,at91sam9x5-clk-programmable"; | |
| 426 | #address-cells = <1>; | |
| 427 | #size-cells = <0>; | |
| 428 | interrupt-parent = <&pmc>; | |
| 429 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; | |
| 430 | ||
| 431 | prog0: prog0 { | |
| 432 | #clock-cells = <0>; | |
| 433 | reg = <0>; | |
| 434 | interrupts = <AT91_PMC_PCKRDY(0)>; | |
| 435 | }; | |
| 436 | ||
| 437 | prog1: prog1 { | |
| 438 | #clock-cells = <0>; | |
| 439 | reg = <1>; | |
| 440 | interrupts = <AT91_PMC_PCKRDY(1)>; | |
| 441 | }; | |
| 442 | ||
| 443 | prog2: prog2 { | |
| 444 | #clock-cells = <0>; | |
| 445 | reg = <2>; | |
| 446 | interrupts = <AT91_PMC_PCKRDY(2)>; | |
| 447 | }; | |
| 448 | }; | |
| 449 | ||
| 450 | smd: smdclk { | |
| 451 | compatible = "atmel,at91sam9x5-clk-smd"; | |
| 452 | #clock-cells = <0>; | |
| 453 | clocks = <&plladiv>, <&utmi>; | |
| 454 | }; | |
| 455 | ||
| 456 | systemck { | |
| 457 | compatible = "atmel,at91rm9200-clk-system"; | |
| 458 | #address-cells = <1>; | |
| 459 | #size-cells = <0>; | |
| 460 | ||
| 461 | ddrck: ddrck { | |
| 462 | #clock-cells = <0>; | |
| 463 | reg = <2>; | |
| 464 | clocks = <&mck>; | |
| 465 | }; | |
| 466 | ||
| 467 | lcdck: lcdck { | |
| 468 | #clock-cells = <0>; | |
| 469 | reg = <4>; | |
| 470 | clocks = <&smd>; | |
| 471 | }; | |
| 472 | ||
| 473 | smdck: smdck { | |
| 474 | #clock-cells = <0>; | |
| 475 | reg = <4>; | |
| 476 | clocks = <&smd>; | |
| 477 | }; | |
| 478 | ||
| 479 | uhpck: uhpck { | |
| 480 | #clock-cells = <0>; | |
| 481 | reg = <6>; | |
| 482 | clocks = <&usb>; | |
| 483 | }; | |
| 484 | ||
| 485 | udpck: udpck { | |
| 486 | #clock-cells = <0>; | |
| 487 | reg = <7>; | |
| 488 | clocks = <&usb>; | |
| 489 | }; | |
| 490 | ||
| 491 | pck0: pck0 { | |
| 492 | #clock-cells = <0>; | |
| 493 | reg = <8>; | |
| 494 | clocks = <&prog0>; | |
| 495 | }; | |
| 496 | ||
| 497 | pck1: pck1 { | |
| 498 | #clock-cells = <0>; | |
| 499 | reg = <9>; | |
| 500 | clocks = <&prog1>; | |
| 501 | }; | |
| 502 | ||
| 503 | pck2: pck2 { | |
| 504 | #clock-cells = <0>; | |
| 505 | reg = <10>; | |
| 506 | clocks = <&prog2>; | |
| 507 | }; | |
| 508 | }; | |
| 509 | ||
| 510 | periph32ck { | |
| 511 | compatible = "atmel,at91sam9x5-clk-peripheral"; | |
| 512 | #address-cells = <1>; | |
| 513 | #size-cells = <0>; | |
| 514 | clocks = <&h32ck>; | |
| 515 | ||
| 516 | pioD_clk: pioD_clk { | |
| 517 | #clock-cells = <0>; | |
| 518 | reg = <5>; | |
| 519 | }; | |
| 520 | ||
| 521 | usart0_clk: usart0_clk { | |
| 522 | #clock-cells = <0>; | |
| 523 | reg = <6>; | |
| 524 | }; | |
| 525 | ||
| 526 | usart1_clk: usart1_clk { | |
| 527 | #clock-cells = <0>; | |
| 528 | reg = <7>; | |
| 529 | }; | |
| 530 | ||
| 531 | icm_clk: icm_clk { | |
| 532 | #clock-cells = <0>; | |
| 533 | reg = <9>; | |
| 534 | }; | |
| 535 | ||
| 536 | aes_clk: aes_clk { | |
| 537 | #clock-cells = <0>; | |
| 538 | reg = <12>; | |
| 539 | }; | |
| 540 | ||
| 541 | tdes_clk: tdes_clk { | |
| 542 | #clock-cells = <0>; | |
| 543 | reg = <14>; | |
| 544 | }; | |
| 545 | ||
| 546 | sha_clk: sha_clk { | |
| 547 | #clock-cells = <0>; | |
| 548 | reg = <15>; | |
| 549 | }; | |
| 550 | ||
| 551 | matrix1_clk: matrix1_clk { | |
| 552 | #clock-cells = <0>; | |
| 553 | reg = <17>; | |
| 554 | }; | |
| 555 | ||
| 556 | hsmc_clk: hsmc_clk { | |
| 557 | #clock-cells = <0>; | |
| 558 | reg = <22>; | |
| 559 | }; | |
| 560 | ||
| 561 | pioA_clk: pioA_clk { | |
| 562 | #clock-cells = <0>; | |
| 563 | reg = <23>; | |
| 564 | }; | |
| 565 | ||
| 566 | pioB_clk: pioB_clk { | |
| 567 | #clock-cells = <0>; | |
| 568 | reg = <24>; | |
| 569 | }; | |
| 570 | ||
| 571 | pioC_clk: pioC_clk { | |
| 572 | #clock-cells = <0>; | |
| 573 | reg = <25>; | |
| 574 | }; | |
| 575 | ||
| 576 | pioE_clk: pioE_clk { | |
| 577 | #clock-cells = <0>; | |
| 578 | reg = <26>; | |
| 579 | }; | |
| 580 | ||
| 581 | uart0_clk: uart0_clk { | |
| 582 | #clock-cells = <0>; | |
| 583 | reg = <27>; | |
| 584 | }; | |
| 585 | ||
| 586 | uart1_clk: uart1_clk { | |
| 587 | #clock-cells = <0>; | |
| 588 | reg = <28>; | |
| 589 | }; | |
| 590 | ||
| 591 | usart2_clk: usart2_clk { | |
| 592 | #clock-cells = <0>; | |
| 593 | reg = <29>; | |
| 594 | }; | |
| 595 | ||
| 596 | usart3_clk: usart3_clk { | |
| 597 | #clock-cells = <0>; | |
| 598 | reg = <30>; | |
| 599 | }; | |
| 600 | ||
| 601 | usart4_clk: usart4_clk { | |
| 602 | #clock-cells = <0>; | |
| 603 | reg = <31>; | |
| 604 | }; | |
| 605 | ||
| 606 | twi0_clk: twi0_clk { | |
| 607 | reg = <32>; | |
| 608 | #clock-cells = <0>; | |
| 609 | }; | |
| 610 | ||
| 611 | twi1_clk: twi1_clk { | |
| 612 | #clock-cells = <0>; | |
| 613 | reg = <33>; | |
| 614 | }; | |
| 615 | ||
| 616 | twi2_clk: twi2_clk { | |
| 617 | #clock-cells = <0>; | |
| 618 | reg = <34>; | |
| 619 | }; | |
| 620 | ||
| 621 | mci0_clk: mci0_clk { | |
| 622 | #clock-cells = <0>; | |
| 623 | reg = <35>; | |
| 624 | }; | |
| 625 | ||
| 626 | mci1_clk: mci1_clk { | |
| 627 | #clock-cells = <0>; | |
| 628 | reg = <36>; | |
| 629 | }; | |
| 630 | ||
| 631 | spi0_clk: spi0_clk { | |
| 632 | #clock-cells = <0>; | |
| 633 | reg = <37>; | |
| 634 | }; | |
| 635 | ||
| 636 | spi1_clk: spi1_clk { | |
| 637 | #clock-cells = <0>; | |
| 638 | reg = <38>; | |
| 639 | }; | |
| 640 | ||
| 641 | spi2_clk: spi2_clk { | |
| 642 | #clock-cells = <0>; | |
| 643 | reg = <39>; | |
| 644 | }; | |
| 645 | ||
| 646 | tcb0_clk: tcb0_clk { | |
| 647 | #clock-cells = <0>; | |
| 648 | reg = <40>; | |
| 649 | }; | |
| 650 | ||
| 651 | tcb1_clk: tcb1_clk { | |
| 652 | #clock-cells = <0>; | |
| 653 | reg = <41>; | |
| 654 | }; | |
| 655 | ||
| 656 | tcb2_clk: tcb2_clk { | |
| 657 | #clock-cells = <0>; | |
| 658 | reg = <42>; | |
| 659 | }; | |
| 660 | ||
| 661 | pwm_clk: pwm_clk { | |
| 662 | #clock-cells = <0>; | |
| 663 | reg = <43>; | |
| 664 | }; | |
| 665 | ||
| 666 | adc_clk: adc_clk { | |
| 667 | #clock-cells = <0>; | |
| 668 | reg = <44>; | |
| 669 | }; | |
| 670 | ||
| 671 | dbgu_clk: dbgu_clk { | |
| 672 | #clock-cells = <0>; | |
| 673 | reg = <45>; | |
| 674 | }; | |
| 675 | ||
| 676 | uhphs_clk: uhphs_clk { | |
| 677 | #clock-cells = <0>; | |
| 678 | reg = <46>; | |
| 679 | }; | |
| 680 | ||
| 681 | udphs_clk: udphs_clk { | |
| 682 | #clock-cells = <0>; | |
| 683 | reg = <47>; | |
| 684 | }; | |
| 685 | ||
| 686 | ssc0_clk: ssc0_clk { | |
| 687 | #clock-cells = <0>; | |
| 688 | reg = <48>; | |
| 689 | }; | |
| 690 | ||
| 691 | ssc1_clk: ssc1_clk { | |
| 692 | #clock-cells = <0>; | |
| 693 | reg = <49>; | |
| 694 | }; | |
| 695 | ||
| 696 | trng_clk: trng_clk { | |
| 697 | #clock-cells = <0>; | |
| 698 | reg = <53>; | |
| 699 | }; | |
| 700 | ||
| 701 | macb0_clk: macb0_clk { | |
| 702 | #clock-cells = <0>; | |
| 703 | reg = <54>; | |
| 704 | }; | |
| 705 | ||
| 706 | macb1_clk: macb1_clk { | |
| 707 | #clock-cells = <0>; | |
| 708 | reg = <55>; | |
| 709 | }; | |
| 710 | ||
| 711 | fuse_clk: fuse_clk { | |
| 712 | #clock-cells = <0>; | |
| 713 | reg = <57>; | |
| 714 | }; | |
| 715 | ||
| 716 | securam_clk: securam_clk { | |
| 717 | #clock-cells = <0>; | |
| 718 | reg = <59>; | |
| 719 | }; | |
| 720 | ||
| 721 | smd_clk: smd_clk { | |
| 722 | #clock-cells = <0>; | |
| 723 | reg = <61>; | |
| 724 | }; | |
| 725 | ||
| 726 | twi3_clk: twi3_clk { | |
| 727 | #clock-cells = <0>; | |
| 728 | reg = <62>; | |
| 729 | }; | |
| 730 | ||
| 731 | catb_clk: catb_clk { | |
| 732 | #clock-cells = <0>; | |
| 733 | reg = <63>; | |
| 734 | }; | |
| 735 | }; | |
| 736 | ||
| 737 | periph64ck { | |
| 738 | compatible = "atmel,at91sam9x5-clk-peripheral"; | |
| 739 | #address-cells = <1>; | |
| 740 | #size-cells = <0>; | |
| 741 | clocks = <&mck>; | |
| 742 | ||
| 743 | dma0_clk: dma0_clk { | |
| 744 | #clock-cells = <0>; | |
| 745 | reg = <8>; | |
| 746 | }; | |
| 747 | ||
| 748 | cpkcc_clk: cpkcc_clk { | |
| 749 | #clock-cells = <0>; | |
| 750 | reg = <10>; | |
| 751 | }; | |
| 752 | ||
| 753 | aesb_clk: aesb_clk { | |
| 754 | #clock-cells = <0>; | |
| 755 | reg = <13>; | |
| 756 | }; | |
| 757 | ||
| 758 | mpddr_clk: mpddr_clk { | |
| 759 | #clock-cells = <0>; | |
| 760 | reg = <16>; | |
| 761 | }; | |
| 762 | ||
| 763 | matrix0_clk: matrix0_clk { | |
| 764 | #clock-cells = <0>; | |
| 765 | reg = <18>; | |
| 766 | }; | |
| 767 | ||
| 768 | vdec_clk: vdec_clk { | |
| 769 | #clock-cells = <0>; | |
| 770 | reg = <19>; | |
| 771 | }; | |
| 772 | ||
| 773 | dma1_clk: dma1_clk { | |
| 774 | #clock-cells = <0>; | |
| 775 | reg = <50>; | |
| 776 | }; | |
| 777 | ||
| 778 | lcd_clk: lcd_clk { | |
| 779 | #clock-cells = <0>; | |
| 780 | reg = <51>; | |
| 781 | }; | |
| 782 | ||
| 783 | isi_clk: isi_clk { | |
| 784 | #clock-cells = <0>; | |
| 785 | reg = <52>; | |
| 786 | }; | |
| 787 | }; | |
| 788 | }; | |
| 789 | ||
| 790 | mmc0: mmc@f8000000 { | |
| 791 | compatible = "atmel,hsmci"; | |
| 792 | reg = <0xf8000000 0x600>; | |
| 793 | interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; | |
| b3c7a497 LD |
794 | dmas = <&dma1 |
| 795 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 796 | | AT91_XDMAC_DT_PERID(0))>; | |
| 797 | dma-names = "rxtx"; | |
| 7c661394 NF |
798 | pinctrl-names = "default"; |
| 799 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; | |
| 800 | status = "disabled"; | |
| 801 | #address-cells = <1>; | |
| 802 | #size-cells = <0>; | |
| 803 | clocks = <&mci0_clk>; | |
| 804 | clock-names = "mci_clk"; | |
| 805 | }; | |
| 806 | ||
| 0697edd7 BS |
807 | ssc0: ssc@f8008000 { |
| 808 | compatible = "atmel,at91sam9g45-ssc"; | |
| 809 | reg = <0xf8008000 0x4000>; | |
| 810 | interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 811 | pinctrl-names = "default"; | |
| 812 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | |
| 813 | dmas = <&dma1 | |
| 814 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 815 | | AT91_XDMAC_DT_PERID(26))>, | |
| 816 | <&dma1 | |
| 817 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 818 | | AT91_XDMAC_DT_PERID(27))>; | |
| 819 | dma-names = "tx", "rx"; | |
| 820 | clocks = <&ssc0_clk>; | |
| 821 | clock-names = "pclk"; | |
| 822 | status = "disabled"; | |
| 823 | }; | |
| 824 | ||
| 0a5c5f84 BS |
825 | pwm0: pwm@f800c000 { |
| 826 | compatible = "atmel,sama5d3-pwm"; | |
| 827 | reg = <0xf800c000 0x300>; | |
| 828 | interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; | |
| 829 | #pwm-cells = <3>; | |
| 830 | clocks = <&pwm_clk>; | |
| 831 | status = "disabled"; | |
| 832 | }; | |
| 833 | ||
| 7c661394 NF |
834 | spi0: spi@f8010000 { |
| 835 | #address-cells = <1>; | |
| 836 | #size-cells = <0>; | |
| 837 | compatible = "atmel,at91rm9200-spi"; | |
| 838 | reg = <0xf8010000 0x100>; | |
| 839 | interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; | |
| b3c7a497 LD |
840 | dmas = <&dma1 |
| 841 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 842 | | AT91_XDMAC_DT_PERID(10))>, | |
| 843 | <&dma1 | |
| 844 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 845 | | AT91_XDMAC_DT_PERID(11))>; | |
| 846 | dma-names = "tx", "rx"; | |
| 7c661394 NF |
847 | pinctrl-names = "default"; |
| 848 | pinctrl-0 = <&pinctrl_spi0>; | |
| 849 | clocks = <&spi0_clk>; | |
| 850 | clock-names = "spi_clk"; | |
| 851 | status = "disabled"; | |
| 852 | }; | |
| 853 | ||
| 854 | i2c0: i2c@f8014000 { | |
| 855 | compatible = "atmel,at91sam9x5-i2c"; | |
| 856 | reg = <0xf8014000 0x4000>; | |
| 857 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; | |
| b3c7a497 LD |
858 | dmas = <&dma1 |
| 859 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 860 | | AT91_XDMAC_DT_PERID(2))>, | |
| 861 | <&dma1 | |
| 862 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 863 | | AT91_XDMAC_DT_PERID(3))>; | |
| 864 | dma-names = "tx", "rx"; | |
| 7c661394 NF |
865 | pinctrl-names = "default"; |
| 866 | pinctrl-0 = <&pinctrl_i2c0>; | |
| 867 | #address-cells = <1>; | |
| 868 | #size-cells = <0>; | |
| 869 | clocks = <&twi0_clk>; | |
| 870 | status = "disabled"; | |
| 871 | }; | |
| 872 | ||
| 4cc7cdf3 PA |
873 | i2c1: i2c@f8018000 { |
| 874 | compatible = "atmel,at91sam9x5-i2c"; | |
| 875 | reg = <0xf8018000 0x4000>; | |
| 876 | interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; | |
| 877 | dmas = <&dma1 | |
| 878 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) | |
| 879 | AT91_XDMAC_DT_PERID(4)>, | |
| 880 | <&dma1 | |
| 881 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) | |
| 882 | AT91_XDMAC_DT_PERID(5)>; | |
| 883 | dma-names = "tx", "rx"; | |
| 884 | pinctrl-names = "default"; | |
| 885 | pinctrl-0 = <&pinctrl_i2c1>; | |
| 886 | #address-cells = <1>; | |
| 887 | #size-cells = <0>; | |
| 888 | clocks = <&twi1_clk>; | |
| 889 | status = "disabled"; | |
| 890 | }; | |
| 891 | ||
| 7c661394 NF |
892 | tcb0: timer@f801c000 { |
| 893 | compatible = "atmel,at91sam9x5-tcb"; | |
| 894 | reg = <0xf801c000 0x100>; | |
| 895 | interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 896 | clocks = <&tcb0_clk>; | |
| 897 | clock-names = "t0_clk"; | |
| 898 | }; | |
| 899 | ||
| 900 | macb0: ethernet@f8020000 { | |
| 901 | compatible = "atmel,sama5d4-gem"; | |
| 902 | reg = <0xf8020000 0x100>; | |
| 903 | interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; | |
| 904 | pinctrl-names = "default"; | |
| 905 | pinctrl-0 = <&pinctrl_macb0_rmii>; | |
| 9917defd JW |
906 | #address-cells = <1>; |
| 907 | #size-cells = <0>; | |
| 7c661394 NF |
908 | clocks = <&macb0_clk>, <&macb0_clk>; |
| 909 | clock-names = "hclk", "pclk"; | |
| 910 | status = "disabled"; | |
| 911 | }; | |
| 912 | ||
| 913 | i2c2: i2c@f8024000 { | |
| 914 | compatible = "atmel,at91sam9x5-i2c"; | |
| 915 | reg = <0xf8024000 0x4000>; | |
| 84f017a7 | 916 | interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; |
| b3c7a497 LD |
917 | dmas = <&dma1 |
| 918 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 919 | | AT91_XDMAC_DT_PERID(6))>, | |
| 920 | <&dma1 | |
| 921 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 922 | | AT91_XDMAC_DT_PERID(7))>; | |
| 923 | dma-names = "tx", "rx"; | |
| 7c661394 NF |
924 | pinctrl-names = "default"; |
| 925 | pinctrl-0 = <&pinctrl_i2c2>; | |
| 926 | #address-cells = <1>; | |
| 927 | #size-cells = <0>; | |
| 928 | clocks = <&twi2_clk>; | |
| 929 | status = "disabled"; | |
| 930 | }; | |
| 931 | ||
| c3ef0b0c AB |
932 | sfr: sfr@f8028000 { |
| 933 | compatible = "atmel,sama5d4-sfr", "syscon"; | |
| 934 | reg = <0xf8028000 0x60>; | |
| 935 | }; | |
| 936 | ||
| 7c661394 NF |
937 | mmc1: mmc@fc000000 { |
| 938 | compatible = "atmel,hsmci"; | |
| 939 | reg = <0xfc000000 0x600>; | |
| 940 | interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; | |
| b3c7a497 LD |
941 | dmas = <&dma1 |
| 942 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 943 | | AT91_XDMAC_DT_PERID(1))>; | |
| 944 | dma-names = "rxtx"; | |
| 7c661394 NF |
945 | pinctrl-names = "default"; |
| 946 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; | |
| 947 | status = "disabled"; | |
| 948 | #address-cells = <1>; | |
| 949 | #size-cells = <0>; | |
| 950 | clocks = <&mci1_clk>; | |
| 951 | clock-names = "mci_clk"; | |
| 952 | }; | |
| 953 | ||
| 954 | usart2: serial@fc008000 { | |
| 955 | compatible = "atmel,at91sam9260-usart"; | |
| 956 | reg = <0xfc008000 0x100>; | |
| 957 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; | |
| b3c7a497 LD |
958 | dmas = <&dma1 |
| 959 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 960 | | AT91_XDMAC_DT_PERID(16))>, | |
| 961 | <&dma1 | |
| 962 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 963 | | AT91_XDMAC_DT_PERID(17))>; | |
| 964 | dma-names = "tx", "rx"; | |
| 7c661394 NF |
965 | pinctrl-names = "default"; |
| 966 | pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; | |
| 967 | clocks = <&usart2_clk>; | |
| 968 | clock-names = "usart"; | |
| 969 | status = "disabled"; | |
| 970 | }; | |
| 971 | ||
| 972 | usart3: serial@fc00c000 { | |
| 973 | compatible = "atmel,at91sam9260-usart"; | |
| 974 | reg = <0xfc00c000 0x100>; | |
| 975 | interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; | |
| b3c7a497 LD |
976 | dmas = <&dma1 |
| 977 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 978 | | AT91_XDMAC_DT_PERID(18))>, | |
| 979 | <&dma1 | |
| 980 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 981 | | AT91_XDMAC_DT_PERID(19))>; | |
| 982 | dma-names = "tx", "rx"; | |
| 7c661394 NF |
983 | pinctrl-names = "default"; |
| 984 | pinctrl-0 = <&pinctrl_usart3>; | |
| 985 | clocks = <&usart3_clk>; | |
| 986 | clock-names = "usart"; | |
| 987 | status = "disabled"; | |
| 988 | }; | |
| 989 | ||
| 990 | usart4: serial@fc010000 { | |
| 991 | compatible = "atmel,at91sam9260-usart"; | |
| 992 | reg = <0xfc010000 0x100>; | |
| 993 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; | |
| b3c7a497 LD |
994 | dmas = <&dma1 |
| 995 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 996 | | AT91_XDMAC_DT_PERID(20))>, | |
| 997 | <&dma1 | |
| 998 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 999 | | AT91_XDMAC_DT_PERID(21))>; | |
| 1000 | dma-names = "tx", "rx"; | |
| 7c661394 NF |
1001 | pinctrl-names = "default"; |
| 1002 | pinctrl-0 = <&pinctrl_usart4>; | |
| 1003 | clocks = <&usart4_clk>; | |
| 1004 | clock-names = "usart"; | |
| 1005 | status = "disabled"; | |
| 1006 | }; | |
| 1007 | ||
| 0697edd7 BS |
1008 | ssc1: ssc@fc014000 { |
| 1009 | compatible = "atmel,at91sam9g45-ssc"; | |
| 1010 | reg = <0xfc014000 0x4000>; | |
| 1011 | interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 1012 | pinctrl-names = "default"; | |
| 1013 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | |
| 1014 | dmas = <&dma1 | |
| 1015 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 1016 | | AT91_XDMAC_DT_PERID(28))>, | |
| 1017 | <&dma1 | |
| 1018 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 1019 | | AT91_XDMAC_DT_PERID(29))>; | |
| 1020 | dma-names = "tx", "rx"; | |
| 1021 | clocks = <&ssc1_clk>; | |
| 1022 | clock-names = "pclk"; | |
| 1023 | status = "disabled"; | |
| 1024 | }; | |
| 1025 | ||
| 7c661394 NF |
1026 | tcb1: timer@fc020000 { |
| 1027 | compatible = "atmel,at91sam9x5-tcb"; | |
| 1028 | reg = <0xfc020000 0x100>; | |
| 1029 | interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 1030 | clocks = <&tcb1_clk>; | |
| 1031 | clock-names = "t0_clk"; | |
| 1032 | }; | |
| 1033 | ||
| 1034 | adc0: adc@fc034000 { | |
| 1035 | compatible = "atmel,at91sam9x5-adc"; | |
| 1036 | reg = <0xfc034000 0x100>; | |
| 1037 | interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; | |
| 1038 | pinctrl-names = "default"; | |
| 1039 | pinctrl-0 = < | |
| 1040 | /* external trigger is conflict with USBA_VBUS */ | |
| 1041 | &pinctrl_adc0_ad0 | |
| 1042 | &pinctrl_adc0_ad1 | |
| 1043 | &pinctrl_adc0_ad2 | |
| 1044 | &pinctrl_adc0_ad3 | |
| 1045 | &pinctrl_adc0_ad4 | |
| 1046 | >; | |
| 1047 | clocks = <&adc_clk>, | |
| 1048 | <&adc_op_clk>; | |
| 1049 | clock-names = "adc_clk", "adc_op_clk"; | |
| 1050 | atmel,adc-channels-used = <0x01f>; | |
| 1051 | atmel,adc-startup-time = <40>; | |
| 1052 | atmel,adc-use-external; | |
| 1053 | atmel,adc-vref = <3000>; | |
| 1054 | atmel,adc-res = <8 10>; | |
| 1055 | atmel,adc-sample-hold-time = <11>; | |
| 1056 | atmel,adc-res-names = "lowres", "highres"; | |
| 1057 | atmel,adc-ts-pressure-threshold = <10000>; | |
| 1058 | status = "disabled"; | |
| 1059 | ||
| 1060 | trigger@0 { | |
| 1061 | trigger-name = "external-rising"; | |
| 1062 | trigger-value = <0x1>; | |
| 1063 | trigger-external; | |
| 1064 | }; | |
| 1065 | trigger@1 { | |
| 1066 | trigger-name = "external-falling"; | |
| 1067 | trigger-value = <0x2>; | |
| 1068 | trigger-external; | |
| 1069 | }; | |
| 1070 | trigger@2 { | |
| 1071 | trigger-name = "external-any"; | |
| 1072 | trigger-value = <0x3>; | |
| 1073 | trigger-external; | |
| 1074 | }; | |
| 1075 | trigger@3 { | |
| 1076 | trigger-name = "continuous"; | |
| 1077 | trigger-value = <0x6>; | |
| 1078 | }; | |
| 1079 | }; | |
| 1080 | ||
| 83906783 LZ |
1081 | aes@fc044000 { |
| 1082 | compatible = "atmel,at91sam9g46-aes"; | |
| 1083 | reg = <0xfc044000 0x100>; | |
| 1084 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 1085 | dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) | |
| 1086 | AT91_XDMAC_DT_PERID(41)>, | |
| 1087 | <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) | |
| 1088 | AT91_XDMAC_DT_PERID(40)>; | |
| 1089 | dma-names = "tx", "rx"; | |
| 1090 | clocks = <&aes_clk>; | |
| 1091 | clock-names = "aes_clk"; | |
| 1092 | status = "disabled"; | |
| 1093 | }; | |
| 1094 | ||
| 1095 | tdes@fc04c000 { | |
| 1096 | compatible = "atmel,at91sam9g46-tdes"; | |
| 1097 | reg = <0xfc04c000 0x100>; | |
| 1098 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 1099 | dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) | |
| 1100 | AT91_XDMAC_DT_PERID(42)>, | |
| 1101 | <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) | |
| 1102 | AT91_XDMAC_DT_PERID(43)>; | |
| 1103 | dma-names = "tx", "rx"; | |
| 1104 | clocks = <&tdes_clk>; | |
| 1105 | clock-names = "tdes_clk"; | |
| 1106 | status = "disabled"; | |
| 1107 | }; | |
| 1108 | ||
| 1109 | sha@fc050000 { | |
| 1110 | compatible = "atmel,at91sam9g46-sha"; | |
| 1111 | reg = <0xfc050000 0x100>; | |
| 1112 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 1113 | dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) | |
| 1114 | AT91_XDMAC_DT_PERID(44)>; | |
| 1115 | dma-names = "tx"; | |
| 1116 | clocks = <&sha_clk>; | |
| 1117 | clock-names = "sha_clk"; | |
| 1118 | status = "disabled"; | |
| 1119 | }; | |
| 1120 | ||
| 7c661394 NF |
1121 | rstc@fc068600 { |
| 1122 | compatible = "atmel,at91sam9g45-rstc"; | |
| 1123 | reg = <0xfc068600 0x10>; | |
| 1124 | }; | |
| 1125 | ||
| 1126 | shdwc@fc068610 { | |
| 1127 | compatible = "atmel,at91sam9x5-shdwc"; | |
| 1128 | reg = <0xfc068610 0x10>; | |
| 1129 | }; | |
| 1130 | ||
| 1131 | pit: timer@fc068630 { | |
| 1132 | compatible = "atmel,at91sam9260-pit"; | |
| 0068b2e1 | 1133 | reg = <0xfc068630 0x10>; |
| 7c661394 NF |
1134 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; |
| 1135 | clocks = <&h32ck>; | |
| 1136 | }; | |
| 1137 | ||
| 1138 | watchdog@fc068640 { | |
| 1139 | compatible = "atmel,at91sam9260-wdt"; | |
| 1140 | reg = <0xfc068640 0x10>; | |
| 1141 | status = "disabled"; | |
| 1142 | }; | |
| 1143 | ||
| 1144 | sckc@fc068650 { | |
| 1145 | compatible = "atmel,at91sam9x5-sckc"; | |
| 1146 | reg = <0xfc068650 0x4>; | |
| 1147 | ||
| 1148 | slow_rc_osc: slow_rc_osc { | |
| 1149 | compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; | |
| 1150 | #clock-cells = <0>; | |
| 1151 | clock-frequency = <32768>; | |
| 1152 | clock-accuracy = <250000000>; | |
| 1153 | atmel,startup-time-usec = <75>; | |
| 1154 | }; | |
| 1155 | ||
| 1156 | slow_osc: slow_osc { | |
| 1157 | compatible = "atmel,at91sam9x5-clk-slow-osc"; | |
| 1158 | #clock-cells = <0>; | |
| 1159 | clocks = <&slow_xtal>; | |
| 1160 | atmel,startup-time-usec = <1200000>; | |
| 1161 | }; | |
| 1162 | ||
| 1163 | clk32k: slowck { | |
| 1164 | compatible = "atmel,at91sam9x5-clk-slow"; | |
| 1165 | #clock-cells = <0>; | |
| 1166 | clocks = <&slow_rc_osc &slow_osc>; | |
| 1167 | }; | |
| 1168 | }; | |
| 1169 | ||
| 1170 | rtc@fc0686b0 { | |
| 1171 | compatible = "atmel,at91rm9200-rtc"; | |
| 1172 | reg = <0xfc0686b0 0x30>; | |
| 1173 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
| 1174 | }; | |
| 1175 | ||
| 1176 | dbgu: serial@fc069000 { | |
| 1177 | compatible = "atmel,at91sam9260-usart"; | |
| 1178 | reg = <0xfc069000 0x200>; | |
| 1179 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; | |
| 1180 | pinctrl-names = "default"; | |
| 1181 | pinctrl-0 = <&pinctrl_dbgu>; | |
| 1182 | clocks = <&dbgu_clk>; | |
| 1183 | clock-names = "usart"; | |
| 1184 | status = "disabled"; | |
| 1185 | }; | |
| 1186 | ||
| 1187 | ||
| 1188 | pinctrl@fc06a000 { | |
| 1189 | #address-cells = <1>; | |
| 1190 | #size-cells = <1>; | |
| 1191 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; | |
| 1192 | ranges = <0xfc06a000 0xfc06a000 0x4000>; | |
| 1193 | /* WARNING: revisit as pin spec has changed */ | |
| 1194 | atmel,mux-mask = < | |
| 1195 | /* A B C */ | |
| 1196 | 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ | |
| 1197 | 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ | |
| 1198 | 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ | |
| 1199 | 0x00000000 0x00000000 0x00000000 /* pioD */ | |
| 1200 | 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ | |
| 1201 | >; | |
| 1202 | ||
| 1203 | pioA: gpio@fc06a000 { | |
| 1204 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 1205 | reg = <0xfc06a000 0x100>; | |
| 1206 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; | |
| 1207 | #gpio-cells = <2>; | |
| 1208 | gpio-controller; | |
| 1209 | interrupt-controller; | |
| 1210 | #interrupt-cells = <2>; | |
| 1211 | clocks = <&pioA_clk>; | |
| 1212 | }; | |
| 1213 | ||
| 1214 | pioB: gpio@fc06b000 { | |
| 1215 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 1216 | reg = <0xfc06b000 0x100>; | |
| 1217 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; | |
| 1218 | #gpio-cells = <2>; | |
| 1219 | gpio-controller; | |
| 1220 | interrupt-controller; | |
| 1221 | #interrupt-cells = <2>; | |
| 1222 | clocks = <&pioB_clk>; | |
| 1223 | }; | |
| 1224 | ||
| 1225 | pioC: gpio@fc06c000 { | |
| 1226 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 1227 | reg = <0xfc06c000 0x100>; | |
| 1228 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; | |
| 1229 | #gpio-cells = <2>; | |
| 1230 | gpio-controller; | |
| 1231 | interrupt-controller; | |
| 1232 | #interrupt-cells = <2>; | |
| 1233 | clocks = <&pioC_clk>; | |
| 1234 | }; | |
| 1235 | ||
| 1de77b7f LD |
1236 | pioD: gpio@fc068000 { |
| 1237 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 1238 | reg = <0xfc068000 0x100>; | |
| 1239 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; | |
| 1240 | #gpio-cells = <2>; | |
| 1241 | gpio-controller; | |
| 1242 | interrupt-controller; | |
| 1243 | #interrupt-cells = <2>; | |
| 1244 | clocks = <&pioD_clk>; | |
| 1245 | status = "disabled"; | |
| 1246 | }; | |
| 1247 | ||
| 7c661394 NF |
1248 | pioE: gpio@fc06d000 { |
| 1249 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 1250 | reg = <0xfc06d000 0x100>; | |
| 1251 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; | |
| 1252 | #gpio-cells = <2>; | |
| 1253 | gpio-controller; | |
| 1254 | interrupt-controller; | |
| 1255 | #interrupt-cells = <2>; | |
| 1256 | clocks = <&pioE_clk>; | |
| 1257 | }; | |
| 1258 | ||
| 1259 | /* pinctrl pin settings */ | |
| 1260 | adc0 { | |
| 1261 | pinctrl_adc0_adtrg: adc0_adtrg { | |
| 1262 | atmel,pins = | |
| 1263 | <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */ | |
| 1264 | }; | |
| 1265 | pinctrl_adc0_ad0: adc0_ad0 { | |
| 1266 | atmel,pins = | |
| 1267 | <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 1268 | }; | |
| 1269 | pinctrl_adc0_ad1: adc0_ad1 { | |
| 1270 | atmel,pins = | |
| 1271 | <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 1272 | }; | |
| 1273 | pinctrl_adc0_ad2: adc0_ad2 { | |
| 1274 | atmel,pins = | |
| 1275 | <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 1276 | }; | |
| 1277 | pinctrl_adc0_ad3: adc0_ad3 { | |
| 1278 | atmel,pins = | |
| 1279 | <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 1280 | }; | |
| 1281 | pinctrl_adc0_ad4: adc0_ad4 { | |
| 1282 | atmel,pins = | |
| 1283 | <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 1284 | }; | |
| 1285 | }; | |
| 1286 | ||
| 1287 | dbgu { | |
| 1288 | pinctrl_dbgu: dbgu-0 { | |
| 1289 | atmel,pins = | |
| 1290 | <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */ | |
| 1291 | <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */ | |
| 1292 | }; | |
| 1293 | }; | |
| 1294 | ||
| 1295 | i2c0 { | |
| 1296 | pinctrl_i2c0: i2c0-0 { | |
| 1297 | atmel,pins = | |
| 1298 | <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE | |
| 1299 | AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 1300 | }; | |
| 1301 | }; | |
| 1302 | ||
| 4cc7cdf3 PA |
1303 | i2c1 { |
| 1304 | pinctrl_i2c1: i2c1-0 { | |
| 1305 | atmel,pins = | |
| 1306 | <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */ | |
| 1307 | AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */ | |
| 1308 | }; | |
| 1309 | }; | |
| 1310 | ||
| 7c661394 NF |
1311 | i2c2 { |
| 1312 | pinctrl_i2c2: i2c2-0 { | |
| 1313 | atmel,pins = | |
| 1314 | <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */ | |
| 1315 | AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */ | |
| 1316 | }; | |
| 1317 | }; | |
| 1318 | ||
| 1319 | macb0 { | |
| 1320 | pinctrl_macb0_rmii: macb0_rmii-0 { | |
| 1321 | atmel,pins = | |
| 1322 | <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */ | |
| 1323 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */ | |
| 1324 | AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */ | |
| 1325 | AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */ | |
| 1326 | AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */ | |
| 1327 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */ | |
| 1328 | AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */ | |
| 1329 | AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */ | |
| 1330 | AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */ | |
| 1331 | AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */ | |
| 1332 | >; | |
| 1333 | }; | |
| 1334 | }; | |
| 1335 | ||
| 1336 | mmc0 { | |
| 1337 | pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { | |
| 1338 | atmel,pins = | |
| 1339 | <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */ | |
| 1340 | AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */ | |
| 1341 | AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */ | |
| 1342 | >; | |
| 1343 | }; | |
| 1344 | pinctrl_mmc0_dat1_3: mmc0_dat1_3 { | |
| 1345 | atmel,pins = | |
| 1346 | <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */ | |
| 1347 | AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */ | |
| 1348 | AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */ | |
| 1349 | >; | |
| 1350 | }; | |
| 1351 | }; | |
| 1352 | ||
| 1353 | mmc1 { | |
| 1354 | pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { | |
| 1355 | atmel,pins = | |
| 1356 | <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */ | |
| 1357 | AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */ | |
| 1358 | AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */ | |
| 1359 | >; | |
| 1360 | }; | |
| 1361 | pinctrl_mmc1_dat1_3: mmc1_dat1_3 { | |
| 1362 | atmel,pins = | |
| 1363 | <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */ | |
| 1364 | AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */ | |
| 1365 | AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */ | |
| 1366 | >; | |
| 1367 | }; | |
| 1368 | }; | |
| 1369 | ||
| 1370 | nand0 { | |
| 1371 | pinctrl_nand: nand-0 { | |
| 1372 | atmel,pins = | |
| 1373 | <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */ | |
| 1374 | AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */ | |
| 1375 | ||
| 1376 | AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */ | |
| 1377 | AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */ | |
| 1378 | ||
| 1379 | AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */ | |
| 1380 | AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */ | |
| 1381 | AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */ | |
| 1382 | AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */ | |
| 1383 | AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */ | |
| 1384 | AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */ | |
| 1385 | AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */ | |
| 1386 | AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */ | |
| 1387 | AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */ | |
| 1388 | AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */ | |
| 1389 | }; | |
| 1390 | }; | |
| 1391 | ||
| 1392 | spi0 { | |
| 1393 | pinctrl_spi0: spi0-0 { | |
| 1394 | atmel,pins = | |
| 1395 | <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */ | |
| 1396 | AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */ | |
| 1397 | AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */ | |
| 1398 | >; | |
| 1399 | }; | |
| 1400 | }; | |
| 1401 | ||
| 0697edd7 BS |
1402 | ssc0 { |
| 1403 | pinctrl_ssc0_tx: ssc0_tx { | |
| 1404 | atmel,pins = | |
| 1405 | <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */ | |
| 1406 | AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */ | |
| 1407 | AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */ | |
| 1408 | }; | |
| 1409 | ||
| 1410 | pinctrl_ssc0_rx: ssc0_rx { | |
| 1411 | atmel,pins = | |
| 1412 | <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */ | |
| 1413 | AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */ | |
| 1414 | AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */ | |
| 1415 | }; | |
| 1416 | }; | |
| 1417 | ||
| 1418 | ssc1 { | |
| 1419 | pinctrl_ssc1_tx: ssc1_tx { | |
| 1420 | atmel,pins = | |
| 1421 | <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */ | |
| 1422 | AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */ | |
| 1423 | AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */ | |
| 1424 | }; | |
| 1425 | ||
| 1426 | pinctrl_ssc1_rx: ssc1_rx { | |
| 1427 | atmel,pins = | |
| 1428 | <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */ | |
| 1429 | AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */ | |
| 1430 | AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */ | |
| 1431 | }; | |
| 1432 | }; | |
| 1433 | ||
| 7c661394 NF |
1434 | usart2 { |
| 1435 | pinctrl_usart2: usart2-0 { | |
| 1436 | atmel,pins = | |
| 1437 | <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */ | |
| 1438 | AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */ | |
| 1439 | >; | |
| 1440 | }; | |
| 1441 | pinctrl_usart2_rts: usart2_rts-0 { | |
| 1442 | atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */ | |
| 1443 | }; | |
| 1444 | pinctrl_usart2_cts: usart2_cts-0 { | |
| 1445 | atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */ | |
| 1446 | }; | |
| 1447 | }; | |
| 1448 | ||
| 1449 | usart3 { | |
| 1450 | pinctrl_usart3: usart3-0 { | |
| 1451 | atmel,pins = | |
| 1452 | <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ | |
| 1453 | AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ | |
| 1454 | >; | |
| 1455 | }; | |
| 1456 | }; | |
| 1457 | ||
| 1458 | usart4 { | |
| 1459 | pinctrl_usart4: usart4-0 { | |
| 1460 | atmel,pins = | |
| 1461 | <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ | |
| 1462 | AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ | |
| 1463 | >; | |
| 1464 | }; | |
| 1465 | pinctrl_usart4_rts: usart4_rts-0 { | |
| 1466 | atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */ | |
| 1467 | }; | |
| 1468 | pinctrl_usart4_cts: usart4_cts-0 { | |
| 1469 | atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */ | |
| 1470 | }; | |
| 1471 | }; | |
| 1472 | }; | |
| 1473 | ||
| 1474 | aic: interrupt-controller@fc06e000 { | |
| 1475 | #interrupt-cells = <3>; | |
| 1476 | compatible = "atmel,sama5d4-aic"; | |
| 1477 | interrupt-controller; | |
| 1478 | reg = <0xfc06e000 0x200>; | |
| 1479 | atmel,external-irqs = <56>; | |
| 1480 | }; | |
| 1481 | }; | |
| 1482 | }; | |
| 1483 | }; |