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ARM: at91/dt: sama5d4 xplained: add i2c0
[deliverable/linux.git] / arch / arm / boot / dts / sama5d4.dtsi
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7c661394
NF		 1/*
2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
1d2a0563 12 * a) This file is free software; you can redistribute it and/or
7c661394
NF		 13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
1d2a0563 17 * This file is distributed in the hope that it will be useful,
7c661394
NF		 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "skeleton.dtsi"
47#include <dt-bindings/clock/at91.h>
b3c7a497 48#include <dt-bindings/dma/at91.h>
7c661394
NF		 49#include <dt-bindings/pinctrl/at91.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51#include <dt-bindings/gpio/gpio.h>
52
53/ {
54 model = "Atmel SAMA5D4 family SoC";
55 compatible = "atmel,sama5d4";
56 interrupt-parent = <&aic>;
57
58 aliases {
59 serial0 = &usart3;
60 serial1 = &usart4;
61 serial2 = &usart2;
62 gpio0 = &pioA;
63 gpio1 = &pioB;
64 gpio2 = &pioC;
1de77b7f 65 gpio3 = &pioD;
7c661394
NF		 66 gpio4 = &pioE;
67 tcb0 = &tcb0;
68 tcb1 = &tcb1;
a547f60a 69 i2c0 = &i2c0;
4cc7cdf3 70 i2c1 = &i2c1;
7c661394
NF		 71 i2c2 = &i2c2;
72 };
73 cpus {
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 cpu@0 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a5";
80 reg = <0>;
81 next-level-cache = <&L2>;
82 };
83 };
84
85 memory {
86 reg = <0x20000000 0x20000000>;
87 };
88
89 clocks {
90 slow_xtal: slow_xtal {
91 compatible = "fixed-clock";
92 #clock-cells = <0>;
93 clock-frequency = <0>;
94 };
95
96 main_xtal: main_xtal {
97 compatible = "fixed-clock";
98 #clock-cells = <0>;
99 clock-frequency = <0>;
100 };
101
102 adc_op_clk: adc_op_clk{
103 compatible = "fixed-clock";
104 #clock-cells = <0>;
105 clock-frequency = <1000000>;
106 };
107 };
108
f04660e4
AB		 109 ns_sram: sram@00210000 {
110 compatible = "mmio-sram";
111 reg = <0x00210000 0x10000>;
112 };
113
7c661394
NF		 114 ahb {
115 compatible = "simple-bus";
116 #address-cells = <1>;
117 #size-cells = <1>;
118 ranges;
119
120 usb0: gadget@00400000 {
121 #address-cells = <1>;
122 #size-cells = <0>;
123 compatible = "atmel,at91sam9rl-udc";
124 reg = <0x00400000 0x100000
125 0xfc02c000 0x4000>;
126 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
127 clocks = <&udphs_clk>, <&utmi>;
128 clock-names = "pclk", "hclk";
129 status = "disabled";
130
131 ep0 {
132 reg = <0>;
133 atmel,fifo-size = <64>;
134 atmel,nb-banks = <1>;
135 };
136
137 ep1 {
138 reg = <1>;
139 atmel,fifo-size = <1024>;
140 atmel,nb-banks = <3>;
141 atmel,can-dma;
142 atmel,can-isoc;
143 };
144
145 ep2 {
146 reg = <2>;
147 atmel,fifo-size = <1024>;
148 atmel,nb-banks = <3>;
149 atmel,can-dma;
150 atmel,can-isoc;
151 };
152
153 ep3 {
154 reg = <3>;
155 atmel,fifo-size = <1024>;
156 atmel,nb-banks = <2>;
157 atmel,can-dma;
158 atmel,can-isoc;
159 };
160
161 ep4 {
162 reg = <4>;
163 atmel,fifo-size = <1024>;
164 atmel,nb-banks = <2>;
165 atmel,can-dma;
166 atmel,can-isoc;
167 };
168
169 ep5 {
170 reg = <5>;
171 atmel,fifo-size = <1024>;
172 atmel,nb-banks = <2>;
173 atmel,can-dma;
174 atmel,can-isoc;
175 };
176
177 ep6 {
178 reg = <6>;
179 atmel,fifo-size = <1024>;
180 atmel,nb-banks = <2>;
181 atmel,can-dma;
182 atmel,can-isoc;
183 };
184
185 ep7 {
186 reg = <7>;
187 atmel,fifo-size = <1024>;
188 atmel,nb-banks = <2>;
189 atmel,can-dma;
190 atmel,can-isoc;
191 };
192
193 ep8 {
194 reg = <8>;
195 atmel,fifo-size = <1024>;
196 atmel,nb-banks = <2>;
197 atmel,can-isoc;
198 };
199
200 ep9 {
201 reg = <9>;
202 atmel,fifo-size = <1024>;
203 atmel,nb-banks = <2>;
204 atmel,can-isoc;
205 };
206
207 ep10 {
208 reg = <10>;
209 atmel,fifo-size = <1024>;
210 atmel,nb-banks = <2>;
211 atmel,can-isoc;
212 };
213
214 ep11 {
215 reg = <11>;
216 atmel,fifo-size = <1024>;
217 atmel,nb-banks = <2>;
218 atmel,can-isoc;
219 };
220
221 ep12 {
222 reg = <12>;
223 atmel,fifo-size = <1024>;
224 atmel,nb-banks = <2>;
225 atmel,can-isoc;
226 };
227
228 ep13 {
229 reg = <13>;
230 atmel,fifo-size = <1024>;
231 atmel,nb-banks = <2>;
232 atmel,can-isoc;
233 };
234
235 ep14 {
236 reg = <14>;
237 atmel,fifo-size = <1024>;
238 atmel,nb-banks = <2>;
239 atmel,can-isoc;
240 };
241
242 ep15 {
243 reg = <15>;
244 atmel,fifo-size = <1024>;
245 atmel,nb-banks = <2>;
246 atmel,can-isoc;
247 };
248 };
249
250 usb1: ohci@00500000 {
251 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
252 reg = <0x00500000 0x100000>;
253 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
254 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
255 <&uhpck>;
256 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
257 status = "disabled";
258 };
259
260 usb2: ehci@00600000 {
261 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
262 reg = <0x00600000 0x100000>;
263 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
264 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
265 clock-names = "usb_clk", "ehci_clk", "uhpck";
266 status = "disabled";
267 };
268
269 L2: cache-controller@00a00000 {
270 compatible = "arm,pl310-cache";
271 reg = <0x00a00000 0x1000>;
272 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
273 cache-unified;
274 cache-level = <2>;
275 };
276
277 nand0: nand@80000000 {
fda077c0 278 compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand";
7c661394
NF		 279 #address-cells = <1>;
280 #size-cells = <1>;
281 ranges;
282 reg = < 0x80000000 0x08000000 /* EBI CS3 */
283 0xfc05c070 0x00000490 /* SMC PMECC regs */
284 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
285 >;
286 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
287 atmel,nand-addr-offset = <21>;
288 atmel,nand-cmd-offset = <22>;
289 atmel,nand-has-dma;
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_nand>;
292 status = "disabled";
293
294 nfc@90000000 {
295 compatible = "atmel,sama5d3-nfc";
296 #address-cells = <1>;
297 #size-cells = <1>;
298 reg = <
299 0x90000000 0x10000000 /* NFC Command Registers */
300 0xfc05c000 0x00000070 /* NFC HSMC regs */
301 0x00100000 0x00100000 /* NFC SRAM banks */
302 >;
303 clocks = <&hsmc_clk>;
304 atmel,write-by-sram;
305 };
306 };
307
308 apb {
309 compatible = "simple-bus";
310 #address-cells = <1>;
311 #size-cells = <1>;
312 ranges;
313
b3c7a497
LD		 314 dma1: dma-controller@f0004000 {
315 compatible = "atmel,sama5d4-dma";
316 reg = <0xf0004000 0x200>;
317 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
318 #dma-cells = <1>;
319 clocks = <&dma1_clk>;
320 clock-names = "dma_clk";
321 };
322
7c661394
NF		 323 ramc0: ramc@f0010000 {
324 compatible = "atmel,sama5d3-ddramc";
325 reg = <0xf0010000 0x200>;
326 clocks = <&ddrck>, <&mpddr_clk>;
327 clock-names = "ddrck", "mpddr";
328 };
329
b3c7a497
LD		 330 dma0: dma-controller@f0014000 {
331 compatible = "atmel,sama5d4-dma";
332 reg = <0xf0014000 0x200>;
333 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
334 #dma-cells = <1>;
335 clocks = <&dma0_clk>;
336 clock-names = "dma_clk";
337 };
338
7c661394
NF		 339 pmc: pmc@f0018000 {
340 compatible = "atmel,sama5d3-pmc";
341 reg = <0xf0018000 0x120>;
342 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
343 interrupt-controller;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 #interrupt-cells = <1>;
347
348 main_rc_osc: main_rc_osc {
349 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
350 #clock-cells = <0>;
351 interrupt-parent = <&pmc>;
352 interrupts = <AT91_PMC_MOSCRCS>;
353 clock-frequency = <12000000>;
354 clock-accuracy = <100000000>;
355 };
356
357 main_osc: main_osc {
358 compatible = "atmel,at91rm9200-clk-main-osc";
359 #clock-cells = <0>;
360 interrupt-parent = <&pmc>;
361 interrupts = <AT91_PMC_MOSCS>;
362 clocks = <&main_xtal>;
363 };
364
365 main: mainck {
366 compatible = "atmel,at91sam9x5-clk-main";
367 #clock-cells = <0>;
368 interrupt-parent = <&pmc>;
369 interrupts = <AT91_PMC_MOSCSELS>;
370 clocks = <&main_rc_osc &main_osc>;
371 };
372
373 plla: pllack {
374 compatible = "atmel,sama5d3-clk-pll";
375 #clock-cells = <0>;
376 interrupt-parent = <&pmc>;
377 interrupts = <AT91_PMC_LOCKA>;
378 clocks = <&main>;
379 reg = <0>;
380 atmel,clk-input-range = <12000000 12000000>;
381 #atmel,pll-clk-output-range-cells = <4>;
382 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
383 };
384
385 plladiv: plladivck {
386 compatible = "atmel,at91sam9x5-clk-plldiv";
387 #clock-cells = <0>;
388 clocks = <&plla>;
389 };
390
391 utmi: utmick {
392 compatible = "atmel,at91sam9x5-clk-utmi";
393 #clock-cells = <0>;
394 interrupt-parent = <&pmc>;
395 interrupts = <AT91_PMC_LOCKU>;
396 clocks = <&main>;
397 };
398
399 mck: masterck {
400 compatible = "atmel,at91sam9x5-clk-master";
401 #clock-cells = <0>;
402 interrupt-parent = <&pmc>;
403 interrupts = <AT91_PMC_MCKRDY>;
404 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
405 atmel,clk-output-range = <125000000 177000000>;
406 atmel,clk-divisors = <1 2 4 3>;
407 };
408
409 h32ck: h32mxck {
410 #clock-cells = <0>;
411 compatible = "atmel,sama5d4-clk-h32mx";
412 clocks = <&mck>;
413 };
414
415 usb: usbck {
416 compatible = "atmel,at91sam9x5-clk-usb";
417 #clock-cells = <0>;
418 clocks = <&plladiv>, <&utmi>;
419 };
420
421 prog: progck {
422 compatible = "atmel,at91sam9x5-clk-programmable";
423 #address-cells = <1>;
424 #size-cells = <0>;
425 interrupt-parent = <&pmc>;
426 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
427
428 prog0: prog0 {
429 #clock-cells = <0>;
430 reg = <0>;
431 interrupts = <AT91_PMC_PCKRDY(0)>;
432 };
433
434 prog1: prog1 {
435 #clock-cells = <0>;
436 reg = <1>;
437 interrupts = <AT91_PMC_PCKRDY(1)>;
438 };
439
440 prog2: prog2 {
441 #clock-cells = <0>;
442 reg = <2>;
443 interrupts = <AT91_PMC_PCKRDY(2)>;
444 };
445 };
446
447 smd: smdclk {
448 compatible = "atmel,at91sam9x5-clk-smd";
449 #clock-cells = <0>;
450 clocks = <&plladiv>, <&utmi>;
451 };
452
453 systemck {
454 compatible = "atmel,at91rm9200-clk-system";
455 #address-cells = <1>;
456 #size-cells = <0>;
457
458 ddrck: ddrck {
459 #clock-cells = <0>;
460 reg = <2>;
461 clocks = <&mck>;
462 };
463
464 lcdck: lcdck {
465 #clock-cells = <0>;
466 reg = <4>;
467 clocks = <&smd>;
468 };
469
470 smdck: smdck {
471 #clock-cells = <0>;
472 reg = <4>;
473 clocks = <&smd>;
474 };
475
476 uhpck: uhpck {
477 #clock-cells = <0>;
478 reg = <6>;
479 clocks = <&usb>;
480 };
481
482 udpck: udpck {
483 #clock-cells = <0>;
484 reg = <7>;
485 clocks = <&usb>;
486 };
487
488 pck0: pck0 {
489 #clock-cells = <0>;
490 reg = <8>;
491 clocks = <&prog0>;
492 };
493
494 pck1: pck1 {
495 #clock-cells = <0>;
496 reg = <9>;
497 clocks = <&prog1>;
498 };
499
500 pck2: pck2 {
501 #clock-cells = <0>;
502 reg = <10>;
503 clocks = <&prog2>;
504 };
505 };
506
507 periph32ck {
508 compatible = "atmel,at91sam9x5-clk-peripheral";
509 #address-cells = <1>;
510 #size-cells = <0>;
511 clocks = <&h32ck>;
512
513 pioD_clk: pioD_clk {
514 #clock-cells = <0>;
515 reg = <5>;
516 };
517
518 usart0_clk: usart0_clk {
519 #clock-cells = <0>;
520 reg = <6>;
521 };
522
523 usart1_clk: usart1_clk {
524 #clock-cells = <0>;
525 reg = <7>;
526 };
527
528 icm_clk: icm_clk {
529 #clock-cells = <0>;
530 reg = <9>;
531 };
532
533 aes_clk: aes_clk {
534 #clock-cells = <0>;
535 reg = <12>;
536 };
537
538 tdes_clk: tdes_clk {
539 #clock-cells = <0>;
540 reg = <14>;
541 };
542
543 sha_clk: sha_clk {
544 #clock-cells = <0>;
545 reg = <15>;
546 };
547
548 matrix1_clk: matrix1_clk {
549 #clock-cells = <0>;
550 reg = <17>;
551 };
552
553 hsmc_clk: hsmc_clk {
554 #clock-cells = <0>;
555 reg = <22>;
556 };
557
558 pioA_clk: pioA_clk {
559 #clock-cells = <0>;
560 reg = <23>;
561 };
562
563 pioB_clk: pioB_clk {
564 #clock-cells = <0>;
565 reg = <24>;
566 };
567
568 pioC_clk: pioC_clk {
569 #clock-cells = <0>;
570 reg = <25>;
571 };
572
573 pioE_clk: pioE_clk {
574 #clock-cells = <0>;
575 reg = <26>;
576 };
577
578 uart0_clk: uart0_clk {
579 #clock-cells = <0>;
580 reg = <27>;
581 };
582
583 uart1_clk: uart1_clk {
584 #clock-cells = <0>;
585 reg = <28>;
586 };
587
588 usart2_clk: usart2_clk {
589 #clock-cells = <0>;
590 reg = <29>;
591 };
592
593 usart3_clk: usart3_clk {
594 #clock-cells = <0>;
595 reg = <30>;
596 };
597
598 usart4_clk: usart4_clk {
599 #clock-cells = <0>;
600 reg = <31>;
601 };
602
603 twi0_clk: twi0_clk {
604 reg = <32>;
605 #clock-cells = <0>;
606 };
607
608 twi1_clk: twi1_clk {
609 #clock-cells = <0>;
610 reg = <33>;
611 };
612
613 twi2_clk: twi2_clk {
614 #clock-cells = <0>;
615 reg = <34>;
616 };
617
618 mci0_clk: mci0_clk {
619 #clock-cells = <0>;
620 reg = <35>;
621 };
622
623 mci1_clk: mci1_clk {
624 #clock-cells = <0>;
625 reg = <36>;
626 };
627
628 spi0_clk: spi0_clk {
629 #clock-cells = <0>;
630 reg = <37>;
631 };
632
633 spi1_clk: spi1_clk {
634 #clock-cells = <0>;
635 reg = <38>;
636 };
637
638 spi2_clk: spi2_clk {
639 #clock-cells = <0>;
640 reg = <39>;
641 };
642
643 tcb0_clk: tcb0_clk {
644 #clock-cells = <0>;
645 reg = <40>;
646 };
647
648 tcb1_clk: tcb1_clk {
649 #clock-cells = <0>;
650 reg = <41>;
651 };
652
653 tcb2_clk: tcb2_clk {
654 #clock-cells = <0>;
655 reg = <42>;
656 };
657
658 pwm_clk: pwm_clk {
659 #clock-cells = <0>;
660 reg = <43>;
661 };
662
663 adc_clk: adc_clk {
664 #clock-cells = <0>;
665 reg = <44>;
666 };
667
668 dbgu_clk: dbgu_clk {
669 #clock-cells = <0>;
670 reg = <45>;
671 };
672
673 uhphs_clk: uhphs_clk {
674 #clock-cells = <0>;
675 reg = <46>;
676 };
677
678 udphs_clk: udphs_clk {
679 #clock-cells = <0>;
680 reg = <47>;
681 };
682
683 ssc0_clk: ssc0_clk {
684 #clock-cells = <0>;
685 reg = <48>;
686 };
687
688 ssc1_clk: ssc1_clk {
689 #clock-cells = <0>;
690 reg = <49>;
691 };
692
693 trng_clk: trng_clk {
694 #clock-cells = <0>;
695 reg = <53>;
696 };
697
698 macb0_clk: macb0_clk {
699 #clock-cells = <0>;
700 reg = <54>;
701 };
702
703 macb1_clk: macb1_clk {
704 #clock-cells = <0>;
705 reg = <55>;
706 };
707
708 fuse_clk: fuse_clk {
709 #clock-cells = <0>;
710 reg = <57>;
711 };
712
713 securam_clk: securam_clk {
714 #clock-cells = <0>;
715 reg = <59>;
716 };
717
718 smd_clk: smd_clk {
719 #clock-cells = <0>;
720 reg = <61>;
721 };
722
723 twi3_clk: twi3_clk {
724 #clock-cells = <0>;
725 reg = <62>;
726 };
727
728 catb_clk: catb_clk {
729 #clock-cells = <0>;
730 reg = <63>;
731 };
732 };
733
734 periph64ck {
735 compatible = "atmel,at91sam9x5-clk-peripheral";
736 #address-cells = <1>;
737 #size-cells = <0>;
738 clocks = <&mck>;
739
740 dma0_clk: dma0_clk {
741 #clock-cells = <0>;
742 reg = <8>;
743 };
744
745 cpkcc_clk: cpkcc_clk {
746 #clock-cells = <0>;
747 reg = <10>;
748 };
749
750 aesb_clk: aesb_clk {
751 #clock-cells = <0>;
752 reg = <13>;
753 };
754
755 mpddr_clk: mpddr_clk {
756 #clock-cells = <0>;
757 reg = <16>;
758 };
759
760 matrix0_clk: matrix0_clk {
761 #clock-cells = <0>;
762 reg = <18>;
763 };
764
765 vdec_clk: vdec_clk {
766 #clock-cells = <0>;
767 reg = <19>;
768 };
769
770 dma1_clk: dma1_clk {
771 #clock-cells = <0>;
772 reg = <50>;
773 };
774
775 lcd_clk: lcd_clk {
776 #clock-cells = <0>;
777 reg = <51>;
778 };
779
780 isi_clk: isi_clk {
781 #clock-cells = <0>;
782 reg = <52>;
783 };
784 };
785 };
786
787 mmc0: mmc@f8000000 {
788 compatible = "atmel,hsmci";
789 reg = <0xf8000000 0x600>;
790 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
b3c7a497
LD		 791 dmas = <&dma1
792 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
793 | AT91_XDMAC_DT_PERID(0))>;
794 dma-names = "rxtx";
7c661394
NF		 795 pinctrl-names = "default";
796 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
797 status = "disabled";
798 #address-cells = <1>;
799 #size-cells = <0>;
800 clocks = <&mci0_clk>;
801 clock-names = "mci_clk";
802 };
803
804 spi0: spi@f8010000 {
805 #address-cells = <1>;
806 #size-cells = <0>;
807 compatible = "atmel,at91rm9200-spi";
808 reg = <0xf8010000 0x100>;
809 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
b3c7a497
LD		 810 dmas = <&dma1
811 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
812 | AT91_XDMAC_DT_PERID(10))>,
813 <&dma1
814 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
815 | AT91_XDMAC_DT_PERID(11))>;
816 dma-names = "tx", "rx";
7c661394
NF		 817 pinctrl-names = "default";
818 pinctrl-0 = <&pinctrl_spi0>;
819 clocks = <&spi0_clk>;
820 clock-names = "spi_clk";
821 status = "disabled";
822 };
823
824 i2c0: i2c@f8014000 {
825 compatible = "atmel,at91sam9x5-i2c";
826 reg = <0xf8014000 0x4000>;
827 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
b3c7a497
LD		 828 dmas = <&dma1
829 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
830 | AT91_XDMAC_DT_PERID(2))>,
831 <&dma1
832 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
833 | AT91_XDMAC_DT_PERID(3))>;
834 dma-names = "tx", "rx";
7c661394
NF		 835 pinctrl-names = "default";
836 pinctrl-0 = <&pinctrl_i2c0>;
837 #address-cells = <1>;
838 #size-cells = <0>;
839 clocks = <&twi0_clk>;
840 status = "disabled";
841 };
842
4cc7cdf3
PA		 843 i2c1: i2c@f8018000 {
844 compatible = "atmel,at91sam9x5-i2c";
845 reg = <0xf8018000 0x4000>;
846 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
847 dmas = <&dma1
848 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
849 AT91_XDMAC_DT_PERID(4)>,
850 <&dma1
851 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
852 AT91_XDMAC_DT_PERID(5)>;
853 dma-names = "tx", "rx";
854 pinctrl-names = "default";
855 pinctrl-0 = <&pinctrl_i2c1>;
856 #address-cells = <1>;
857 #size-cells = <0>;
858 clocks = <&twi1_clk>;
859 status = "disabled";
860 };
861
7c661394
NF		 862 tcb0: timer@f801c000 {
863 compatible = "atmel,at91sam9x5-tcb";
864 reg = <0xf801c000 0x100>;
865 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
866 clocks = <&tcb0_clk>;
867 clock-names = "t0_clk";
868 };
869
870 macb0: ethernet@f8020000 {
871 compatible = "atmel,sama5d4-gem";
872 reg = <0xf8020000 0x100>;
873 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
874 pinctrl-names = "default";
875 pinctrl-0 = <&pinctrl_macb0_rmii>;
9917defd
JW		 876 #address-cells = <1>;
877 #size-cells = <0>;
7c661394
NF		 878 clocks = <&macb0_clk>, <&macb0_clk>;
879 clock-names = "hclk", "pclk";
880 status = "disabled";
881 };
882
883 i2c2: i2c@f8024000 {
884 compatible = "atmel,at91sam9x5-i2c";
885 reg = <0xf8024000 0x4000>;
84f017a7 886 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
b3c7a497
LD		 887 dmas = <&dma1
888 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
889 | AT91_XDMAC_DT_PERID(6))>,
890 <&dma1
891 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
892 | AT91_XDMAC_DT_PERID(7))>;
893 dma-names = "tx", "rx";
7c661394
NF		 894 pinctrl-names = "default";
895 pinctrl-0 = <&pinctrl_i2c2>;
896 #address-cells = <1>;
897 #size-cells = <0>;
898 clocks = <&twi2_clk>;
899 status = "disabled";
900 };
901
c3ef0b0c
AB		 902 sfr: sfr@f8028000 {
903 compatible = "atmel,sama5d4-sfr", "syscon";
904 reg = <0xf8028000 0x60>;
905 };
906
7c661394
NF		 907 mmc1: mmc@fc000000 {
908 compatible = "atmel,hsmci";
909 reg = <0xfc000000 0x600>;
910 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
b3c7a497
LD		 911 dmas = <&dma1
912 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
913 | AT91_XDMAC_DT_PERID(1))>;
914 dma-names = "rxtx";
7c661394
NF		 915 pinctrl-names = "default";
916 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
917 status = "disabled";
918 #address-cells = <1>;
919 #size-cells = <0>;
920 clocks = <&mci1_clk>;
921 clock-names = "mci_clk";
922 };
923
924 usart2: serial@fc008000 {
925 compatible = "atmel,at91sam9260-usart";
926 reg = <0xfc008000 0x100>;
927 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
b3c7a497
LD		 928 dmas = <&dma1
929 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
930 | AT91_XDMAC_DT_PERID(16))>,
931 <&dma1
932 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
933 | AT91_XDMAC_DT_PERID(17))>;
934 dma-names = "tx", "rx";
7c661394
NF		 935 pinctrl-names = "default";
936 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
937 clocks = <&usart2_clk>;
938 clock-names = "usart";
939 status = "disabled";
940 };
941
942 usart3: serial@fc00c000 {
943 compatible = "atmel,at91sam9260-usart";
944 reg = <0xfc00c000 0x100>;
945 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
b3c7a497
LD		 946 dmas = <&dma1
947 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
948 | AT91_XDMAC_DT_PERID(18))>,
949 <&dma1
950 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
951 | AT91_XDMAC_DT_PERID(19))>;
952 dma-names = "tx", "rx";
7c661394
NF		 953 pinctrl-names = "default";
954 pinctrl-0 = <&pinctrl_usart3>;
955 clocks = <&usart3_clk>;
956 clock-names = "usart";
957 status = "disabled";
958 };
959
960 usart4: serial@fc010000 {
961 compatible = "atmel,at91sam9260-usart";
962 reg = <0xfc010000 0x100>;
963 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
b3c7a497
LD		 964 dmas = <&dma1
965 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
966 | AT91_XDMAC_DT_PERID(20))>,
967 <&dma1
968 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
969 | AT91_XDMAC_DT_PERID(21))>;
970 dma-names = "tx", "rx";
7c661394
NF		 971 pinctrl-names = "default";
972 pinctrl-0 = <&pinctrl_usart4>;
973 clocks = <&usart4_clk>;
974 clock-names = "usart";
975 status = "disabled";
976 };
977
978 tcb1: timer@fc020000 {
979 compatible = "atmel,at91sam9x5-tcb";
980 reg = <0xfc020000 0x100>;
981 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
982 clocks = <&tcb1_clk>;
983 clock-names = "t0_clk";
984 };
985
986 adc0: adc@fc034000 {
987 compatible = "atmel,at91sam9x5-adc";
988 reg = <0xfc034000 0x100>;
989 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
990 pinctrl-names = "default";
991 pinctrl-0 = <
992 /* external trigger is conflict with USBA_VBUS */
993 &pinctrl_adc0_ad0
994 &pinctrl_adc0_ad1
995 &pinctrl_adc0_ad2
996 &pinctrl_adc0_ad3
997 &pinctrl_adc0_ad4
998 >;
999 clocks = <&adc_clk>,
1000 <&adc_op_clk>;
1001 clock-names = "adc_clk", "adc_op_clk";
1002 atmel,adc-channels-used = <0x01f>;
1003 atmel,adc-startup-time = <40>;
1004 atmel,adc-use-external;
1005 atmel,adc-vref = <3000>;
1006 atmel,adc-res = <8 10>;
1007 atmel,adc-sample-hold-time = <11>;
1008 atmel,adc-res-names = "lowres", "highres";
1009 atmel,adc-ts-pressure-threshold = <10000>;
1010 status = "disabled";
1011
1012 trigger@0 {
1013 trigger-name = "external-rising";
1014 trigger-value = <0x1>;
1015 trigger-external;
1016 };
1017 trigger@1 {
1018 trigger-name = "external-falling";
1019 trigger-value = <0x2>;
1020 trigger-external;
1021 };
1022 trigger@2 {
1023 trigger-name = "external-any";
1024 trigger-value = <0x3>;
1025 trigger-external;
1026 };
1027 trigger@3 {
1028 trigger-name = "continuous";
1029 trigger-value = <0x6>;
1030 };
1031 };
1032
1033 rstc@fc068600 {
1034 compatible = "atmel,at91sam9g45-rstc";
1035 reg = <0xfc068600 0x10>;
1036 };
1037
1038 shdwc@fc068610 {
1039 compatible = "atmel,at91sam9x5-shdwc";
1040 reg = <0xfc068610 0x10>;
1041 };
1042
1043 pit: timer@fc068630 {
1044 compatible = "atmel,at91sam9260-pit";
0068b2e1 1045 reg = <0xfc068630 0x10>;
7c661394
NF		 1046 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1047 clocks = <&h32ck>;
1048 };
1049
1050 watchdog@fc068640 {
1051 compatible = "atmel,at91sam9260-wdt";
1052 reg = <0xfc068640 0x10>;
1053 status = "disabled";
1054 };
1055
1056 sckc@fc068650 {
1057 compatible = "atmel,at91sam9x5-sckc";
1058 reg = <0xfc068650 0x4>;
1059
1060 slow_rc_osc: slow_rc_osc {
1061 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1062 #clock-cells = <0>;
1063 clock-frequency = <32768>;
1064 clock-accuracy = <250000000>;
1065 atmel,startup-time-usec = <75>;
1066 };
1067
1068 slow_osc: slow_osc {
1069 compatible = "atmel,at91sam9x5-clk-slow-osc";
1070 #clock-cells = <0>;
1071 clocks = <&slow_xtal>;
1072 atmel,startup-time-usec = <1200000>;
1073 };
1074
1075 clk32k: slowck {
1076 compatible = "atmel,at91sam9x5-clk-slow";
1077 #clock-cells = <0>;
1078 clocks = <&slow_rc_osc &slow_osc>;
1079 };
1080 };
1081
1082 rtc@fc0686b0 {
1083 compatible = "atmel,at91rm9200-rtc";
1084 reg = <0xfc0686b0 0x30>;
1085 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1086 };
1087
1088 dbgu: serial@fc069000 {
1089 compatible = "atmel,at91sam9260-usart";
1090 reg = <0xfc069000 0x200>;
1091 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
1092 pinctrl-names = "default";
1093 pinctrl-0 = <&pinctrl_dbgu>;
1094 clocks = <&dbgu_clk>;
1095 clock-names = "usart";
1096 status = "disabled";
1097 };
1098
1099
1100 pinctrl@fc06a000 {
1101 #address-cells = <1>;
1102 #size-cells = <1>;
1103 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1104 ranges = <0xfc06a000 0xfc06a000 0x4000>;
1105 /* WARNING: revisit as pin spec has changed */
1106 atmel,mux-mask = <
1107 /* A B C */
1108 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1109 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1110 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1111 0x00000000 0x00000000 0x00000000 /* pioD */
1112 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1113 >;
1114
1115 pioA: gpio@fc06a000 {
1116 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1117 reg = <0xfc06a000 0x100>;
1118 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1119 #gpio-cells = <2>;
1120 gpio-controller;
1121 interrupt-controller;
1122 #interrupt-cells = <2>;
1123 clocks = <&pioA_clk>;
1124 };
1125
1126 pioB: gpio@fc06b000 {
1127 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1128 reg = <0xfc06b000 0x100>;
1129 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1130 #gpio-cells = <2>;
1131 gpio-controller;
1132 interrupt-controller;
1133 #interrupt-cells = <2>;
1134 clocks = <&pioB_clk>;
1135 };
1136
1137 pioC: gpio@fc06c000 {
1138 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1139 reg = <0xfc06c000 0x100>;
1140 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1141 #gpio-cells = <2>;
1142 gpio-controller;
1143 interrupt-controller;
1144 #interrupt-cells = <2>;
1145 clocks = <&pioC_clk>;
1146 };
1147
1de77b7f
LD		 1148 pioD: gpio@fc068000 {
1149 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1150 reg = <0xfc068000 0x100>;
1151 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1152 #gpio-cells = <2>;
1153 gpio-controller;
1154 interrupt-controller;
1155 #interrupt-cells = <2>;
1156 clocks = <&pioD_clk>;
1157 status = "disabled";
1158 };
1159
7c661394
NF		 1160 pioE: gpio@fc06d000 {
1161 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1162 reg = <0xfc06d000 0x100>;
1163 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1164 #gpio-cells = <2>;
1165 gpio-controller;
1166 interrupt-controller;
1167 #interrupt-cells = <2>;
1168 clocks = <&pioE_clk>;
1169 };
1170
1171 /* pinctrl pin settings */
1172 adc0 {
1173 pinctrl_adc0_adtrg: adc0_adtrg {
1174 atmel,pins =
1175 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1176 };
1177 pinctrl_adc0_ad0: adc0_ad0 {
1178 atmel,pins =
1179 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1180 };
1181 pinctrl_adc0_ad1: adc0_ad1 {
1182 atmel,pins =
1183 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1184 };
1185 pinctrl_adc0_ad2: adc0_ad2 {
1186 atmel,pins =
1187 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1188 };
1189 pinctrl_adc0_ad3: adc0_ad3 {
1190 atmel,pins =
1191 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1192 };
1193 pinctrl_adc0_ad4: adc0_ad4 {
1194 atmel,pins =
1195 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1196 };
1197 };
1198
1199 dbgu {
1200 pinctrl_dbgu: dbgu-0 {
1201 atmel,pins =
1202 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
1203 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
1204 };
1205 };
1206
1207 i2c0 {
1208 pinctrl_i2c0: i2c0-0 {
1209 atmel,pins =
1210 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1211 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1212 };
1213 };
1214
4cc7cdf3
PA		 1215 i2c1 {
1216 pinctrl_i2c1: i2c1-0 {
1217 atmel,pins =
1218 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
1219 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1220 };
1221 };
1222
7c661394
NF		 1223 i2c2 {
1224 pinctrl_i2c2: i2c2-0 {
1225 atmel,pins =
1226 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1227 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1228 };
1229 };
1230
1231 macb0 {
1232 pinctrl_macb0_rmii: macb0_rmii-0 {
1233 atmel,pins =
1234 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1235 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1236 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1237 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1238 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1239 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1240 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1241 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1242 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1243 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1244 >;
1245 };
1246 };
1247
1248 mmc0 {
1249 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1250 atmel,pins =
1251 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1252 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1253 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1254 >;
1255 };
1256 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1257 atmel,pins =
1258 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1259 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1260 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1261 >;
1262 };
1263 };
1264
1265 mmc1 {
1266 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1267 atmel,pins =
1268 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1269 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1270 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1271 >;
1272 };
1273 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1274 atmel,pins =
1275 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1276 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1277 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1278 >;
1279 };
1280 };
1281
1282 nand0 {
1283 pinctrl_nand: nand-0 {
1284 atmel,pins =
1285 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1286 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1287
1288 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1289 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1290
1291 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1292 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1293 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1294 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1295 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1296 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1297 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1298 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1299 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1300 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1301 };
1302 };
1303
1304 spi0 {
1305 pinctrl_spi0: spi0-0 {
1306 atmel,pins =
1307 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1308 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1309 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1310 >;
1311 };
1312 };
1313
1314 usart2 {
1315 pinctrl_usart2: usart2-0 {
1316 atmel,pins =
1317 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1318 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
1319 >;
1320 };
1321 pinctrl_usart2_rts: usart2_rts-0 {
1322 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1323 };
1324 pinctrl_usart2_cts: usart2_cts-0 {
1325 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1326 };
1327 };
1328
1329 usart3 {
1330 pinctrl_usart3: usart3-0 {
1331 atmel,pins =
1332 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1333 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1334 >;
1335 };
1336 };
1337
1338 usart4 {
1339 pinctrl_usart4: usart4-0 {
1340 atmel,pins =
1341 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1342 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1343 >;
1344 };
1345 pinctrl_usart4_rts: usart4_rts-0 {
1346 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1347 };
1348 pinctrl_usart4_cts: usart4_cts-0 {
1349 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1350 };
1351 };
1352 };
1353
1354 aic: interrupt-controller@fc06e000 {
1355 #interrupt-cells = <3>;
1356 compatible = "atmel,sama5d4-aic";
1357 interrupt-controller;
1358 reg = <0xfc06e000 0x200>;
1359 atmel,external-irqs = <56>;
1360 };
1361 };
1362 };
1363};
Linux kernel - Deliverables
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