[deliverable/linux.git] / arch / arm / boot / dts / sh73a0.dtsi

/*
 * Device Tree Source for the SH73A0 SoC
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/include/ "skeleton.dtsi"

#include <dt-bindings/clock/sh73a0-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,sh73a0";
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <1196000000>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clock-frequency = <1196000000>;
		};
	};

	gic: interrupt-controller@f0001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xf0001000 0x1000>,
		      <0xf0000100 0x100>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
			     <0 56 IRQ_TYPE_LEVEL_HIGH>;
	};

	cmt1: timer@e6138000 {
		compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
		reg = <0xe6138000 0x200>;
		interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;

		renesas,channels-mask = <0x3f>;

		status = "disabled";
	};

	irqpin0: irqpin@e6900000 {
		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe6900000 4>,
			<0xe6900010 4>,
			<0xe6900020 1>,
			<0xe6900040 1>,
			<0xe6900060 1>;
		interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
			      0 2 IRQ_TYPE_LEVEL_HIGH
			      0 3 IRQ_TYPE_LEVEL_HIGH
			      0 4 IRQ_TYPE_LEVEL_HIGH
			      0 5 IRQ_TYPE_LEVEL_HIGH
			      0 6 IRQ_TYPE_LEVEL_HIGH
			      0 7 IRQ_TYPE_LEVEL_HIGH
			      0 8 IRQ_TYPE_LEVEL_HIGH>;
	};

	irqpin1: irqpin@e6900004 {
		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe6900004 4>,
			<0xe6900014 4>,
			<0xe6900024 1>,
			<0xe6900044 1>,
			<0xe6900064 1>;
		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
			      0 10 IRQ_TYPE_LEVEL_HIGH
			      0 11 IRQ_TYPE_LEVEL_HIGH
			      0 12 IRQ_TYPE_LEVEL_HIGH
			      0 13 IRQ_TYPE_LEVEL_HIGH
			      0 14 IRQ_TYPE_LEVEL_HIGH
			      0 15 IRQ_TYPE_LEVEL_HIGH
			      0 16 IRQ_TYPE_LEVEL_HIGH>;
		control-parent;
	};

	irqpin2: irqpin@e6900008 {
		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe6900008 4>,
			<0xe6900018 4>,
			<0xe6900028 1>,
			<0xe6900048 1>,
			<0xe6900068 1>;
		interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
			      0 18 IRQ_TYPE_LEVEL_HIGH
			      0 19 IRQ_TYPE_LEVEL_HIGH
			      0 20 IRQ_TYPE_LEVEL_HIGH
			      0 21 IRQ_TYPE_LEVEL_HIGH
			      0 22 IRQ_TYPE_LEVEL_HIGH
			      0 23 IRQ_TYPE_LEVEL_HIGH
			      0 24 IRQ_TYPE_LEVEL_HIGH>;
	};

	irqpin3: irqpin@e690000c {
		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe690000c 4>,
			<0xe690001c 4>,
			<0xe690002c 1>,
			<0xe690004c 1>,
			<0xe690006c 1>;
		interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
			      0 26 IRQ_TYPE_LEVEL_HIGH
			      0 27 IRQ_TYPE_LEVEL_HIGH
			      0 28 IRQ_TYPE_LEVEL_HIGH
			      0 29 IRQ_TYPE_LEVEL_HIGH
			      0 30 IRQ_TYPE_LEVEL_HIGH
			      0 31 IRQ_TYPE_LEVEL_HIGH
			      0 32 IRQ_TYPE_LEVEL_HIGH>;
	};

	i2c0: i2c@e6820000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6820000 0x425>;
		interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
			      0 168 IRQ_TYPE_LEVEL_HIGH
			      0 169 IRQ_TYPE_LEVEL_HIGH
			      0 170 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	i2c1: i2c@e6822000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6822000 0x425>;
		interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
			      0 52 IRQ_TYPE_LEVEL_HIGH
			      0 53 IRQ_TYPE_LEVEL_HIGH
			      0 54 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	i2c2: i2c@e6824000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6824000 0x425>;
		interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
			      0 172 IRQ_TYPE_LEVEL_HIGH
			      0 173 IRQ_TYPE_LEVEL_HIGH
			      0 174 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	i2c3: i2c@e6826000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6826000 0x425>;
		interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
			      0 184 IRQ_TYPE_LEVEL_HIGH
			      0 185 IRQ_TYPE_LEVEL_HIGH
			      0 186 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	i2c4: i2c@e6828000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6828000 0x425>;
		interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
			      0 188 IRQ_TYPE_LEVEL_HIGH
			      0 189 IRQ_TYPE_LEVEL_HIGH
			      0 190 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	mmcif: mmc@e6bd0000 {
		compatible = "renesas,sh-mmcif";
		reg = <0xe6bd0000 0x100>;
		interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
			      0 141 IRQ_TYPE_LEVEL_HIGH>;
		reg-io-width = <4>;
		status = "disabled";
	};

	sdhi0: sd@ee100000 {
		compatible = "renesas,sdhi-sh73a0";
		reg = <0xee100000 0x100>;
		interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
			      0 84 IRQ_TYPE_LEVEL_HIGH
			      0 85 IRQ_TYPE_LEVEL_HIGH>;
		cap-sd-highspeed;
		status = "disabled";
	};

	/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
	sdhi1: sd@ee120000 {
		compatible = "renesas,sdhi-sh73a0";
		reg = <0xee120000 0x100>;
		interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
			      0 89 IRQ_TYPE_LEVEL_HIGH>;
		toshiba,mmc-wrprotect-disable;
		cap-sd-highspeed;
		status = "disabled";
	};

	sdhi2: sd@ee140000 {
		compatible = "renesas,sdhi-sh73a0";
		reg = <0xee140000 0x100>;
		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
			      0 105 IRQ_TYPE_LEVEL_HIGH>;
		toshiba,mmc-wrprotect-disable;
		cap-sd-highspeed;
		status = "disabled";
	};

	scifa0: serial@e6c40000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c40000 0x100>;
		interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	scifa1: serial@e6c50000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c50000 0x100>;
		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	scifa2: serial@e6c60000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c60000 0x100>;
		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	scifa3: serial@e6c70000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c70000 0x100>;
		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	scifa4: serial@e6c80000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c80000 0x100>;
		interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	scifa5: serial@e6cb0000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6cb0000 0x100>;
		interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	scifa6: serial@e6cc0000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6cc0000 0x100>;
		interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	scifa7: serial@e6cd0000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6cd0000 0x100>;
		interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	scifb8: serial@e6c30000 {
		compatible = "renesas,scifb-sh73a0", "renesas,scifb";
		reg = <0xe6c30000 0x100>;
		interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	pfc: pfc@e6050000 {
		compatible = "renesas,pfc-sh73a0";
		reg = <0xe6050000 0x8000>,
		      <0xe605801c 0x1c>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupts-extended =
			<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
			<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
			<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
			<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
			<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
			<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
			<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
			<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
	};

	sh_fsi2: sound@ec230000 {
		#sound-dai-cells = <1>;
		compatible = "renesas,sh_fsi2";
		reg = <0xec230000 0x400>;
		interrupts = <0 146 0x4>;
		status = "disabled";
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* External root clocks */
		extalr_clk: extalr_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "extalr";
		};
		extal1_clk: extal1_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <26000000>;
			clock-output-names = "extal1";
		};
		extal2_clk: extal2_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-output-names = "extal2";
		};
		extcki_clk: extcki_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-output-names = "extcki";
		};
		fsiack_clk: fsiack_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "fsiack";
		};
		fsibck_clk: fsibck_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "fsibck";
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@e6150000 {
			compatible = "renesas,sh73a0-cpg-clocks";
			reg = <0xe6150000 0x10000>;
			clocks = <&extal1_clk>, <&extal2_clk>;
			#clock-cells = <1>;
			clock-output-names = "main", "pll0", "pll1", "pll2",
					     "pll3", "dsi0phy", "dsi1phy",
					     "zg", "m3", "b", "m1", "m2",
					     "z", "zx", "hp";
		};

		/* Variable factor clocks (DIV6) */
		vclk1_clk: vclk1_clk@e6150008 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150008 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "vclk1";
		};
		vclk2_clk: vclk2_clk@e615000c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615000c 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "vclk2";
		};
		vclk3_clk: vclk3_clk@e615001c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615001c 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "vclk3";
		};
		zb_clk: zb_clk@e6150010 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150010 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "zb";
		};
		flctl_clk: flctl_clk@e6150014 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150014 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "flctlck";
		};
		sdhi0_clk: sdhi0_clk@e6150074 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150074 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "sdhi0ck";
		};
		sdhi1_clk: sdhi1_clk@e6150078 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150078 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "sdhi1ck";
		};
		sdhi2_clk: sdhi2_clk@e615007c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615007c 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "sdhi2ck";
		};
		fsia_clk: fsia_clk@e6150018 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150018 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "fsia";
		};
		fsib_clk: fsib_clk@e6150090 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150090 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "fsib";
		};
		sub_clk: sub_clk@e6150080 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150080 4>;
			clocks = <&extal2_clk>;
			#clock-cells = <0>;
			clock-output-names = "sub";
		};
		spua_clk: spua_clk@e6150084 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150084 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "spua";
		};
		spuv_clk: spuv_clk@e6150094 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150094 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "spuv";
		};
		msu_clk: msu_clk@e6150088 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150088 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "msu";
		};
		hsi_clk: hsi_clk@e615008c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615008c 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "hsi";
		};
		mfg1_clk: mfg1_clk@e6150098 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150098 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "mfg1";
		};
		mfg2_clk: mfg2_clk@e615009c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615009c 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "mfg2";
		};
		dsit_clk: dsit_clk@e6150060 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150060 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "dsit";
		};
		dsi0p_clk: dsi0p_clk@e6150064 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150064 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "dsi0pck";
		};

		/* Fixed factor clocks */
		main_div2_clk: main_div2_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "main_div2";
		};
		pll1_div2_clk: pll1_div2_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "pll1_div2";
		};
		pll1_div7_clk: pll1_div7_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <7>;
			clock-mult = <1>;
			clock-output-names = "pll1_div7";
		};
		pll1_div13_clk: pll1_div13_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <13>;
			clock-mult = <1>;
			clock-output-names = "pll1_div13";
		};
		twd_clk: twd_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_Z>;
			#clock-cells = <0>;
			clock-div = <4>;
			clock-mult = <1>;
			clock-output-names = "twd";
		};

		/* Gate clocks */
		mstp0_clks: mstp0_clks@e6150130 {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150130 4>, <0xe6150030 4>;
			clocks = <&cpg_clocks SH73A0_CLK_HP>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_IIC2
			>;
			clock-output-names =
				"iic2";
		};
		mstp1_clks: mstp1_clks@e6150134 {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150134 4>, <0xe6150038 4>;
			clocks = <&cpg_clocks SH73A0_CLK_B>,
				 <&cpg_clocks SH73A0_CLK_B>,
				 <&cpg_clocks SH73A0_CLK_B>,
				 <&cpg_clocks SH73A0_CLK_B>,
				 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
				 <&cpg_clocks SH73A0_CLK_HP>,
				 <&cpg_clocks SH73A0_CLK_ZG>,
				 <&cpg_clocks SH73A0_CLK_B>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
				SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
				SH73A0_CLK_TMU0	SH73A0_CLK_DSITX0
				SH73A0_CLK_IIC0 SH73A0_CLK_SGX
				SH73A0_CLK_LCDC0
			>;
			clock-output-names =
				"ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
				"tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
		};
		mstp2_clks: mstp2_clks@e6150138 {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150138 4>, <0xe6150040 4>;
			clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
				 <&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>,
				 <&sub_clk>, <&sub_clk>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
				SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5
				SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0
				SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2
				SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4
			>;
			clock-output-names =
				"scifa7", "sy_dmac", "mp_dmac", "scifa5",
				"scifb", "scifa0", "scifa1", "scifa2",
				"scifa3", "scifa4";
		};
		mstp3_clks: mstp3_clks@e615013c {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe615013c 4>, <0xe6150048 4>;
			clocks = <&sub_clk>, <&extalr_clk>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
				 <&cpg_clocks SH73A0_CLK_HP>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
				 <&sdhi0_clk>, <&sdhi1_clk>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
				 <&main_div2_clk>, <&main_div2_clk>,
				 <&main_div2_clk>, <&main_div2_clk>,
				 <&main_div2_clk>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
				SH73A0_CLK_FSI SH73A0_CLK_IRDA
				SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
				SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
				SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
				SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
				SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
				SH73A0_CLK_TPU4
			>;
			clock-output-names =
				"scifa6", "cmt1", "fsi", "irda", "iic1",
				"usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
				"tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
		};
		mstp4_clks: mstp4_clks@e6150140 {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150140 4>, <0xe615004c 4>;
			clocks = <&cpg_clocks SH73A0_CLK_HP>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
				SH73A0_CLK_KEYSC
			>;
			clock-output-names =
				"iic3", "iic4", "keysc";
		};
	};
};
Commit	Line	Data
a3f22db5 SH	1	/*
	2	* Device Tree Source for the SH73A0 SoC
	3	*
	4	* Copyright (C) 2012 Renesas Solutions Corp.
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
	11	/include/ "skeleton.dtsi"
	12
00df6113	13	#include <dt-bindings/clock/sh73a0-clock.h>
5f75e73c LP	14	#include <dt-bindings/interrupt-controller/irq.h>
5f75e73c LP	15
a3f22db5 SH	16	/ {
a3f22db5 SH	17	compatible = "renesas,sh73a0";
f170b97c	18	interrupt-parent = <&gic>;
a3f22db5 SH	19
a3f22db5 SH	20	cpus {
c5795aec SH	21	#address-cells = <1>;
	22	#size-cells = <0>;
	23
a3f22db5	24	cpu@0 {
c5795aec	25	device_type = "cpu";
a3f22db5	26	compatible = "arm,cortex-a9";
c5795aec	27	reg = <0>;
13bd825b	28	clock-frequency = <1196000000>;
a3f22db5 SH	29	};
a3f22db5 SH	30	cpu@1 {
c5795aec	31	device_type = "cpu";
a3f22db5	32	compatible = "arm,cortex-a9";
c5795aec	33	reg = <1>;
13bd825b	34	clock-frequency = <1196000000>;
a3f22db5 SH	35	};
	36	};
	37
	38	gic: interrupt-controller@f0001000 {
	39	compatible = "arm,cortex-a9-gic";
	40	#interrupt-cells = <3>;
a3f22db5 SH	41	interrupt-controller;
	42	reg = <0xf0001000 0x1000>,
	43	<0xf0000100 0x100>;
	44	};
48609533	45
4c90483a MD	46	pmu {
4c90483a MD	47	compatible = "arm,cortex-a9-pmu";
5f75e73c LP	48	interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
5f75e73c LP	49	<0 56 IRQ_TYPE_LEVEL_HIGH>;
4c90483a MD	50	};
4c90483a MD	51
6a5336a7 UH	52	cmt1: timer@e6138000 {
	53	compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
	54	reg = <0xe6138000 0x200>;
	55	interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
	56
	57	renesas,channels-mask = <0x3f>;
	58
	59	status = "disabled";
	60	};
	61
558f8740	62	irqpin0: irqpin@e6900000 {
8bb44445	63	compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
558f8740 GL	64	#interrupt-cells = <2>;
	65	interrupt-controller;
	66	reg = <0xe6900000 4>,
	67	<0xe6900010 4>,
	68	<0xe6900020 1>,
	69	<0xe6900040 1>,
	70	<0xe6900060 1>;
5f75e73c LP	71	interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
	72	0 2 IRQ_TYPE_LEVEL_HIGH
	73	0 3 IRQ_TYPE_LEVEL_HIGH
	74	0 4 IRQ_TYPE_LEVEL_HIGH
	75	0 5 IRQ_TYPE_LEVEL_HIGH
	76	0 6 IRQ_TYPE_LEVEL_HIGH
	77	0 7 IRQ_TYPE_LEVEL_HIGH
	78	0 8 IRQ_TYPE_LEVEL_HIGH>;
558f8740 GL	79	};
	80
	81	irqpin1: irqpin@e6900004 {
8bb44445	82	compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
558f8740 GL	83	#interrupt-cells = <2>;
	84	interrupt-controller;
	85	reg = <0xe6900004 4>,
	86	<0xe6900014 4>,
	87	<0xe6900024 1>,
	88	<0xe6900044 1>,
	89	<0xe6900064 1>;
5f75e73c LP	90	interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
	91	0 10 IRQ_TYPE_LEVEL_HIGH
	92	0 11 IRQ_TYPE_LEVEL_HIGH
	93	0 12 IRQ_TYPE_LEVEL_HIGH
	94	0 13 IRQ_TYPE_LEVEL_HIGH
	95	0 14 IRQ_TYPE_LEVEL_HIGH
	96	0 15 IRQ_TYPE_LEVEL_HIGH
	97	0 16 IRQ_TYPE_LEVEL_HIGH>;
558f8740 GL	98	control-parent;
	99	};
	100
	101	irqpin2: irqpin@e6900008 {
8bb44445	102	compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
558f8740 GL	103	#interrupt-cells = <2>;
	104	interrupt-controller;
	105	reg = <0xe6900008 4>,
	106	<0xe6900018 4>,
	107	<0xe6900028 1>,
	108	<0xe6900048 1>,
	109	<0xe6900068 1>;
5f75e73c LP	110	interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
	111	0 18 IRQ_TYPE_LEVEL_HIGH
	112	0 19 IRQ_TYPE_LEVEL_HIGH
	113	0 20 IRQ_TYPE_LEVEL_HIGH
	114	0 21 IRQ_TYPE_LEVEL_HIGH
	115	0 22 IRQ_TYPE_LEVEL_HIGH
	116	0 23 IRQ_TYPE_LEVEL_HIGH
	117	0 24 IRQ_TYPE_LEVEL_HIGH>;
558f8740 GL	118	};
	119
	120	irqpin3: irqpin@e690000c {
8bb44445	121	compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
558f8740 GL	122	#interrupt-cells = <2>;
	123	interrupt-controller;
	124	reg = <0xe690000c 4>,
	125	<0xe690001c 4>,
	126	<0xe690002c 1>,
	127	<0xe690004c 1>,
	128	<0xe690006c 1>;
5f75e73c LP	129	interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
	130	0 26 IRQ_TYPE_LEVEL_HIGH
	131	0 27 IRQ_TYPE_LEVEL_HIGH
	132	0 28 IRQ_TYPE_LEVEL_HIGH
	133	0 29 IRQ_TYPE_LEVEL_HIGH
	134	0 30 IRQ_TYPE_LEVEL_HIGH
	135	0 31 IRQ_TYPE_LEVEL_HIGH
	136	0 32 IRQ_TYPE_LEVEL_HIGH>;
558f8740 GL	137	};
558f8740 GL	138
561a1a31	139	i2c0: i2c@e6820000 {
48609533 SH	140	#address-cells = <1>;
48609533 SH	141	#size-cells = <0>;
dd4dc874	142	compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
48609533	143	reg = <0xe6820000 0x425>;
5f75e73c LP	144	interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
	145	0 168 IRQ_TYPE_LEVEL_HIGH
	146	0 169 IRQ_TYPE_LEVEL_HIGH
	147	0 170 IRQ_TYPE_LEVEL_HIGH>;
eda3a4fa	148	status = "disabled";
48609533 SH	149	};
48609533 SH	150
561a1a31	151	i2c1: i2c@e6822000 {
48609533 SH	152	#address-cells = <1>;
48609533 SH	153	#size-cells = <0>;
dd4dc874	154	compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
48609533	155	reg = <0xe6822000 0x425>;
5f75e73c LP	156	interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
	157	0 52 IRQ_TYPE_LEVEL_HIGH
	158	0 53 IRQ_TYPE_LEVEL_HIGH
	159	0 54 IRQ_TYPE_LEVEL_HIGH>;
eda3a4fa	160	status = "disabled";
48609533 SH	161	};
48609533 SH	162
561a1a31	163	i2c2: i2c@e6824000 {
48609533 SH	164	#address-cells = <1>;
48609533 SH	165	#size-cells = <0>;
dd4dc874	166	compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
48609533	167	reg = <0xe6824000 0x425>;
5f75e73c LP	168	interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
	169	0 172 IRQ_TYPE_LEVEL_HIGH
	170	0 173 IRQ_TYPE_LEVEL_HIGH
	171	0 174 IRQ_TYPE_LEVEL_HIGH>;
eda3a4fa	172	status = "disabled";
48609533 SH	173	};
48609533 SH	174
561a1a31	175	i2c3: i2c@e6826000 {
48609533 SH	176	#address-cells = <1>;
48609533 SH	177	#size-cells = <0>;
dd4dc874	178	compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
48609533	179	reg = <0xe6826000 0x425>;
5f75e73c LP	180	interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
	181	0 184 IRQ_TYPE_LEVEL_HIGH
	182	0 185 IRQ_TYPE_LEVEL_HIGH
	183	0 186 IRQ_TYPE_LEVEL_HIGH>;
eda3a4fa	184	status = "disabled";
48609533 SH	185	};
48609533 SH	186
561a1a31	187	i2c4: i2c@e6828000 {
48609533 SH	188	#address-cells = <1>;
48609533 SH	189	#size-cells = <0>;
dd4dc874	190	compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
48609533	191	reg = <0xe6828000 0x425>;
5f75e73c LP	192	interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
	193	0 188 IRQ_TYPE_LEVEL_HIGH
	194	0 189 IRQ_TYPE_LEVEL_HIGH
	195	0 190 IRQ_TYPE_LEVEL_HIGH>;
eda3a4fa	196	status = "disabled";
48609533	197	};
546e5d3e	198
33f6be3b	199	mmcif: mmc@e6bd0000 {
546e5d3e GL	200	compatible = "renesas,sh-mmcif";
546e5d3e GL	201	reg = <0xe6bd0000 0x100>;
5f75e73c LP	202	interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
5f75e73c LP	203	0 141 IRQ_TYPE_LEVEL_HIGH>;
546e5d3e GL	204	reg-io-width = <4>;
	205	status = "disabled";
	206	};
	207
33f6be3b	208	sdhi0: sd@ee100000 {
e8a8b8a3	209	compatible = "renesas,sdhi-sh73a0";
546e5d3e	210	reg = <0xee100000 0x100>;
5f75e73c LP	211	interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
	212	0 84 IRQ_TYPE_LEVEL_HIGH
	213	0 85 IRQ_TYPE_LEVEL_HIGH>;
a463f731	214	cap-sd-highspeed;
546e5d3e GL	215	status = "disabled";
	216	};
	217
	218	/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
33f6be3b	219	sdhi1: sd@ee120000 {
e8a8b8a3	220	compatible = "renesas,sdhi-sh73a0";
546e5d3e	221	reg = <0xee120000 0x100>;
5f75e73c LP	222	interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
5f75e73c LP	223	0 89 IRQ_TYPE_LEVEL_HIGH>;
546e5d3e	224	toshiba,mmc-wrprotect-disable;
a463f731	225	cap-sd-highspeed;
546e5d3e GL	226	status = "disabled";
	227	};
	228
33f6be3b	229	sdhi2: sd@ee140000 {
e8a8b8a3	230	compatible = "renesas,sdhi-sh73a0";
546e5d3e	231	reg = <0xee140000 0x100>;
5f75e73c LP	232	interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
5f75e73c LP	233	0 105 IRQ_TYPE_LEVEL_HIGH>;
546e5d3e	234	toshiba,mmc-wrprotect-disable;
a463f731	235	cap-sd-highspeed;
546e5d3e GL	236	status = "disabled";
546e5d3e GL	237	};
3f59007e	238
2131421b SH	239	scifa0: serial@e6c40000 {
	240	compatible = "renesas,scifa-sh73a0", "renesas,scifa";
	241	reg = <0xe6c40000 0x100>;
2131421b SH	242	interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
	243	status = "disabled";
	244	};
	245
	246	scifa1: serial@e6c50000 {
	247	compatible = "renesas,scifa-sh73a0", "renesas,scifa";
	248	reg = <0xe6c50000 0x100>;
2131421b SH	249	interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
	250	status = "disabled";
	251	};
	252
	253	scifa2: serial@e6c60000 {
	254	compatible = "renesas,scifa-sh73a0", "renesas,scifa";
	255	reg = <0xe6c60000 0x100>;
2131421b SH	256	interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
	257	status = "disabled";
	258	};
	259
	260	scifa3: serial@e6c70000 {
	261	compatible = "renesas,scifa-sh73a0", "renesas,scifa";
	262	reg = <0xe6c70000 0x100>;
2131421b SH	263	interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
	264	status = "disabled";
	265	};
	266
	267	scifa4: serial@e6c80000 {
	268	compatible = "renesas,scifa-sh73a0", "renesas,scifa";
	269	reg = <0xe6c80000 0x100>;
2131421b SH	270	interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
	271	status = "disabled";
	272	};
	273
	274	scifa5: serial@e6cb0000 {
	275	compatible = "renesas,scifa-sh73a0", "renesas,scifa";
	276	reg = <0xe6cb0000 0x100>;
2131421b SH	277	interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
	278	status = "disabled";
	279	};
	280
	281	scifa6: serial@e6cc0000 {
	282	compatible = "renesas,scifa-sh73a0", "renesas,scifa";
	283	reg = <0xe6cc0000 0x100>;
2131421b SH	284	interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
	285	status = "disabled";
	286	};
	287
	288	scifa7: serial@e6cd0000 {
	289	compatible = "renesas,scifa-sh73a0", "renesas,scifa";
	290	reg = <0xe6cd0000 0x100>;
2131421b SH	291	interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
	292	status = "disabled";
	293	};
	294
	295	scifb8: serial@e6c30000 {
	296	compatible = "renesas,scifb-sh73a0", "renesas,scifb";
	297	reg = <0xe6c30000 0x100>;
2131421b SH	298	interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
	299	status = "disabled";
	300	};
	301
3f59007e LP	302	pfc: pfc@e6050000 {
	303	compatible = "renesas,pfc-sh73a0";
	304	reg = <0xe6050000 0x8000>,
	305	<0xe605801c 0x1c>;
	306	gpio-controller;
	307	#gpio-cells = <2>;
aba76d28 LP	308	interrupts-extended =
	309	<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
	310	<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
	311	<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
	312	<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
	313	<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
	314	<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
	315	<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
	316	<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
3f59007e	317	};
63b1303d KM	318
	319	sh_fsi2: sound@ec230000 {
	320	#sound-dai-cells = <1>;
	321	compatible = "renesas,sh_fsi2";
	322	reg = <0xec230000 0x400>;
63b1303d KM	323	interrupts = <0 146 0x4>;
	324	status = "disabled";
	325	};
00df6113 UH	326
	327	clocks {
	328	#address-cells = <1>;
	329	#size-cells = <1>;
	330	ranges;
	331
	332	/* External root clocks */
	333	extalr_clk: extalr_clk {
	334	compatible = "fixed-clock";
	335	#clock-cells = <0>;
	336	clock-frequency = <32768>;
	337	clock-output-names = "extalr";
	338	};
	339	extal1_clk: extal1_clk {
	340	compatible = "fixed-clock";
	341	#clock-cells = <0>;
	342	clock-frequency = <26000000>;
	343	clock-output-names = "extal1";
	344	};
	345	extal2_clk: extal2_clk {
	346	compatible = "fixed-clock";
	347	#clock-cells = <0>;
	348	clock-output-names = "extal2";
	349	};
	350	extcki_clk: extcki_clk {
	351	compatible = "fixed-clock";
	352	#clock-cells = <0>;
	353	clock-output-names = "extcki";
	354	};
	355	fsiack_clk: fsiack_clk {
	356	compatible = "fixed-clock";
	357	#clock-cells = <0>;
	358	clock-frequency = <0>;
	359	clock-output-names = "fsiack";
	360	};
	361	fsibck_clk: fsibck_clk {
	362	compatible = "fixed-clock";
	363	#clock-cells = <0>;
	364	clock-frequency = <0>;
	365	clock-output-names = "fsibck";
	366	};
	367
	368	/* Special CPG clocks */
	369	cpg_clocks: cpg_clocks@e6150000 {
	370	compatible = "renesas,sh73a0-cpg-clocks";
	371	reg = <0xe6150000 0x10000>;
	372	clocks = <&extal1_clk>, <&extal2_clk>;
	373	#clock-cells = <1>;
	374	clock-output-names = "main", "pll0", "pll1", "pll2",
	375	"pll3", "dsi0phy", "dsi1phy",
	376	"zg", "m3", "b", "m1", "m2",
	377	"z", "zx", "hp";
	378	};
	379
	380	/* Variable factor clocks (DIV6) */
	381	vclk1_clk: vclk1_clk@e6150008 {
	382	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
	383	reg = <0xe6150008 4>;
	384	clocks = <&pll1_div2_clk>;
	385	#clock-cells = <0>;
	386	clock-output-names = "vclk1";
	387	};
	388	vclk2_clk: vclk2_clk@e615000c {
	389	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
390	reg = <0xe615000c 4>;
391	clocks = <&pll1_div2_clk>;
392	#clock-cells = <0>;
393	clock-output-names = "vclk2";
394	};
395	vclk3_clk: vclk3_clk@e615001c {
396	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
397	reg = <0xe615001c 4>;
398	clocks = <&pll1_div2_clk>;
399	#clock-cells = <0>;
400	clock-output-names = "vclk3";
401	};
402	zb_clk: zb_clk@e6150010 {
403	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
404	reg = <0xe6150010 4>;
405	clocks = <&pll1_div2_clk>;
406	#clock-cells = <0>;
407	clock-output-names = "zb";
408	};
409	flctl_clk: flctl_clk@e6150014 {
410	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
411	reg = <0xe6150014 4>;
412	clocks = <&pll1_div2_clk>;
413	#clock-cells = <0>;
414	clock-output-names = "flctlck";
415	};
416	sdhi0_clk: sdhi0_clk@e6150074 {
417	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
418	reg = <0xe6150074 4>;
419	clocks = <&pll1_div2_clk>;
420	#clock-cells = <0>;
421	clock-output-names = "sdhi0ck";
422	};
423	sdhi1_clk: sdhi1_clk@e6150078 {
424	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
425	reg = <0xe6150078 4>;
426	clocks = <&pll1_div2_clk>;
427	#clock-cells = <0>;
428	clock-output-names = "sdhi1ck";
429	};
430	sdhi2_clk: sdhi2_clk@e615007c {
431	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
432	reg = <0xe615007c 4>;
433	clocks = <&pll1_div2_clk>;
434	#clock-cells = <0>;
435	clock-output-names = "sdhi2ck";
436	};
437	fsia_clk: fsia_clk@e6150018 {
438	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
439	reg = <0xe6150018 4>;
440	clocks = <&pll1_div2_clk>;
441	#clock-cells = <0>;
442	clock-output-names = "fsia";
443	};
444	fsib_clk: fsib_clk@e6150090 {
445	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
446	reg = <0xe6150090 4>;
447	clocks = <&pll1_div2_clk>;
448	#clock-cells = <0>;
449	clock-output-names = "fsib";
450	};
451	sub_clk: sub_clk@e6150080 {
452	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
453	reg = <0xe6150080 4>;
454	clocks = <&extal2_clk>;
455	#clock-cells = <0>;
456	clock-output-names = "sub";
457	};
458	spua_clk: spua_clk@e6150084 {
459	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
460	reg = <0xe6150084 4>;
461	clocks = <&pll1_div2_clk>;
462	#clock-cells = <0>;
463	clock-output-names = "spua";
464	};
465	spuv_clk: spuv_clk@e6150094 {
466	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
467	reg = <0xe6150094 4>;
468	clocks = <&pll1_div2_clk>;
469	#clock-cells = <0>;
470	clock-output-names = "spuv";
471	};
472	msu_clk: msu_clk@e6150088 {
473	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
474	reg = <0xe6150088 4>;
475	clocks = <&pll1_div2_clk>;
476	#clock-cells = <0>;
477	clock-output-names = "msu";
478	};
479	hsi_clk: hsi_clk@e615008c {
480	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
481	reg = <0xe615008c 4>;
482	clocks = <&pll1_div2_clk>;
483	#clock-cells = <0>;
484	clock-output-names = "hsi";
485	};
486	mfg1_clk: mfg1_clk@e6150098 {
487	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
488	reg = <0xe6150098 4>;
489	clocks = <&pll1_div2_clk>;
490	#clock-cells = <0>;
491	clock-output-names = "mfg1";
492	};
493	mfg2_clk: mfg2_clk@e615009c {
494	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
495	reg = <0xe615009c 4>;
496	clocks = <&pll1_div2_clk>;
497	#clock-cells = <0>;
498	clock-output-names = "mfg2";
499	};
500	dsit_clk: dsit_clk@e6150060 {
501	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
502	reg = <0xe6150060 4>;
503	clocks = <&pll1_div2_clk>;
504	#clock-cells = <0>;
505	clock-output-names = "dsit";
506	};
507	dsi0p_clk: dsi0p_clk@e6150064 {
508	compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
509	reg = <0xe6150064 4>;
510	clocks = <&pll1_div2_clk>;
511	#clock-cells = <0>;
512	clock-output-names = "dsi0pck";
513	};
514
515	/* Fixed factor clocks */
516	main_div2_clk: main_div2_clk {
517	compatible = "fixed-factor-clock";
518	clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
519	#clock-cells = <0>;
520	clock-div = <2>;
521	clock-mult = <1>;
522	clock-output-names = "main_div2";
523	};
524	pll1_div2_clk: pll1_div2_clk {
525	compatible = "fixed-factor-clock";
526	clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
527	#clock-cells = <0>;
528	clock-div = <2>;
529	clock-mult = <1>;
530	clock-output-names = "pll1_div2";
531	};
532	pll1_div7_clk: pll1_div7_clk {
533	compatible = "fixed-factor-clock";
534	clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
535	#clock-cells = <0>;
536	clock-div = <7>;
537	clock-mult = <1>;
538	clock-output-names = "pll1_div7";
539	};
540	pll1_div13_clk: pll1_div13_clk {
541	compatible = "fixed-factor-clock";
542	clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
543	#clock-cells = <0>;
544	clock-div = <13>;
545	clock-mult = <1>;
546	clock-output-names = "pll1_div13";
547	};
548	twd_clk: twd_clk {
549	compatible = "fixed-factor-clock";
550	clocks = <&cpg_clocks SH73A0_CLK_Z>;
551	#clock-cells = <0>;
552	clock-div = <4>;
553	clock-mult = <1>;
554	clock-output-names = "twd";
555	};
556
557	/* Gate clocks */
558	mstp0_clks: mstp0_clks@e6150130 {
559	compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
560	reg = <0xe6150130 4>, <0xe6150030 4>;
561	clocks = <&cpg_clocks SH73A0_CLK_HP>;
562	#clock-cells = <1>;
563	clock-indices = <
564	SH73A0_CLK_IIC2
565	>;
566	clock-output-names =
567	"iic2";
568	};
569	mstp1_clks: mstp1_clks@e6150134 {
570	compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
571	reg = <0xe6150134 4>, <0xe6150038 4>;
572	clocks = <&cpg_clocks SH73A0_CLK_B>,
573	<&cpg_clocks SH73A0_CLK_B>,
574	<&cpg_clocks SH73A0_CLK_B>,
575	<&cpg_clocks SH73A0_CLK_B>,
576	<&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
577	<&cpg_clocks SH73A0_CLK_HP>,
578	<&cpg_clocks SH73A0_CLK_ZG>,
579	<&cpg_clocks SH73A0_CLK_B>;
580	#clock-cells = <1>;
581	clock-indices = <
582	SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
583	SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
584	SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
585	SH73A0_CLK_IIC0 SH73A0_CLK_SGX
586	SH73A0_CLK_LCDC0
587	>;
588	clock-output-names =
589	"ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
590	"tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
591	};
592	mstp2_clks: mstp2_clks@e6150138 {
593	compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
594	reg = <0xe6150138 4>, <0xe6150040 4>;
595	clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
596	<&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
597	<&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>,
598	<&sub_clk>, <&sub_clk>;
599	#clock-cells = <1>;
600	clock-indices = <
601	SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
602	SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5
603	SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0
604	SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2
605	SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4
606	>;
607	clock-output-names =
608	"scifa7", "sy_dmac", "mp_dmac", "scifa5",
609	"scifb", "scifa0", "scifa1", "scifa2",
610	"scifa3", "scifa4";
611	};
612	mstp3_clks: mstp3_clks@e615013c {
613	compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
614	reg = <0xe615013c 4>, <0xe6150048 4>;
615	clocks = <&sub_clk>, <&extalr_clk>,
616	<&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
617	<&cpg_clocks SH73A0_CLK_HP>,
618	<&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
619	<&sdhi0_clk>, <&sdhi1_clk>,
620	<&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
621	<&main_div2_clk>, <&main_div2_clk>,
622	<&main_div2_clk>, <&main_div2_clk>,
623	<&main_div2_clk>;
624	#clock-cells = <1>;
625	clock-indices = <
626	SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
627	SH73A0_CLK_FSI SH73A0_CLK_IRDA
628	SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
629	SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
630	SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
631	SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
632	SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
633	SH73A0_CLK_TPU4
634	>;
635	clock-output-names =
636	"scifa6", "cmt1", "fsi", "irda", "iic1",
637	"usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
638	"tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
639	};
640	mstp4_clks: mstp4_clks@e6150140 {
641	compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
642	reg = <0xe6150140 4>, <0xe615004c 4>;
643	clocks = <&cpg_clocks SH73A0_CLK_HP>,
644	<&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
645	#clock-cells = <1>;
646	clock-indices = <
647	SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
648	SH73A0_CLK_KEYSC
649	>;
650	clock-output-names =
651	"iic3", "iic4", "keysc";
652	};
653	};
a3f22db5	654	};