[deliverable/linux.git] / arch / arm / boot / dts / socfpga.dtsi

/*
 *  Copyright (C) 2012 Altera <www.altera.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/include/ "skeleton.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
		serial0 = &uart0;
		serial1 = &uart1;
		timer0 = &timer0;
		timer1 = &timer1;
		timer2 = &timer2;
		timer3 = &timer3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
		};
		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};
	};

	intc: intc@fffed000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xfffed000 0x1000>,
		      <0xfffec100 0x100>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges;

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pdma: pdma@ffe01000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0xffe01000 0x1000>;
				interrupts = <0 180 4>;
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};
		};

		clkmgr@ffd04000 {
				compatible = "altr,clk-mgr";
				reg = <0xffd04000 0x1000>;

				clocks {
					#address-cells = <1>;
					#size-cells = <0>;

					osc: osc1 {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					main_pll: main_pll {
						#address-cells = <1>;
						#size-cells = <0>;
						#clock-cells = <0>;
						compatible = "altr,socfpga-pll-clock";
						clocks = <&osc>;
						reg = <0x40>;

						mpuclk: mpuclk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							fixed-divider = <2>;
							reg = <0x48>;
						};

						mainclk: mainclk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							fixed-divider = <4>;
							reg = <0x4C>;
						};

						dbg_base_clk: dbg_base_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							fixed-divider = <4>;
							reg = <0x50>;
						};

						main_qspi_clk: main_qspi_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							reg = <0x54>;
						};

						main_nand_sdmmc_clk: main_nand_sdmmc_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							reg = <0x58>;
						};

						cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							reg = <0x5C>;
						};
					};

					periph_pll: periph_pll {
						#address-cells = <1>;
						#size-cells = <0>;
						#clock-cells = <0>;
						compatible = "altr,socfpga-pll-clock";
						clocks = <&osc>;
						reg = <0x80>;

						emac0_clk: emac0_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x88>;
						};

						emac1_clk: emac1_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x8C>;
						};

						per_qspi_clk: per_qsi_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x90>;
						};

						per_nand_mmc_clk: per_nand_mmc_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x94>;
						};

						per_base_clk: per_base_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x98>;
						};

						s2f_usr1_clk: s2f_usr1_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x9C>;
						};
					};

					sdram_pll: sdram_pll {
						#address-cells = <1>;
						#size-cells = <0>;
						#clock-cells = <0>;
						compatible = "altr,socfpga-pll-clock";
						clocks = <&osc>;
						reg = <0xC0>;

						ddr_dqs_clk: ddr_dqs_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&sdram_pll>;
							reg = <0xC8>;
						};

						ddr_2x_dqs_clk: ddr_2x_dqs_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&sdram_pll>;
							reg = <0xCC>;
						};

						ddr_dq_clk: ddr_dq_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&sdram_pll>;
							reg = <0xD0>;
						};

						s2f_usr2_clk: s2f_usr2_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&sdram_pll>;
							reg = <0xD4>;
						};
					};
				};
			};

		gmac0: ethernet@ff700000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
			reg = <0xff700000 0x2000>;
			interrupts = <0 115 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
			clocks = <&emac0_clk>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		gmac1: ethernet@ff702000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
			reg = <0xff702000 0x2000>;
			interrupts = <0 120 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
			clocks = <&emac1_clk>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		L2: l2-cache@fffef000 {
			compatible = "arm,pl310-cache";
			reg = <0xfffef000 0x1000>;
			interrupts = <0 38 0x04>;
			cache-unified;
			cache-level = <2>;
		};

		/* Local timer */
		timer@fffec600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xfffec600 0x100>;
			interrupts = <1 13 0xf04>;
		};

		timer0: timer0@ffc08000 {
			compatible = "snps,dw-apb-timer-sp";
			interrupts = <0 167 4>;
			reg = <0xffc08000 0x1000>;
		};

		timer1: timer1@ffc09000 {
			compatible = "snps,dw-apb-timer-sp";
			interrupts = <0 168 4>;
			reg = <0xffc09000 0x1000>;
		};

		timer2: timer2@ffd00000 {
			compatible = "snps,dw-apb-timer-osc";
			interrupts = <0 169 4>;
			reg = <0xffd00000 0x1000>;
		};

		timer3: timer3@ffd01000 {
			compatible = "snps,dw-apb-timer-osc";
			interrupts = <0 170 4>;
			reg = <0xffd01000 0x1000>;
		};

		uart0: serial0@ffc02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02000 0x1000>;
			interrupts = <0 162 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

		uart1: serial1@ffc03000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc03000 0x1000>;
			interrupts = <0 163 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

		rstmgr@ffd05000 {
				compatible = "altr,rst-mgr";
				reg = <0xffd05000 0x1000>;
			};

		sysmgr@ffd08000 {
				compatible = "altr,sys-mgr";
				reg = <0xffd08000 0x4000>;
			};
	};
};
Commit	Line	Data
66314223 DN	1	/*
	2	* Copyright (C) 2012 Altera <www.altera.com>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	/include/ "skeleton.dtsi"
	19
	20	/ {
	21	#address-cells = <1>;
	22	#size-cells = <1>;
	23
	24	aliases {
	25	ethernet0 = &gmac0;
3d954cf1	26	ethernet1 = &gmac1;
66314223 DN	27	serial0 = &uart0;
66314223 DN	28	serial1 = &uart1;
c2ad2844 DN	29	timer0 = &timer0;
	30	timer1 = &timer1;
	31	timer2 = &timer2;
	32	timer3 = &timer3;
66314223 DN	33	};
	34
	35	cpus {
	36	#address-cells = <1>;
	37	#size-cells = <0>;
	38
	39	cpu@0 {
	40	compatible = "arm,cortex-a9";
	41	device_type = "cpu";
	42	reg = <0>;
	43	next-level-cache = <&L2>;
	44	};
	45	cpu@1 {
	46	compatible = "arm,cortex-a9";
	47	device_type = "cpu";
	48	reg = <1>;
	49	next-level-cache = <&L2>;
	50	};
	51	};
	52
	53	intc: intc@fffed000 {
	54	compatible = "arm,cortex-a9-gic";
	55	#interrupt-cells = <3>;
	56	interrupt-controller;
	57	reg = <0xfffed000 0x1000>,
	58	<0xfffec100 0x100>;
	59	};
	60
	61	soc {
	62	#address-cells = <1>;
	63	#size-cells = <1>;
	64	compatible = "simple-bus";
	65	device_type = "soc";
	66	interrupt-parent = <&intc>;
	67	ranges;
	68
	69	amba {
	70	compatible = "arm,amba-bus";
	71	#address-cells = <1>;
	72	#size-cells = <1>;
	73	ranges;
	74
	75	pdma: pdma@ffe01000 {
	76	compatible = "arm,pl330", "arm,primecell";
	77	reg = <0xffe01000 0x1000>;
	78	interrupts = <0 180 4>;
0d8abbfd PV	79	#dma-cells = <1>;
	80	#dma-channels = <8>;
	81	#dma-requests = <32>;
66314223 DN	82	};
	83	};
	84
042000b0 DN	85	clkmgr@ffd04000 {
	86	compatible = "altr,clk-mgr";
	87	reg = <0xffd04000 0x1000>;
	88
	89	clocks {
	90	#address-cells = <1>;
	91	#size-cells = <0>;
	92
	93	osc: osc1 {
	94	#clock-cells = <0>;
	95	compatible = "fixed-clock";
	96	};
	97
	98	main_pll: main_pll {
	99	#address-cells = <1>;
	100	#size-cells = <0>;
	101	#clock-cells = <0>;
	102	compatible = "altr,socfpga-pll-clock";
	103	clocks = <&osc>;
	104	reg = <0x40>;
	105
	106	mpuclk: mpuclk {
	107	#clock-cells = <0>;
	108	compatible = "altr,socfpga-perip-clk";
	109	clocks = <&main_pll>;
	110	fixed-divider = <2>;
	111	reg = <0x48>;
	112	};
	113
	114	mainclk: mainclk {
	115	#clock-cells = <0>;
	116	compatible = "altr,socfpga-perip-clk";
	117	clocks = <&main_pll>;
	118	fixed-divider = <4>;
	119	reg = <0x4C>;
	120	};
	121
	122	dbg_base_clk: dbg_base_clk {
	123	#clock-cells = <0>;
	124	compatible = "altr,socfpga-perip-clk";
	125	clocks = <&main_pll>;
	126	fixed-divider = <4>;
	127	reg = <0x50>;
	128	};
	129
	130	main_qspi_clk: main_qspi_clk {
	131	#clock-cells = <0>;
	132	compatible = "altr,socfpga-perip-clk";
	133	clocks = <&main_pll>;
	134	reg = <0x54>;
	135	};
	136
	137	main_nand_sdmmc_clk: main_nand_sdmmc_clk {
	138	#clock-cells = <0>;
	139	compatible = "altr,socfpga-perip-clk";
	140	clocks = <&main_pll>;
	141	reg = <0x58>;
	142	};
	143
	144	cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
	145	#clock-cells = <0>;
	146	compatible = "altr,socfpga-perip-clk";
	147	clocks = <&main_pll>;
	148	reg = <0x5C>;
149	};
150	};
151
152	periph_pll: periph_pll {
153	#address-cells = <1>;
154	#size-cells = <0>;
155	#clock-cells = <0>;
156	compatible = "altr,socfpga-pll-clock";
157	clocks = <&osc>;
158	reg = <0x80>;
159
160	emac0_clk: emac0_clk {
161	#clock-cells = <0>;
162	compatible = "altr,socfpga-perip-clk";
163	clocks = <&periph_pll>;
164	reg = <0x88>;
165	};
166
167	emac1_clk: emac1_clk {
168	#clock-cells = <0>;
169	compatible = "altr,socfpga-perip-clk";
170	clocks = <&periph_pll>;
171	reg = <0x8C>;
172	};
173
174	per_qspi_clk: per_qsi_clk {
175	#clock-cells = <0>;
176	compatible = "altr,socfpga-perip-clk";
177	clocks = <&periph_pll>;
178	reg = <0x90>;
179	};
180
181	per_nand_mmc_clk: per_nand_mmc_clk {
182	#clock-cells = <0>;
183	compatible = "altr,socfpga-perip-clk";
184	clocks = <&periph_pll>;
185	reg = <0x94>;
186	};
187
188	per_base_clk: per_base_clk {
189	#clock-cells = <0>;
190	compatible = "altr,socfpga-perip-clk";
191	clocks = <&periph_pll>;
192	reg = <0x98>;
193	};
194
195	s2f_usr1_clk: s2f_usr1_clk {
196	#clock-cells = <0>;
197	compatible = "altr,socfpga-perip-clk";
198	clocks = <&periph_pll>;
199	reg = <0x9C>;
200	};
201	};
202
203	sdram_pll: sdram_pll {
204	#address-cells = <1>;
205	#size-cells = <0>;
206	#clock-cells = <0>;
207	compatible = "altr,socfpga-pll-clock";
208	clocks = <&osc>;
209	reg = <0xC0>;
210
211	ddr_dqs_clk: ddr_dqs_clk {
212	#clock-cells = <0>;
213	compatible = "altr,socfpga-perip-clk";
214	clocks = <&sdram_pll>;
215	reg = <0xC8>;
216	};
217
218	ddr_2x_dqs_clk: ddr_2x_dqs_clk {
219	#clock-cells = <0>;
220	compatible = "altr,socfpga-perip-clk";
221	clocks = <&sdram_pll>;
222	reg = <0xCC>;
223	};
224
225	ddr_dq_clk: ddr_dq_clk {
226	#clock-cells = <0>;
227	compatible = "altr,socfpga-perip-clk";
228	clocks = <&sdram_pll>;
229	reg = <0xD0>;
230	};
231
232	s2f_usr2_clk: s2f_usr2_clk {
233	#clock-cells = <0>;
234	compatible = "altr,socfpga-perip-clk";
235	clocks = <&sdram_pll>;
236	reg = <0xD4>;
237	};
238	};
239	};
240	};
241
3d954cf1	242	gmac0: ethernet@ff700000 {
66314223 DN	243	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
	244	reg = <0xff700000 0x2000>;
	245	interrupts = <0 115 4>;
	246	interrupt-names = "macirq";
	247	mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
3d954cf1 DN	248	clocks = <&emac0_clk>;
	249	clock-names = "stmmaceth";
	250	status = "disabled";
	251	};
	252
	253	gmac1: ethernet@ff702000 {
	254	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
	255	reg = <0xff702000 0x2000>;
	256	interrupts = <0 120 4>;
	257	interrupt-names = "macirq";
	258	mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
	259	clocks = <&emac1_clk>;
	260	clock-names = "stmmaceth";
	261	status = "disabled";
66314223 DN	262	};
	263
	264	L2: l2-cache@fffef000 {
	265	compatible = "arm,pl310-cache";
	266	reg = <0xfffef000 0x1000>;
	267	interrupts = <0 38 0x04>;
	268	cache-unified;
	269	cache-level = <2>;
	270	};
	271
	272	/* Local timer */
	273	timer@fffec600 {
	274	compatible = "arm,cortex-a9-twd-timer";
	275	reg = <0xfffec600 0x100>;
	276	interrupts = <1 13 0xf04>;
	277	};
	278
c2ad2844	279	timer0: timer0@ffc08000 {
66314223 DN	280	compatible = "snps,dw-apb-timer-sp";
66314223 DN	281	interrupts = <0 167 4>;
66314223 DN	282	reg = <0xffc08000 0x1000>;
	283	};
	284
c2ad2844	285	timer1: timer1@ffc09000 {
66314223 DN	286	compatible = "snps,dw-apb-timer-sp";
66314223 DN	287	interrupts = <0 168 4>;
66314223 DN	288	reg = <0xffc09000 0x1000>;
	289	};
	290
c2ad2844	291	timer2: timer2@ffd00000 {
66314223 DN	292	compatible = "snps,dw-apb-timer-osc";
66314223 DN	293	interrupts = <0 169 4>;
66314223 DN	294	reg = <0xffd00000 0x1000>;
	295	};
	296
c2ad2844	297	timer3: timer3@ffd01000 {
66314223 DN	298	compatible = "snps,dw-apb-timer-osc";
66314223 DN	299	interrupts = <0 170 4>;
66314223 DN	300	reg = <0xffd01000 0x1000>;
	301	};
	302
c2ad2844	303	uart0: serial0@ffc02000 {
66314223 DN	304	compatible = "snps,dw-apb-uart";
66314223 DN	305	reg = <0xffc02000 0x1000>;
66314223 DN	306	interrupts = <0 162 4>;
	307	reg-shift = <2>;
	308	reg-io-width = <4>;
	309	};
	310
c2ad2844	311	uart1: serial1@ffc03000 {
66314223 DN	312	compatible = "snps,dw-apb-uart";
66314223 DN	313	reg = <0xffc03000 0x1000>;
66314223 DN	314	interrupts = <0 163 4>;
	315	reg-shift = <2>;
	316	reg-io-width = <4>;
	317	};
9c4566a1 DN	318
	319	rstmgr@ffd05000 {
	320	compatible = "altr,rst-mgr";
	321	reg = <0xffd05000 0x1000>;
	322	};
	323
	324	sysmgr@ffd08000 {
	325	compatible = "altr,sys-mgr";
	326	reg = <0xffd08000 0x4000>;
	327	};
66314223 DN	328	};
66314223 DN	329	};