[deliverable/linux.git] / arch / arm / boot / dts / socfpga_arria10.dtsi

/*
 * Copyright Altera Corporation (C) 2014. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/altr,rst-mgr-a10.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "altr,socfpga-a10-smp";

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
		};
		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};
	};

	intc: intc@ffffd000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xffffd000 0x1000>,
		      <0xffffc100 0x100>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges;

		amba {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pdma: pdma@ffda1000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0xffda1000 0x1000>;
				interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
					     <0 84 IRQ_TYPE_LEVEL_HIGH>,
					     <0 85 IRQ_TYPE_LEVEL_HIGH>,
					     <0 86 IRQ_TYPE_LEVEL_HIGH>,
					     <0 87 IRQ_TYPE_LEVEL_HIGH>,
					     <0 88 IRQ_TYPE_LEVEL_HIGH>,
					     <0 89 IRQ_TYPE_LEVEL_HIGH>,
					     <0 90 IRQ_TYPE_LEVEL_HIGH>;
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};
		};

		clkmgr@ffd04000 {
				compatible = "altr,clk-mgr";
				reg = <0xffd04000 0x1000>;

				clocks {
					#address-cells = <1>;
					#size-cells = <0>;

					cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					cb_intosc_ls_clk: cb_intosc_ls_clk {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					f2s_free_clk: f2s_free_clk {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					osc1: osc1 {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					main_pll: main_pll {
						#address-cells = <1>;
						#size-cells = <0>;
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-pll-clock";
						clocks = <&osc1>, <&cb_intosc_ls_clk>,
							 <&f2s_free_clk>;
						reg = <0x40>;

						main_mpu_base_clk: main_mpu_base_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							div-reg = <0x140 0 11>;
						};

						main_noc_base_clk: main_noc_base_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							div-reg = <0x144 0 11>;
						};

						main_emaca_clk: main_emaca_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x68>;
						};

						main_emacb_clk: main_emacb_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x6C>;
						};

						main_emac_ptp_clk: main_emac_ptp_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x70>;
						};

						main_gpio_db_clk: main_gpio_db_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x74>;
						};

						main_sdmmc_clk: main_sdmmc_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk"
;
							clocks = <&main_pll>;
							reg = <0x78>;
						};

						main_s2f_usr0_clk: main_s2f_usr0_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x7C>;
						};

						main_s2f_usr1_clk: main_s2f_usr1_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x80>;
						};

						main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x84>;
						};

						main_periph_ref_clk: main_periph_ref_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x9C>;
						};
					};

					periph_pll: periph_pll {
						#address-cells = <1>;
						#size-cells = <0>;
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-pll-clock";
						clocks = <&osc1>, <&cb_intosc_ls_clk>,
							 <&f2s_free_clk>, <&main_periph_ref_clk>;
						reg = <0xC0>;

						peri_mpu_base_clk: peri_mpu_base_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							div-reg = <0x140 16 11>;
						};

						peri_noc_base_clk: peri_noc_base_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							div-reg = <0x144 16 11>;
						};

						peri_emaca_clk: peri_emaca_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0xE8>;
						};

						peri_emacb_clk: peri_emacb_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0xEC>;
						};

						peri_emac_ptp_clk: peri_emac_ptp_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0xF0>;
						};

						peri_gpio_db_clk: peri_gpio_db_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0xF4>;
						};

						peri_sdmmc_clk: peri_sdmmc_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0xF8>;
						};

						peri_s2f_usr0_clk: peri_s2f_usr0_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0xFC>;
						};

						peri_s2f_usr1_clk: peri_s2f_usr1_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x100>;
						};

						peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x104>;
						};
					};

					mpu_free_clk: mpu_free_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
							 <&osc1>, <&cb_intosc_hs_div2_clk>,
							 <&f2s_free_clk>;
						reg = <0x60>;
					};

					noc_free_clk: noc_free_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
							 <&osc1>, <&cb_intosc_hs_div2_clk>,
							 <&f2s_free_clk>;
						reg = <0x64>;
					};

					s2f_user1_free_clk: s2f_user1_free_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
							 <&osc1>, <&cb_intosc_hs_div2_clk>,
							 <&f2s_free_clk>;
						reg = <0x104>;
					};

					sdmmc_free_clk: sdmmc_free_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
							 <&osc1>, <&cb_intosc_hs_div2_clk>,
							 <&f2s_free_clk>;
						fixed-divider = <4>;
						reg = <0xF8>;
					};

					l4_sys_free_clk: l4_sys_free_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <&noc_free_clk>;
						fixed-divider = <4>;
					};

					l4_main_clk: l4_main_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&noc_free_clk>;
						div-reg = <0xA8 0 2>;
						clk-gate = <0x48 1>;
					};

					l4_mp_clk: l4_mp_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&noc_free_clk>;
						div-reg = <0xA8 8 2>;
						clk-gate = <0x48 2>;
					};

					l4_sp_clk: l4_sp_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&noc_free_clk>;
						div-reg = <0xA8 16 2>;
						clk-gate = <0x48 3>;
					};

					mpu_periph_clk: mpu_periph_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&mpu_free_clk>;
						fixed-divider = <4>;
						clk-gate = <0x48 0>;
					};

					sdmmc_clk: sdmmc_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&sdmmc_free_clk>;
						clk-gate = <0xC8 5>;
						clk-phase = <0 135>;
					};

					qspi_clk: qspi_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&l4_main_clk>;
						clk-gate = <0xC8 11>;
					};

					nand_clk: nand_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&l4_mp_clk>;
						clk-gate = <0xC8 10>;
					};

					spi_m_clk: spi_m_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&l4_main_clk>;
						clk-gate = <0xC8 9>;
					};

					usb_clk: usb_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&l4_mp_clk>;
						clk-gate = <0xC8 8>;
					};

					s2f_usr1_clk: s2f_usr1_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&peri_s2f_usr1_clk>;
						clk-gate = <0xC8 6>;
					};
				};
		};

		gmac0: ethernet@ff800000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
			reg = <0xff800000 0x2000>;
			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";
			/* Filled in by bootloader */
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <256>;
			snps,perfect-filter-entries = <128>;
			tx-fifo-depth = <4096>;
			rx-fifo-depth = <16384>;
			clocks = <&l4_mp_clk>;
			clock-names = "stmmaceth";
			resets = <&rst EMAC0_RESET>;
			reset-names = "stmmaceth";
			status = "disabled";
		};

		gmac1: ethernet@ff802000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
			altr,sysmgr-syscon = <&sysmgr 0x48 0>;
		        reg = <0xff802000 0x2000>;
			interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";
			/* Filled in by bootloader */
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <256>;
			snps,perfect-filter-entries = <128>;
			tx-fifo-depth = <4096>;
			rx-fifo-depth = <16384>;
			clocks = <&l4_mp_clk>;
			clock-names = "stmmaceth";
			resets = <&rst EMAC1_RESET>;
			reset-names = "stmmaceth";
			status = "disabled";
		};

		gmac2: ethernet@ff804000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
			altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
			reg = <0xff804000 0x2000>;
			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";
			/* Filled in by bootloader */
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <256>;
			snps,perfect-filter-entries = <128>;
			tx-fifo-depth = <4096>;
			rx-fifo-depth = <16384>;
			clocks = <&l4_mp_clk>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		gpio0: gpio@ffc02900 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02900 0x100>;
			status = "disabled";

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <29>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio1: gpio@ffc02a00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02a00 0x100>;
			status = "disabled";

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <29>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio2: gpio@ffc02b00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02b00 0x100>;
			status = "disabled";

			portc: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <27>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		i2c0: i2c@ffc02200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02200 0x100>;
			interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&l4_sp_clk>;
			status = "disabled";
		};

		i2c1: i2c@ffc02300 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02300 0x100>;
			interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&l4_sp_clk>;
			status = "disabled";
		};

		i2c2: i2c@ffc02400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02400 0x100>;
			interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&l4_sp_clk>;
			status = "disabled";
		};

		i2c3: i2c@ffc02500 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02500 0x100>;
			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&l4_sp_clk>;
			status = "disabled";
		};

		i2c4: i2c@ffc02600 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02600 0x100>;
			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&l4_sp_clk>;
			status = "disabled";
		};

		sdr: sdr@ffc25000 {
			compatible = "syscon";
			reg = <0xffcfb100 0x80>;
		};

		sdramedac {
			compatible = "altr,sdram-edac-a10";
			altr,sdr-syscon = <&sdr>;
			interrupts = <0 2 4>, <0 0 4>;
		};

		L2: l2-cache@fffff000 {
			compatible = "arm,pl310-cache";
			reg = <0xfffff000 0x1000>;
			interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-level = <2>;
		};

		mmc: dwmmc0@ff808000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "altr,socfpga-dw-mshc";
			reg = <0xff808000 0x1000>;
			interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
			fifo-depth = <0x400>;
			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
			clock-names = "biu", "ciu";
			status = "disabled";
		};

		ocram: sram@ffe00000 {
			compatible = "mmio-sram";
			reg = <0xffe00000 0x40000>;
		};

		rst: rstmgr@ffd05000 {
			#reset-cells = <1>;
			compatible = "altr,rst-mgr";
			reg = <0xffd05000 0x100>;
			altr,modrst-offset = <0x20>;
		};

		scu: snoop-control-unit@ffffc000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xffffc000 0x100>;
		};

		sysmgr: sysmgr@ffd06000 {
			compatible = "altr,sys-mgr", "syscon";
			reg = <0xffd06000 0x300>;
			cpu1-start-addr = <0xffd06230>;
		};

		/* Local timer */
		timer@ffffc600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xffffc600 0x100>;
			interrupts = <1 13 0xf04>;
			clocks = <&mpu_periph_clk>;
		};

		timer0: timer0@ffc02700 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0xffc02700 0x100>;
			clocks = <&l4_sp_clk>;
			clock-names = "timer";
		};

		timer1: timer1@ffc02800 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0xffc02800 0x100>;
			clocks = <&l4_sp_clk>;
			clock-names = "timer";
		};

		timer2: timer2@ffd00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0xffd00000 0x100>;
			clocks = <&l4_sys_free_clk>;
			clock-names = "timer";
		};

		timer3: timer3@ffd00100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0xffd01000 0x100>;
			clocks = <&l4_sys_free_clk>;
			clock-names = "timer";
		};

		uart0: serial0@ffc02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02000 0x100>;
			interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&l4_sp_clk>;
			status = "disabled";
		};

		uart1: serial1@ffc02100 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02100 0x100>;
			interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&l4_sp_clk>;
			status = "disabled";
		};

		usbphy0: usbphy@0 {
			#phy-cells = <0>;
			compatible = "usb-nop-xceiv";
			status = "okay";
		};

		usb0: usb@ffb00000 {
			compatible = "snps,dwc2";
			reg = <0xffb00000 0xffff>;
			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&usb_clk>;
			clock-names = "otg";
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			status = "disabled";
		};

		usb1: usb@ffb40000 {
			compatible = "snps,dwc2";
			reg = <0xffb40000 0xffff>;
			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&usb_clk>;
			clock-names = "otg";
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			status = "disabled";
		};

		watchdog0: watchdog@ffd00200 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00200 0x100>;
			interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&l4_sys_free_clk>;
			status = "disabled";
		};

		watchdog1: watchdog@ffd00300 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00300 0x100>;
			interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&l4_sys_free_clk>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
475dc86d DN	1	/*
	2	* Copyright Altera Corporation (C) 2014. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#include "skeleton.dtsi"
	18	#include <dt-bindings/interrupt-controller/arm-gic.h>
6855e5b7	19	#include <dt-bindings/reset/altr,rst-mgr-a10.h>
475dc86d DN	20
	21	/ {
	22	#address-cells = <1>;
	23	#size-cells = <1>;
	24
efc1985c DN	25	aliases {
	26	serial0 = &uart0;
	27	serial1 = &uart1;
	28	};
	29
475dc86d DN	30	cpus {
	31	#address-cells = <1>;
	32	#size-cells = <0>;
ebbce1bb	33	enable-method = "altr,socfpga-a10-smp";
475dc86d DN	34
	35	cpu@0 {
	36	compatible = "arm,cortex-a9";
	37	device_type = "cpu";
	38	reg = <0>;
	39	next-level-cache = <&L2>;
	40	};
	41	cpu@1 {
	42	compatible = "arm,cortex-a9";
	43	device_type = "cpu";
	44	reg = <1>;
	45	next-level-cache = <&L2>;
	46	};
	47	};
	48
	49	intc: intc@ffffd000 {
	50	compatible = "arm,cortex-a9-gic";
	51	#interrupt-cells = <3>;
	52	interrupt-controller;
	53	reg = <0xffffd000 0x1000>,
	54	<0xffffc100 0x100>;
	55	};
	56
	57	soc {
	58	#address-cells = <1>;
	59	#size-cells = <1>;
	60	compatible = "simple-bus";
	61	device_type = "soc";
	62	interrupt-parent = <&intc>;
	63	ranges;
	64
	65	amba {
2ef7d5f3	66	compatible = "simple-bus";
475dc86d DN	67	#address-cells = <1>;
	68	#size-cells = <1>;
	69	ranges;
	70
	71	pdma: pdma@ffda1000 {
	72	compatible = "arm,pl330", "arm,primecell";
	73	reg = <0xffda1000 0x1000>;
	74	interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
	75	<0 84 IRQ_TYPE_LEVEL_HIGH>,
	76	<0 85 IRQ_TYPE_LEVEL_HIGH>,
	77	<0 86 IRQ_TYPE_LEVEL_HIGH>,
	78	<0 87 IRQ_TYPE_LEVEL_HIGH>,
	79	<0 88 IRQ_TYPE_LEVEL_HIGH>,
	80	<0 89 IRQ_TYPE_LEVEL_HIGH>,
	81	<0 90 IRQ_TYPE_LEVEL_HIGH>;
	82	#dma-cells = <1>;
	83	#dma-channels = <8>;
	84	#dma-requests = <32>;
	85	};
	86	};
	87
	88	clkmgr@ffd04000 {
	89	compatible = "altr,clk-mgr";
	90	reg = <0xffd04000 0x1000>;
	91
	92	clocks {
	93	#address-cells = <1>;
	94	#size-cells = <0>;
	95
da29d824 DN	96	cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
	97	#clock-cells = <0>;
	98	compatible = "fixed-clock";
	99	};
	100
	101	cb_intosc_ls_clk: cb_intosc_ls_clk {
	102	#clock-cells = <0>;
	103	compatible = "fixed-clock";
	104	};
	105
	106	f2s_free_clk: f2s_free_clk {
	107	#clock-cells = <0>;
	108	compatible = "fixed-clock";
	109	};
	110
475dc86d DN	111	osc1: osc1 {
	112	#clock-cells = <0>;
	113	compatible = "fixed-clock";
	114	};
	115
	116	main_pll: main_pll {
	117	#address-cells = <1>;
	118	#size-cells = <0>;
	119	#clock-cells = <0>;
da29d824 DN	120	compatible = "altr,socfpga-a10-pll-clock";
	121	clocks = <&osc1>, <&cb_intosc_ls_clk>,
	122	<&f2s_free_clk>;
	123	reg = <0x40>;
	124
	125	main_mpu_base_clk: main_mpu_base_clk {
	126	#clock-cells = <0>;
	127	compatible = "altr,socfpga-a10-perip-clk";
	128	clocks = <&main_pll>;
	129	div-reg = <0x140 0 11>;
	130	};
	131
	132	main_noc_base_clk: main_noc_base_clk {
	133	#clock-cells = <0>;
	134	compatible = "altr,socfpga-a10-perip-clk";
	135	clocks = <&main_pll>;
	136	div-reg = <0x144 0 11>;
	137	};
	138
	139	main_emaca_clk: main_emaca_clk {
	140	#clock-cells = <0>;
	141	compatible = "altr,socfpga-a10-perip-clk";
	142	clocks = <&main_pll>;
	143	reg = <0x68>;
	144	};
	145
	146	main_emacb_clk: main_emacb_clk {
	147	#clock-cells = <0>;
	148	compatible = "altr,socfpga-a10-perip-clk";
	149	clocks = <&main_pll>;
	150	reg = <0x6C>;
	151	};
	152
	153	main_emac_ptp_clk: main_emac_ptp_clk {
	154	#clock-cells = <0>;
	155	compatible = "altr,socfpga-a10-perip-clk";
	156	clocks = <&main_pll>;
	157	reg = <0x70>;
	158	};
	159
	160	main_gpio_db_clk: main_gpio_db_clk {
	161	#clock-cells = <0>;
	162	compatible = "altr,socfpga-a10-perip-clk";
	163	clocks = <&main_pll>;
	164	reg = <0x74>;
	165	};
	166
	167	main_sdmmc_clk: main_sdmmc_clk {
	168	#clock-cells = <0>;
	169	compatible = "altr,socfpga-a10-perip-clk"
	170	;
	171	clocks = <&main_pll>;
	172	reg = <0x78>;
	173	};
	174
	175	main_s2f_usr0_clk: main_s2f_usr0_clk {
	176	#clock-cells = <0>;
	177	compatible = "altr,socfpga-a10-perip-clk";
	178	clocks = <&main_pll>;
	179	reg = <0x7C>;
	180	};
	181
	182	main_s2f_usr1_clk: main_s2f_usr1_clk {
	183	#clock-cells = <0>;
184	compatible = "altr,socfpga-a10-perip-clk";
185	clocks = <&main_pll>;
186	reg = <0x80>;
187	};
188
189	main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
190	#clock-cells = <0>;
191	compatible = "altr,socfpga-a10-perip-clk";
192	clocks = <&main_pll>;
193	reg = <0x84>;
194	};
195
196	main_periph_ref_clk: main_periph_ref_clk {
197	#clock-cells = <0>;
198	compatible = "altr,socfpga-a10-perip-clk";
199	clocks = <&main_pll>;
200	reg = <0x9C>;
201	};
475dc86d DN	202	};
	203
	204	periph_pll: periph_pll {
	205	#address-cells = <1>;
	206	#size-cells = <0>;
	207	#clock-cells = <0>;
da29d824 DN	208	compatible = "altr,socfpga-a10-pll-clock";
	209	clocks = <&osc1>, <&cb_intosc_ls_clk>,
	210	<&f2s_free_clk>, <&main_periph_ref_clk>;
	211	reg = <0xC0>;
	212
	213	peri_mpu_base_clk: peri_mpu_base_clk {
	214	#clock-cells = <0>;
	215	compatible = "altr,socfpga-a10-perip-clk";
	216	clocks = <&periph_pll>;
	217	div-reg = <0x140 16 11>;
	218	};
	219
	220	peri_noc_base_clk: peri_noc_base_clk {
	221	#clock-cells = <0>;
	222	compatible = "altr,socfpga-a10-perip-clk";
	223	clocks = <&periph_pll>;
	224	div-reg = <0x144 16 11>;
	225	};
	226
	227	peri_emaca_clk: peri_emaca_clk {
	228	#clock-cells = <0>;
	229	compatible = "altr,socfpga-a10-perip-clk";
	230	clocks = <&periph_pll>;
	231	reg = <0xE8>;
	232	};
	233
	234	peri_emacb_clk: peri_emacb_clk {
	235	#clock-cells = <0>;
	236	compatible = "altr,socfpga-a10-perip-clk";
	237	clocks = <&periph_pll>;
	238	reg = <0xEC>;
	239	};
	240
	241	peri_emac_ptp_clk: peri_emac_ptp_clk {
	242	#clock-cells = <0>;
	243	compatible = "altr,socfpga-a10-perip-clk";
	244	clocks = <&periph_pll>;
	245	reg = <0xF0>;
	246	};
	247
	248	peri_gpio_db_clk: peri_gpio_db_clk {
	249	#clock-cells = <0>;
	250	compatible = "altr,socfpga-a10-perip-clk";
	251	clocks = <&periph_pll>;
	252	reg = <0xF4>;
	253	};
	254
	255	peri_sdmmc_clk: peri_sdmmc_clk {
	256	#clock-cells = <0>;
	257	compatible = "altr,socfpga-a10-perip-clk";
	258	clocks = <&periph_pll>;
	259	reg = <0xF8>;
	260	};
	261
	262	peri_s2f_usr0_clk: peri_s2f_usr0_clk {
	263	#clock-cells = <0>;
	264	compatible = "altr,socfpga-a10-perip-clk";
	265	clocks = <&periph_pll>;
	266	reg = <0xFC>;
	267	};
	268
	269	peri_s2f_usr1_clk: peri_s2f_usr1_clk {
	270	#clock-cells = <0>;
	271	compatible = "altr,socfpga-a10-perip-clk";
272	clocks = <&periph_pll>;
273	reg = <0x100>;
274	};
275
276	peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
277	#clock-cells = <0>;
278	compatible = "altr,socfpga-a10-perip-clk";
279	clocks = <&periph_pll>;
280	reg = <0x104>;
281	};
282	};
283
284	mpu_free_clk: mpu_free_clk {
285	#clock-cells = <0>;
286	compatible = "altr,socfpga-a10-perip-clk";
287	clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
288	<&osc1>, <&cb_intosc_hs_div2_clk>,
289	<&f2s_free_clk>;
290	reg = <0x60>;
291	};
292
293	noc_free_clk: noc_free_clk {
294	#clock-cells = <0>;
295	compatible = "altr,socfpga-a10-perip-clk";
296	clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
297	<&osc1>, <&cb_intosc_hs_div2_clk>,
298	<&f2s_free_clk>;
299	reg = <0x64>;
300	};
301
302	s2f_user1_free_clk: s2f_user1_free_clk {
303	#clock-cells = <0>;
304	compatible = "altr,socfpga-a10-perip-clk";
305	clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
306	<&osc1>, <&cb_intosc_hs_div2_clk>,
307	<&f2s_free_clk>;
308	reg = <0x104>;
309	};
310
311	sdmmc_free_clk: sdmmc_free_clk {
312	#clock-cells = <0>;
313	compatible = "altr,socfpga-a10-perip-clk";
314	clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
315	<&osc1>, <&cb_intosc_hs_div2_clk>,
316	<&f2s_free_clk>;
317	fixed-divider = <4>;
318	reg = <0xF8>;
319	};
320
321	l4_sys_free_clk: l4_sys_free_clk {
322	#clock-cells = <0>;
323	compatible = "altr,socfpga-a10-perip-clk";
324	clocks = <&noc_free_clk>;
325	fixed-divider = <4>;
326	};
327
328	l4_main_clk: l4_main_clk {
329	#clock-cells = <0>;
330	compatible = "altr,socfpga-a10-gate-clk";
331	clocks = <&noc_free_clk>;
332	div-reg = <0xA8 0 2>;
333	clk-gate = <0x48 1>;
334	};
335
336	l4_mp_clk: l4_mp_clk {
337	#clock-cells = <0>;
338	compatible = "altr,socfpga-a10-gate-clk";
339	clocks = <&noc_free_clk>;
340	div-reg = <0xA8 8 2>;
341	clk-gate = <0x48 2>;
342	};
343
344	l4_sp_clk: l4_sp_clk {
345	#clock-cells = <0>;
346	compatible = "altr,socfpga-a10-gate-clk";
347	clocks = <&noc_free_clk>;
348	div-reg = <0xA8 16 2>;
349	clk-gate = <0x48 3>;
350	};
351
352	mpu_periph_clk: mpu_periph_clk {
353	#clock-cells = <0>;
354	compatible = "altr,socfpga-a10-gate-clk";
355	clocks = <&mpu_free_clk>;
356	fixed-divider = <4>;
357	clk-gate = <0x48 0>;
358	};
359
360	sdmmc_clk: sdmmc_clk {
361	#clock-cells = <0>;
362	compatible = "altr,socfpga-a10-gate-clk";
363	clocks = <&sdmmc_free_clk>;
364	clk-gate = <0xC8 5>;
faf68cdf	365	clk-phase = <0 135>;
da29d824 DN	366	};
	367
	368	qspi_clk: qspi_clk {
	369	#clock-cells = <0>;
	370	compatible = "altr,socfpga-a10-gate-clk";
	371	clocks = <&l4_main_clk>;
	372	clk-gate = <0xC8 11>;
	373	};
	374
	375	nand_clk: nand_clk {
	376	#clock-cells = <0>;
	377	compatible = "altr,socfpga-a10-gate-clk";
	378	clocks = <&l4_mp_clk>;
	379	clk-gate = <0xC8 10>;
	380	};
	381
	382	spi_m_clk: spi_m_clk {
	383	#clock-cells = <0>;
	384	compatible = "altr,socfpga-a10-gate-clk";
	385	clocks = <&l4_main_clk>;
	386	clk-gate = <0xC8 9>;
	387	};
	388
	389	usb_clk: usb_clk {
	390	#clock-cells = <0>;
	391	compatible = "altr,socfpga-a10-gate-clk";
	392	clocks = <&l4_mp_clk>;
	393	clk-gate = <0xC8 8>;
	394	};
	395
	396	s2f_usr1_clk: s2f_usr1_clk {
	397	#clock-cells = <0>;
	398	compatible = "altr,socfpga-a10-gate-clk";
	399	clocks = <&peri_s2f_usr1_clk>;
	400	clk-gate = <0xC8 6>;
475dc86d DN	401	};
	402	};
	403	};
	404
	405	gmac0: ethernet@ff800000 {
	406	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
112cadfd	407	altr,sysmgr-syscon = <&sysmgr 0x44 0>;
475dc86d DN	408	reg = <0xff800000 0x2000>;
	409	interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
	410	interrupt-names = "macirq";
	411	/* Filled in by bootloader */
	412	mac-address = [00 00 00 00 00 00];
be9863ca VB	413	snps,multicast-filter-bins = <256>;
be9863ca VB	414	snps,perfect-filter-entries = <128>;
112cadfd DN	415	tx-fifo-depth = <4096>;
	416	rx-fifo-depth = <16384>;
	417	clocks = <&l4_mp_clk>;
	418	clock-names = "stmmaceth";
6855e5b7 DN	419	resets = <&rst EMAC0_RESET>;
6855e5b7 DN	420	reset-names = "stmmaceth";
475dc86d DN	421	status = "disabled";
	422	};
	423
	424	gmac1: ethernet@ff802000 {
	425	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
112cadfd	426	altr,sysmgr-syscon = <&sysmgr 0x48 0>;
475dc86d DN	427	reg = <0xff802000 0x2000>;
	428	interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
	429	interrupt-names = "macirq";
	430	/* Filled in by bootloader */
	431	mac-address = [00 00 00 00 00 00];
be9863ca VB	432	snps,multicast-filter-bins = <256>;
be9863ca VB	433	snps,perfect-filter-entries = <128>;
c01e8cdb VB	434	tx-fifo-depth = <4096>;
c01e8cdb VB	435	rx-fifo-depth = <16384>;
112cadfd DN	436	clocks = <&l4_mp_clk>;
112cadfd DN	437	clock-names = "stmmaceth";
6855e5b7 DN	438	resets = <&rst EMAC1_RESET>;
6855e5b7 DN	439	reset-names = "stmmaceth";
475dc86d DN	440	status = "disabled";
	441	};
	442
	443	gmac2: ethernet@ff804000 {
	444	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
112cadfd	445	altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
475dc86d DN	446	reg = <0xff804000 0x2000>;
	447	interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
	448	interrupt-names = "macirq";
	449	/* Filled in by bootloader */
	450	mac-address = [00 00 00 00 00 00];
be9863ca VB	451	snps,multicast-filter-bins = <256>;
be9863ca VB	452	snps,perfect-filter-entries = <128>;
c01e8cdb VB	453	tx-fifo-depth = <4096>;
c01e8cdb VB	454	rx-fifo-depth = <16384>;
112cadfd DN	455	clocks = <&l4_mp_clk>;
112cadfd DN	456	clock-names = "stmmaceth";
475dc86d DN	457	status = "disabled";
	458	};
	459
	460	gpio0: gpio@ffc02900 {
	461	#address-cells = <1>;
	462	#size-cells = <0>;
	463	compatible = "snps,dw-apb-gpio";
	464	reg = <0xffc02900 0x100>;
	465	status = "disabled";
	466
	467	porta: gpio-controller@0 {
	468	compatible = "snps,dw-apb-gpio-port";
	469	gpio-controller;
	470	#gpio-cells = <2>;
	471	snps,nr-gpios = <29>;
	472	reg = <0>;
	473	interrupt-controller;
	474	#interrupt-cells = <2>;
	475	interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
	476	};
	477	};
	478
	479	gpio1: gpio@ffc02a00 {
	480	#address-cells = <1>;
	481	#size-cells = <0>;
	482	compatible = "snps,dw-apb-gpio";
	483	reg = <0xffc02a00 0x100>;
	484	status = "disabled";
	485
	486	portb: gpio-controller@0 {
	487	compatible = "snps,dw-apb-gpio-port";
	488	gpio-controller;
	489	#gpio-cells = <2>;
	490	snps,nr-gpios = <29>;
	491	reg = <0>;
	492	interrupt-controller;
	493	#interrupt-cells = <2>;
	494	interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
	495	};
	496	};
	497
	498	gpio2: gpio@ffc02b00 {
	499	#address-cells = <1>;
	500	#size-cells = <0>;
	501	compatible = "snps,dw-apb-gpio";
	502	reg = <0xffc02b00 0x100>;
	503	status = "disabled";
	504
	505	portc: gpio-controller@0 {
	506	compatible = "snps,dw-apb-gpio-port";
	507	gpio-controller;
	508	#gpio-cells = <2>;
	509	snps,nr-gpios = <27>;
	510	reg = <0>;
	511	interrupt-controller;
	512	#interrupt-cells = <2>;
	513	interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
	514	};
	515	};
	516
	517	i2c0: i2c@ffc02200 {
	518	#address-cells = <1>;
	519	#size-cells = <0>;
	520	compatible = "snps,designware-i2c";
521	reg = <0xffc02200 0x100>;
522	interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
e7604ae2	523	clocks = <&l4_sp_clk>;
475dc86d DN	524	status = "disabled";
	525	};
	526
	527	i2c1: i2c@ffc02300 {
	528	#address-cells = <1>;
	529	#size-cells = <0>;
	530	compatible = "snps,designware-i2c";
	531	reg = <0xffc02300 0x100>;
	532	interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
e7604ae2	533	clocks = <&l4_sp_clk>;
475dc86d DN	534	status = "disabled";
	535	};
	536
	537	i2c2: i2c@ffc02400 {
	538	#address-cells = <1>;
	539	#size-cells = <0>;
	540	compatible = "snps,designware-i2c";
	541	reg = <0xffc02400 0x100>;
	542	interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
e7604ae2	543	clocks = <&l4_sp_clk>;
475dc86d DN	544	status = "disabled";
	545	};
	546
	547	i2c3: i2c@ffc02500 {
	548	#address-cells = <1>;
	549	#size-cells = <0>;
	550	compatible = "snps,designware-i2c";
	551	reg = <0xffc02500 0x100>;
	552	interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
e7604ae2	553	clocks = <&l4_sp_clk>;
475dc86d DN	554	status = "disabled";
	555	};
	556
	557	i2c4: i2c@ffc02600 {
	558	#address-cells = <1>;
	559	#size-cells = <0>;
	560	compatible = "snps,designware-i2c";
	561	reg = <0xffc02600 0x100>;
	562	interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
e7604ae2	563	clocks = <&l4_sp_clk>;
475dc86d DN	564	status = "disabled";
	565	};
	566
54b4a8f5 TT	567	sdr: sdr@ffc25000 {
	568	compatible = "syscon";
	569	reg = <0xffcfb100 0x80>;
	570	};
	571
	572	sdramedac {
	573	compatible = "altr,sdram-edac-a10";
	574	altr,sdr-syscon = <&sdr>;
	575	interrupts = <0 2 4>, <0 0 4>;
	576	};
	577
475dc86d DN	578	L2: l2-cache@fffff000 {
	579	compatible = "arm,pl310-cache";
	580	reg = <0xfffff000 0x1000>;
	581	interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
	582	cache-unified;
	583	cache-level = <2>;
	584	};
	585
	586	mmc: dwmmc0@ff808000 {
	587	#address-cells = <1>;
	588	#size-cells = <0>;
	589	compatible = "altr,socfpga-dw-mshc";
	590	reg = <0xff808000 0x1000>;
	591	interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
	592	fifo-depth = <0x400>;
faf68cdf	593	clocks = <&l4_mp_clk>, <&sdmmc_clk>;
da29d824	594	clock-names = "biu", "ciu";
1dfb7d2f	595	status = "disabled";
475dc86d DN	596	};
	597
	598	ocram: sram@ffe00000 {
	599	compatible = "mmio-sram";
	600	reg = <0xffe00000 0x40000>;
	601	};
	602
	603	rst: rstmgr@ffd05000 {
	604	#reset-cells = <1>;
	605	compatible = "altr,rst-mgr";
	606	reg = <0xffd05000 0x100>;
1a94acf8	607	altr,modrst-offset = <0x20>;
475dc86d DN	608	};
475dc86d DN	609
479f8df0 DN	610	scu: snoop-control-unit@ffffc000 {
	611	compatible = "arm,cortex-a9-scu";
	612	reg = <0xffffc000 0x100>;
	613	};
	614
475dc86d DN	615	sysmgr: sysmgr@ffd06000 {
	616	compatible = "altr,sys-mgr", "syscon";
	617	reg = <0xffd06000 0x300>;
08d6638f	618	cpu1-start-addr = <0xffd06230>;
475dc86d DN	619	};
	620
	621	/* Local timer */
	622	timer@ffffc600 {
	623	compatible = "arm,cortex-a9-twd-timer";
	624	reg = <0xffffc600 0x100>;
	625	interrupts = <1 13 0xf04>;
da29d824	626	clocks = <&mpu_periph_clk>;
475dc86d DN	627	};
	628
	629	timer0: timer0@ffc02700 {
	630	compatible = "snps,dw-apb-timer";
	631	interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
	632	reg = <0xffc02700 0x100>;
da29d824 DN	633	clocks = <&l4_sp_clk>;
da29d824 DN	634	clock-names = "timer";
475dc86d DN	635	};
	636
	637	timer1: timer1@ffc02800 {
	638	compatible = "snps,dw-apb-timer";
	639	interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
	640	reg = <0xffc02800 0x100>;
da29d824 DN	641	clocks = <&l4_sp_clk>;
da29d824 DN	642	clock-names = "timer";
475dc86d DN	643	};
	644
	645	timer2: timer2@ffd00000 {
	646	compatible = "snps,dw-apb-timer";
	647	interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
	648	reg = <0xffd00000 0x100>;
da29d824 DN	649	clocks = <&l4_sys_free_clk>;
da29d824 DN	650	clock-names = "timer";
475dc86d DN	651	};
	652
	653	timer3: timer3@ffd00100 {
	654	compatible = "snps,dw-apb-timer";
	655	interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
	656	reg = <0xffd01000 0x100>;
da29d824 DN	657	clocks = <&l4_sys_free_clk>;
da29d824 DN	658	clock-names = "timer";
475dc86d DN	659	};
	660
	661	uart0: serial0@ffc02000 {
	662	compatible = "snps,dw-apb-uart";
	663	reg = <0xffc02000 0x100>;
	664	interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
	665	reg-shift = <2>;
	666	reg-io-width = <4>;
e7604ae2	667	clocks = <&l4_sp_clk>;
1dfb7d2f	668	status = "disabled";
475dc86d DN	669	};
	670
	671	uart1: serial1@ffc02100 {
	672	compatible = "snps,dw-apb-uart";
	673	reg = <0xffc02100 0x100>;
	674	interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
	675	reg-shift = <2>;
	676	reg-io-width = <4>;
da29d824	677	clocks = <&l4_sp_clk>;
1dfb7d2f	678	status = "disabled";
475dc86d DN	679	};
	680
	681	usbphy0: usbphy@0 {
	682	#phy-cells = <0>;
	683	compatible = "usb-nop-xceiv";
	684	status = "okay";
	685	};
	686
	687	usb0: usb@ffb00000 {
	688	compatible = "snps,dwc2";
	689	reg = <0xffb00000 0xffff>;
	690	interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
da29d824 DN	691	clocks = <&usb_clk>;
da29d824 DN	692	clock-names = "otg";
475dc86d DN	693	phys = <&usbphy0>;
	694	phy-names = "usb2-phy";
	695	status = "disabled";
	696	};
	697
	698	usb1: usb@ffb40000 {
	699	compatible = "snps,dwc2";
	700	reg = <0xffb40000 0xffff>;
	701	interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
e7604ae2 DN	702	clocks = <&usb_clk>;
e7604ae2 DN	703	clock-names = "otg";
475dc86d DN	704	phys = <&usbphy0>;
	705	phy-names = "usb2-phy";
	706	status = "disabled";
	707	};
	708
	709	watchdog0: watchdog@ffd00200 {
	710	compatible = "snps,dw-wdt";
	711	reg = <0xffd00200 0x100>;
	712	interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
da29d824	713	clocks = <&l4_sys_free_clk>;
475dc86d DN	714	status = "disabled";
	715	};
	716
	717	watchdog1: watchdog@ffd00300 {
	718	compatible = "snps,dw-wdt";
	719	reg = <0xffd00300 0x100>;
	720	interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
da29d824	721	clocks = <&l4_sys_free_clk>;
475dc86d DN	722	status = "disabled";
	723	};
	724	};
	725	};