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Merge tag 'sunxi-dt-for-4.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mripa...
[deliverable/linux.git] / arch / arm / boot / dts / ste-dbx5x0.dtsi
CommitLineData
5d0769f0
AB		 1/*
2 * Copyright 2012 Linaro Ltd
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
90c40257 12#include <dt-bindings/interrupt-controller/irq.h>
0bfe5167 13#include <dt-bindings/interrupt-controller/arm-gic.h>
841cd0c0 14#include <dt-bindings/mfd/dbx500-prcmu.h>
067addec 15#include <dt-bindings/arm/ux500_pm_domains.h>
1b1e8e02 16#include <dt-bindings/gpio/gpio.h>
807e8838 17#include "skeleton.dtsi"
5d0769f0
AB		 18
19/ {
bf64dd26
LW		 20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "ste,dbx500-smp";
24
25 cpu-map {
26 cluster0 {
27 core0 {
28 cpu = <&CPU0>;
29 };
30 core1 {
31 cpu = <&CPU1>;
32 };
33 };
34 };
35 CPU0: cpu@300 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 reg = <0x300>;
39 };
40 CPU1: cpu@301 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a9";
43 reg = <0x301>;
44 };
45 };
46
b1ba1439 47 soc {
5d0769f0
AB		 48 #address-cells = <1>;
49 #size-cells = <1>;
7e0ce270 50 compatible = "stericsson,db8500";
dab6487e 51 interrupt-parent = <&intc>;
5d0769f0 52 ranges;
7e0ce270 53
b557457f
LW		 54 ptm@801ae000 {
55 compatible = "arm,coresight-etm3x", "arm,primecell";
56 reg = <0x801ae000 0x1000>;
57
58 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
59 clock-names = "apb_pclk", "atclk";
60 cpu = <&CPU0>;
61 port {
62 ptm0_out_port: endpoint {
63 remote-endpoint = <&funnel_in_port0>;
64 };
65 };
66 };
67
68 ptm@801af000 {
69 compatible = "arm,coresight-etm3x", "arm,primecell";
70 reg = <0x801af000 0x1000>;
71
72 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
73 clock-names = "apb_pclk", "atclk";
74 cpu = <&CPU1>;
75 port {
76 ptm1_out_port: endpoint {
77 remote-endpoint = <&funnel_in_port1>;
78 };
79 };
80 };
81
82 funnel@801a6000 {
83 compatible = "arm,coresight-funnel", "arm,primecell";
84 reg = <0x801a6000 0x1000>;
85
86 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
87 clock-names = "apb_pclk", "atclk";
88 ports {
89 #address-cells = <1>;
90 #size-cells = <0>;
91
92 /* funnel output ports */
93 port@0 {
94 reg = <0>;
95 funnel_out_port: endpoint {
96 remote-endpoint =
97 <&replicator_in_port0>;
98 };
99 };
100
101 /* funnel input ports */
102 port@1 {
103 reg = <0>;
104 funnel_in_port0: endpoint {
105 slave-mode;
106 remote-endpoint = <&ptm0_out_port>;
107 };
108 };
109
110 port@2 {
111 reg = <1>;
112 funnel_in_port1: endpoint {
113 slave-mode;
114 remote-endpoint = <&ptm1_out_port>;
115 };
116 };
117 };
118 };
119
120 replicator {
121 compatible = "arm,coresight-replicator";
122 clocks = <&prcmu_clk PRCMU_APEATCLK>;
123 clock-names = "atclk";
124
125 ports {
126 #address-cells = <1>;
127 #size-cells = <0>;
128
129 /* replicator output ports */
130 port@0 {
131 reg = <0>;
132 replicator_out_port0: endpoint {
133 remote-endpoint = <&tpiu_in_port>;
134 };
135 };
136 port@1 {
137 reg = <1>;
138 replicator_out_port1: endpoint {
139 remote-endpoint = <&etb_in_port>;
140 };
141 };
142
143 /* replicator input port */
144 port@2 {
145 reg = <0>;
146 replicator_in_port0: endpoint {
147 slave-mode;
148 remote-endpoint = <&funnel_out_port>;
149 };
150 };
151 };
152 };
153
154 tpiu@80190000 {
155 compatible = "arm,coresight-tpiu", "arm,primecell";
156 reg = <0x80190000 0x1000>;
157
158 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
159 clock-names = "apb_pclk", "atclk";
160 port {
161 tpiu_in_port: endpoint {
162 slave-mode;
163 remote-endpoint = <&replicator_out_port0>;
164 };
165 };
166 };
167
168 etb@801a4000 {
169 compatible = "arm,coresight-etb10", "arm,primecell";
170 reg = <0x801a4000 0x1000>;
171
172 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
173 clock-names = "apb_pclk", "atclk";
174 port {
175 etb_in_port: endpoint {
176 slave-mode;
177 remote-endpoint = <&replicator_out_port1>;
178 };
179 };
180 };
181
dab6487e
LJ		 182 intc: interrupt-controller@a0411000 {
183 compatible = "arm,cortex-a9-gic";
184 #interrupt-cells = <3>;
185 #address-cells = <1>;
186 interrupt-controller;
dab6487e
LJ		 187 reg = <0xa0411000 0x1000>,
188 <0xa0410100 0x100>;
189 };
190
48793410
LW		 191 scu@a04100000 {
192 compatible = "arm,cortex-a9-scu";
193 reg = <0xa0410000 0x100>;
194 };
195
724814b4
LW		 196 /*
197 * The backup RAM is used for retention during sleep
198 * and various things like spin tables
199 */
200 backupram@80150000 {
201 compatible = "ste,dbx500-backupram";
202 reg = <0x80150000 0x2000>;
203 };
204
f1949ea0
LJ		 205 L2: l2-cache {
206 compatible = "arm,pl310-cache";
207 reg = <0xa0412000 0x1000>;
0bfe5167 208 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
f1949ea0
LJ		 209 cache-unified;
210 cache-level = <2>;
211 };
212
7e0ce270
LJ		 213 pmu {
214 compatible = "arm,cortex-a9-pmu";
0bfe5167 215 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
7e0ce270
LJ		 216 };
217
6c669359
UH		 218 pm_domains: pm_domains0 {
219 compatible = "stericsson,ux500-pm-domains";
220 #power-domain-cells = <1>;
221 };
8132ed1b 222
841cd0c0
LJ		 223 clocks {
224 compatible = "stericsson,u8500-clks";
5dc0fe19
LW		 225 /*
226 * Registers for the CLKRST block on peripheral
227 * groups 1, 2, 3, 5, 6,
228 */
229 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
230 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
231 <0xa03cf000 0x1000>;
841cd0c0
LJ		 232
233 prcmu_clk: prcmu-clock {
234 #clock-cells = <1>;
235 };
fcbe5e90
LJ		 236
237 prcc_pclk: prcc-periph-clock {
238 #clock-cells = <2>;
239 };
2588fea6
LJ		 240
241 prcc_kclk: prcc-kernel-clock {
242 #clock-cells = <2>;
243 };
589d9839
LJ		 244
245 rtc_clk: rtc32k-clock {
246 #clock-cells = <0>;
247 };
309012d7
LJ		 248
249 smp_twd_clk: smp-twd-clock {
250 #clock-cells = <0>;
251 };
841cd0c0
LJ		 252 };
253
8132ed1b
LJ		 254 mtu@a03c6000 {
255 /* Nomadik System Timer */
256 compatible = "st,nomadik-mtu";
257 reg = <0xa03c6000 0x1000>;
0bfe5167 258 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
8132ed1b
LJ		 259
260 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
261 clock-names = "timclk", "apb_pclk";
262 };
263
71de5c46
LJ		 264 timer@a0410600 {
265 compatible = "arm,cortex-a9-twd-timer";
266 reg = <0xa0410600 0x20>;
0bfe5167 267 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
a8acb1ec
LJ		 268
269 clocks = <&smp_twd_clk>;
71de5c46
LJ		 270 };
271
48793410
LW		 272 watchdog@a0410620 {
273 compatible = "arm,cortex-a9-twd-wdt";
274 reg = <0xa0410620 0x20>;
0bfe5167 275 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
48793410
LW		 276 clocks = <&smp_twd_clk>;
277 };
278
7e0ce270 279 rtc@80154000 {
ddb3b99c 280 compatible = "arm,rtc-pl031", "arm,primecell";
7e0ce270 281 reg = <0x80154000 0x1000>;
0bfe5167 282 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
d299b5a5
LJ		 283
284 clocks = <&rtc_clk>;
285 clock-names = "apb_pclk";
7e0ce270
LJ		 286 };
287
288 gpio0: gpio@8012e000 {
289 compatible = "stericsson,db8500-gpio",
fd9a80b2 290 "st,nomadik-gpio";
7e0ce270 291 reg = <0x8012e000 0x80>;
0bfe5167 292 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 293 interrupt-controller;
294 #interrupt-cells = <2>;
61be4981 295 st,supports-sleepmode;
7e0ce270 296 gpio-controller;
c0b133bd
LJ		 297 #gpio-cells = <2>;
298 gpio-bank = <0>;
ee04139d 299 gpio-ranges = <&pinctrl 0 0 32>;
9d891073 300 clocks = <&prcc_pclk 1 9>;
7e0ce270
LJ		 301 };
302
303 gpio1: gpio@8012e080 {
304 compatible = "stericsson,db8500-gpio",
fd9a80b2 305 "st,nomadik-gpio";
7e0ce270 306 reg = <0x8012e080 0x80>;
0bfe5167 307 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 308 interrupt-controller;
309 #interrupt-cells = <2>;
61be4981 310 st,supports-sleepmode;
7e0ce270 311 gpio-controller;
c0b133bd
LJ		 312 #gpio-cells = <2>;
313 gpio-bank = <1>;
ee04139d 314 gpio-ranges = <&pinctrl 0 32 5>;
9d891073 315 clocks = <&prcc_pclk 1 9>;
7e0ce270
LJ		 316 };
317
318 gpio2: gpio@8000e000 {
319 compatible = "stericsson,db8500-gpio",
fd9a80b2 320 "st,nomadik-gpio";
7e0ce270 321 reg = <0x8000e000 0x80>;
0bfe5167 322 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 323 interrupt-controller;
324 #interrupt-cells = <2>;
61be4981 325 st,supports-sleepmode;
7e0ce270 326 gpio-controller;
c0b133bd
LJ		 327 #gpio-cells = <2>;
328 gpio-bank = <2>;
ee04139d 329 gpio-ranges = <&pinctrl 0 64 32>;
9d891073 330 clocks = <&prcc_pclk 3 8>;
7e0ce270
LJ		 331 };
332
333 gpio3: gpio@8000e080 {
334 compatible = "stericsson,db8500-gpio",
fd9a80b2 335 "st,nomadik-gpio";
7e0ce270 336 reg = <0x8000e080 0x80>;
0bfe5167 337 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 338 interrupt-controller;
339 #interrupt-cells = <2>;
61be4981 340 st,supports-sleepmode;
7e0ce270 341 gpio-controller;
c0b133bd
LJ		 342 #gpio-cells = <2>;
343 gpio-bank = <3>;
ee04139d 344 gpio-ranges = <&pinctrl 0 96 2>;
9d891073 345 clocks = <&prcc_pclk 3 8>;
7e0ce270
LJ		 346 };
347
348 gpio4: gpio@8000e100 {
349 compatible = "stericsson,db8500-gpio",
fd9a80b2 350 "st,nomadik-gpio";
7e0ce270 351 reg = <0x8000e100 0x80>;
0bfe5167 352 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 353 interrupt-controller;
354 #interrupt-cells = <2>;
61be4981 355 st,supports-sleepmode;
7e0ce270 356 gpio-controller;
c0b133bd
LJ		 357 #gpio-cells = <2>;
358 gpio-bank = <4>;
ee04139d 359 gpio-ranges = <&pinctrl 0 128 32>;
9d891073 360 clocks = <&prcc_pclk 3 8>;
7e0ce270
LJ		 361 };
362
363 gpio5: gpio@8000e180 {
364 compatible = "stericsson,db8500-gpio",
fd9a80b2 365 "st,nomadik-gpio";
7e0ce270 366 reg = <0x8000e180 0x80>;
0bfe5167 367 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 368 interrupt-controller;
369 #interrupt-cells = <2>;
61be4981 370 st,supports-sleepmode;
7e0ce270 371 gpio-controller;
c0b133bd
LJ		 372 #gpio-cells = <2>;
373 gpio-bank = <5>;
ee04139d 374 gpio-ranges = <&pinctrl 0 160 12>;
9d891073 375 clocks = <&prcc_pclk 3 8>;
7e0ce270
LJ		 376 };
377
378 gpio6: gpio@8011e000 {
379 compatible = "stericsson,db8500-gpio",
fd9a80b2 380 "st,nomadik-gpio";
7e0ce270 381 reg = <0x8011e000 0x80>;
0bfe5167 382 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 383 interrupt-controller;
384 #interrupt-cells = <2>;
61be4981 385 st,supports-sleepmode;
7e0ce270 386 gpio-controller;
c0b133bd
LJ		 387 #gpio-cells = <2>;
388 gpio-bank = <6>;
ee04139d 389 gpio-ranges = <&pinctrl 0 192 32>;
d591640a 390 clocks = <&prcc_pclk 2 11>;
7e0ce270
LJ		 391 };
392
393 gpio7: gpio@8011e080 {
394 compatible = "stericsson,db8500-gpio",
fd9a80b2 395 "st,nomadik-gpio";
7e0ce270 396 reg = <0x8011e080 0x80>;
0bfe5167 397 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 398 interrupt-controller;
399 #interrupt-cells = <2>;
61be4981 400 st,supports-sleepmode;
7e0ce270 401 gpio-controller;
c0b133bd
LJ		 402 #gpio-cells = <2>;
403 gpio-bank = <7>;
ee04139d 404 gpio-ranges = <&pinctrl 0 224 7>;
d591640a 405 clocks = <&prcc_pclk 2 11>;
7e0ce270
LJ		 406 };
407
408 gpio8: gpio@a03fe000 {
409 compatible = "stericsson,db8500-gpio",
fd9a80b2 410 "st,nomadik-gpio";
7e0ce270 411 reg = <0xa03fe000 0x80>;
0bfe5167 412 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 413 interrupt-controller;
414 #interrupt-cells = <2>;
61be4981 415 st,supports-sleepmode;
7e0ce270 416 gpio-controller;
c0b133bd
LJ		 417 #gpio-cells = <2>;
418 gpio-bank = <8>;
ee04139d 419 gpio-ranges = <&pinctrl 0 256 12>;
84873cb7 420 clocks = <&prcc_pclk 5 1>;
7e0ce270
LJ		 421 };
422
ee04139d 423 pinctrl: pinctrl {
818d99a9 424 compatible = "stericsson,db8500-pinctrl";
ee04139d
LW		 425 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
426 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
427 <&gpio8>;
8979cfef 428 prcm = <&prcmu>;
5910de9e
LJ		 429 };
430
b32dc865 431 usb_per5@a03e0000 {
4a6cd43f 432 compatible = "stericsson,db8500-musb";
7e0ce270 433 reg = <0xa03e0000 0x10000>;
0bfe5167 434 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
b32dc865
LJ		 435 interrupt-names = "mc";
436
437 dr_mode = "otg";
438
439 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
440 <&dma 38 0 0x0>, /* Logical - MemToDev */
441 <&dma 37 0 0x2>, /* Logical - DevToMem */
442 <&dma 37 0 0x0>, /* Logical - MemToDev */
443 <&dma 36 0 0x2>, /* Logical - DevToMem */
444 <&dma 36 0 0x0>, /* Logical - MemToDev */
445 <&dma 19 0 0x2>, /* Logical - DevToMem */
446 <&dma 19 0 0x0>, /* Logical - MemToDev */
447 <&dma 18 0 0x2>, /* Logical - DevToMem */
448 <&dma 18 0 0x0>, /* Logical - MemToDev */
449 <&dma 17 0 0x2>, /* Logical - DevToMem */
450 <&dma 17 0 0x0>, /* Logical - MemToDev */
451 <&dma 16 0 0x2>, /* Logical - DevToMem */
452 <&dma 16 0 0x0>, /* Logical - MemToDev */
453 <&dma 39 0 0x2>, /* Logical - DevToMem */
454 <&dma 39 0 0x0>; /* Logical - MemToDev */
455
456 dma-names = "iep_1_9", "oep_1_9",
457 "iep_2_10", "oep_2_10",
458 "iep_3_11", "oep_3_11",
459 "iep_4_12", "oep_4_12",
460 "iep_5_13", "oep_5_13",
461 "iep_6_14", "oep_6_14",
462 "iep_7_15", "oep_7_15",
463 "iep_8", "oep_8";
e47339ff
LJ		 464
465 clocks = <&prcc_pclk 5 0>;
7e0ce270
LJ		 466 };
467
ba074aec
LJ		 468 dma: dma-controller@801C0000 {
469 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
7e0ce270 470 reg = <0x801C0000 0x1000 0x40010000 0x800>;
70d39a8d 471 reg-names = "base", "lcpa";
0bfe5167 472 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
ba074aec
LJ		 473
474 #dma-cells = <3>;
d37fcdb6 475 memcpy-channels = <56 57 58 59 60>;
e064cb24
LJ		 476
477 clocks = <&prcmu_clk PRCMU_DMACLK>;
7e0ce270
LJ		 478 };
479
8979cfef 480 prcmu: prcmu@80157000 {
7e0ce270 481 compatible = "stericsson,db8500-prcmu";
4d26aa30 482 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
e73081d9 483 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
0bfe5167 484 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
7e0ce270 485 #address-cells = <1>;
3de3d749 486 #size-cells = <1>;
c09090bb
LJ		 487 interrupt-controller;
488 #interrupt-cells = <2>;
3de3d749
LJ		 489 ranges;
490
ccf74f76 491 prcmu-timer-4@80157450 {
3de3d749
LJ		 492 compatible = "stericsson,db8500-prcmu-timer-4";
493 reg = <0x80157450 0xC>;
494 };
7e0ce270 495
98585616
LJ		 496 cpufreq {
497 compatible = "stericsson,cpufreq-ux500";
498 clocks = <&prcmu_clk PRCMU_ARMSS>;
499 clock-names = "armss";
500 status = "disabled";
501 };
502
dc1956b5 503 thermal@801573c0 {
504 compatible = "stericsson,db8500-thermal";
505 reg = <0x801573c0 0x40>;
90c40257
LW		 506 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
507 <22 IRQ_TYPE_LEVEL_HIGH>;
dc1956b5 508 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
509 status = "disabled";
1d3f99f5 510 };
dc1956b5 511
e5999f28
LJ		 512 db8500-prcmu-regulators {
513 compatible = "stericsson,db8500-prcmu-regulator";
514
515 // DB8500_REGULATOR_VAPE
516 db8500_vape_reg: db8500_vape {
e5999f28
LJ		 517 regulator-always-on;
518 };
519
520 // DB8500_REGULATOR_VARM
521 db8500_varm_reg: db8500_varm {
e5999f28
LJ		 522 };
523
524 // DB8500_REGULATOR_VMODEM
525 db8500_vmodem_reg: db8500_vmodem {
e5999f28
LJ		 526 };
527
528 // DB8500_REGULATOR_VPLL
529 db8500_vpll_reg: db8500_vpll {
e5999f28
LJ		 530 };
531
532 // DB8500_REGULATOR_VSMPS1
533 db8500_vsmps1_reg: db8500_vsmps1 {
e5999f28
LJ		 534 };
535
536 // DB8500_REGULATOR_VSMPS2
537 db8500_vsmps2_reg: db8500_vsmps2 {
e5999f28
LJ		 538 };
539
540 // DB8500_REGULATOR_VSMPS3
541 db8500_vsmps3_reg: db8500_vsmps3 {
e5999f28
LJ		 542 };
543
544 // DB8500_REGULATOR_VRF1
545 db8500_vrf1_reg: db8500_vrf1 {
e5999f28
LJ		 546 };
547
548 // DB8500_REGULATOR_SWITCH_SVAMMDSP
549 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
e5999f28
LJ		 550 };
551
552 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
553 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
e5999f28
LJ		 554 };
555
556 // DB8500_REGULATOR_SWITCH_SVAPIPE
557 db8500_sva_pipe_reg: db8500_sva_pipe {
e5999f28
LJ		 558 };
559
560 // DB8500_REGULATOR_SWITCH_SIAMMDSP
561 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
e5999f28
LJ		 562 };
563
564 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
565 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
e5999f28
LJ		 566 };
567
568 // DB8500_REGULATOR_SWITCH_SIAPIPE
569 db8500_sia_pipe_reg: db8500_sia_pipe {
e5999f28
LJ		 570 };
571
572 // DB8500_REGULATOR_SWITCH_SGA
573 db8500_sga_reg: db8500_sga {
e5999f28
LJ		 574 vin-supply = <&db8500_vape_reg>;
575 };
576
577 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
578 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
e5999f28
LJ		 579 vin-supply = <&db8500_vape_reg>;
580 };
581
582 // DB8500_REGULATOR_SWITCH_ESRAM12
583 db8500_esram12_reg: db8500_esram12 {
e5999f28
LJ		 584 };
585
586 // DB8500_REGULATOR_SWITCH_ESRAM12RET
587 db8500_esram12_ret_reg: db8500_esram12_ret {
e5999f28
LJ		 588 };
589
590 // DB8500_REGULATOR_SWITCH_ESRAM34
591 db8500_esram34_reg: db8500_esram34 {
e5999f28
LJ		 592 };
593
594 // DB8500_REGULATOR_SWITCH_ESRAM34RET
595 db8500_esram34_ret_reg: db8500_esram34_ret {
e5999f28
LJ		 596 };
597 };
598
d52701d3 599 ab8500 {
7e0ce270 600 compatible = "stericsson,ab8500";
8d4c6d45 601 interrupt-parent = <&intc>;
0bfe5167 602 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
732973c8
LJ		 603 interrupt-controller;
604 #interrupt-cells = <2>;
4a85c7fa 605
348f3bc6 606 ab8500_gpio: ab8500-gpio {
ba3fb047 607 compatible = "stericsson,ab8500-gpio";
348f3bc6
LJ		 608 gpio-controller;
609 #gpio-cells = <2>;
610 };
611
d4b29ac1
LJ		 612 ab8500-rtc {
613 compatible = "stericsson,ab8500-rtc";
90c40257
LW		 614 interrupts = <17 IRQ_TYPE_LEVEL_HIGH
615 18 IRQ_TYPE_LEVEL_HIGH>;
d4b29ac1
LJ		 616 interrupt-names = "60S", "ALARM";
617 };
618
4eda9129
LJ		 619 ab8500-gpadc {
620 compatible = "stericsson,ab8500-gpadc";
90c40257
LW		 621 interrupts = <32 IRQ_TYPE_LEVEL_HIGH
622 39 IRQ_TYPE_LEVEL_HIGH>;
4eda9129
LJ		 623 interrupt-names = "HW_CONV_END", "SW_CONV_END";
624 vddadc-supply = <&ab8500_ldo_tvout_reg>;
625 };
626
e0f1abeb
R		 627 ab8500_battery: ab8500_battery {
628 stericsson,battery-type = "LIPO";
629 thermistor-on-batctrl;
630 };
631
632 ab8500_fg {
633 compatible = "stericsson,ab8500-fg";
634 battery = <&ab8500_battery>;
635 };
636
bd9e8ab2
R		 637 ab8500_btemp {
638 compatible = "stericsson,ab8500-btemp";
639 battery = <&ab8500_battery>;
640 };
641
4aef72db
R		 642 ab8500_charger {
643 compatible = "stericsson,ab8500-charger";
644 battery = <&ab8500_battery>;
645 vddadc-supply = <&ab8500_ldo_tvout_reg>;
646 };
647
a12810ab
R		 648 ab8500_chargalg {
649 compatible = "stericsson,ab8500-chargalg";
650 battery = <&ab8500_battery>;
651 };
652
e0f1abeb 653 ab8500_usb {
ee189cef 654 compatible = "stericsson,ab8500-usb";
90c40257
LW		 655 interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
656 96 IRQ_TYPE_LEVEL_HIGH
657 14 IRQ_TYPE_LEVEL_HIGH
658 15 IRQ_TYPE_LEVEL_HIGH
659 79 IRQ_TYPE_LEVEL_HIGH
660 74 IRQ_TYPE_LEVEL_HIGH
661 75 IRQ_TYPE_LEVEL_HIGH>;
ee189cef
LJ		 662 interrupt-names = "ID_WAKEUP_R",
663 "ID_WAKEUP_F",
664 "VBUS_DET_F",
665 "VBUS_DET_R",
666 "USB_LINK_STATUS",
667 "USB_ADP_PROBE_PLUG",
668 "USB_ADP_PROBE_UNPLUG";
99b38eef 669 vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
ee189cef
LJ		 670 v-ape-supply = <&db8500_vape_reg>;
671 musb_1v8-supply = <&db8500_vsmps2_reg>;
672 };
673
12cb7bd4 674 ab8500-ponkey {
74630706 675 compatible = "stericsson,ab8500-poweron-key";
90c40257
LW		 676 interrupts = <6 IRQ_TYPE_LEVEL_HIGH
677 7 IRQ_TYPE_LEVEL_HIGH>;
12cb7bd4
LJ		 678 interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
679 };
680
401cd1b8
LJ		 681 ab8500-sysctrl {
682 compatible = "stericsson,ab8500-sysctrl";
683 };
684
78451de7
LJ		 685 ab8500-pwm {
686 compatible = "stericsson,ab8500-pwm";
687 };
688
215891ec
LJ		 689 ab8500-debugfs {
690 compatible = "stericsson,ab8500-debug";
691 };
4a85c7fa 692
9c06af30
LJ		 693 codec: ab8500-codec {
694 compatible = "stericsson,ab8500-codec";
695
f99808a6
FB		 696 V-AUD-supply = <&ab8500_ldo_audio_reg>;
697 V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
698 V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
699 V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
700
9c06af30
LJ		 701 stericsson,earpeice-cmv = <950>; /* Units in mV. */
702 };
703
62ebfe6b
LJ		 704 ext_regulators: ab8500-ext-regulators {
705 compatible = "stericsson,ab8500-ext-regulator";
706
707 ab8500_ext1_reg: ab8500_ext1 {
62ebfe6b
LJ		 708 regulator-min-microvolt = <1800000>;
709 regulator-max-microvolt = <1800000>;
710 regulator-boot-on;
711 regulator-always-on;
712 };
713
714 ab8500_ext2_reg: ab8500_ext2 {
62ebfe6b
LJ		 715 regulator-min-microvolt = <1360000>;
716 regulator-max-microvolt = <1360000>;
717 regulator-boot-on;
718 regulator-always-on;
719 };
720
721 ab8500_ext3_reg: ab8500_ext3 {
62ebfe6b
LJ		 722 regulator-min-microvolt = <3400000>;
723 regulator-max-microvolt = <3400000>;
724 regulator-boot-on;
725 };
726 };
727
4a85c7fa
LJ		 728 ab8500-regulators {
729 compatible = "stericsson,ab8500-regulator";
75f0999a 730 vin-supply = <&ab8500_ext3_reg>;
4a85c7fa
LJ		 731
732 // supplies to the display/camera
733 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
4a85c7fa
LJ		 734 regulator-min-microvolt = <2500000>;
735 regulator-max-microvolt = <2900000>;
736 regulator-boot-on;
737 /* BUG: If turned off MMC will be affected. */
738 regulator-always-on;
739 };
740
741 // supplies to the on-board eMMC
742 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
4a85c7fa
LJ		 743 regulator-min-microvolt = <1100000>;
744 regulator-max-microvolt = <3300000>;
745 };
746
747 // supply for VAUX3; SDcard slots
748 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
4a85c7fa
LJ		 749 regulator-min-microvolt = <1100000>;
750 regulator-max-microvolt = <3300000>;
751 };
752
753 // supply for v-intcore12; VINTCORE12 LDO
99b38eef 754 ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
4a85c7fa
LJ		 755 };
756
757 // supply for tvout; gpadc; TVOUT LDO
758 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
4a85c7fa
LJ		 759 };
760
761 // supply for ab8500-usb; USB LDO
762 ab8500_ldo_usb_reg: ab8500_ldo_usb {
4a85c7fa
LJ		 763 };
764
765 // supply for ab8500-vaudio; VAUDIO LDO
766 ab8500_ldo_audio_reg: ab8500_ldo_audio {
4a85c7fa
LJ		 767 };
768
4aa44874 769 // supply for v-anamic1 VAMIC1 LDO
4a85c7fa 770 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
4a85c7fa
LJ		 771 };
772
773 // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
5510ed9f 774 ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
4a85c7fa
LJ		 775 };
776
777 // supply for v-dmic; VDMIC LDO
778 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
4a85c7fa
LJ		 779 };
780
781 // supply for U8500 CSI/DSI; VANA LDO
782 ab8500_ldo_ana_reg: ab8500_ldo_ana {
4a85c7fa
LJ		 783 };
784 };
7e0ce270
LJ		 785 };
786 };
787
788 i2c@80004000 {
d524fa7f 789 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
7e0ce270 790 reg = <0x80004000 0x1000>;
0bfe5167 791 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
35b33d23 792
7e0ce270
LJ		 793 #address-cells = <1>;
794 #size-cells = <0>;
d524fa7f
LJ		 795 v-i2c-supply = <&db8500_vape_reg>;
796
797 clock-frequency = <400000>;
afd653e9
LJ		 798 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
799 clock-names = "i2cclk", "apb_pclk";
29417fe8 800 power-domains = <&pm_domains DOMAIN_VAPE>;
7e0ce270
LJ		 801 };
802
803 i2c@80122000 {
d524fa7f 804 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
7e0ce270 805 reg = <0x80122000 0x1000>;
0bfe5167 806 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
35b33d23 807
7e0ce270
LJ		 808 #address-cells = <1>;
809 #size-cells = <0>;
d524fa7f
LJ		 810 v-i2c-supply = <&db8500_vape_reg>;
811
812 clock-frequency = <400000>;
afd653e9
LJ		 813
814 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
815 clock-names = "i2cclk", "apb_pclk";
29417fe8 816 power-domains = <&pm_domains DOMAIN_VAPE>;
7e0ce270
LJ		 817 };
818
819 i2c@80128000 {
d524fa7f 820 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
7e0ce270 821 reg = <0x80128000 0x1000>;
0bfe5167 822 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
35b33d23 823
7e0ce270
LJ		 824 #address-cells = <1>;
825 #size-cells = <0>;
d524fa7f
LJ		 826 v-i2c-supply = <&db8500_vape_reg>;
827
828 clock-frequency = <400000>;
afd653e9
LJ		 829
830 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
831 clock-names = "i2cclk", "apb_pclk";
29417fe8 832 power-domains = <&pm_domains DOMAIN_VAPE>;
7e0ce270
LJ		 833 };
834
835 i2c@80110000 {
d524fa7f 836 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
7e0ce270 837 reg = <0x80110000 0x1000>;
0bfe5167 838 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
35b33d23 839
7e0ce270
LJ		 840 #address-cells = <1>;
841 #size-cells = <0>;
d524fa7f
LJ		 842 v-i2c-supply = <&db8500_vape_reg>;
843
844 clock-frequency = <400000>;
afd653e9
LJ		 845
846 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
847 clock-names = "i2cclk", "apb_pclk";
29417fe8 848 power-domains = <&pm_domains DOMAIN_VAPE>;
7e0ce270
LJ		 849 };
850
851 i2c@8012a000 {
d524fa7f 852 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
7e0ce270 853 reg = <0x8012a000 0x1000>;
0bfe5167 854 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
35b33d23 855
7e0ce270
LJ		 856 #address-cells = <1>;
857 #size-cells = <0>;
d524fa7f
LJ		 858 v-i2c-supply = <&db8500_vape_reg>;
859
860 clock-frequency = <400000>;
afd653e9 861
72b3e249 862 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
afd653e9 863 clock-names = "i2cclk", "apb_pclk";
29417fe8 864 power-domains = <&pm_domains DOMAIN_VAPE>;
7e0ce270
LJ		 865 };
866
867 ssp@80002000 {
868 compatible = "arm,pl022", "arm,primecell";
c164fa62 869 reg = <0x80002000 0x1000>;
0bfe5167 870 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
7e0ce270
LJ		 871 #address-cells = <1>;
872 #size-cells = <0>;
6e1484c2 873 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
80fbe30f 874 clock-names = "SSPCLK", "apb_pclk";
6e1484c2
LW		 875 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
876 <&dma 8 0 0x0>; /* Logical - MemToDev */
877 dma-names = "rx", "tx";
770e2f6b 878 power-domains = <&pm_domains DOMAIN_VAPE>;
6e1484c2
LW		 879 };
880
881 ssp@80003000 {
882 compatible = "arm,pl022", "arm,primecell";
883 reg = <0x80003000 0x1000>;
0bfe5167 884 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
6e1484c2
LW		 885 #address-cells = <1>;
886 #size-cells = <0>;
887 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
80fbe30f 888 clock-names = "SSPCLK", "apb_pclk";
6e1484c2
LW		 889 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
890 <&dma 9 0 0x0>; /* Logical - MemToDev */
891 dma-names = "rx", "tx";
770e2f6b 892 power-domains = <&pm_domains DOMAIN_VAPE>;
6e1484c2
LW		 893 };
894
895 spi@8011a000 {
896 compatible = "arm,pl022", "arm,primecell";
897 reg = <0x8011a000 0x1000>;
0bfe5167 898 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
6e1484c2
LW		 899 #address-cells = <1>;
900 #size-cells = <0>;
901 /* Same clock wired to kernel and pclk */
902 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
80fbe30f 903 clock-names = "SSPCLK", "apb_pclk";
6e1484c2
LW		 904 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
905 <&dma 0 0 0x0>; /* Logical - MemToDev */
906 dma-names = "rx", "tx";
770e2f6b 907 power-domains = <&pm_domains DOMAIN_VAPE>;
6e1484c2
LW		 908 };
909
910 spi@80112000 {
911 compatible = "arm,pl022", "arm,primecell";
912 reg = <0x80112000 0x1000>;
0bfe5167 913 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
6e1484c2
LW		 914 #address-cells = <1>;
915 #size-cells = <0>;
916 /* Same clock wired to kernel and pclk */
917 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
80fbe30f 918 clock-names = "SSPCLK", "apb_pclk";
6e1484c2
LW		 919 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
920 <&dma 35 0 0x0>; /* Logical - MemToDev */
921 dma-names = "rx", "tx";
770e2f6b 922 power-domains = <&pm_domains DOMAIN_VAPE>;
6e1484c2
LW		 923 };
924
925 spi@80111000 {
926 compatible = "arm,pl022", "arm,primecell";
927 reg = <0x80111000 0x1000>;
0bfe5167 928 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6e1484c2
LW		 929 #address-cells = <1>;
930 #size-cells = <0>;
931 /* Same clock wired to kernel and pclk */
932 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
80fbe30f 933 clock-names = "SSPCLK", "apb_pclk";
6e1484c2
LW		 934 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
935 <&dma 33 0 0x0>; /* Logical - MemToDev */
936 dma-names = "rx", "tx";
770e2f6b 937 power-domains = <&pm_domains DOMAIN_VAPE>;
6e1484c2
LW		 938 };
939
940 spi@80129000 {
941 compatible = "arm,pl022", "arm,primecell";
942 reg = <0x80129000 0x1000>;
0bfe5167 943 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
6e1484c2
LW		 944 #address-cells = <1>;
945 #size-cells = <0>;
946 /* Same clock wired to kernel and pclk */
947 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
80fbe30f 948 clock-names = "SSPCLK", "apb_pclk";
6e1484c2
LW		 949 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
950 <&dma 40 0 0x0>; /* Logical - MemToDev */
951 dma-names = "rx", "tx";
770e2f6b 952 power-domains = <&pm_domains DOMAIN_VAPE>;
7e0ce270
LJ		 953 };
954
109978de 955 ux500_serial0: uart@80120000 {
7e0ce270
LJ		 956 compatible = "arm,pl011", "arm,primecell";
957 reg = <0x80120000 0x1000>;
0bfe5167 958 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
fbff01cc
LJ		 959
960 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
961 <&dma 13 0 0x0>; /* Logical - MemToDev */
962 dma-names = "rx", "tx";
963
5a323fb4
LJ		 964 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
965 clock-names = "uart", "apb_pclk";
966
7e0ce270
LJ		 967 status = "disabled";
968 };
fbff01cc 969
109978de 970 ux500_serial1: uart@80121000 {
7e0ce270
LJ		 971 compatible = "arm,pl011", "arm,primecell";
972 reg = <0x80121000 0x1000>;
0bfe5167 973 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
fbff01cc
LJ		 974
975 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
976 <&dma 12 0 0x0>; /* Logical - MemToDev */
977 dma-names = "rx", "tx";
978
5a323fb4
LJ		 979 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
980 clock-names = "uart", "apb_pclk";
981
7e0ce270
LJ		 982 status = "disabled";
983 };
fbff01cc 984
109978de 985 ux500_serial2: uart@80007000 {
7e0ce270
LJ		 986 compatible = "arm,pl011", "arm,primecell";
987 reg = <0x80007000 0x1000>;
0bfe5167 988 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
fbff01cc
LJ		 989
990 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
991 <&dma 11 0 0x0>; /* Logical - MemToDev */
992 dma-names = "rx", "tx";
993
5a323fb4
LJ		 994 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
995 clock-names = "uart", "apb_pclk";
996
7e0ce270
LJ		 997 status = "disabled";
998 };
999
81bf8c2e 1000 sdi0_per1@80126000 {
7e0ce270
LJ		 1001 compatible = "arm,pl18x", "arm,primecell";
1002 reg = <0x80126000 0x1000>;
0bfe5167 1003 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
498315b9
LJ		 1004
1005 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
1006 <&dma 29 0 0x0>; /* Logical - MemToDev */
1007 dma-names = "rx", "tx";
1008
604be898
LJ		 1009 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
1010 clock-names = "sdi", "apb_pclk";
067addec 1011 power-domains = <&pm_domains DOMAIN_VAPE>;
604be898 1012
7e0ce270
LJ		 1013 status = "disabled";
1014 };
76ff4e43 1015
81bf8c2e 1016 sdi1_per2@80118000 {
7e0ce270
LJ		 1017 compatible = "arm,pl18x", "arm,primecell";
1018 reg = <0x80118000 0x1000>;
0bfe5167 1019 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
498315b9
LJ		 1020
1021 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
1022 <&dma 32 0 0x0>; /* Logical - MemToDev */
1023 dma-names = "rx", "tx";
1024
604be898
LJ		 1025 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
1026 clock-names = "sdi", "apb_pclk";
067addec 1027 power-domains = <&pm_domains DOMAIN_VAPE>;
604be898 1028
7e0ce270
LJ		 1029 status = "disabled";
1030 };
76ff4e43 1031
81bf8c2e 1032 sdi2_per3@80005000 {
7e0ce270
LJ		 1033 compatible = "arm,pl18x", "arm,primecell";
1034 reg = <0x80005000 0x1000>;
0bfe5167 1035 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
498315b9
LJ		 1036
1037 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
1038 <&dma 28 0 0x0>; /* Logical - MemToDev */
1039 dma-names = "rx", "tx";
1040
604be898
LJ		 1041 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
1042 clock-names = "sdi", "apb_pclk";
067addec 1043 power-domains = <&pm_domains DOMAIN_VAPE>;
604be898 1044
7e0ce270
LJ		 1045 status = "disabled";
1046 };
76ff4e43 1047
81bf8c2e 1048 sdi3_per2@80119000 {
7e0ce270
LJ		 1049 compatible = "arm,pl18x", "arm,primecell";
1050 reg = <0x80119000 0x1000>;
0bfe5167 1051 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
604be898 1052
14cdf8cb
LW		 1053 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
1054 <&dma 41 0 0x0>; /* Logical - MemToDev */
1055 dma-names = "rx", "tx";
1056
604be898
LJ		 1057 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
1058 clock-names = "sdi", "apb_pclk";
067addec 1059 power-domains = <&pm_domains DOMAIN_VAPE>;
604be898 1060
7e0ce270
LJ		 1061 status = "disabled";
1062 };
76ff4e43 1063
81bf8c2e 1064 sdi4_per2@80114000 {
7e0ce270
LJ		 1065 compatible = "arm,pl18x", "arm,primecell";
1066 reg = <0x80114000 0x1000>;
0bfe5167 1067 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
498315b9
LJ		 1068
1069 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
1070 <&dma 42 0 0x0>; /* Logical - MemToDev */
1071 dma-names = "rx", "tx";
1072
604be898
LJ		 1073 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
1074 clock-names = "sdi", "apb_pclk";
067addec 1075 power-domains = <&pm_domains DOMAIN_VAPE>;
604be898 1076
7e0ce270
LJ		 1077 status = "disabled";
1078 };
76ff4e43 1079
81bf8c2e 1080 sdi5_per3@80008000 {
7e0ce270 1081 compatible = "arm,pl18x", "arm,primecell";
76ff4e43 1082 reg = <0x80008000 0x1000>;
0bfe5167 1083 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
604be898 1084
14cdf8cb
LW		 1085 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
1086 <&dma 43 0 0x0>; /* Logical - MemToDev */
1087 dma-names = "rx", "tx";
1088
604be898
LJ		 1089 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
1090 clock-names = "sdi", "apb_pclk";
067addec 1091 power-domains = <&pm_domains DOMAIN_VAPE>;
604be898 1092
7e0ce270
LJ		 1093 status = "disabled";
1094 };
bf76e062 1095
fe164529
LJ		 1096 msp0: msp@80123000 {
1097 compatible = "stericsson,ux500-msp-i2s";
1098 reg = <0x80123000 0x1000>;
0bfe5167 1099 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
fe164529 1100 v-ape-supply = <&db8500_vape_reg>;
133e6027 1101
618111ca
LJ		 1102 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1103 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1104 dma-names = "rx", "tx";
1105
133e6027
LJ		 1106 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1107 clock-names = "msp", "apb_pclk";
1108
fe164529
LJ		 1109 status = "disabled";
1110 };
1111
1112 msp1: msp@80124000 {
1113 compatible = "stericsson,ux500-msp-i2s";
1114 reg = <0x80124000 0x1000>;
0bfe5167 1115 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
fe164529 1116 v-ape-supply = <&db8500_vape_reg>;
133e6027 1117
14cdf8cb 1118 /* This DMA channel only exist on DB8500 v1 */
618111ca
LJ		 1119 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1120 dma-names = "tx";
1121
133e6027
LJ		 1122 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1123 clock-names = "msp", "apb_pclk";
1124
fe164529
LJ		 1125 status = "disabled";
1126 };
1127
1128 // HDMI sound
1129 msp2: msp@80117000 {
1130 compatible = "stericsson,ux500-msp-i2s";
1131 reg = <0x80117000 0x1000>;
0bfe5167 1132 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
fe164529 1133 v-ape-supply = <&db8500_vape_reg>;
133e6027 1134
618111ca
LJ		 1135 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
1136 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1137 HighPrio - Fixed */
1138 dma-names = "rx", "tx";
1139
133e6027
LJ		 1140 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1141 clock-names = "msp", "apb_pclk";
1142
fe164529
LJ		 1143 status = "disabled";
1144 };
1145
1146 msp3: msp@80125000 {
1147 compatible = "stericsson,ux500-msp-i2s";
1148 reg = <0x80125000 0x1000>;
0bfe5167 1149 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
fe164529 1150 v-ape-supply = <&db8500_vape_reg>;
133e6027 1151
14cdf8cb 1152 /* This DMA channel only exist on DB8500 v2 */
618111ca
LJ		 1153 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1154 dma-names = "rx";
1155
133e6027
LJ		 1156 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1157 clock-names = "msp", "apb_pclk";
1158
fe164529
LJ		 1159 status = "disabled";
1160 };
1161
bf76e062
LJ		 1162 external-bus@50000000 {
1163 compatible = "simple-bus";
1164 reg = <0x50000000 0x4000000>;
1165 #address-cells = <1>;
1166 #size-cells = <1>;
1167 ranges = <0 0x50000000 0x4000000>;
1168 status = "disabled";
1169 };
dc1956b5 1170
1171 cpufreq-cooling {
1172 compatible = "stericsson,db8500-cpufreq-cooling";
1173 status = "disabled";
d460d28b 1174 };
dc1956b5 1175
6e9a88a0
LW		 1176 mcde@a0350000 {
1177 compatible = "stericsson,mcde";
1178 reg = <0xa0350000 0x1000>, /* MCDE */
1179 <0xa0351000 0x1000>, /* DSI link 1 */
1180 <0xa0352000 0x1000>, /* DSI link 2 */
1181 <0xa0353000 0x1000>; /* DSI link 3 */
0bfe5167 1182 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
6e9a88a0
LW		 1183 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1184 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1185 <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
1186 <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
1187 <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
1188 <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
1189 <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
1190 <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
1191 };
1192
fe2e9f92
LJ		 1193 cryp@a03cb000 {
1194 compatible = "stericsson,ux500-cryp";
1195 reg = <0xa03cb000 0x1000>;
0bfe5167 1196 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
fe2e9f92
LJ		 1197
1198 v-ape-supply = <&db8500_vape_reg>;
d2f898ce 1199 clocks = <&prcc_pclk 6 1>;
fe2e9f92 1200 };
61122cf2
LJ		 1201
1202 hash@a03c2000 {
1203 compatible = "stericsson,ux500-hash";
1204 reg = <0xa03c2000 0x1000>;
1205
1206 v-ape-supply = <&db8500_vape_reg>;
024cfe88 1207 clocks = <&prcc_pclk 6 2>;
61122cf2 1208 };
5d0769f0
AB		 1209 };
1210};
Linux kernel - Deliverables
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