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clk: remove duplicated code with __clk_set_parent_after
[deliverable/linux.git] / arch / arm / boot / dts / ste-dbx5x0.dtsi
CommitLineData
5d0769f0
AB		 1/*
2 * Copyright 2012 Linaro Ltd
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
90c40257 12#include <dt-bindings/interrupt-controller/irq.h>
841cd0c0 13#include <dt-bindings/mfd/dbx500-prcmu.h>
067addec 14#include <dt-bindings/arm/ux500_pm_domains.h>
807e8838 15#include "skeleton.dtsi"
5d0769f0
AB		 16
17/ {
b1ba1439 18 soc {
5d0769f0
AB		 19 #address-cells = <1>;
20 #size-cells = <1>;
7e0ce270 21 compatible = "stericsson,db8500";
dab6487e 22 interrupt-parent = <&intc>;
5d0769f0 23 ranges;
7e0ce270 24
771969ec
LW		 25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu-map {
30 cluster0 {
31 core0 {
32 cpu = <&CPU0>;
33 };
34 core1 {
35 cpu = <&CPU1>;
36 };
37 };
38 };
39 CPU0: cpu@0 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a9";
42 reg = <0>;
43 };
44 CPU1: cpu@1 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a9";
47 reg = <1>;
48 };
49 };
50
b557457f
LW		 51 ptm@801ae000 {
52 compatible = "arm,coresight-etm3x", "arm,primecell";
53 reg = <0x801ae000 0x1000>;
54
55 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
56 clock-names = "apb_pclk", "atclk";
57 cpu = <&CPU0>;
58 port {
59 ptm0_out_port: endpoint {
60 remote-endpoint = <&funnel_in_port0>;
61 };
62 };
63 };
64
65 ptm@801af000 {
66 compatible = "arm,coresight-etm3x", "arm,primecell";
67 reg = <0x801af000 0x1000>;
68
69 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
70 clock-names = "apb_pclk", "atclk";
71 cpu = <&CPU1>;
72 port {
73 ptm1_out_port: endpoint {
74 remote-endpoint = <&funnel_in_port1>;
75 };
76 };
77 };
78
79 funnel@801a6000 {
80 compatible = "arm,coresight-funnel", "arm,primecell";
81 reg = <0x801a6000 0x1000>;
82
83 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
84 clock-names = "apb_pclk", "atclk";
85 ports {
86 #address-cells = <1>;
87 #size-cells = <0>;
88
89 /* funnel output ports */
90 port@0 {
91 reg = <0>;
92 funnel_out_port: endpoint {
93 remote-endpoint =
94 <&replicator_in_port0>;
95 };
96 };
97
98 /* funnel input ports */
99 port@1 {
100 reg = <0>;
101 funnel_in_port0: endpoint {
102 slave-mode;
103 remote-endpoint = <&ptm0_out_port>;
104 };
105 };
106
107 port@2 {
108 reg = <1>;
109 funnel_in_port1: endpoint {
110 slave-mode;
111 remote-endpoint = <&ptm1_out_port>;
112 };
113 };
114 };
115 };
116
117 replicator {
118 compatible = "arm,coresight-replicator";
119 clocks = <&prcmu_clk PRCMU_APEATCLK>;
120 clock-names = "atclk";
121
122 ports {
123 #address-cells = <1>;
124 #size-cells = <0>;
125
126 /* replicator output ports */
127 port@0 {
128 reg = <0>;
129 replicator_out_port0: endpoint {
130 remote-endpoint = <&tpiu_in_port>;
131 };
132 };
133 port@1 {
134 reg = <1>;
135 replicator_out_port1: endpoint {
136 remote-endpoint = <&etb_in_port>;
137 };
138 };
139
140 /* replicator input port */
141 port@2 {
142 reg = <0>;
143 replicator_in_port0: endpoint {
144 slave-mode;
145 remote-endpoint = <&funnel_out_port>;
146 };
147 };
148 };
149 };
150
151 tpiu@80190000 {
152 compatible = "arm,coresight-tpiu", "arm,primecell";
153 reg = <0x80190000 0x1000>;
154
155 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
156 clock-names = "apb_pclk", "atclk";
157 port {
158 tpiu_in_port: endpoint {
159 slave-mode;
160 remote-endpoint = <&replicator_out_port0>;
161 };
162 };
163 };
164
165 etb@801a4000 {
166 compatible = "arm,coresight-etb10", "arm,primecell";
167 reg = <0x801a4000 0x1000>;
168
169 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
170 clock-names = "apb_pclk", "atclk";
171 port {
172 etb_in_port: endpoint {
173 slave-mode;
174 remote-endpoint = <&replicator_out_port1>;
175 };
176 };
177 };
178
dab6487e
LJ		 179 intc: interrupt-controller@a0411000 {
180 compatible = "arm,cortex-a9-gic";
181 #interrupt-cells = <3>;
182 #address-cells = <1>;
183 interrupt-controller;
dab6487e
LJ		 184 reg = <0xa0411000 0x1000>,
185 <0xa0410100 0x100>;
186 };
187
48793410
LW		 188 scu@a04100000 {
189 compatible = "arm,cortex-a9-scu";
190 reg = <0xa0410000 0x100>;
191 };
192
724814b4
LW		 193 /*
194 * The backup RAM is used for retention during sleep
195 * and various things like spin tables
196 */
197 backupram@80150000 {
198 compatible = "ste,dbx500-backupram";
199 reg = <0x80150000 0x2000>;
200 };
201
f1949ea0
LJ		 202 L2: l2-cache {
203 compatible = "arm,pl310-cache";
204 reg = <0xa0412000 0x1000>;
90c40257 205 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
f1949ea0
LJ		 206 cache-unified;
207 cache-level = <2>;
208 };
209
7e0ce270
LJ		 210 pmu {
211 compatible = "arm,cortex-a9-pmu";
90c40257 212 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
7e0ce270
LJ		 213 };
214
6c669359
UH		 215 pm_domains: pm_domains0 {
216 compatible = "stericsson,ux500-pm-domains";
217 #power-domain-cells = <1>;
218 };
8132ed1b 219
841cd0c0
LJ		 220 clocks {
221 compatible = "stericsson,u8500-clks";
222
223 prcmu_clk: prcmu-clock {
224 #clock-cells = <1>;
225 };
fcbe5e90
LJ		 226
227 prcc_pclk: prcc-periph-clock {
228 #clock-cells = <2>;
229 };
2588fea6
LJ		 230
231 prcc_kclk: prcc-kernel-clock {
232 #clock-cells = <2>;
233 };
589d9839
LJ		 234
235 rtc_clk: rtc32k-clock {
236 #clock-cells = <0>;
237 };
309012d7
LJ		 238
239 smp_twd_clk: smp-twd-clock {
240 #clock-cells = <0>;
241 };
841cd0c0
LJ		 242 };
243
8132ed1b
LJ		 244 mtu@a03c6000 {
245 /* Nomadik System Timer */
246 compatible = "st,nomadik-mtu";
247 reg = <0xa03c6000 0x1000>;
248 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
249
250 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
251 clock-names = "timclk", "apb_pclk";
252 };
253
71de5c46
LJ		 254 timer@a0410600 {
255 compatible = "arm,cortex-a9-twd-timer";
256 reg = <0xa0410600 0x20>;
90c40257 257 interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
a8acb1ec
LJ		 258
259 clocks = <&smp_twd_clk>;
71de5c46
LJ		 260 };
261
48793410
LW		 262 watchdog@a0410620 {
263 compatible = "arm,cortex-a9-twd-wdt";
264 reg = <0xa0410620 0x20>;
265 interrupts = <1 14 0x304>;
266 clocks = <&smp_twd_clk>;
267 };
268
7e0ce270 269 rtc@80154000 {
ddb3b99c 270 compatible = "arm,rtc-pl031", "arm,primecell";
7e0ce270 271 reg = <0x80154000 0x1000>;
90c40257 272 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
d299b5a5
LJ		 273
274 clocks = <&rtc_clk>;
275 clock-names = "apb_pclk";
7e0ce270
LJ		 276 };
277
278 gpio0: gpio@8012e000 {
279 compatible = "stericsson,db8500-gpio",
fd9a80b2 280 "st,nomadik-gpio";
7e0ce270 281 reg = <0x8012e000 0x80>;
90c40257 282 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 283 interrupt-controller;
284 #interrupt-cells = <2>;
61be4981 285 st,supports-sleepmode;
7e0ce270 286 gpio-controller;
c0b133bd
LJ		 287 #gpio-cells = <2>;
288 gpio-bank = <0>;
9d891073
LJ		 289
290 clocks = <&prcc_pclk 1 9>;
7e0ce270
LJ		 291 };
292
293 gpio1: gpio@8012e080 {
294 compatible = "stericsson,db8500-gpio",
fd9a80b2 295 "st,nomadik-gpio";
7e0ce270 296 reg = <0x8012e080 0x80>;
90c40257 297 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 298 interrupt-controller;
299 #interrupt-cells = <2>;
61be4981 300 st,supports-sleepmode;
7e0ce270 301 gpio-controller;
c0b133bd
LJ		 302 #gpio-cells = <2>;
303 gpio-bank = <1>;
9d891073
LJ		 304
305 clocks = <&prcc_pclk 1 9>;
7e0ce270
LJ		 306 };
307
308 gpio2: gpio@8000e000 {
309 compatible = "stericsson,db8500-gpio",
fd9a80b2 310 "st,nomadik-gpio";
7e0ce270 311 reg = <0x8000e000 0x80>;
90c40257 312 interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 313 interrupt-controller;
314 #interrupt-cells = <2>;
61be4981 315 st,supports-sleepmode;
7e0ce270 316 gpio-controller;
c0b133bd
LJ		 317 #gpio-cells = <2>;
318 gpio-bank = <2>;
9d891073
LJ		 319
320 clocks = <&prcc_pclk 3 8>;
7e0ce270
LJ		 321 };
322
323 gpio3: gpio@8000e080 {
324 compatible = "stericsson,db8500-gpio",
fd9a80b2 325 "st,nomadik-gpio";
7e0ce270 326 reg = <0x8000e080 0x80>;
90c40257 327 interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 328 interrupt-controller;
329 #interrupt-cells = <2>;
61be4981 330 st,supports-sleepmode;
7e0ce270 331 gpio-controller;
c0b133bd
LJ		 332 #gpio-cells = <2>;
333 gpio-bank = <3>;
9d891073
LJ		 334
335 clocks = <&prcc_pclk 3 8>;
7e0ce270
LJ		 336 };
337
338 gpio4: gpio@8000e100 {
339 compatible = "stericsson,db8500-gpio",
fd9a80b2 340 "st,nomadik-gpio";
7e0ce270 341 reg = <0x8000e100 0x80>;
90c40257 342 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 343 interrupt-controller;
344 #interrupt-cells = <2>;
61be4981 345 st,supports-sleepmode;
7e0ce270 346 gpio-controller;
c0b133bd
LJ		 347 #gpio-cells = <2>;
348 gpio-bank = <4>;
9d891073
LJ		 349
350 clocks = <&prcc_pclk 3 8>;
7e0ce270
LJ		 351 };
352
353 gpio5: gpio@8000e180 {
354 compatible = "stericsson,db8500-gpio",
fd9a80b2 355 "st,nomadik-gpio";
7e0ce270 356 reg = <0x8000e180 0x80>;
90c40257 357 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 358 interrupt-controller;
359 #interrupt-cells = <2>;
61be4981 360 st,supports-sleepmode;
7e0ce270 361 gpio-controller;
c0b133bd
LJ		 362 #gpio-cells = <2>;
363 gpio-bank = <5>;
9d891073
LJ		 364
365 clocks = <&prcc_pclk 3 8>;
7e0ce270
LJ		 366 };
367
368 gpio6: gpio@8011e000 {
369 compatible = "stericsson,db8500-gpio",
fd9a80b2 370 "st,nomadik-gpio";
7e0ce270 371 reg = <0x8011e000 0x80>;
90c40257 372 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 373 interrupt-controller;
374 #interrupt-cells = <2>;
61be4981 375 st,supports-sleepmode;
7e0ce270 376 gpio-controller;
c0b133bd
LJ		 377 #gpio-cells = <2>;
378 gpio-bank = <6>;
9d891073 379
d591640a 380 clocks = <&prcc_pclk 2 11>;
7e0ce270
LJ		 381 };
382
383 gpio7: gpio@8011e080 {
384 compatible = "stericsson,db8500-gpio",
fd9a80b2 385 "st,nomadik-gpio";
7e0ce270 386 reg = <0x8011e080 0x80>;
90c40257 387 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 388 interrupt-controller;
389 #interrupt-cells = <2>;
61be4981 390 st,supports-sleepmode;
7e0ce270 391 gpio-controller;
c0b133bd
LJ		 392 #gpio-cells = <2>;
393 gpio-bank = <7>;
9d891073 394
d591640a 395 clocks = <&prcc_pclk 2 11>;
7e0ce270
LJ		 396 };
397
398 gpio8: gpio@a03fe000 {
399 compatible = "stericsson,db8500-gpio",
fd9a80b2 400 "st,nomadik-gpio";
7e0ce270 401 reg = <0xa03fe000 0x80>;
90c40257 402 interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
93b5698a
LJ		 403 interrupt-controller;
404 #interrupt-cells = <2>;
61be4981 405 st,supports-sleepmode;
7e0ce270 406 gpio-controller;
c0b133bd
LJ		 407 #gpio-cells = <2>;
408 gpio-bank = <8>;
9d891073 409
84873cb7 410 clocks = <&prcc_pclk 5 1>;
7e0ce270
LJ		 411 };
412
8979cfef 413 pinctrl {
818d99a9 414 compatible = "stericsson,db8500-pinctrl";
8979cfef 415 prcm = <&prcmu>;
5910de9e
LJ		 416 };
417
b32dc865 418 usb_per5@a03e0000 {
4a6cd43f 419 compatible = "stericsson,db8500-musb";
7e0ce270 420 reg = <0xa03e0000 0x10000>;
90c40257 421 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
b32dc865
LJ		 422 interrupt-names = "mc";
423
424 dr_mode = "otg";
425
426 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
427 <&dma 38 0 0x0>, /* Logical - MemToDev */
428 <&dma 37 0 0x2>, /* Logical - DevToMem */
429 <&dma 37 0 0x0>, /* Logical - MemToDev */
430 <&dma 36 0 0x2>, /* Logical - DevToMem */
431 <&dma 36 0 0x0>, /* Logical - MemToDev */
432 <&dma 19 0 0x2>, /* Logical - DevToMem */
433 <&dma 19 0 0x0>, /* Logical - MemToDev */
434 <&dma 18 0 0x2>, /* Logical - DevToMem */
435 <&dma 18 0 0x0>, /* Logical - MemToDev */
436 <&dma 17 0 0x2>, /* Logical - DevToMem */
437 <&dma 17 0 0x0>, /* Logical - MemToDev */
438 <&dma 16 0 0x2>, /* Logical - DevToMem */
439 <&dma 16 0 0x0>, /* Logical - MemToDev */
440 <&dma 39 0 0x2>, /* Logical - DevToMem */
441 <&dma 39 0 0x0>; /* Logical - MemToDev */
442
443 dma-names = "iep_1_9", "oep_1_9",
444 "iep_2_10", "oep_2_10",
445 "iep_3_11", "oep_3_11",
446 "iep_4_12", "oep_4_12",
447 "iep_5_13", "oep_5_13",
448 "iep_6_14", "oep_6_14",
449 "iep_7_15", "oep_7_15",
450 "iep_8", "oep_8";
e47339ff
LJ		 451
452 clocks = <&prcc_pclk 5 0>;
7e0ce270
LJ		 453 };
454
ba074aec
LJ		 455 dma: dma-controller@801C0000 {
456 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
7e0ce270 457 reg = <0x801C0000 0x1000 0x40010000 0x800>;
70d39a8d 458 reg-names = "base", "lcpa";
90c40257 459 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
ba074aec
LJ		 460
461 #dma-cells = <3>;
d37fcdb6 462 memcpy-channels = <56 57 58 59 60>;
e064cb24
LJ		 463
464 clocks = <&prcmu_clk PRCMU_DMACLK>;
7e0ce270
LJ		 465 };
466
8979cfef 467 prcmu: prcmu@80157000 {
7e0ce270 468 compatible = "stericsson,db8500-prcmu";
4d26aa30 469 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
e73081d9 470 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
90c40257 471 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
7e0ce270 472 #address-cells = <1>;
3de3d749 473 #size-cells = <1>;
c09090bb
LJ		 474 interrupt-controller;
475 #interrupt-cells = <2>;
3de3d749
LJ		 476 ranges;
477
ccf74f76 478 prcmu-timer-4@80157450 {
3de3d749
LJ		 479 compatible = "stericsson,db8500-prcmu-timer-4";
480 reg = <0x80157450 0xC>;
481 };
7e0ce270 482
98585616
LJ		 483 cpufreq {
484 compatible = "stericsson,cpufreq-ux500";
485 clocks = <&prcmu_clk PRCMU_ARMSS>;
486 clock-names = "armss";
487 status = "disabled";
488 };
489
dc1956b5 490 thermal@801573c0 {
491 compatible = "stericsson,db8500-thermal";
492 reg = <0x801573c0 0x40>;
90c40257
LW		 493 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
494 <22 IRQ_TYPE_LEVEL_HIGH>;
dc1956b5 495 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
496 status = "disabled";
1d3f99f5 497 };
dc1956b5 498
e5999f28
LJ		 499 db8500-prcmu-regulators {
500 compatible = "stericsson,db8500-prcmu-regulator";
501
502 // DB8500_REGULATOR_VAPE
503 db8500_vape_reg: db8500_vape {
da26848a 504 regulator-compatible = "db8500_vape";
e5999f28
LJ		 505 regulator-always-on;
506 };
507
508 // DB8500_REGULATOR_VARM
509 db8500_varm_reg: db8500_varm {
da26848a 510 regulator-compatible = "db8500_varm";
e5999f28
LJ		 511 };
512
513 // DB8500_REGULATOR_VMODEM
514 db8500_vmodem_reg: db8500_vmodem {
da26848a 515 regulator-compatible = "db8500_vmodem";
e5999f28
LJ		 516 };
517
518 // DB8500_REGULATOR_VPLL
519 db8500_vpll_reg: db8500_vpll {
da26848a 520 regulator-compatible = "db8500_vpll";
e5999f28
LJ		 521 };
522
523 // DB8500_REGULATOR_VSMPS1
524 db8500_vsmps1_reg: db8500_vsmps1 {
da26848a 525 regulator-compatible = "db8500_vsmps1";
e5999f28
LJ		 526 };
527
528 // DB8500_REGULATOR_VSMPS2
529 db8500_vsmps2_reg: db8500_vsmps2 {
da26848a 530 regulator-compatible = "db8500_vsmps2";
e5999f28
LJ		 531 };
532
533 // DB8500_REGULATOR_VSMPS3
534 db8500_vsmps3_reg: db8500_vsmps3 {
da26848a 535 regulator-compatible = "db8500_vsmps3";
e5999f28
LJ		 536 };
537
538 // DB8500_REGULATOR_VRF1
539 db8500_vrf1_reg: db8500_vrf1 {
da26848a 540 regulator-compatible = "db8500_vrf1";
e5999f28
LJ		 541 };
542
543 // DB8500_REGULATOR_SWITCH_SVAMMDSP
544 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
da26848a 545 regulator-compatible = "db8500_sva_mmdsp";
e5999f28
LJ		 546 };
547
548 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
549 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
da26848a 550 regulator-compatible = "db8500_sva_mmdsp_ret";
e5999f28
LJ		 551 };
552
553 // DB8500_REGULATOR_SWITCH_SVAPIPE
554 db8500_sva_pipe_reg: db8500_sva_pipe {
da26848a 555 regulator-compatible = "db8500_sva_pipe";
e5999f28
LJ		 556 };
557
558 // DB8500_REGULATOR_SWITCH_SIAMMDSP
559 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
da26848a 560 regulator-compatible = "db8500_sia_mmdsp";
e5999f28
LJ		 561 };
562
563 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
564 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
e5999f28
LJ		 565 };
566
567 // DB8500_REGULATOR_SWITCH_SIAPIPE
568 db8500_sia_pipe_reg: db8500_sia_pipe {
da26848a 569 regulator-compatible = "db8500_sia_pipe";
e5999f28
LJ		 570 };
571
572 // DB8500_REGULATOR_SWITCH_SGA
573 db8500_sga_reg: db8500_sga {
da26848a 574 regulator-compatible = "db8500_sga";
e5999f28
LJ		 575 vin-supply = <&db8500_vape_reg>;
576 };
577
578 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
579 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
da26848a 580 regulator-compatible = "db8500_b2r2_mcde";
e5999f28
LJ		 581 vin-supply = <&db8500_vape_reg>;
582 };
583
584 // DB8500_REGULATOR_SWITCH_ESRAM12
585 db8500_esram12_reg: db8500_esram12 {
da26848a 586 regulator-compatible = "db8500_esram12";
e5999f28
LJ		 587 };
588
589 // DB8500_REGULATOR_SWITCH_ESRAM12RET
590 db8500_esram12_ret_reg: db8500_esram12_ret {
da26848a 591 regulator-compatible = "db8500_esram12_ret";
e5999f28
LJ		 592 };
593
594 // DB8500_REGULATOR_SWITCH_ESRAM34
595 db8500_esram34_reg: db8500_esram34 {
da26848a 596 regulator-compatible = "db8500_esram34";
e5999f28
LJ		 597 };
598
599 // DB8500_REGULATOR_SWITCH_ESRAM34RET
600 db8500_esram34_ret_reg: db8500_esram34_ret {
da26848a 601 regulator-compatible = "db8500_esram34_ret";
e5999f28
LJ		 602 };
603 };
604
d52701d3 605 ab8500 {
7e0ce270 606 compatible = "stericsson,ab8500";
8d4c6d45 607 interrupt-parent = <&intc>;
90c40257 608 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
732973c8
LJ		 609 interrupt-controller;
610 #interrupt-cells = <2>;
4a85c7fa 611
348f3bc6
LJ		 612 ab8500_gpio: ab8500-gpio {
613 gpio-controller;
614 #gpio-cells = <2>;
615 };
616
d4b29ac1
LJ		 617 ab8500-rtc {
618 compatible = "stericsson,ab8500-rtc";
90c40257
LW		 619 interrupts = <17 IRQ_TYPE_LEVEL_HIGH
620 18 IRQ_TYPE_LEVEL_HIGH>;
d4b29ac1
LJ		 621 interrupt-names = "60S", "ALARM";
622 };
623
4eda9129
LJ		 624 ab8500-gpadc {
625 compatible = "stericsson,ab8500-gpadc";
90c40257
LW		 626 interrupts = <32 IRQ_TYPE_LEVEL_HIGH
627 39 IRQ_TYPE_LEVEL_HIGH>;
4eda9129
LJ		 628 interrupt-names = "HW_CONV_END", "SW_CONV_END";
629 vddadc-supply = <&ab8500_ldo_tvout_reg>;
630 };
631
e0f1abeb
R		 632 ab8500_battery: ab8500_battery {
633 stericsson,battery-type = "LIPO";
634 thermistor-on-batctrl;
635 };
636
637 ab8500_fg {
638 compatible = "stericsson,ab8500-fg";
639 battery = <&ab8500_battery>;
640 };
641
bd9e8ab2
R		 642 ab8500_btemp {
643 compatible = "stericsson,ab8500-btemp";
644 battery = <&ab8500_battery>;
645 };
646
4aef72db
R		 647 ab8500_charger {
648 compatible = "stericsson,ab8500-charger";
649 battery = <&ab8500_battery>;
650 vddadc-supply = <&ab8500_ldo_tvout_reg>;
651 };
652
a12810ab
R		 653 ab8500_chargalg {
654 compatible = "stericsson,ab8500-chargalg";
655 battery = <&ab8500_battery>;
656 };
657
e0f1abeb 658 ab8500_usb {
ee189cef 659 compatible = "stericsson,ab8500-usb";
90c40257
LW		 660 interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
661 96 IRQ_TYPE_LEVEL_HIGH
662 14 IRQ_TYPE_LEVEL_HIGH
663 15 IRQ_TYPE_LEVEL_HIGH
664 79 IRQ_TYPE_LEVEL_HIGH
665 74 IRQ_TYPE_LEVEL_HIGH
666 75 IRQ_TYPE_LEVEL_HIGH>;
ee189cef
LJ		 667 interrupt-names = "ID_WAKEUP_R",
668 "ID_WAKEUP_F",
669 "VBUS_DET_F",
670 "VBUS_DET_R",
671 "USB_LINK_STATUS",
672 "USB_ADP_PROBE_PLUG",
673 "USB_ADP_PROBE_UNPLUG";
99b38eef 674 vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
ee189cef
LJ		 675 v-ape-supply = <&db8500_vape_reg>;
676 musb_1v8-supply = <&db8500_vsmps2_reg>;
677 };
678
12cb7bd4 679 ab8500-ponkey {
74630706 680 compatible = "stericsson,ab8500-poweron-key";
90c40257
LW		 681 interrupts = <6 IRQ_TYPE_LEVEL_HIGH
682 7 IRQ_TYPE_LEVEL_HIGH>;
12cb7bd4
LJ		 683 interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
684 };
685
401cd1b8
LJ		 686 ab8500-sysctrl {
687 compatible = "stericsson,ab8500-sysctrl";
688 };
689
78451de7
LJ		 690 ab8500-pwm {
691 compatible = "stericsson,ab8500-pwm";
692 };
693
215891ec
LJ		 694 ab8500-debugfs {
695 compatible = "stericsson,ab8500-debug";
696 };
4a85c7fa 697
9c06af30
LJ		 698 codec: ab8500-codec {
699 compatible = "stericsson,ab8500-codec";
700
f99808a6
FB		 701 V-AUD-supply = <&ab8500_ldo_audio_reg>;
702 V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
703 V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
704 V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
705
9c06af30
LJ		 706 stericsson,earpeice-cmv = <950>; /* Units in mV. */
707 };
708
62ebfe6b
LJ		 709 ext_regulators: ab8500-ext-regulators {
710 compatible = "stericsson,ab8500-ext-regulator";
711
712 ab8500_ext1_reg: ab8500_ext1 {
713 regulator-compatible = "ab8500_ext1";
714 regulator-min-microvolt = <1800000>;
715 regulator-max-microvolt = <1800000>;
716 regulator-boot-on;
717 regulator-always-on;
718 };
719
720 ab8500_ext2_reg: ab8500_ext2 {
721 regulator-compatible = "ab8500_ext2";
722 regulator-min-microvolt = <1360000>;
723 regulator-max-microvolt = <1360000>;
724 regulator-boot-on;
725 regulator-always-on;
726 };
727
728 ab8500_ext3_reg: ab8500_ext3 {
729 regulator-compatible = "ab8500_ext3";
730 regulator-min-microvolt = <3400000>;
731 regulator-max-microvolt = <3400000>;
732 regulator-boot-on;
733 };
734 };
735
4a85c7fa
LJ		 736 ab8500-regulators {
737 compatible = "stericsson,ab8500-regulator";
75f0999a 738 vin-supply = <&ab8500_ext3_reg>;
4a85c7fa
LJ		 739
740 // supplies to the display/camera
741 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
da26848a 742 regulator-compatible = "ab8500_ldo_aux1";
4a85c7fa
LJ		 743 regulator-min-microvolt = <2500000>;
744 regulator-max-microvolt = <2900000>;
745 regulator-boot-on;
746 /* BUG: If turned off MMC will be affected. */
747 regulator-always-on;
748 };
749
750 // supplies to the on-board eMMC
751 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
da26848a 752 regulator-compatible = "ab8500_ldo_aux2";
4a85c7fa
LJ		 753 regulator-min-microvolt = <1100000>;
754 regulator-max-microvolt = <3300000>;
755 };
756
757 // supply for VAUX3; SDcard slots
758 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
da26848a 759 regulator-compatible = "ab8500_ldo_aux3";
4a85c7fa
LJ		 760 regulator-min-microvolt = <1100000>;
761 regulator-max-microvolt = <3300000>;
762 };
763
764 // supply for v-intcore12; VINTCORE12 LDO
99b38eef
FB		 765 ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
766 regulator-compatible = "ab8500_ldo_intcore";
4a85c7fa
LJ		 767 };
768
769 // supply for tvout; gpadc; TVOUT LDO
770 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
da26848a 771 regulator-compatible = "ab8500_ldo_tvout";
4a85c7fa
LJ		 772 };
773
774 // supply for ab8500-usb; USB LDO
775 ab8500_ldo_usb_reg: ab8500_ldo_usb {
da26848a 776 regulator-compatible = "ab8500_ldo_usb";
4a85c7fa
LJ		 777 };
778
779 // supply for ab8500-vaudio; VAUDIO LDO
780 ab8500_ldo_audio_reg: ab8500_ldo_audio {
da26848a 781 regulator-compatible = "ab8500_ldo_audio";
4a85c7fa
LJ		 782 };
783
4aa44874 784 // supply for v-anamic1 VAMIC1 LDO
4a85c7fa 785 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
da26848a 786 regulator-compatible = "ab8500_ldo_anamic1";
4a85c7fa
LJ		 787 };
788
789 // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
5510ed9f
FB		 790 ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
791 regulator-compatible = "ab8500_ldo_anamic2";
4a85c7fa
LJ		 792 };
793
794 // supply for v-dmic; VDMIC LDO
795 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
da26848a 796 regulator-compatible = "ab8500_ldo_dmic";
4a85c7fa
LJ		 797 };
798
799 // supply for U8500 CSI/DSI; VANA LDO
800 ab8500_ldo_ana_reg: ab8500_ldo_ana {
da26848a 801 regulator-compatible = "ab8500_ldo_ana";
4a85c7fa
LJ		 802 };
803 };
7e0ce270
LJ		 804 };
805 };
806
807 i2c@80004000 {
d524fa7f 808 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
7e0ce270 809 reg = <0x80004000 0x1000>;
90c40257 810 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
35b33d23 811
7e0ce270
LJ		 812 #address-cells = <1>;
813 #size-cells = <0>;
d524fa7f
LJ		 814 v-i2c-supply = <&db8500_vape_reg>;
815
816 clock-frequency = <400000>;
afd653e9
LJ		 817 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
818 clock-names = "i2cclk", "apb_pclk";
29417fe8 819 power-domains = <&pm_domains DOMAIN_VAPE>;
7e0ce270
LJ		 820 };
821
822 i2c@80122000 {
d524fa7f 823 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
7e0ce270 824 reg = <0x80122000 0x1000>;
90c40257 825 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
35b33d23 826
7e0ce270
LJ		 827 #address-cells = <1>;
828 #size-cells = <0>;
d524fa7f
LJ		 829 v-i2c-supply = <&db8500_vape_reg>;
830
831 clock-frequency = <400000>;
afd653e9
LJ		 832
833 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
834 clock-names = "i2cclk", "apb_pclk";
29417fe8 835 power-domains = <&pm_domains DOMAIN_VAPE>;
7e0ce270
LJ		 836 };
837
838 i2c@80128000 {
d524fa7f 839 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
7e0ce270 840 reg = <0x80128000 0x1000>;
90c40257 841 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
35b33d23 842
7e0ce270
LJ		 843 #address-cells = <1>;
844 #size-cells = <0>;
d524fa7f
LJ		 845 v-i2c-supply = <&db8500_vape_reg>;
846
847 clock-frequency = <400000>;
afd653e9
LJ		 848
849 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
850 clock-names = "i2cclk", "apb_pclk";
29417fe8 851 power-domains = <&pm_domains DOMAIN_VAPE>;
7e0ce270
LJ		 852 };
853
854 i2c@80110000 {
d524fa7f 855 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
7e0ce270 856 reg = <0x80110000 0x1000>;
90c40257 857 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
35b33d23 858
7e0ce270
LJ		 859 #address-cells = <1>;
860 #size-cells = <0>;
d524fa7f
LJ		 861 v-i2c-supply = <&db8500_vape_reg>;
862
863 clock-frequency = <400000>;
afd653e9
LJ		 864
865 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
866 clock-names = "i2cclk", "apb_pclk";
29417fe8 867 power-domains = <&pm_domains DOMAIN_VAPE>;
7e0ce270
LJ		 868 };
869
870 i2c@8012a000 {
d524fa7f 871 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
7e0ce270 872 reg = <0x8012a000 0x1000>;
90c40257 873 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
35b33d23 874
7e0ce270
LJ		 875 #address-cells = <1>;
876 #size-cells = <0>;
d524fa7f
LJ		 877 v-i2c-supply = <&db8500_vape_reg>;
878
879 clock-frequency = <400000>;
afd653e9 880
72b3e249 881 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
afd653e9 882 clock-names = "i2cclk", "apb_pclk";
29417fe8 883 power-domains = <&pm_domains DOMAIN_VAPE>;
7e0ce270
LJ		 884 };
885
886 ssp@80002000 {
887 compatible = "arm,pl022", "arm,primecell";
c164fa62 888 reg = <0x80002000 0x1000>;
90c40257 889 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
7e0ce270
LJ		 890 #address-cells = <1>;
891 #size-cells = <0>;
6e1484c2 892 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
80fbe30f 893 clock-names = "SSPCLK", "apb_pclk";
6e1484c2
LW		 894 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
895 <&dma 8 0 0x0>; /* Logical - MemToDev */
896 dma-names = "rx", "tx";
770e2f6b 897 power-domains = <&pm_domains DOMAIN_VAPE>;
6e1484c2
LW		 898 };
899
900 ssp@80003000 {
901 compatible = "arm,pl022", "arm,primecell";
902 reg = <0x80003000 0x1000>;
903 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
904 #address-cells = <1>;
905 #size-cells = <0>;
906 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
80fbe30f 907 clock-names = "SSPCLK", "apb_pclk";
6e1484c2
LW		 908 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
909 <&dma 9 0 0x0>; /* Logical - MemToDev */
910 dma-names = "rx", "tx";
770e2f6b 911 power-domains = <&pm_domains DOMAIN_VAPE>;
6e1484c2
LW		 912 };
913
914 spi@8011a000 {
915 compatible = "arm,pl022", "arm,primecell";
916 reg = <0x8011a000 0x1000>;
917 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
918 #address-cells = <1>;
919 #size-cells = <0>;
920 /* Same clock wired to kernel and pclk */
921 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
80fbe30f 922 clock-names = "SSPCLK", "apb_pclk";
6e1484c2
LW		 923 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
924 <&dma 0 0 0x0>; /* Logical - MemToDev */
925 dma-names = "rx", "tx";
770e2f6b 926 power-domains = <&pm_domains DOMAIN_VAPE>;
6e1484c2
LW		 927 };
928
929 spi@80112000 {
930 compatible = "arm,pl022", "arm,primecell";
931 reg = <0x80112000 0x1000>;
932 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
933 #address-cells = <1>;
934 #size-cells = <0>;
935 /* Same clock wired to kernel and pclk */
936 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
80fbe30f 937 clock-names = "SSPCLK", "apb_pclk";
6e1484c2
LW		 938 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
939 <&dma 35 0 0x0>; /* Logical - MemToDev */
940 dma-names = "rx", "tx";
770e2f6b 941 power-domains = <&pm_domains DOMAIN_VAPE>;
6e1484c2
LW		 942 };
943
944 spi@80111000 {
945 compatible = "arm,pl022", "arm,primecell";
946 reg = <0x80111000 0x1000>;
947 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
948 #address-cells = <1>;
949 #size-cells = <0>;
950 /* Same clock wired to kernel and pclk */
951 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
80fbe30f 952 clock-names = "SSPCLK", "apb_pclk";
6e1484c2
LW		 953 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
954 <&dma 33 0 0x0>; /* Logical - MemToDev */
955 dma-names = "rx", "tx";
770e2f6b 956 power-domains = <&pm_domains DOMAIN_VAPE>;
6e1484c2
LW		 957 };
958
959 spi@80129000 {
960 compatible = "arm,pl022", "arm,primecell";
961 reg = <0x80129000 0x1000>;
962 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
963 #address-cells = <1>;
964 #size-cells = <0>;
965 /* Same clock wired to kernel and pclk */
966 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
80fbe30f 967 clock-names = "SSPCLK", "apb_pclk";
6e1484c2
LW		 968 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
969 <&dma 40 0 0x0>; /* Logical - MemToDev */
970 dma-names = "rx", "tx";
770e2f6b 971 power-domains = <&pm_domains DOMAIN_VAPE>;
7e0ce270
LJ		 972 };
973
974 uart@80120000 {
975 compatible = "arm,pl011", "arm,primecell";
976 reg = <0x80120000 0x1000>;
90c40257 977 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
fbff01cc
LJ		 978
979 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
980 <&dma 13 0 0x0>; /* Logical - MemToDev */
981 dma-names = "rx", "tx";
982
5a323fb4
LJ		 983 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
984 clock-names = "uart", "apb_pclk";
985
7e0ce270
LJ		 986 status = "disabled";
987 };
fbff01cc 988
7e0ce270
LJ		 989 uart@80121000 {
990 compatible = "arm,pl011", "arm,primecell";
991 reg = <0x80121000 0x1000>;
90c40257 992 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
fbff01cc
LJ		 993
994 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
995 <&dma 12 0 0x0>; /* Logical - MemToDev */
996 dma-names = "rx", "tx";
997
5a323fb4
LJ		 998 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
999 clock-names = "uart", "apb_pclk";
1000
7e0ce270
LJ		 1001 status = "disabled";
1002 };
fbff01cc 1003
7e0ce270
LJ		 1004 uart@80007000 {
1005 compatible = "arm,pl011", "arm,primecell";
1006 reg = <0x80007000 0x1000>;
90c40257 1007 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
fbff01cc
LJ		 1008
1009 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
1010 <&dma 11 0 0x0>; /* Logical - MemToDev */
1011 dma-names = "rx", "tx";
1012
5a323fb4
LJ		 1013 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
1014 clock-names = "uart", "apb_pclk";
1015
7e0ce270
LJ		 1016 status = "disabled";
1017 };
1018
81bf8c2e 1019 sdi0_per1@80126000 {
7e0ce270
LJ		 1020 compatible = "arm,pl18x", "arm,primecell";
1021 reg = <0x80126000 0x1000>;
90c40257 1022 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
498315b9
LJ		 1023
1024 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
1025 <&dma 29 0 0x0>; /* Logical - MemToDev */
1026 dma-names = "rx", "tx";
1027
604be898
LJ		 1028 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
1029 clock-names = "sdi", "apb_pclk";
067addec 1030 power-domains = <&pm_domains DOMAIN_VAPE>;
604be898 1031
7e0ce270
LJ		 1032 status = "disabled";
1033 };
76ff4e43 1034
81bf8c2e 1035 sdi1_per2@80118000 {
7e0ce270
LJ		 1036 compatible = "arm,pl18x", "arm,primecell";
1037 reg = <0x80118000 0x1000>;
90c40257 1038 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
498315b9
LJ		 1039
1040 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
1041 <&dma 32 0 0x0>; /* Logical - MemToDev */
1042 dma-names = "rx", "tx";
1043
604be898
LJ		 1044 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
1045 clock-names = "sdi", "apb_pclk";
067addec 1046 power-domains = <&pm_domains DOMAIN_VAPE>;
604be898 1047
7e0ce270
LJ		 1048 status = "disabled";
1049 };
76ff4e43 1050
81bf8c2e 1051 sdi2_per3@80005000 {
7e0ce270
LJ		 1052 compatible = "arm,pl18x", "arm,primecell";
1053 reg = <0x80005000 0x1000>;
90c40257 1054 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
498315b9
LJ		 1055
1056 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
1057 <&dma 28 0 0x0>; /* Logical - MemToDev */
1058 dma-names = "rx", "tx";
1059
604be898
LJ		 1060 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
1061 clock-names = "sdi", "apb_pclk";
067addec 1062 power-domains = <&pm_domains DOMAIN_VAPE>;
604be898 1063
7e0ce270
LJ		 1064 status = "disabled";
1065 };
76ff4e43 1066
81bf8c2e 1067 sdi3_per2@80119000 {
7e0ce270
LJ		 1068 compatible = "arm,pl18x", "arm,primecell";
1069 reg = <0x80119000 0x1000>;
90c40257 1070 interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
604be898 1071
14cdf8cb
LW		 1072 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
1073 <&dma 41 0 0x0>; /* Logical - MemToDev */
1074 dma-names = "rx", "tx";
1075
604be898
LJ		 1076 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
1077 clock-names = "sdi", "apb_pclk";
067addec 1078 power-domains = <&pm_domains DOMAIN_VAPE>;
604be898 1079
7e0ce270
LJ		 1080 status = "disabled";
1081 };
76ff4e43 1082
81bf8c2e 1083 sdi4_per2@80114000 {
7e0ce270
LJ		 1084 compatible = "arm,pl18x", "arm,primecell";
1085 reg = <0x80114000 0x1000>;
90c40257 1086 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
498315b9
LJ		 1087
1088 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
1089 <&dma 42 0 0x0>; /* Logical - MemToDev */
1090 dma-names = "rx", "tx";
1091
604be898
LJ		 1092 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
1093 clock-names = "sdi", "apb_pclk";
067addec 1094 power-domains = <&pm_domains DOMAIN_VAPE>;
604be898 1095
7e0ce270
LJ		 1096 status = "disabled";
1097 };
76ff4e43 1098
81bf8c2e 1099 sdi5_per3@80008000 {
7e0ce270 1100 compatible = "arm,pl18x", "arm,primecell";
76ff4e43 1101 reg = <0x80008000 0x1000>;
90c40257 1102 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
604be898 1103
14cdf8cb
LW		 1104 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
1105 <&dma 43 0 0x0>; /* Logical - MemToDev */
1106 dma-names = "rx", "tx";
1107
604be898
LJ		 1108 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
1109 clock-names = "sdi", "apb_pclk";
067addec 1110 power-domains = <&pm_domains DOMAIN_VAPE>;
604be898 1111
7e0ce270
LJ		 1112 status = "disabled";
1113 };
bf76e062 1114
fe164529
LJ		 1115 msp0: msp@80123000 {
1116 compatible = "stericsson,ux500-msp-i2s";
1117 reg = <0x80123000 0x1000>;
90c40257 1118 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
fe164529 1119 v-ape-supply = <&db8500_vape_reg>;
133e6027 1120
618111ca
LJ		 1121 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1122 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1123 dma-names = "rx", "tx";
1124
133e6027
LJ		 1125 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1126 clock-names = "msp", "apb_pclk";
1127
fe164529
LJ		 1128 status = "disabled";
1129 };
1130
1131 msp1: msp@80124000 {
1132 compatible = "stericsson,ux500-msp-i2s";
1133 reg = <0x80124000 0x1000>;
90c40257 1134 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
fe164529 1135 v-ape-supply = <&db8500_vape_reg>;
133e6027 1136
14cdf8cb 1137 /* This DMA channel only exist on DB8500 v1 */
618111ca
LJ		 1138 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1139 dma-names = "tx";
1140
133e6027
LJ		 1141 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1142 clock-names = "msp", "apb_pclk";
1143
fe164529
LJ		 1144 status = "disabled";
1145 };
1146
1147 // HDMI sound
1148 msp2: msp@80117000 {
1149 compatible = "stericsson,ux500-msp-i2s";
1150 reg = <0x80117000 0x1000>;
90c40257 1151 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
fe164529 1152 v-ape-supply = <&db8500_vape_reg>;
133e6027 1153
618111ca
LJ		 1154 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
1155 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1156 HighPrio - Fixed */
1157 dma-names = "rx", "tx";
1158
133e6027
LJ		 1159 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1160 clock-names = "msp", "apb_pclk";
1161
fe164529
LJ		 1162 status = "disabled";
1163 };
1164
1165 msp3: msp@80125000 {
1166 compatible = "stericsson,ux500-msp-i2s";
1167 reg = <0x80125000 0x1000>;
90c40257 1168 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
fe164529 1169 v-ape-supply = <&db8500_vape_reg>;
133e6027 1170
14cdf8cb 1171 /* This DMA channel only exist on DB8500 v2 */
618111ca
LJ		 1172 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1173 dma-names = "rx";
1174
133e6027
LJ		 1175 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1176 clock-names = "msp", "apb_pclk";
1177
fe164529
LJ		 1178 status = "disabled";
1179 };
1180
bf76e062
LJ		 1181 external-bus@50000000 {
1182 compatible = "simple-bus";
1183 reg = <0x50000000 0x4000000>;
1184 #address-cells = <1>;
1185 #size-cells = <1>;
1186 ranges = <0 0x50000000 0x4000000>;
1187 status = "disabled";
1188 };
dc1956b5 1189
1190 cpufreq-cooling {
1191 compatible = "stericsson,db8500-cpufreq-cooling";
1192 status = "disabled";
d460d28b 1193 };
dc1956b5 1194
6e9a88a0
LW		 1195 mcde@a0350000 {
1196 compatible = "stericsson,mcde";
1197 reg = <0xa0350000 0x1000>, /* MCDE */
1198 <0xa0351000 0x1000>, /* DSI link 1 */
1199 <0xa0352000 0x1000>, /* DSI link 2 */
1200 <0xa0353000 0x1000>; /* DSI link 3 */
1201 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
1202 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1203 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1204 <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
1205 <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
1206 <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
1207 <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
1208 <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
1209 <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
1210 };
1211
fe2e9f92
LJ		 1212 cryp@a03cb000 {
1213 compatible = "stericsson,ux500-cryp";
1214 reg = <0xa03cb000 0x1000>;
90c40257 1215 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
fe2e9f92
LJ		 1216
1217 v-ape-supply = <&db8500_vape_reg>;
d2f898ce 1218 clocks = <&prcc_pclk 6 1>;
fe2e9f92 1219 };
61122cf2
LJ		 1220
1221 hash@a03c2000 {
1222 compatible = "stericsson,ux500-hash";
1223 reg = <0xa03c2000 0x1000>;
1224
1225 v-ape-supply = <&db8500_vape_reg>;
024cfe88 1226 clocks = <&prcc_pclk 6 2>;
61122cf2 1227 };
5d0769f0
AB		 1228 };
1229};
Linux kernel - Deliverables
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