Commit | Line | Data |
---|---|---|
dd06faff LJ |
1 | /* |
2 | * Copyright 2012 ST-Ericsson AB | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
01dc909f LW |
10 | * |
11 | * Device Tree for the HREF+ prior to the v60 variant. | |
dd06faff LJ |
12 | */ |
13 | ||
2ce05a14 LW |
14 | #include "ste-dbx5x0.dtsi" |
15 | #include "ste-href.dtsi" | |
dd06faff LJ |
16 | |
17 | / { | |
6b8db132 LJ |
18 | gpio_keys { |
19 | button@1 { | |
20 | gpios = <&tc3589x_gpio 7 0x4>; | |
21 | }; | |
22 | }; | |
23 | ||
b1ba1439 | 24 | soc { |
dd06faff LJ |
25 | i2c@80004000 { |
26 | tps61052@33 { | |
27 | compatible = "tps61052"; | |
28 | reg = <0x33>; | |
29 | }; | |
d62407b0 | 30 | |
7e0a51a0 LW |
31 | tc35892@42 { |
32 | compatible = "toshiba,tc35892"; | |
d62407b0 LW |
33 | reg = <0x42>; |
34 | interrupt-parent = <&gpio6>; | |
35 | interrupts = <25 IRQ_TYPE_EDGE_RISING>; | |
a45cb698 LW |
36 | pinctrl-names = "default"; |
37 | pinctrl-0 = <&tc35892_hrefprev60_mode>; | |
d62407b0 LW |
38 | |
39 | interrupt-controller; | |
7e0a51a0 | 40 | #interrupt-cells = <1>; |
d62407b0 LW |
41 | |
42 | tc3589x_gpio: tc3589x_gpio { | |
43 | compatible = "tc3589x-gpio"; | |
7e0a51a0 | 44 | interrupts = <0>; |
d62407b0 LW |
45 | |
46 | interrupt-controller; | |
47 | #interrupt-cells = <2>; | |
48 | gpio-controller; | |
49 | #gpio-cells = <2>; | |
50 | }; | |
51 | }; | |
dd06faff | 52 | }; |
cbebba7d | 53 | |
38656820 LW |
54 | ssp@80002000 { |
55 | /* | |
56 | * On the first generation boards, this SSP/SPI port was connected | |
57 | * to the AB8500. | |
58 | */ | |
59 | pinctrl-names = "default"; | |
60 | pinctrl-0 = <&ssp0_hrefprev60_mode>; | |
61 | }; | |
62 | ||
a987a3ac UH |
63 | // External Micro SD slot |
64 | sdi0_per1@80126000 { | |
65 | cd-gpios = <&tc3589x_gpio 3 0x4>; | |
66 | }; | |
67 | ||
8ad49c65 LJ |
68 | vmmci: regulator-gpio { |
69 | gpios = <&tc3589x_gpio 18 0x4>; | |
75766003 | 70 | enable-gpio = <&tc3589x_gpio 17 0x4>; |
8ad49c65 | 71 | }; |
1e662353 LW |
72 | |
73 | pinctrl { | |
3ae2750a LW |
74 | /* Set this up using hogs */ |
75 | pinctrl-names = "default"; | |
76 | pinctrl-0 = <&ipgpio_hrefprev60_mode>; | |
77 | ||
38656820 LW |
78 | ssp0 { |
79 | ssp0_hrefprev60_mode: ssp0_hrefprev60_default { | |
80 | hrefprev60_mux { | |
81 | ste,function = "ssp0"; | |
82 | ste,pins = "ssp0_a_1"; | |
83 | }; | |
84 | hrefprev60_cfg1 { | |
85 | ste,pins = "GPIO145_C13"; /* RXD */ | |
86 | ste,config = <&in_pd>; | |
87 | }; | |
88 | ||
89 | }; | |
90 | }; | |
1e662353 LW |
91 | sdi0 { |
92 | /* This additional pin needed on early MOP500 and HREFs previous to v60 */ | |
93 | sdi0_default_mode: sdi0_default { | |
94 | hrefprev60_mux { | |
95 | ste,function = "mc0"; | |
96 | ste,pins = "mc0dat31dir_a_1"; | |
97 | }; | |
98 | hrefprev60_cfg1 { | |
99 | ste,pins = "GPIO21_AB3"; /* DAT31DIR */ | |
100 | ste,config = <&out_hi>; | |
101 | }; | |
102 | ||
103 | }; | |
104 | }; | |
a45cb698 LW |
105 | tc35892 { |
106 | tc35892_hrefprev60_mode: tc35892_hrefprev60 { | |
107 | hrefprev60_cfg { | |
108 | ste,pins = "GPIO217_AH12"; | |
109 | ste,config = <&gpio_in_pu>; | |
110 | }; | |
111 | }; | |
112 | }; | |
3ae2750a LW |
113 | ipgpio { |
114 | ipgpio_hrefprev60_mode: ipgpio_hrefprev60 { | |
115 | hrefprev60_mux { | |
116 | ste,function = "ipgpio"; | |
117 | ste,pins = "ipgpio0_c_1", "ipgpio1_c_1"; | |
118 | }; | |
119 | hrefprev60_cfg1 { | |
120 | ste,pins = "GPIO6_AF6", "GPIO7_AG5"; | |
121 | ste,config = <&in_pu>; | |
122 | }; | |
123 | }; | |
124 | }; | |
1e662353 | 125 | }; |
dd06faff LJ |
126 | }; |
127 | }; |