projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f8635abd LW |
1 | /* |
| 2 | * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC | |
| 3 | */ | |
| 4 | /include/ "skeleton.dtsi" | |
| 5 | ||
| 6 | / { | |
| 7 | #address-cells = <1>; | |
| 8 | #size-cells = <1>; | |
| 9 | ||
| 10 | memory { | |
| 11 | reg = <0x00000000 0x04000000>, | |
| 12 | <0x08000000 0x04000000>; | |
| 13 | }; | |
| 14 | ||
| 15 | L2: l2-cache { | |
| 16 | compatible = "arm,l210-cache"; | |
| 17 | reg = <0x10210000 0x1000>; | |
| 18 | interrupt-parent = <&vica>; | |
| 19 | interrupts = <30>; | |
| 20 | cache-unified; | |
| 21 | cache-level = <2>; | |
| 22 | }; | |
| 23 | ||
| 7690fbb2 | 24 | mtu0: mtu@101e2000 { |
| f8635abd | 25 | /* Nomadik system timer */ |
| 7690fbb2 | 26 | compatible = "st,nomadik-mtu"; |
| f8635abd LW |
27 | reg = <0x101e2000 0x1000>; |
| 28 | interrupt-parent = <&vica>; | |
| 29 | interrupts = <4>; | |
| 7690fbb2 LW |
30 | clocks = <&timclk>, <&pclk>; |
| 31 | clock-names = "timclk", "apb_pclk"; | |
| f8635abd LW |
32 | }; |
| 33 | ||
| 7690fbb2 | 34 | mtu1: mtu@101e3000 { |
| f8635abd LW |
35 | /* Secondary timer */ |
| 36 | reg = <0x101e3000 0x1000>; | |
| 37 | interrupt-parent = <&vica>; | |
| 38 | interrupts = <5>; | |
| 7690fbb2 LW |
39 | clocks = <&timclk>, <&pclk>; |
| 40 | clock-names = "timclk", "apb_pclk"; | |
| f8635abd LW |
41 | }; |
| 42 | ||
| 6010d403 LW |
43 | gpio0: gpio@101e4000 { |
| 44 | compatible = "st,nomadik-gpio"; | |
| 45 | reg = <0x101e4000 0x80>; | |
| 46 | interrupt-parent = <&vica>; | |
| 47 | interrupts = <6>; | |
| 48 | interrupt-controller; | |
| 49 | #interrupt-cells = <2>; | |
| 50 | gpio-controller; | |
| 51 | #gpio-cells = <2>; | |
| 52 | gpio-bank = <0>; | |
| 6e2b07a1 | 53 | clocks = <&pclk>; |
| 6010d403 LW |
54 | }; |
| 55 | ||
| 56 | gpio1: gpio@101e5000 { | |
| 57 | compatible = "st,nomadik-gpio"; | |
| 58 | reg = <0x101e5000 0x80>; | |
| 59 | interrupt-parent = <&vica>; | |
| 60 | interrupts = <7>; | |
| 61 | interrupt-controller; | |
| 62 | #interrupt-cells = <2>; | |
| 63 | gpio-controller; | |
| 64 | #gpio-cells = <2>; | |
| 65 | gpio-bank = <1>; | |
| 6e2b07a1 | 66 | clocks = <&pclk>; |
| 6010d403 LW |
67 | }; |
| 68 | ||
| 69 | gpio2: gpio@101e6000 { | |
| 70 | compatible = "st,nomadik-gpio"; | |
| 71 | reg = <0x101e6000 0x80>; | |
| 72 | interrupt-parent = <&vica>; | |
| 73 | interrupts = <8>; | |
| 74 | interrupt-controller; | |
| 75 | #interrupt-cells = <2>; | |
| 76 | gpio-controller; | |
| 77 | #gpio-cells = <2>; | |
| 78 | gpio-bank = <2>; | |
| 6e2b07a1 | 79 | clocks = <&pclk>; |
| 6010d403 LW |
80 | }; |
| 81 | ||
| 82 | gpio3: gpio@101e7000 { | |
| 83 | compatible = "st,nomadik-gpio"; | |
| 84 | reg = <0x101e7000 0x80>; | |
| 85 | interrupt-parent = <&vica>; | |
| 86 | interrupts = <9>; | |
| 87 | interrupt-controller; | |
| 88 | #interrupt-cells = <2>; | |
| 89 | gpio-controller; | |
| 90 | #gpio-cells = <2>; | |
| 91 | gpio-bank = <3>; | |
| 6e2b07a1 | 92 | clocks = <&pclk>; |
| 6010d403 LW |
93 | }; |
| 94 | ||
| 95 | pinctrl { | |
| cdfa9273 | 96 | compatible = "stericsson,stn8815-pinctrl"; |
| 49932f5e LW |
97 | /* Pin configurations */ |
| 98 | uart0 { | |
| 99 | uart0_default_mux: uart0_mux { | |
| 100 | u0_default_mux { | |
| 101 | ste,function = "u0"; | |
| 102 | ste,pins = "u0_a_1"; | |
| 103 | }; | |
| 104 | }; | |
| 105 | }; | |
| 106 | uart1 { | |
| 107 | uart1_default_mux: uart1_mux { | |
| 108 | u1_default_mux { | |
| 109 | ste,function = "u1"; | |
| 110 | ste,pins = "u1_a_1"; | |
| 111 | }; | |
| 112 | }; | |
| 113 | }; | |
| 114 | mmcsd { | |
| 115 | mmcsd_default_mux: mmcsd_mux { | |
| 116 | mmcsd_default_mux { | |
| 117 | ste,function = "mmcsd"; | |
| 118 | ste,pins = "mmcsd_a_1"; | |
| 119 | }; | |
| 120 | }; | |
| 121 | mmcsd_default_mode: mmcsd_default { | |
| 122 | mmcsd_default_cfg1 { | |
| 123 | /* MCCLK */ | |
| 124 | ste,pins = "GPIO8_B10"; | |
| 125 | ste,output = <0>; | |
| 126 | }; | |
| 127 | mmcsd_default_cfg2 { | |
| 128 | /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */ | |
| 129 | ste,pins = "GPIO10_C11", "GPIO15_A12", | |
| 130 | "GPIO16_C13"; | |
| 131 | ste,output = <1>; | |
| 132 | }; | |
| 133 | mmcsd_default_cfg3 { | |
| 134 | /* MCCMD, MCDAT3-0, MCMSFBCLK */ | |
| 135 | ste,pins = "GPIO9_A10", "GPIO11_B11", | |
| 136 | "GPIO12_A11", "GPIO13_C12", | |
| 137 | "GPIO14_B12", "GPIO24_C15"; | |
| 138 | ste,input = <1>; | |
| 139 | }; | |
| 140 | }; | |
| 141 | }; | |
| 142 | i2c0 { | |
| 143 | i2c0_default_mode: i2c0_default { | |
| 144 | i2c0_default_cfg { | |
| 145 | ste,pins = "GPIO62_D3", "GPIO63_D2"; | |
| 146 | ste,input = <1>; | |
| 147 | }; | |
| 148 | }; | |
| 149 | }; | |
| 150 | i2c1 { | |
| 151 | i2c1_default_mode: i2c1_default { | |
| 152 | i2c1_default_cfg { | |
| 153 | ste,pins = "GPIO53_L4", "GPIO54_L3"; | |
| 154 | ste,input = <1>; | |
| 155 | }; | |
| 156 | }; | |
| 157 | }; | |
| 158 | i2c2 { | |
| 159 | i2c2_default_mode: i2c2_default { | |
| 160 | i2c2_default_cfg { | |
| 161 | ste,pins = "GPIO73_C21", "GPIO74_C20"; | |
| 162 | ste,input = <1>; | |
| 163 | }; | |
| 164 | }; | |
| 165 | }; | |
| 6010d403 LW |
166 | }; |
| 167 | ||
| 6e2b07a1 LW |
168 | src: src@101e0000 { |
| 169 | compatible = "stericsson,nomadik-src"; | |
| 170 | reg = <0x101e0000 0x1000>; | |
| c641d4df LW |
171 | disable-sxtalo; |
| 172 | disable-mxtalo; | |
| 173 | ||
| 174 | /* | |
| 175 | * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz | |
| 176 | * that is parent of TIMCLK, PLL1 and PLL2 | |
| 177 | */ | |
| 178 | mxtal: mxtal@19.2M { | |
| 179 | #clock-cells = <0>; | |
| 180 | compatible = "fixed-clock"; | |
| 181 | clock-frequency = <19200000>; | |
| 182 | }; | |
| 183 | ||
| 184 | /* | |
| 185 | * The 2.4 MHz TIMCLK reference clock is active at | |
| 186 | * boot time, this is actually the MXTALCLK @19.2 MHz | |
| 187 | * divided by 8. This clock is used by the timers and | |
| 188 | * watchdog. See page 105 ff. | |
| 189 | */ | |
| 190 | timclk: timclk@2.4M { | |
| 191 | #clock-cells = <0>; | |
| 192 | compatible = "fixed-factor-clock"; | |
| 193 | clock-div = <8>; | |
| 194 | clock-mult = <1>; | |
| 195 | clocks = <&mxtal>; | |
| 196 | }; | |
| 197 | ||
| 198 | /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */ | |
| 199 | pll1: pll1@0 { | |
| 200 | #clock-cells = <0>; | |
| 201 | compatible = "st,nomadik-pll-clock"; | |
| 202 | pll-id = <1>; | |
| 203 | clocks = <&mxtal>; | |
| 204 | }; | |
| 205 | ||
| 206 | /* HCLK divides the PLL1 with 1,2,3 or 4 */ | |
| 207 | hclk: hclk@0 { | |
| 208 | #clock-cells = <0>; | |
| 209 | compatible = "st,nomadik-hclk-clock"; | |
| 210 | clocks = <&pll1>; | |
| 211 | }; | |
| 212 | /* The PCLK domain uses HCLK right off */ | |
| 213 | pclk: pclk@0 { | |
| 214 | #clock-cells = <0>; | |
| 215 | compatible = "fixed-factor-clock"; | |
| 216 | clock-div = <1>; | |
| 217 | clock-mult = <1>; | |
| 218 | clocks = <&hclk>; | |
| 219 | }; | |
| 220 | ||
| 221 | /* PLL2 is usually 864 MHz and divided into a few fixed rates */ | |
| 222 | pll2: pll2@0 { | |
| 223 | #clock-cells = <0>; | |
| 224 | compatible = "st,nomadik-pll-clock"; | |
| 225 | pll-id = <2>; | |
| 226 | clocks = <&mxtal>; | |
| 227 | }; | |
| 228 | clk216: clk216@216M { | |
| 229 | #clock-cells = <0>; | |
| 230 | compatible = "fixed-factor-clock"; | |
| 231 | clock-div = <4>; | |
| 232 | clock-mult = <1>; | |
| 233 | clocks = <&pll2>; | |
| 234 | }; | |
| 235 | clk108: clk108@108M { | |
| 236 | #clock-cells = <0>; | |
| 237 | compatible = "fixed-factor-clock"; | |
| 238 | clock-div = <2>; | |
| 239 | clock-mult = <1>; | |
| 240 | clocks = <&clk216>; | |
| 241 | }; | |
| 242 | clk72: clk72@72M { | |
| 243 | #clock-cells = <0>; | |
| 244 | compatible = "fixed-factor-clock"; | |
| 245 | /* The data sheet does not say how this is derived */ | |
| 246 | clock-div = <12>; | |
| 247 | clock-mult = <1>; | |
| 248 | clocks = <&pll2>; | |
| 249 | }; | |
| 250 | clk48: clk48@48M { | |
| 251 | #clock-cells = <0>; | |
| 252 | compatible = "fixed-factor-clock"; | |
| 253 | /* The data sheet does not say how this is derived */ | |
| 254 | clock-div = <18>; | |
| 255 | clock-mult = <1>; | |
| 256 | clocks = <&pll2>; | |
| 257 | }; | |
| 258 | clk27: clk27@27M { | |
| 259 | #clock-cells = <0>; | |
| 260 | compatible = "fixed-factor-clock"; | |
| 261 | clock-div = <4>; | |
| 262 | clock-mult = <1>; | |
| 263 | clocks = <&clk108>; | |
| 264 | }; | |
| 265 | ||
| 266 | /* This apparently exists as well */ | |
| 267 | ulpiclk: ulpiclk@60M { | |
| 268 | #clock-cells = <0>; | |
| 269 | compatible = "fixed-clock"; | |
| 270 | clock-frequency = <60000000>; | |
| 271 | }; | |
| 272 | ||
| 273 | /* | |
| 274 | * IP AMBA bus clocks, driving the bus side of the | |
| 275 | * peripheral clocking, clock gates. | |
| 276 | */ | |
| 277 | ||
| 278 | hclkdma0: hclkdma0@48M { | |
| 279 | #clock-cells = <0>; | |
| 280 | compatible = "st,nomadik-src-clock"; | |
| 281 | clock-id = <0>; | |
| 282 | clocks = <&hclk>; | |
| 283 | }; | |
| 284 | hclksmc: hclksmc@48M { | |
| 285 | #clock-cells = <0>; | |
| 286 | compatible = "st,nomadik-src-clock"; | |
| 287 | clock-id = <1>; | |
| 288 | clocks = <&hclk>; | |
| 289 | }; | |
| 290 | hclksdram: hclksdram@48M { | |
| 291 | #clock-cells = <0>; | |
| 292 | compatible = "st,nomadik-src-clock"; | |
| 293 | clock-id = <2>; | |
| 294 | clocks = <&hclk>; | |
| 295 | }; | |
| 296 | hclkdma1: hclkdma1@48M { | |
| 297 | #clock-cells = <0>; | |
| 298 | compatible = "st,nomadik-src-clock"; | |
| 299 | clock-id = <3>; | |
| 300 | clocks = <&hclk>; | |
| 301 | }; | |
| 302 | hclkclcd: hclkclcd@48M { | |
| 303 | #clock-cells = <0>; | |
| 304 | compatible = "st,nomadik-src-clock"; | |
| 305 | clock-id = <4>; | |
| 306 | clocks = <&hclk>; | |
| 307 | }; | |
| 308 | pclkirda: pclkirda@48M { | |
| 309 | #clock-cells = <0>; | |
| 310 | compatible = "st,nomadik-src-clock"; | |
| 311 | clock-id = <5>; | |
| 312 | clocks = <&pclk>; | |
| 313 | }; | |
| 314 | pclkssp: pclkssp@48M { | |
| 315 | #clock-cells = <0>; | |
| 316 | compatible = "st,nomadik-src-clock"; | |
| 317 | clock-id = <6>; | |
| 318 | clocks = <&pclk>; | |
| 319 | }; | |
| 320 | pclkuart0: pclkuart0@48M { | |
| 321 | #clock-cells = <0>; | |
| 322 | compatible = "st,nomadik-src-clock"; | |
| 323 | clock-id = <7>; | |
| 324 | clocks = <&pclk>; | |
| 325 | }; | |
| 326 | pclksdi: pclksdi@48M { | |
| 327 | #clock-cells = <0>; | |
| 328 | compatible = "st,nomadik-src-clock"; | |
| 329 | clock-id = <8>; | |
| 330 | clocks = <&pclk>; | |
| 331 | }; | |
| 332 | pclki2c0: pclki2c0@48M { | |
| 333 | #clock-cells = <0>; | |
| 334 | compatible = "st,nomadik-src-clock"; | |
| 335 | clock-id = <9>; | |
| 336 | clocks = <&pclk>; | |
| 337 | }; | |
| 338 | pclki2c1: pclki2c1@48M { | |
| 339 | #clock-cells = <0>; | |
| 340 | compatible = "st,nomadik-src-clock"; | |
| 341 | clock-id = <10>; | |
| 342 | clocks = <&pclk>; | |
| 343 | }; | |
| 344 | pclkuart1: pclkuart1@48M { | |
| 345 | #clock-cells = <0>; | |
| 346 | compatible = "st,nomadik-src-clock"; | |
| 347 | clock-id = <11>; | |
| 348 | clocks = <&pclk>; | |
| 349 | }; | |
| 350 | pclkmsp0: pclkmsp0@48M { | |
| 351 | #clock-cells = <0>; | |
| 352 | compatible = "st,nomadik-src-clock"; | |
| 353 | clock-id = <12>; | |
| 354 | clocks = <&pclk>; | |
| 355 | }; | |
| 356 | hclkusb: hclkusb@48M { | |
| 357 | #clock-cells = <0>; | |
| 358 | compatible = "st,nomadik-src-clock"; | |
| 359 | clock-id = <13>; | |
| 360 | clocks = <&hclk>; | |
| 361 | }; | |
| 362 | hclkdif: hclkdif@48M { | |
| 363 | #clock-cells = <0>; | |
| 364 | compatible = "st,nomadik-src-clock"; | |
| 365 | clock-id = <14>; | |
| 366 | clocks = <&hclk>; | |
| 367 | }; | |
| 368 | hclksaa: hclksaa@48M { | |
| 369 | #clock-cells = <0>; | |
| 370 | compatible = "st,nomadik-src-clock"; | |
| 371 | clock-id = <15>; | |
| 372 | clocks = <&hclk>; | |
| 373 | }; | |
| 374 | hclksva: hclksva@48M { | |
| 375 | #clock-cells = <0>; | |
| 376 | compatible = "st,nomadik-src-clock"; | |
| 377 | clock-id = <16>; | |
| 378 | clocks = <&hclk>; | |
| 379 | }; | |
| 380 | pclkhsi: pclkhsi@48M { | |
| 381 | #clock-cells = <0>; | |
| 382 | compatible = "st,nomadik-src-clock"; | |
| 383 | clock-id = <17>; | |
| 384 | clocks = <&pclk>; | |
| 385 | }; | |
| 386 | pclkxti: pclkxti@48M { | |
| 387 | #clock-cells = <0>; | |
| 388 | compatible = "st,nomadik-src-clock"; | |
| 389 | clock-id = <18>; | |
| 390 | clocks = <&pclk>; | |
| 391 | }; | |
| 392 | pclkuart2: pclkuart2@48M { | |
| 393 | #clock-cells = <0>; | |
| 394 | compatible = "st,nomadik-src-clock"; | |
| 395 | clock-id = <19>; | |
| 396 | clocks = <&pclk>; | |
| 397 | }; | |
| 398 | pclkmsp1: pclkmsp1@48M { | |
| 399 | #clock-cells = <0>; | |
| 400 | compatible = "st,nomadik-src-clock"; | |
| 401 | clock-id = <20>; | |
| 402 | clocks = <&pclk>; | |
| 403 | }; | |
| 404 | pclkmsp2: pclkmsp2@48M { | |
| 405 | #clock-cells = <0>; | |
| 406 | compatible = "st,nomadik-src-clock"; | |
| 407 | clock-id = <21>; | |
| 408 | clocks = <&pclk>; | |
| 409 | }; | |
| 410 | pclkowm: pclkowm@48M { | |
| 411 | #clock-cells = <0>; | |
| 412 | compatible = "st,nomadik-src-clock"; | |
| 413 | clock-id = <22>; | |
| 414 | clocks = <&pclk>; | |
| 415 | }; | |
| 416 | hclkhpi: hclkhpi@48M { | |
| 417 | #clock-cells = <0>; | |
| 418 | compatible = "st,nomadik-src-clock"; | |
| 419 | clock-id = <23>; | |
| 420 | clocks = <&hclk>; | |
| 421 | }; | |
| 422 | pclkske: pclkske@48M { | |
| 423 | #clock-cells = <0>; | |
| 424 | compatible = "st,nomadik-src-clock"; | |
| 425 | clock-id = <24>; | |
| 426 | clocks = <&pclk>; | |
| 427 | }; | |
| 428 | pclkhsem: pclkhsem@48M { | |
| 429 | #clock-cells = <0>; | |
| 430 | compatible = "st,nomadik-src-clock"; | |
| 431 | clock-id = <25>; | |
| 432 | clocks = <&pclk>; | |
| 433 | }; | |
| 434 | hclk3d: hclk3d@48M { | |
| 435 | #clock-cells = <0>; | |
| 436 | compatible = "st,nomadik-src-clock"; | |
| 437 | clock-id = <26>; | |
| 438 | clocks = <&hclk>; | |
| 439 | }; | |
| 440 | hclkhash: hclkhash@48M { | |
| 441 | #clock-cells = <0>; | |
| 442 | compatible = "st,nomadik-src-clock"; | |
| 443 | clock-id = <27>; | |
| 444 | clocks = <&hclk>; | |
| 445 | }; | |
| 446 | hclkcryp: hclkcryp@48M { | |
| 447 | #clock-cells = <0>; | |
| 448 | compatible = "st,nomadik-src-clock"; | |
| 449 | clock-id = <28>; | |
| 450 | clocks = <&hclk>; | |
| 451 | }; | |
| 452 | pclkmshc: pclkmshc@48M { | |
| 453 | #clock-cells = <0>; | |
| 454 | compatible = "st,nomadik-src-clock"; | |
| 455 | clock-id = <29>; | |
| 456 | clocks = <&pclk>; | |
| 457 | }; | |
| 458 | hclkusbm: hclkusbm@48M { | |
| 459 | #clock-cells = <0>; | |
| 460 | compatible = "st,nomadik-src-clock"; | |
| 461 | clock-id = <30>; | |
| 462 | clocks = <&hclk>; | |
| 463 | }; | |
| 464 | hclkrng: hclkrng@48M { | |
| 465 | #clock-cells = <0>; | |
| 466 | compatible = "st,nomadik-src-clock"; | |
| 467 | clock-id = <31>; | |
| 468 | clocks = <&hclk>; | |
| 469 | }; | |
| 470 | ||
| 471 | /* IP kernel clocks */ | |
| 472 | clcdclk: clcdclk@0 { | |
| 473 | #clock-cells = <0>; | |
| 474 | compatible = "st,nomadik-src-clock"; | |
| 475 | clock-id = <36>; | |
| 476 | clocks = <&clk72 &clk48>; | |
| 477 | }; | |
| 478 | irdaclk: irdaclk@48M { | |
| 479 | #clock-cells = <0>; | |
| 480 | compatible = "st,nomadik-src-clock"; | |
| 481 | clock-id = <37>; | |
| 482 | clocks = <&clk48>; | |
| 483 | }; | |
| 484 | sspiclk: sspiclk@48M { | |
| 485 | #clock-cells = <0>; | |
| 486 | compatible = "st,nomadik-src-clock"; | |
| 487 | clock-id = <38>; | |
| 488 | clocks = <&clk48>; | |
| 489 | }; | |
| 490 | uart0clk: uart0clk@48M { | |
| 491 | #clock-cells = <0>; | |
| 492 | compatible = "st,nomadik-src-clock"; | |
| 493 | clock-id = <39>; | |
| 494 | clocks = <&clk48>; | |
| 495 | }; | |
| 496 | sdiclk: sdiclk@48M { | |
| 497 | /* Also called MCCLK in some documents */ | |
| 498 | #clock-cells = <0>; | |
| 499 | compatible = "st,nomadik-src-clock"; | |
| 500 | clock-id = <40>; | |
| 501 | clocks = <&clk48>; | |
| 502 | }; | |
| 503 | i2c0clk: i2c0clk@48M { | |
| 504 | #clock-cells = <0>; | |
| 505 | compatible = "st,nomadik-src-clock"; | |
| 506 | clock-id = <41>; | |
| 507 | clocks = <&clk48>; | |
| 508 | }; | |
| 509 | i2c1clk: i2c1clk@48M { | |
| 510 | #clock-cells = <0>; | |
| 511 | compatible = "st,nomadik-src-clock"; | |
| 512 | clock-id = <42>; | |
| 513 | clocks = <&clk48>; | |
| 514 | }; | |
| 515 | uart1clk: uart1clk@48M { | |
| 516 | #clock-cells = <0>; | |
| 517 | compatible = "st,nomadik-src-clock"; | |
| 518 | clock-id = <43>; | |
| 519 | clocks = <&clk48>; | |
| 520 | }; | |
| 521 | mspclk0: mspclk0@48M { | |
| 522 | #clock-cells = <0>; | |
| 523 | compatible = "st,nomadik-src-clock"; | |
| 524 | clock-id = <44>; | |
| 525 | clocks = <&clk48>; | |
| 526 | }; | |
| 527 | usbclk: usbclk@48M { | |
| 528 | #clock-cells = <0>; | |
| 529 | compatible = "st,nomadik-src-clock"; | |
| 530 | clock-id = <45>; | |
| 531 | clocks = <&clk48>; /* 48 MHz not ULPI */ | |
| 532 | }; | |
| 533 | difclk: difclk@72M { | |
| 534 | #clock-cells = <0>; | |
| 535 | compatible = "st,nomadik-src-clock"; | |
| 536 | clock-id = <46>; | |
| 537 | clocks = <&clk72>; | |
| 538 | }; | |
| 539 | ipi2cclk: ipi2cclk@48M { | |
| 540 | #clock-cells = <0>; | |
| 541 | compatible = "st,nomadik-src-clock"; | |
| 542 | clock-id = <47>; | |
| 543 | clocks = <&clk48>; /* Guess */ | |
| 544 | }; | |
| 545 | ipbmcclk: ipbmcclk@48M { | |
| 546 | #clock-cells = <0>; | |
| 547 | compatible = "st,nomadik-src-clock"; | |
| 548 | clock-id = <48>; | |
| 549 | clocks = <&clk48>; /* Guess */ | |
| 550 | }; | |
| 551 | hsiclkrx: hsiclkrx@216M { | |
| 552 | #clock-cells = <0>; | |
| 553 | compatible = "st,nomadik-src-clock"; | |
| 554 | clock-id = <49>; | |
| 555 | clocks = <&clk216>; | |
| 556 | }; | |
| 557 | hsiclktx: hsiclktx@108M { | |
| 558 | #clock-cells = <0>; | |
| 559 | compatible = "st,nomadik-src-clock"; | |
| 560 | clock-id = <50>; | |
| 561 | clocks = <&clk108>; | |
| 562 | }; | |
| 563 | uart2clk: uart2clk@48M { | |
| 564 | #clock-cells = <0>; | |
| 565 | compatible = "st,nomadik-src-clock"; | |
| 566 | clock-id = <51>; | |
| 567 | clocks = <&clk48>; | |
| 568 | }; | |
| 569 | mspclk1: mspclk1@48M { | |
| 570 | #clock-cells = <0>; | |
| 571 | compatible = "st,nomadik-src-clock"; | |
| 572 | clock-id = <52>; | |
| 573 | clocks = <&clk48>; | |
| 574 | }; | |
| 575 | mspclk2: mspclk2@48M { | |
| 576 | #clock-cells = <0>; | |
| 577 | compatible = "st,nomadik-src-clock"; | |
| 578 | clock-id = <53>; | |
| 579 | clocks = <&clk48>; | |
| 580 | }; | |
| 581 | owmclk: owmclk@48M { | |
| 582 | #clock-cells = <0>; | |
| 583 | compatible = "st,nomadik-src-clock"; | |
| 584 | clock-id = <54>; | |
| 585 | clocks = <&clk48>; /* Guess */ | |
| 586 | }; | |
| 587 | skeclk: skeclk@48M { | |
| 588 | #clock-cells = <0>; | |
| 589 | compatible = "st,nomadik-src-clock"; | |
| 590 | clock-id = <56>; | |
| 591 | clocks = <&clk48>; /* Guess */ | |
| 592 | }; | |
| 593 | x3dclk: x3dclk@48M { | |
| 594 | #clock-cells = <0>; | |
| 595 | compatible = "st,nomadik-src-clock"; | |
| 596 | clock-id = <58>; | |
| 597 | clocks = <&clk48>; /* Guess */ | |
| 598 | }; | |
| 599 | pclkmsp3: pclkmsp3@48M { | |
| 600 | #clock-cells = <0>; | |
| 601 | compatible = "st,nomadik-src-clock"; | |
| 602 | clock-id = <59>; | |
| 603 | clocks = <&pclk>; | |
| 604 | }; | |
| 605 | mspclk3: mspclk3@48M { | |
| 606 | #clock-cells = <0>; | |
| 607 | compatible = "st,nomadik-src-clock"; | |
| 608 | clock-id = <60>; | |
| 609 | clocks = <&clk48>; | |
| 610 | }; | |
| 611 | mshcclk: mshcclk@48M { | |
| 612 | #clock-cells = <0>; | |
| 613 | compatible = "st,nomadik-src-clock"; | |
| 614 | clock-id = <61>; | |
| 615 | clocks = <&clk48>; /* Guess */ | |
| 616 | }; | |
| 617 | usbmclk: usbmclk@48M { | |
| 618 | #clock-cells = <0>; | |
| 619 | compatible = "st,nomadik-src-clock"; | |
| 620 | clock-id = <62>; | |
| 621 | /* Stated as "48 MHz not ULPI clock" */ | |
| 622 | clocks = <&clk48>; | |
| 623 | }; | |
| 624 | rngcclk: rngcclk@48M { | |
| 625 | #clock-cells = <0>; | |
| 626 | compatible = "st,nomadik-src-clock"; | |
| 627 | clock-id = <63>; | |
| 628 | clocks = <&clk48>; /* Guess */ | |
| 6e2b07a1 LW |
629 | }; |
| 630 | }; | |
| 631 | ||
| ba785205 LW |
632 | /* A NAND flash of 128 MiB */ |
| 633 | fsmc: flash@40000000 { | |
| 634 | compatible = "stericsson,fsmc-nand"; | |
| 635 | #address-cells = <1>; | |
| 636 | #size-cells = <1>; | |
| 637 | reg = <0x10100000 0x1000>, /* FSMC Register*/ | |
| 638 | <0x40000000 0x2000>, /* NAND Base DATA */ | |
| 639 | <0x41000000 0x2000>, /* NAND Base ADDR */ | |
| 640 | <0x40800000 0x2000>; /* NAND Base CMD */ | |
| 641 | reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; | |
| c641d4df | 642 | clocks = <&hclksmc>; |
| ba785205 LW |
643 | status = "okay"; |
| 644 | ||
| 645 | partition@0 { | |
| 646 | label = "X-Loader(NAND)"; | |
| 647 | reg = <0x0 0x40000>; | |
| 648 | }; | |
| 649 | partition@40000 { | |
| 650 | label = "MemInit(NAND)"; | |
| 651 | reg = <0x40000 0x40000>; | |
| 652 | }; | |
| 653 | partition@80000 { | |
| 654 | label = "BootLoader(NAND)"; | |
| 655 | reg = <0x80000 0x200000>; | |
| 656 | }; | |
| 657 | partition@280000 { | |
| 658 | label = "Kernel zImage(NAND)"; | |
| 659 | reg = <0x280000 0x300000>; | |
| 660 | }; | |
| 661 | partition@580000 { | |
| 662 | label = "Root Filesystem(NAND)"; | |
| 663 | reg = <0x580000 0x1600000>; | |
| 664 | }; | |
| 665 | partition@1b80000 { | |
| 666 | label = "User Filesystem(NAND)"; | |
| 667 | reg = <0x1b80000 0x6480000>; | |
| 668 | }; | |
| 669 | }; | |
| 670 | ||
| 2ad6e398 LW |
671 | external-bus@34000000 { |
| 672 | compatible = "simple-bus"; | |
| 673 | reg = <0x34000000 0x1000000>; | |
| 674 | #address-cells = <1>; | |
| 675 | #size-cells = <1>; | |
| 676 | ranges = <0 0x34000000 0x1000000>; | |
| 677 | ethernet@300 { | |
| 678 | compatible = "smsc,lan91c111"; | |
| 679 | reg = <0x300 0x0fd00>; | |
| 680 | }; | |
| 681 | }; | |
| 682 | ||
| 09e02f4d LW |
683 | /* I2C0 connected to the STw4811 power management chip */ |
| 684 | i2c0 { | |
| 685 | compatible = "i2c-gpio"; | |
| 686 | gpios = <&gpio1 31 0>, /* sda */ | |
| 687 | <&gpio1 30 0>; /* scl */ | |
| 688 | #address-cells = <1>; | |
| 689 | #size-cells = <0>; | |
| 49932f5e LW |
690 | pinctrl-names = "default"; |
| 691 | pinctrl-0 = <&i2c0_default_mode>; | |
| 09e02f4d LW |
692 | |
| 693 | stw4811@2d { | |
| 694 | compatible = "st,stw4811"; | |
| 695 | reg = <0x2d>; | |
| 696 | }; | |
| 697 | }; | |
| 698 | ||
| 699 | /* I2C1 connected to various sensors */ | |
| 700 | i2c1 { | |
| 701 | compatible = "i2c-gpio"; | |
| 702 | gpios = <&gpio1 22 0>, /* sda */ | |
| 703 | <&gpio1 21 0>; /* scl */ | |
| 704 | #address-cells = <1>; | |
| 705 | #size-cells = <0>; | |
| 49932f5e LW |
706 | pinctrl-names = "default"; |
| 707 | pinctrl-0 = <&i2c1_default_mode>; | |
| 09e02f4d LW |
708 | |
| 709 | camera@2d { | |
| 710 | compatible = "st,camera"; | |
| 711 | reg = <0x10>; | |
| 712 | }; | |
| 713 | stw5095@1a { | |
| 714 | compatible = "st,stw5095"; | |
| 715 | reg = <0x1a>; | |
| 716 | }; | |
| 717 | lis3lv02dl@1d { | |
| 718 | compatible = "st,lis3lv02dl"; | |
| 719 | reg = <0x1d>; | |
| 720 | }; | |
| 721 | }; | |
| 722 | ||
| 723 | /* I2C2 connected to the USB portions of the STw4811 only */ | |
| 724 | i2c2 { | |
| 725 | compatible = "i2c-gpio"; | |
| 726 | gpios = <&gpio2 10 0>, /* sda */ | |
| 727 | <&gpio2 9 0>; /* scl */ | |
| 728 | #address-cells = <1>; | |
| 729 | #size-cells = <0>; | |
| 49932f5e LW |
730 | pinctrl-names = "default"; |
| 731 | pinctrl-0 = <&i2c2_default_mode>; | |
| 732 | ||
| 09e02f4d LW |
733 | stw4811@2d { |
| 734 | compatible = "st,stw4811-usb"; | |
| 735 | reg = <0x2d>; | |
| 736 | }; | |
| 737 | }; | |
| 738 | ||
| f8635abd LW |
739 | amba { |
| 740 | compatible = "arm,amba-bus"; | |
| 741 | #address-cells = <1>; | |
| 742 | #size-cells = <1>; | |
| 743 | ranges; | |
| 744 | ||
| 745 | vica: intc@0x10140000 { | |
| 746 | compatible = "arm,versatile-vic"; | |
| 747 | interrupt-controller; | |
| 748 | #interrupt-cells = <1>; | |
| 749 | reg = <0x10140000 0x20>; | |
| 750 | }; | |
| 751 | ||
| 752 | vicb: intc@0x10140020 { | |
| 753 | compatible = "arm,versatile-vic"; | |
| 754 | interrupt-controller; | |
| 755 | #interrupt-cells = <1>; | |
| 756 | reg = <0x10140020 0x20>; | |
| 757 | }; | |
| 758 | ||
| 759 | uart0: uart@101fd000 { | |
| 760 | compatible = "arm,pl011", "arm,primecell"; | |
| 761 | reg = <0x101fd000 0x1000>; | |
| 762 | interrupt-parent = <&vica>; | |
| 763 | interrupts = <12>; | |
| c641d4df | 764 | clocks = <&uart0clk>, <&pclkuart0>; |
| 6e2b07a1 | 765 | clock-names = "uartclk", "apb_pclk"; |
| 49932f5e LW |
766 | pinctrl-names = "default"; |
| 767 | pinctrl-0 = <&uart0_default_mux>; | |
| f8635abd LW |
768 | }; |
| 769 | ||
| 770 | uart1: uart@101fb000 { | |
| 771 | compatible = "arm,pl011", "arm,primecell"; | |
| 772 | reg = <0x101fb000 0x1000>; | |
| 773 | interrupt-parent = <&vica>; | |
| 774 | interrupts = <17>; | |
| c641d4df | 775 | clocks = <&uart1clk>, <&pclkuart1>; |
| 6e2b07a1 | 776 | clock-names = "uartclk", "apb_pclk"; |
| 49932f5e LW |
777 | pinctrl-names = "default"; |
| 778 | pinctrl-0 = <&uart1_default_mux>; | |
| f8635abd LW |
779 | }; |
| 780 | ||
| 781 | uart2: uart@101f2000 { | |
| 782 | compatible = "arm,pl011", "arm,primecell"; | |
| 783 | reg = <0x101f2000 0x1000>; | |
| 784 | interrupt-parent = <&vica>; | |
| 785 | interrupts = <28>; | |
| c641d4df | 786 | clocks = <&uart2clk>, <&pclkuart2>; |
| 6e2b07a1 | 787 | clock-names = "uartclk", "apb_pclk"; |
| f8635abd LW |
788 | status = "disabled"; |
| 789 | }; | |
| 27bda036 LW |
790 | |
| 791 | rng: rng@101b0000 { | |
| 792 | compatible = "arm,primecell"; | |
| 793 | reg = <0x101b0000 0x1000>; | |
| c641d4df | 794 | clocks = <&rngcclk>, <&hclkrng>; |
| 6e2b07a1 | 795 | clock-names = "rng", "apb_pclk"; |
| 27bda036 LW |
796 | }; |
| 797 | ||
| 798 | rtc: rtc@101e8000 { | |
| 799 | compatible = "arm,pl031", "arm,primecell"; | |
| 800 | reg = <0x101e8000 0x1000>; | |
| 6e2b07a1 LW |
801 | clocks = <&pclk>; |
| 802 | clock-names = "apb_pclk"; | |
| 27bda036 LW |
803 | interrupt-parent = <&vica>; |
| 804 | interrupts = <10>; | |
| 805 | }; | |
| 4fd243c6 LW |
806 | |
| 807 | mmcsd: sdi@101f6000 { | |
| 808 | compatible = "arm,pl18x", "arm,primecell"; | |
| 809 | reg = <0x101f6000 0x1000>; | |
| c641d4df | 810 | clocks = <&sdiclk>, <&pclksdi>; |
| 6e2b07a1 | 811 | clock-names = "mclk", "apb_pclk"; |
| 4fd243c6 LW |
812 | interrupt-parent = <&vica>; |
| 813 | interrupts = <22>; | |
| 814 | max-frequency = <48000000>; | |
| 815 | bus-width = <4>; | |
| 816 | mmc-cap-mmc-highspeed; | |
| 817 | mmc-cap-sd-highspeed; | |
| 818 | cd-gpios = <&gpio3 15 0x1>; | |
| 819 | cd-inverted; | |
| 49932f5e LW |
820 | pinctrl-names = "default"; |
| 821 | pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; | |
| 4fd243c6 | 822 | }; |
| f8635abd LW |
823 | }; |
| 824 | }; |