projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f563a571 MC |
1 | /* |
| 2 | * Copyright (C) 2014 STMicroelectronics R&D Limited | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 as | |
| 6 | * published by the Free Software Foundation. | |
| 7 | */ | |
| 1befe7e4 | 8 | #include <dt-bindings/clock/stih407-clks.h> |
| f563a571 MC |
9 | / { |
| 10 | clocks { | |
| 58a8d9be GF |
11 | #address-cells = <1>; |
| 12 | #size-cells = <1>; | |
| 13 | ranges; | |
| 14 | ||
| f563a571 MC |
15 | /* |
| 16 | * Fixed 30MHz oscillator inputs to SoC | |
| 17 | */ | |
| 18 | clk_sysin: clk-sysin { | |
| 19 | #clock-cells = <0>; | |
| 20 | compatible = "fixed-clock"; | |
| 21 | clock-frequency = <30000000>; | |
| 22 | }; | |
| 23 | ||
| 24 | /* | |
| 25 | * ARM Peripheral clock for timers | |
| 26 | */ | |
| 27 | arm_periph_clk: arm-periph-clk { | |
| 28 | #clock-cells = <0>; | |
| 29 | compatible = "fixed-clock"; | |
| 30 | clock-frequency = <600000000>; | |
| 31 | }; | |
| 32 | ||
| 33 | /* | |
| 34 | * Bootloader initialized system infrastructure clock for | |
| 35 | * serial devices. | |
| 36 | */ | |
| 37 | clk_ext2f_a9: clockgen-c0@13 { | |
| 38 | #clock-cells = <0>; | |
| 39 | compatible = "fixed-clock"; | |
| 40 | clock-frequency = <200000000>; | |
| 41 | clock-output-names = "clk-s-icn-reg-0"; | |
| 42 | }; | |
| 58a8d9be GF |
43 | |
| 44 | clockgen-a@090ff000 { | |
| 45 | compatible = "st,clkgen-c32"; | |
| 46 | reg = <0x90ff000 0x1000>; | |
| 47 | ||
| 48 | clk_s_a0_pll: clk-s-a0-pll { | |
| 49 | #clock-cells = <1>; | |
| 50 | compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; | |
| 51 | ||
| 52 | clocks = <&clk_sysin>; | |
| 53 | ||
| 54 | clock-output-names = "clk-s-a0-pll-ofd-0"; | |
| 55 | }; | |
| 56 | ||
| 57 | clk_s_a0_flexgen: clk-s-a0-flexgen { | |
| 58 | compatible = "st,flexgen"; | |
| 59 | ||
| 60 | #clock-cells = <1>; | |
| 61 | ||
| 62 | clocks = <&clk_s_a0_pll 0>, | |
| 63 | <&clk_sysin>; | |
| 64 | ||
| 65 | clock-output-names = "clk-ic-lmi0"; | |
| 66 | }; | |
| 67 | }; | |
| 1befe7e4 GF |
68 | |
| 69 | clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { | |
| 70 | #clock-cells = <1>; | |
| 71 | compatible = "st,stih407-quadfs660-C", "st,quadfs"; | |
| 72 | reg = <0x9103000 0x1000>; | |
| 73 | ||
| 74 | clocks = <&clk_sysin>; | |
| 75 | ||
| 76 | clock-output-names = "clk-s-c0-fs0-ch0", | |
| 77 | "clk-s-c0-fs0-ch1", | |
| 78 | "clk-s-c0-fs0-ch2", | |
| 79 | "clk-s-c0-fs0-ch3"; | |
| 80 | }; | |
| 81 | ||
| 82 | clk_s_c0: clockgen-c@09103000 { | |
| 83 | compatible = "st,clkgen-c32"; | |
| 84 | reg = <0x9103000 0x1000>; | |
| 85 | ||
| 86 | clk_s_c0_pll0: clk-s-c0-pll0 { | |
| 87 | #clock-cells = <1>; | |
| 88 | compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; | |
| 89 | ||
| 90 | clocks = <&clk_sysin>; | |
| 91 | ||
| 92 | clock-output-names = "clk-s-c0-pll0-odf-0"; | |
| 93 | }; | |
| 94 | ||
| 95 | clk_s_c0_pll1: clk-s-c0-pll1 { | |
| 96 | #clock-cells = <1>; | |
| 97 | compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; | |
| 98 | ||
| 99 | clocks = <&clk_sysin>; | |
| 100 | ||
| 101 | clock-output-names = "clk-s-c0-pll1-odf-0"; | |
| 102 | }; | |
| 103 | ||
| 104 | clk_s_c0_flexgen: clk-s-c0-flexgen { | |
| 105 | #clock-cells = <1>; | |
| 106 | compatible = "st,flexgen"; | |
| 107 | ||
| 108 | clocks = <&clk_s_c0_pll0 0>, | |
| 109 | <&clk_s_c0_pll1 0>, | |
| 110 | <&clk_s_c0_quadfs 0>, | |
| 111 | <&clk_s_c0_quadfs 1>, | |
| 112 | <&clk_s_c0_quadfs 2>, | |
| 113 | <&clk_s_c0_quadfs 3>, | |
| 114 | <&clk_sysin>; | |
| 115 | ||
| 116 | clock-output-names = "clk-icn-gpu", | |
| 117 | "clk-fdma", | |
| 118 | "clk-nand", | |
| 119 | "clk-hva", | |
| 120 | "clk-proc-stfe", | |
| 121 | "clk-proc-tp", | |
| 122 | "clk-rx-icn-dmu", | |
| 123 | "clk-rx-icn-hva", | |
| 124 | "clk-icn-cpu", | |
| 125 | "clk-tx-icn-dmu", | |
| 126 | "clk-mmc-0", | |
| 127 | "clk-mmc-1", | |
| 128 | "clk-jpegdec", | |
| 129 | "clk-ext2fa9", | |
| 130 | "clk-ic-bdisp-0", | |
| 131 | "clk-ic-bdisp-1", | |
| 132 | "clk-pp-dmu", | |
| 133 | "clk-vid-dmu", | |
| 134 | "clk-dss-lpc", | |
| 135 | "clk-st231-aud-0", | |
| 136 | "clk-st231-gp-1", | |
| 137 | "clk-st231-dmu", | |
| 138 | "clk-icn-lmi", | |
| 139 | "clk-tx-icn-disp-1", | |
| 140 | "clk-icn-sbc", | |
| 141 | "clk-stfe-frc2", | |
| 142 | "clk-eth-phy", | |
| 143 | "clk-eth-ref-phyclk", | |
| 144 | "clk-flash-promip", | |
| 145 | "clk-main-disp", | |
| 146 | "clk-aux-disp", | |
| 147 | "clk-compo-dvp"; | |
| 148 | }; | |
| 149 | }; | |
| 6e67a510 GF |
150 | |
| 151 | clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { | |
| 152 | #clock-cells = <1>; | |
| 153 | compatible = "st,stih407-quadfs660-D", "st,quadfs"; | |
| 154 | reg = <0x9104000 0x1000>; | |
| 155 | ||
| 156 | clocks = <&clk_sysin>; | |
| 157 | ||
| 158 | clock-output-names = "clk-s-d0-fs0-ch0", | |
| 159 | "clk-s-d0-fs0-ch1", | |
| 160 | "clk-s-d0-fs0-ch2", | |
| 161 | "clk-s-d0-fs0-ch3"; | |
| 162 | }; | |
| 163 | ||
| 164 | clockgen-d0@09104000 { | |
| 165 | compatible = "st,clkgen-c32"; | |
| 166 | reg = <0x9104000 0x1000>; | |
| 167 | ||
| 168 | clk_s_d0_flexgen: clk-s-d0-flexgen { | |
| 169 | #clock-cells = <1>; | |
| 170 | compatible = "st,flexgen"; | |
| 171 | ||
| 172 | clocks = <&clk_s_d0_quadfs 0>, | |
| 173 | <&clk_s_d0_quadfs 1>, | |
| 174 | <&clk_s_d0_quadfs 2>, | |
| 175 | <&clk_s_d0_quadfs 3>, | |
| 176 | <&clk_sysin>; | |
| 177 | ||
| 178 | clock-output-names = "clk-pcm-0", | |
| 179 | "clk-pcm-1", | |
| 180 | "clk-pcm-2", | |
| 181 | "clk-spdiff"; | |
| 182 | }; | |
| 183 | }; | |
| 184 | ||
| 185 | clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { | |
| 186 | #clock-cells = <1>; | |
| 187 | compatible = "st,stih407-quadfs660-D", "st,quadfs"; | |
| 188 | reg = <0x9106000 0x1000>; | |
| 189 | ||
| 190 | clocks = <&clk_sysin>; | |
| 191 | ||
| 192 | clock-output-names = "clk-s-d2-fs0-ch0", | |
| 193 | "clk-s-d2-fs0-ch1", | |
| 194 | "clk-s-d2-fs0-ch2", | |
| 195 | "clk-s-d2-fs0-ch3"; | |
| 196 | }; | |
| 197 | ||
| 198 | clk_tmdsout_hdmi: clk-tmdsout-hdmi { | |
| 199 | #clock-cells = <0>; | |
| 200 | compatible = "fixed-clock"; | |
| 201 | clock-frequency = <0>; | |
| 202 | }; | |
| 203 | ||
| 204 | clockgen-d2@x9106000 { | |
| 205 | compatible = "st,clkgen-c32"; | |
| 206 | reg = <0x9106000 0x1000>; | |
| 207 | ||
| 208 | clk_s_d2_flexgen: clk-s-d2-flexgen { | |
| 209 | #clock-cells = <1>; | |
| 210 | compatible = "st,flexgen"; | |
| 211 | ||
| 212 | clocks = <&clk_s_d2_quadfs 0>, | |
| 213 | <&clk_s_d2_quadfs 1>, | |
| 214 | <&clk_s_d2_quadfs 2>, | |
| 215 | <&clk_s_d2_quadfs 3>, | |
| 216 | <&clk_sysin>, | |
| 217 | <&clk_sysin>, | |
| 218 | <&clk_tmdsout_hdmi>; | |
| 219 | ||
| 220 | clock-output-names = "clk-pix-main-disp", | |
| 221 | "clk-pix-pip", | |
| 222 | "clk-pix-gdp1", | |
| 223 | "clk-pix-gdp2", | |
| 224 | "clk-pix-gdp3", | |
| 225 | "clk-pix-gdp4", | |
| 226 | "clk-pix-aux-disp", | |
| 227 | "clk-denc", | |
| 228 | "clk-pix-hddac", | |
| 229 | "clk-hddac", | |
| 230 | "clk-sddac", | |
| 231 | "clk-pix-dvo", | |
| 232 | "clk-dvo", | |
| 233 | "clk-pix-hdmi", | |
| 234 | "", | |
| 235 | "clk-ref-hdmiphy"; | |
| 236 | }; | |
| 237 | }; | |
| 238 | ||
| 239 | clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { | |
| 240 | #clock-cells = <1>; | |
| 241 | compatible = "st,stih407-quadfs660-D", "st,quadfs"; | |
| 242 | reg = <0x9107000 0x1000>; | |
| 243 | ||
| 244 | clocks = <&clk_sysin>; | |
| 245 | ||
| 246 | clock-output-names = "clk-s-d3-fs0-ch0", | |
| 247 | "clk-s-d3-fs0-ch1", | |
| 248 | "clk-s-d3-fs0-ch2", | |
| 249 | "clk-s-d3-fs0-ch3"; | |
| 250 | }; | |
| 251 | ||
| 252 | clockgen-d3@9107000 { | |
| 253 | compatible = "st,clkgen-c32"; | |
| 254 | reg = <0x9107000 0x1000>; | |
| 255 | ||
| 256 | clk_s_d3_flexgen: clk-s-d3-flexgen { | |
| 257 | #clock-cells = <1>; | |
| 258 | compatible = "st,flexgen"; | |
| 259 | ||
| 260 | clocks = <&clk_s_d3_quadfs 0>, | |
| 261 | <&clk_s_d3_quadfs 1>, | |
| 262 | <&clk_s_d3_quadfs 2>, | |
| 263 | <&clk_s_d3_quadfs 3>, | |
| 264 | <&clk_sysin>; | |
| 265 | ||
| 266 | clock-output-names = "clk-stfe-frc1", | |
| 267 | "clk-tsout-0", | |
| 268 | "clk-tsout-1", | |
| 269 | "clk-mchi", | |
| 270 | "clk-vsens-compo", | |
| 271 | "clk-frc1-remote", | |
| 272 | "clk-lpc-0", | |
| 273 | "clk-lpc-1"; | |
| 274 | }; | |
| 275 | }; | |
| f563a571 MC |
276 | }; |
| 277 | }; |